Cross Reference: /freebsd-10.3-release/sys/dev/ata/ata-all.h

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1/- 2 Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 *	1/- 2 Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 *
26 * $FreeBSD: head/sys/dev/ata/ata-all.h 200171 2009-12-06 00:10:13Z mav $	26 * $FreeBSD: head/sys/dev/ata/ata-all.h 200459 2009-12-13 00:13:21Z marius $
27 / 28 29#if 0 30#define ATA_LEGACY_SUPPORT / Enable obsolete features that break 31 * some modern devices / 32#endif 33 34/ ATA register defines / 35#define ATA_DATA 0 / (RW) data / 36 37#define ATA_FEATURE 1 / (W) feature / 38#define ATA_F_DMA 0x01 / enable DMA / 39#define ATA_F_OVL 0x02 / enable overlap / 40 41#define ATA_COUNT 2 / (W) sector count / 42 43#define ATA_SECTOR 3 / (RW) sector # / 44#define ATA_CYL_LSB 4 / (RW) cylinder# LSB / 45#define ATA_CYL_MSB 5 / (RW) cylinder# MSB / 46#define ATA_DRIVE 6 / (W) Sector/Drive/Head / 47#define ATA_D_LBA 0x40 / use LBA addressing / 48#define ATA_D_IBM 0xa0 / 512 byte sectors, ECC / 49 50#define ATA_COMMAND 7 / (W) command / 51 52#define ATA_ERROR 8 / (R) error / 53#define ATA_E_ILI 0x01 / illegal length / 54#define ATA_E_NM 0x02 / no media / 55#define ATA_E_ABORT 0x04 / command aborted / 56#define ATA_E_MCR 0x08 / media change request / 57#define ATA_E_IDNF 0x10 / ID not found / 58#define ATA_E_MC 0x20 / media changed / 59#define ATA_E_UNC 0x40 / uncorrectable data / 60#define ATA_E_ICRC 0x80 / UDMA crc error / 61#define ATA_E_ATAPI_SENSE_MASK 0xf0 / ATAPI sense key mask / 62 63#define ATA_IREASON 9 / (R) interrupt reason / 64#define ATA_I_CMD 0x01 / cmd (1) \| data (0) / 65#define ATA_I_IN 0x02 / read (1) \| write (0) / 66#define ATA_I_RELEASE 0x04 / released bus (1) / 67#define ATA_I_TAGMASK 0xf8 / tag mask / 68 69#define ATA_STATUS 10 / (R) status / 70#define ATA_ALTSTAT 11 / (R) alternate status / 71#define ATA_S_ERROR 0x01 / error / 72#define ATA_S_INDEX 0x02 / index / 73#define ATA_S_CORR 0x04 / data corrected / 74#define ATA_S_DRQ 0x08 / data request / 75#define ATA_S_DSC 0x10 / drive seek completed / 76#define ATA_S_SERVICE 0x10 / drive needs service / 77#define ATA_S_DWF 0x20 / drive write fault / 78#define ATA_S_DMA 0x20 / DMA ready / 79#define ATA_S_READY 0x40 / drive ready / 80#define ATA_S_BUSY 0x80 / busy / 81 82#define ATA_CONTROL 12 / (W) control / 83 84#define ATA_CTLOFFSET 0x206 / control register offset / 85#define ATA_PCCARD_CTLOFFSET 0x0e / do for PCCARD devices / 86#define ATA_PC98_CTLOFFSET 0x10c / do for PC98 devices / 87#define ATA_A_IDS 0x02 / disable interrupts / 88#define ATA_A_RESET 0x04 / RESET controller / 89#ifdef ATA_LEGACY_SUPPORT 90#define ATA_A_4BIT 0x08 / 4 head bits: obsolete 1996 / 91#else 92#define ATA_A_4BIT 0x00 93#endif 94#define ATA_A_HOB 0x80 / High Order Byte enable / 95 96/ SATA register defines / 97#define ATA_SSTATUS 13 98#define ATA_SS_DET_MASK 0x0000000f 99#define ATA_SS_DET_NO_DEVICE 0x00000000 100#define ATA_SS_DET_DEV_PRESENT 0x00000001 101#define ATA_SS_DET_PHY_ONLINE 0x00000003 102#define ATA_SS_DET_PHY_OFFLINE 0x00000004 103* 104#define ATA_SS_SPD_MASK 0x000000f0 105#define ATA_SS_SPD_NO_SPEED 0x00000000 106#define ATA_SS_SPD_GEN1 0x00000010 107#define ATA_SS_SPD_GEN2 0x00000020 108 109#define ATA_SS_IPM_MASK 0x00000f00 110#define ATA_SS_IPM_NO_DEVICE 0x00000000 111#define ATA_SS_IPM_ACTIVE 0x00000100 112#define ATA_SS_IPM_PARTIAL 0x00000200 113#define ATA_SS_IPM_SLUMBER 0x00000600 114 115#define ATA_SS_CONWELL_MASK \ 116 (ATA_SS_DET_MASK\|ATA_SS_SPD_MASK\|ATA_SS_IPM_MASK) 117#define ATA_SS_CONWELL_GEN1 \ 118 (ATA_SS_DET_PHY_ONLINE\|ATA_SS_SPD_GEN1\|ATA_SS_IPM_ACTIVE) 119#define ATA_SS_CONWELL_GEN2 \ 120 (ATA_SS_DET_PHY_ONLINE\|ATA_SS_SPD_GEN2\|ATA_SS_IPM_ACTIVE) 121 122#define ATA_SERROR 14 123#define ATA_SE_DATA_CORRECTED 0x00000001 124#define ATA_SE_COMM_CORRECTED 0x00000002 125#define ATA_SE_DATA_ERR 0x00000100 126#define ATA_SE_COMM_ERR 0x00000200 127#define ATA_SE_PROT_ERR 0x00000400 128#define ATA_SE_HOST_ERR 0x00000800 129#define ATA_SE_PHY_CHANGED 0x00010000 130#define ATA_SE_PHY_IERROR 0x00020000 131#define ATA_SE_COMM_WAKE 0x00040000 132#define ATA_SE_DECODE_ERR 0x00080000 133#define ATA_SE_PARITY_ERR 0x00100000 134#define ATA_SE_CRC_ERR 0x00200000 135#define ATA_SE_HANDSHAKE_ERR 0x00400000 136#define ATA_SE_LINKSEQ_ERR 0x00800000 137#define ATA_SE_TRANSPORT_ERR 0x01000000 138#define ATA_SE_UNKNOWN_FIS 0x02000000 139 140#define ATA_SCONTROL 15 141#define ATA_SC_DET_MASK 0x0000000f 142#define ATA_SC_DET_IDLE 0x00000000 143#define ATA_SC_DET_RESET 0x00000001 144#define ATA_SC_DET_DISABLE 0x00000004 145 146#define ATA_SC_SPD_MASK 0x000000f0 147#define ATA_SC_SPD_NO_SPEED 0x00000000 148#define ATA_SC_SPD_SPEED_GEN1 0x00000010 149#define ATA_SC_SPD_SPEED_GEN2 0x00000020 150 151#define ATA_SC_IPM_MASK 0x00000f00 152#define ATA_SC_IPM_NONE 0x00000000 153#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 154#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 155 156#define ATA_SACTIVE 16 157 158/* SATA AHCI v1.0 register defines / 159#define ATA_AHCI_CAP 0x00 160#define ATA_AHCI_CAP_NPMASK 0x0000001f 161#define ATA_AHCI_CAP_SXS 0x00000020 162#define ATA_AHCI_CAP_EMS 0x00000040 163#define ATA_AHCI_CAP_CCCS 0x00000080 164#define ATA_AHCI_CAP_NCS 0x00001F00 165#define ATA_AHCI_CAP_NCS_SHIFT 8 166#define ATA_AHCI_CAP_PSC 0x00002000 167#define ATA_AHCI_CAP_SSC 0x00004000 168#define ATA_AHCI_CAP_PMD 0x00008000 169#define ATA_AHCI_CAP_FBSS 0x00010000 170#define ATA_AHCI_CAP_SPM 0x00020000 171#define ATA_AHCI_CAP_SAM 0x00080000 172#define ATA_AHCI_CAP_ISS 0x00F00000 173#define ATA_AHCI_CAP_ISS_SHIFT 20 174#define ATA_AHCI_CAP_SCLO 0x01000000 175#define ATA_AHCI_CAP_SAL 0x02000000 176#define ATA_AHCI_CAP_SALP 0x04000000 177#define ATA_AHCI_CAP_SSS 0x08000000 178#define ATA_AHCI_CAP_SMPS 0x10000000 179#define ATA_AHCI_CAP_SSNTF 0x20000000 180#define ATA_AHCI_CAP_SNCQ 0x40000000 181#define ATA_AHCI_CAP_64BIT 0x80000000 182* 183#define ATA_AHCI_GHC 0x04 184#define ATA_AHCI_GHC_AE 0x80000000 185#define ATA_AHCI_GHC_IE 0x00000002 186#define ATA_AHCI_GHC_HR 0x00000001 187 188#define ATA_AHCI_IS 0x08 189#define ATA_AHCI_PI 0x0c 190#define ATA_AHCI_VS 0x10 191 192#define ATA_AHCI_OFFSET 0x80 193 194#define ATA_AHCI_P_CLB 0x100 195#define ATA_AHCI_P_CLBU 0x104 196#define ATA_AHCI_P_FB 0x108 197#define ATA_AHCI_P_FBU 0x10c 198#define ATA_AHCI_P_IS 0x110 199#define ATA_AHCI_P_IE 0x114 200#define ATA_AHCI_P_IX_DHR 0x00000001 201#define ATA_AHCI_P_IX_PS 0x00000002 202#define ATA_AHCI_P_IX_DS 0x00000004 203#define ATA_AHCI_P_IX_SDB 0x00000008 204#define ATA_AHCI_P_IX_UF 0x00000010 205#define ATA_AHCI_P_IX_DP 0x00000020 206#define ATA_AHCI_P_IX_PC 0x00000040 207#define ATA_AHCI_P_IX_DI 0x00000080 208 209#define ATA_AHCI_P_IX_PRC 0x00400000 210#define ATA_AHCI_P_IX_IPM 0x00800000 211#define ATA_AHCI_P_IX_OF 0x01000000 212#define ATA_AHCI_P_IX_INF 0x04000000 213#define ATA_AHCI_P_IX_IF 0x08000000 214#define ATA_AHCI_P_IX_HBD 0x10000000 215#define ATA_AHCI_P_IX_HBF 0x20000000 216#define ATA_AHCI_P_IX_TFE 0x40000000 217#define ATA_AHCI_P_IX_CPD 0x80000000 218 219#define ATA_AHCI_P_CMD 0x118 220#define ATA_AHCI_P_CMD_ST 0x00000001 221#define ATA_AHCI_P_CMD_SUD 0x00000002 222#define ATA_AHCI_P_CMD_POD 0x00000004 223#define ATA_AHCI_P_CMD_CLO 0x00000008 224#define ATA_AHCI_P_CMD_FRE 0x00000010 225#define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00 226#define ATA_AHCI_P_CMD_ISS 0x00002000 227#define ATA_AHCI_P_CMD_FR 0x00004000 228#define ATA_AHCI_P_CMD_CR 0x00008000 229#define ATA_AHCI_P_CMD_CPS 0x00010000 230#define ATA_AHCI_P_CMD_PMA 0x00020000 231#define ATA_AHCI_P_CMD_HPCP 0x00040000 232#define ATA_AHCI_P_CMD_ISP 0x00080000 233#define ATA_AHCI_P_CMD_CPD 0x00100000 234#define ATA_AHCI_P_CMD_ATAPI 0x01000000 235#define ATA_AHCI_P_CMD_DLAE 0x02000000 236#define ATA_AHCI_P_CMD_ALPE 0x04000000 237#define ATA_AHCI_P_CMD_ASP 0x08000000 238#define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000 239#define ATA_AHCI_P_CMD_NOOP 0x00000000 240#define ATA_AHCI_P_CMD_ACTIVE 0x10000000 241#define ATA_AHCI_P_CMD_PARTIAL 0x20000000 242#define ATA_AHCI_P_CMD_SLUMBER 0x60000000 243 244#define ATA_AHCI_P_TFD 0x120 245#define ATA_AHCI_P_SIG 0x124 246#define ATA_AHCI_P_SSTS 0x128 247#define ATA_AHCI_P_SCTL 0x12c 248#define ATA_AHCI_P_SERR 0x130 249#define ATA_AHCI_P_SACT 0x134 250#define ATA_AHCI_P_CI 0x138 251#define ATA_AHCI_P_SNTF 0x13C 252#define ATA_AHCI_P_FBS 0x140 253 254#define ATA_AHCI_CL_SIZE 32 255#define ATA_AHCI_CL_OFFSET 0 256#define ATA_AHCI_FB_OFFSET (ATA_AHCI_CL_SIZE * 32) 257#define ATA_AHCI_CT_OFFSET (ATA_AHCI_FB_OFFSET + 4096) 258#define ATA_AHCI_CT_SIZE (2176 + 128) 259 260struct ata_ahci_dma_prd { 261 u_int64_t dba; 262 u_int32_t reserved; 263 u_int32_t dbc; /* 0 based / 264#define ATA_AHCI_PRD_MASK 0x003fffff / max 4MB / 265#define ATA_AHCI_PRD_IPC (1<<31) 266} __packed; 267* 268struct ata_ahci_cmd_tab { 269 u_int8_t cfis[64]; 270 u_int8_t acmd[32]; 271 u_int8_t reserved[32]; 272#define ATA_AHCI_DMA_ENTRIES 129 273 struct ata_ahci_dma_prd prd_tab[ATA_AHCI_DMA_ENTRIES]; 274} __packed; 275 276struct ata_ahci_cmd_list { 277 u_int16_t cmd_flags; 278#define ATA_AHCI_CMD_ATAPI 0x0020 279#define ATA_AHCI_CMD_WRITE 0x0040 280#define ATA_AHCI_CMD_PREFETCH 0x0080 281#define ATA_AHCI_CMD_RESET 0x0100 282#define ATA_AHCI_CMD_BIST 0x0200 283#define ATA_AHCI_CMD_CLR_BUSY 0x0400 284 285 u_int16_t prd_length; /* PRD entries / 286* u_int32_t bytecount; 287 u_int64_t cmd_table_phys; /* 128byte aligned / 288} __packed; 289* 290 291/* DMA register defines / 292#define ATA_DMA_ENTRIES 256 293#define ATA_DMA_EOT 0x80000000 294* 295#define ATA_BMCMD_PORT 17 296#define ATA_BMCMD_START_STOP 0x01 297#define ATA_BMCMD_WRITE_READ 0x08 298 299#define ATA_BMDEVSPEC_0 18 300#define ATA_BMSTAT_PORT 19 301#define ATA_BMSTAT_ACTIVE 0x01 302#define ATA_BMSTAT_ERROR 0x02 303#define ATA_BMSTAT_INTERRUPT 0x04 304#define ATA_BMSTAT_MASK 0x07 305#define ATA_BMSTAT_DMA_MASTER 0x20 306#define ATA_BMSTAT_DMA_SLAVE 0x40 307#define ATA_BMSTAT_DMA_SIMPLEX 0x80 308 309#define ATA_BMDEVSPEC_1 20 310#define ATA_BMDTP_PORT 21 311 312#define ATA_IDX_ADDR 22 313#define ATA_IDX_DATA 23 314#define ATA_MAX_RES 24 315 316/* misc defines / 317#define ATA_PRIMARY 0x1f0 318#define ATA_SECONDARY 0x170 319#define ATA_PC98_BANK 0x432 320#define ATA_IOSIZE 0x08 321#define ATA_PC98_IOSIZE 0x10 322#define ATA_CTLIOSIZE 0x01 323#define ATA_BMIOSIZE 0x08 324#define ATA_PC98_BANKIOSIZE 0x01 325#define ATA_IOADDR_RID 0 326#define ATA_CTLADDR_RID 1 327#define ATA_BMADDR_RID 0x20 328#define ATA_PC98_CTLADDR_RID 8 329#define ATA_PC98_BANKADDR_RID 9 330#define ATA_IRQ_RID 0 331#define ATA_DEV(unit) ((unit > 0) ? 0x10 : 0) 332#define ATA_CFA_MAGIC1 0x844A 333#define ATA_CFA_MAGIC2 0x848A 334#define ATA_CFA_MAGIC3 0x8400 335#define ATAPI_MAGIC_LSB 0x14 336#define ATAPI_MAGIC_MSB 0xeb 337#define ATAPI_P_READ (ATA_S_DRQ \| ATA_I_IN) 338#define ATAPI_P_WRITE (ATA_S_DRQ) 339#define ATAPI_P_CMDOUT (ATA_S_DRQ \| ATA_I_CMD) 340#define ATAPI_P_DONEDRQ (ATA_S_DRQ \| ATA_I_CMD \| ATA_I_IN) 341#define ATAPI_P_DONE (ATA_I_CMD \| ATA_I_IN) 342#define ATAPI_P_ABORT 0 343#define ATA_INTR_FLAGS (INTR_MPSAFE\|INTR_TYPE_BIO\|INTR_ENTROPY) 344#define ATA_OP_CONTINUES 0 345#define ATA_OP_FINISHED 1 346#define ATA_MAX_28BIT_LBA 268435455UL 347* 348#ifndef ATA_REQUEST_TIMEOUT 349#define ATA_REQUEST_TIMEOUT 10 350#endif 351 352/* structure used for composite atomic operations / 353#define MAX_COMPOSITES 32 / u_int32_t bits / 354struct ata_composite { 355* struct mtx lock; /* control lock / 356* u_int32_t rd_needed; /* needed read subdisks / 357* u_int32_t rd_done; /* done read subdisks / 358* u_int32_t wr_needed; /* needed write subdisks / 359* u_int32_t wr_depend; /* write depends on subdisks / 360* u_int32_t wr_done; /* done write subdisks / 361* struct ata_request request[MAX_COMPOSITES]; 362* u_int32_t residual; /* bytes still to transfer / 363* caddr_t data_1; 364 caddr_t data_2; 365}; 366 367/* structure used to queue an ATA/ATAPI request / 368struct ata_request { 369* device_t dev; /* device handle / 370* device_t parent; /* channel handle / 371* int unit; /* physical unit / 372* union { 373 struct { 374 u_int8_t command; /* command reg / 375* u_int16_t feature; /* feature reg / 376* u_int16_t count; /* count reg / 377* u_int64_t lba; /* lba reg / 378* } ata; 379 struct { 380 u_int8_t ccb[16]; /* ATAPI command block / 381* struct atapi_sense sense; /* ATAPI request sense data / 382* u_int8_t saved_cmd; /* ATAPI saved command / 383* } atapi; 384 } u; 385 u_int32_t bytecount; /* bytes to transfer / 386* u_int32_t transfersize; /* bytes pr transfer / 387* caddr_t data; /* pointer to data buf / 388* u_int32_t tag; /* HW tag of this request / 389* int flags; 390#define ATA_R_CONTROL 0x00000001 391#define ATA_R_READ 0x00000002 392#define ATA_R_WRITE 0x00000004 393#define ATA_R_ATAPI 0x00000008 394#define ATA_R_DMA 0x00000010 395#define ATA_R_QUIET 0x00000020 396#define ATA_R_TIMEOUT 0x00000040 397#define ATA_R_48BIT 0x00000080 398 399#define ATA_R_ORDERED 0x00000100 400#define ATA_R_AT_HEAD 0x00000200 401#define ATA_R_REQUEUE 0x00000400 402#define ATA_R_THREAD 0x00000800 403#define ATA_R_DIRECT 0x00001000 404 405#define ATA_R_ATAPI16 0x00010000 406#define ATA_R_ATAPI_INTR 0x00020000 407 408#define ATA_R_DEBUG 0x10000000 409#define ATA_R_DANGER1 0x20000000 410#define ATA_R_DANGER2 0x40000000 411 412 struct ata_dmaslot dma; / DMA slot of this request / 413* u_int8_t status; /* ATA status / 414* u_int8_t error; /* ATA error / 415* u_int32_t donecount; /* bytes transferred / 416* int result; /* result error code / 417* void (callback)(struct ata_request request); 418 struct sema done; /* request done sema / 419* int retries; /* retry count / 420* int timeout; /* timeout for this cmd / 421* struct callout callout; /* callout management / 422* struct task task; /* task management / 423* struct bio bio; / bio for this request / 424* int this; /* this request ID / 425* struct ata_composite composite; / for composite atomic ops / 426* void driver; / driver specific / 427* TAILQ_ENTRY(ata_request) chain; /* list management / 428#ifdef ATA_CAM 429* union ccb ccb; 430#endif 431}; 432* 433/* define this for debugging request processing / 434#if 0 435#define ATA_DEBUG_RQ(request, string) \ 436* { \ 437 if (request->flags & ATA_R_DEBUG) \ 438 device_printf(request->parent, "req=%p %s " string "\n", \ 439 request, ata_cmd2str(request)); \ 440 } 441#else 442#define ATA_DEBUG_RQ(request, string) 443#endif 444 445 446/* structure describing an ATA/ATAPI device / 447struct ata_device { 448* device_t dev; /* device handle / 449* int unit; /* physical unit / 450#define ATA_MASTER 0x00 451#define ATA_SLAVE 0x01 452#define ATA_PM 0x0f 453* 454 struct ata_params param; /* ata param structure / 455* int mode; /* current transfermode / 456* u_int32_t max_iosize; /* max IO size / 457* int spindown; /* idle spindown timeout / 458* struct callout spindown_timer; 459 int spindown_state; 460 int flags; 461#define ATA_D_USE_CHS 0x0001 462#define ATA_D_MEDIA_CHANGED 0x0002 463#define ATA_D_ENC_PRESENT 0x0004 464}; 465 466/* structure for holding DMA Physical Region Descriptors (PRD) entries / 467struct ata_dma_prdentry { 468* u_int32_t addr; 469 u_int32_t count; 470}; 471 472/* structure used by the setprd function / 473struct ata_dmasetprd_args { 474* void dmatab; 475* int nsegs; 476 int error; 477}; 478 479struct ata_dmaslot { 480 u_int8_t status; /* DMA status / 481* bus_dma_tag_t sg_tag; /* SG list DMA tag / 482* bus_dmamap_t sg_map; /* SG list DMA map / 483* void sg; / DMA transfer table / 484* bus_addr_t sg_bus; /* bus address of dmatab / 485* bus_dma_tag_t data_tag; /* data DMA tag / 486* bus_dmamap_t data_map; /* data DMA map / 487}; 488* 489/* structure holding DMA related information / 490struct ata_dma { 491* bus_dma_tag_t dmatag; /* parent DMA tag / 492* bus_dma_tag_t work_tag; /* workspace DMA tag / 493* bus_dmamap_t work_map; /* workspace DMA map / 494* u_int8_t work; / workspace / 495* bus_addr_t work_bus; /* bus address of dmatab / 496* 497#define ATA_DMA_SLOTS 1 498 int dma_slots; /* DMA slots allocated / 499* struct ata_dmaslot slot[ATA_DMA_SLOTS]; 500 u_int32_t alignment; /* DMA SG list alignment / 501* u_int32_t boundary; /* DMA SG list boundary / 502* u_int32_t segsize; /* DMA SG list segment size / 503* u_int32_t max_iosize; /* DMA data max IO size / 504* u_int64_t max_address; /* highest DMA'able address / 505* int flags; 506#define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress / 507* 508 void (alloc)(device_t dev); 509* void (free)(device_t dev); 510* void (setprd)(void xsc, bus_dma_segment_t segs, int nsegs, int error); 511* int (load)(struct ata_request request, void addr, int nsegs); 512 int (unload)(struct ata_request request); 513 int (start)(struct ata_request request); 514 int (stop)(struct ata_request request); 515 void (reset)(device_t dev); 516}; 517* 518/* structure holding lowlevel functions / 519struct ata_lowlevel { 520* u_int32_t (softreset)(device_t dev, int pmport); 521* int (pm_read)(device_t dev, int port, int reg, u_int32_t result); 522 int (pm_write)(device_t dev, int port, int reg, u_int32_t value); 523* int (status)(device_t dev); 524* int (begin_transaction)(struct ata_request request); 525 int (end_transaction)(struct ata_request request); 526 int (command)(struct ata_request request); 527 void (tf_read)(struct ata_request request); 528 void (tf_write)(struct ata_request request); 529}; 530 531/* structure holding resources for an ATA channel / 532struct ata_resource { 533* struct resource res; 534* int offset; 535}; 536 537#ifdef ATA_CAM 538struct ata_cam_device { 539 u_int revision; 540 int mode; 541 u_int bytecount; 542}; 543#endif 544 545/* structure describing an ATA channel / 546struct ata_channel { 547* device_t dev; /* device handle / 548* int unit; /* physical channel / 549* int attached; /* channel is attached / 550* struct ata_resource r_io[ATA_MAX_RES];/* I/O resources / 551* struct resource r_irq; / interrupt of this channel / 552* void ih; / interrupt handle / 553* struct ata_lowlevel hw; /* lowlevel HW functions / 554* struct ata_dma dma; /* DMA data / functions / 555* int flags; /* channel flags / 556#define ATA_NO_SLAVE 0x01 557#define ATA_USE_16BIT 0x02 558#define ATA_ATAPI_DMA_RO 0x04 559#define ATA_NO_48BIT_DMA 0x08 560#define ATA_ALWAYS_DMASTAT 0x10 561#define ATA_CHECKS_CABLE 0x20 562#define ATA_NO_ATAPI_DMA 0x40 563#define ATA_SATA 0x80 564* 565 int pm_level; /* power management level / 566* int devices; /* what is present / 567#define ATA_ATA_MASTER 0x00000001 568#define ATA_ATA_SLAVE 0x00000002 569#define ATA_PORTMULTIPLIER 0x00008000 570#define ATA_ATAPI_MASTER 0x00010000 571#define ATA_ATAPI_SLAVE 0x00020000 572* 573 struct mtx state_mtx; /* state lock / 574* int state; /* ATA channel state / 575#define ATA_IDLE 0x0000 576#define ATA_ACTIVE 0x0001 577#define ATA_STALL_QUEUE 0x0002 578* 579 struct mtx queue_mtx; /* queue lock / 580* TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue / 581* struct ata_request freezepoint; / composite freezepoint / 582* struct ata_request running; / currently running request / 583* struct task conntask; /* PHY events handling task / 584#ifdef ATA_CAM 585* struct cam_sim sim; 586* struct cam_path path; 587* struct ata_cam_device user[16]; /* User-specified settings / 588* struct ata_cam_device curr[16]; /* Current settings / 589#endif 590}; 591* 592/* disk bay/enclosure related / 593#define ATA_LED_OFF 0x00 594#define ATA_LED_RED 0x01 595#define ATA_LED_GREEN 0x02 596#define ATA_LED_ORANGE 0x03 597#define ATA_LED_MASK 0x03 598* 599/* externs / 600extern int (ata_raid_ioctl_func)(u_long cmd, caddr_t data); 601extern struct intr_config_hook ata_delayed_attach; 602extern devclass_t ata_devclass; 603extern int ata_wc; 604extern int ata_setmax; 605extern int ata_dma_check_80pin; 606* 607/* public prototypes / 608/ ata-all.c: / 609int ata_probe(device_t dev); 610int ata_attach(device_t dev); 611int ata_detach(device_t dev); 612int ata_reinit(device_t dev); 613int ata_suspend(device_t dev); 614int ata_resume(device_t dev); 615void ata_interrupt(void data); 616int ata_device_ioctl(device_t dev, u_long cmd, caddr_t data); 617int ata_getparam(struct ata_device atadev, int init); 618int ata_identify(device_t dev); 619void ata_default_registers(device_t dev); 620void ata_modify_if_48bit(struct ata_request request); 621void ata_udelay(int interval); 622char ata_unit2str(struct ata_device atadev); 623const char ata_mode2str(int mode); 624const char ata_satarev2str(int rev);	27 / 28 29#if 0 30#define ATA_LEGACY_SUPPORT / Enable obsolete features that break 31 * some modern devices / 32#endif 33 34/ ATA register defines / 35#define ATA_DATA 0 / (RW) data / 36 37#define ATA_FEATURE 1 / (W) feature / 38#define ATA_F_DMA 0x01 / enable DMA / 39#define ATA_F_OVL 0x02 / enable overlap / 40 41#define ATA_COUNT 2 / (W) sector count / 42 43#define ATA_SECTOR 3 / (RW) sector # / 44#define ATA_CYL_LSB 4 / (RW) cylinder# LSB / 45#define ATA_CYL_MSB 5 / (RW) cylinder# MSB / 46#define ATA_DRIVE 6 / (W) Sector/Drive/Head / 47#define ATA_D_LBA 0x40 / use LBA addressing / 48#define ATA_D_IBM 0xa0 / 512 byte sectors, ECC / 49 50#define ATA_COMMAND 7 / (W) command / 51 52#define ATA_ERROR 8 / (R) error / 53#define ATA_E_ILI 0x01 / illegal length / 54#define ATA_E_NM 0x02 / no media / 55#define ATA_E_ABORT 0x04 / command aborted / 56#define ATA_E_MCR 0x08 / media change request / 57#define ATA_E_IDNF 0x10 / ID not found / 58#define ATA_E_MC 0x20 / media changed / 59#define ATA_E_UNC 0x40 / uncorrectable data / 60#define ATA_E_ICRC 0x80 / UDMA crc error / 61#define ATA_E_ATAPI_SENSE_MASK 0xf0 / ATAPI sense key mask / 62 63#define ATA_IREASON 9 / (R) interrupt reason / 64#define ATA_I_CMD 0x01 / cmd (1) \| data (0) / 65#define ATA_I_IN 0x02 / read (1) \| write (0) / 66#define ATA_I_RELEASE 0x04 / released bus (1) / 67#define ATA_I_TAGMASK 0xf8 / tag mask / 68 69#define ATA_STATUS 10 / (R) status / 70#define ATA_ALTSTAT 11 / (R) alternate status / 71#define ATA_S_ERROR 0x01 / error / 72#define ATA_S_INDEX 0x02 / index / 73#define ATA_S_CORR 0x04 / data corrected / 74#define ATA_S_DRQ 0x08 / data request / 75#define ATA_S_DSC 0x10 / drive seek completed / 76#define ATA_S_SERVICE 0x10 / drive needs service / 77#define ATA_S_DWF 0x20 / drive write fault / 78#define ATA_S_DMA 0x20 / DMA ready / 79#define ATA_S_READY 0x40 / drive ready / 80#define ATA_S_BUSY 0x80 / busy / 81 82#define ATA_CONTROL 12 / (W) control / 83 84#define ATA_CTLOFFSET 0x206 / control register offset / 85#define ATA_PCCARD_CTLOFFSET 0x0e / do for PCCARD devices / 86#define ATA_PC98_CTLOFFSET 0x10c / do for PC98 devices / 87#define ATA_A_IDS 0x02 / disable interrupts / 88#define ATA_A_RESET 0x04 / RESET controller / 89#ifdef ATA_LEGACY_SUPPORT 90#define ATA_A_4BIT 0x08 / 4 head bits: obsolete 1996 / 91#else 92#define ATA_A_4BIT 0x00 93#endif 94#define ATA_A_HOB 0x80 / High Order Byte enable / 95 96/ SATA register defines / 97#define ATA_SSTATUS 13 98#define ATA_SS_DET_MASK 0x0000000f 99#define ATA_SS_DET_NO_DEVICE 0x00000000 100#define ATA_SS_DET_DEV_PRESENT 0x00000001 101#define ATA_SS_DET_PHY_ONLINE 0x00000003 102#define ATA_SS_DET_PHY_OFFLINE 0x00000004 103* 104#define ATA_SS_SPD_MASK 0x000000f0 105#define ATA_SS_SPD_NO_SPEED 0x00000000 106#define ATA_SS_SPD_GEN1 0x00000010 107#define ATA_SS_SPD_GEN2 0x00000020 108 109#define ATA_SS_IPM_MASK 0x00000f00 110#define ATA_SS_IPM_NO_DEVICE 0x00000000 111#define ATA_SS_IPM_ACTIVE 0x00000100 112#define ATA_SS_IPM_PARTIAL 0x00000200 113#define ATA_SS_IPM_SLUMBER 0x00000600 114 115#define ATA_SS_CONWELL_MASK \ 116 (ATA_SS_DET_MASK\|ATA_SS_SPD_MASK\|ATA_SS_IPM_MASK) 117#define ATA_SS_CONWELL_GEN1 \ 118 (ATA_SS_DET_PHY_ONLINE\|ATA_SS_SPD_GEN1\|ATA_SS_IPM_ACTIVE) 119#define ATA_SS_CONWELL_GEN2 \ 120 (ATA_SS_DET_PHY_ONLINE\|ATA_SS_SPD_GEN2\|ATA_SS_IPM_ACTIVE) 121 122#define ATA_SERROR 14 123#define ATA_SE_DATA_CORRECTED 0x00000001 124#define ATA_SE_COMM_CORRECTED 0x00000002 125#define ATA_SE_DATA_ERR 0x00000100 126#define ATA_SE_COMM_ERR 0x00000200 127#define ATA_SE_PROT_ERR 0x00000400 128#define ATA_SE_HOST_ERR 0x00000800 129#define ATA_SE_PHY_CHANGED 0x00010000 130#define ATA_SE_PHY_IERROR 0x00020000 131#define ATA_SE_COMM_WAKE 0x00040000 132#define ATA_SE_DECODE_ERR 0x00080000 133#define ATA_SE_PARITY_ERR 0x00100000 134#define ATA_SE_CRC_ERR 0x00200000 135#define ATA_SE_HANDSHAKE_ERR 0x00400000 136#define ATA_SE_LINKSEQ_ERR 0x00800000 137#define ATA_SE_TRANSPORT_ERR 0x01000000 138#define ATA_SE_UNKNOWN_FIS 0x02000000 139 140#define ATA_SCONTROL 15 141#define ATA_SC_DET_MASK 0x0000000f 142#define ATA_SC_DET_IDLE 0x00000000 143#define ATA_SC_DET_RESET 0x00000001 144#define ATA_SC_DET_DISABLE 0x00000004 145 146#define ATA_SC_SPD_MASK 0x000000f0 147#define ATA_SC_SPD_NO_SPEED 0x00000000 148#define ATA_SC_SPD_SPEED_GEN1 0x00000010 149#define ATA_SC_SPD_SPEED_GEN2 0x00000020 150 151#define ATA_SC_IPM_MASK 0x00000f00 152#define ATA_SC_IPM_NONE 0x00000000 153#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 154#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 155 156#define ATA_SACTIVE 16 157 158/* SATA AHCI v1.0 register defines / 159#define ATA_AHCI_CAP 0x00 160#define ATA_AHCI_CAP_NPMASK 0x0000001f 161#define ATA_AHCI_CAP_SXS 0x00000020 162#define ATA_AHCI_CAP_EMS 0x00000040 163#define ATA_AHCI_CAP_CCCS 0x00000080 164#define ATA_AHCI_CAP_NCS 0x00001F00 165#define ATA_AHCI_CAP_NCS_SHIFT 8 166#define ATA_AHCI_CAP_PSC 0x00002000 167#define ATA_AHCI_CAP_SSC 0x00004000 168#define ATA_AHCI_CAP_PMD 0x00008000 169#define ATA_AHCI_CAP_FBSS 0x00010000 170#define ATA_AHCI_CAP_SPM 0x00020000 171#define ATA_AHCI_CAP_SAM 0x00080000 172#define ATA_AHCI_CAP_ISS 0x00F00000 173#define ATA_AHCI_CAP_ISS_SHIFT 20 174#define ATA_AHCI_CAP_SCLO 0x01000000 175#define ATA_AHCI_CAP_SAL 0x02000000 176#define ATA_AHCI_CAP_SALP 0x04000000 177#define ATA_AHCI_CAP_SSS 0x08000000 178#define ATA_AHCI_CAP_SMPS 0x10000000 179#define ATA_AHCI_CAP_SSNTF 0x20000000 180#define ATA_AHCI_CAP_SNCQ 0x40000000 181#define ATA_AHCI_CAP_64BIT 0x80000000 182* 183#define ATA_AHCI_GHC 0x04 184#define ATA_AHCI_GHC_AE 0x80000000 185#define ATA_AHCI_GHC_IE 0x00000002 186#define ATA_AHCI_GHC_HR 0x00000001 187 188#define ATA_AHCI_IS 0x08 189#define ATA_AHCI_PI 0x0c 190#define ATA_AHCI_VS 0x10 191 192#define ATA_AHCI_OFFSET 0x80 193 194#define ATA_AHCI_P_CLB 0x100 195#define ATA_AHCI_P_CLBU 0x104 196#define ATA_AHCI_P_FB 0x108 197#define ATA_AHCI_P_FBU 0x10c 198#define ATA_AHCI_P_IS 0x110 199#define ATA_AHCI_P_IE 0x114 200#define ATA_AHCI_P_IX_DHR 0x00000001 201#define ATA_AHCI_P_IX_PS 0x00000002 202#define ATA_AHCI_P_IX_DS 0x00000004 203#define ATA_AHCI_P_IX_SDB 0x00000008 204#define ATA_AHCI_P_IX_UF 0x00000010 205#define ATA_AHCI_P_IX_DP 0x00000020 206#define ATA_AHCI_P_IX_PC 0x00000040 207#define ATA_AHCI_P_IX_DI 0x00000080 208 209#define ATA_AHCI_P_IX_PRC 0x00400000 210#define ATA_AHCI_P_IX_IPM 0x00800000 211#define ATA_AHCI_P_IX_OF 0x01000000 212#define ATA_AHCI_P_IX_INF 0x04000000 213#define ATA_AHCI_P_IX_IF 0x08000000 214#define ATA_AHCI_P_IX_HBD 0x10000000 215#define ATA_AHCI_P_IX_HBF 0x20000000 216#define ATA_AHCI_P_IX_TFE 0x40000000 217#define ATA_AHCI_P_IX_CPD 0x80000000 218 219#define ATA_AHCI_P_CMD 0x118 220#define ATA_AHCI_P_CMD_ST 0x00000001 221#define ATA_AHCI_P_CMD_SUD 0x00000002 222#define ATA_AHCI_P_CMD_POD 0x00000004 223#define ATA_AHCI_P_CMD_CLO 0x00000008 224#define ATA_AHCI_P_CMD_FRE 0x00000010 225#define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00 226#define ATA_AHCI_P_CMD_ISS 0x00002000 227#define ATA_AHCI_P_CMD_FR 0x00004000 228#define ATA_AHCI_P_CMD_CR 0x00008000 229#define ATA_AHCI_P_CMD_CPS 0x00010000 230#define ATA_AHCI_P_CMD_PMA 0x00020000 231#define ATA_AHCI_P_CMD_HPCP 0x00040000 232#define ATA_AHCI_P_CMD_ISP 0x00080000 233#define ATA_AHCI_P_CMD_CPD 0x00100000 234#define ATA_AHCI_P_CMD_ATAPI 0x01000000 235#define ATA_AHCI_P_CMD_DLAE 0x02000000 236#define ATA_AHCI_P_CMD_ALPE 0x04000000 237#define ATA_AHCI_P_CMD_ASP 0x08000000 238#define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000 239#define ATA_AHCI_P_CMD_NOOP 0x00000000 240#define ATA_AHCI_P_CMD_ACTIVE 0x10000000 241#define ATA_AHCI_P_CMD_PARTIAL 0x20000000 242#define ATA_AHCI_P_CMD_SLUMBER 0x60000000 243 244#define ATA_AHCI_P_TFD 0x120 245#define ATA_AHCI_P_SIG 0x124 246#define ATA_AHCI_P_SSTS 0x128 247#define ATA_AHCI_P_SCTL 0x12c 248#define ATA_AHCI_P_SERR 0x130 249#define ATA_AHCI_P_SACT 0x134 250#define ATA_AHCI_P_CI 0x138 251#define ATA_AHCI_P_SNTF 0x13C 252#define ATA_AHCI_P_FBS 0x140 253 254#define ATA_AHCI_CL_SIZE 32 255#define ATA_AHCI_CL_OFFSET 0 256#define ATA_AHCI_FB_OFFSET (ATA_AHCI_CL_SIZE * 32) 257#define ATA_AHCI_CT_OFFSET (ATA_AHCI_FB_OFFSET + 4096) 258#define ATA_AHCI_CT_SIZE (2176 + 128) 259 260struct ata_ahci_dma_prd { 261 u_int64_t dba; 262 u_int32_t reserved; 263 u_int32_t dbc; /* 0 based / 264#define ATA_AHCI_PRD_MASK 0x003fffff / max 4MB / 265#define ATA_AHCI_PRD_IPC (1<<31) 266} __packed; 267* 268struct ata_ahci_cmd_tab { 269 u_int8_t cfis[64]; 270 u_int8_t acmd[32]; 271 u_int8_t reserved[32]; 272#define ATA_AHCI_DMA_ENTRIES 129 273 struct ata_ahci_dma_prd prd_tab[ATA_AHCI_DMA_ENTRIES]; 274} __packed; 275 276struct ata_ahci_cmd_list { 277 u_int16_t cmd_flags; 278#define ATA_AHCI_CMD_ATAPI 0x0020 279#define ATA_AHCI_CMD_WRITE 0x0040 280#define ATA_AHCI_CMD_PREFETCH 0x0080 281#define ATA_AHCI_CMD_RESET 0x0100 282#define ATA_AHCI_CMD_BIST 0x0200 283#define ATA_AHCI_CMD_CLR_BUSY 0x0400 284 285 u_int16_t prd_length; /* PRD entries / 286* u_int32_t bytecount; 287 u_int64_t cmd_table_phys; /* 128byte aligned / 288} __packed; 289* 290 291/* DMA register defines / 292#define ATA_DMA_ENTRIES 256 293#define ATA_DMA_EOT 0x80000000 294* 295#define ATA_BMCMD_PORT 17 296#define ATA_BMCMD_START_STOP 0x01 297#define ATA_BMCMD_WRITE_READ 0x08 298 299#define ATA_BMDEVSPEC_0 18 300#define ATA_BMSTAT_PORT 19 301#define ATA_BMSTAT_ACTIVE 0x01 302#define ATA_BMSTAT_ERROR 0x02 303#define ATA_BMSTAT_INTERRUPT 0x04 304#define ATA_BMSTAT_MASK 0x07 305#define ATA_BMSTAT_DMA_MASTER 0x20 306#define ATA_BMSTAT_DMA_SLAVE 0x40 307#define ATA_BMSTAT_DMA_SIMPLEX 0x80 308 309#define ATA_BMDEVSPEC_1 20 310#define ATA_BMDTP_PORT 21 311 312#define ATA_IDX_ADDR 22 313#define ATA_IDX_DATA 23 314#define ATA_MAX_RES 24 315 316/* misc defines / 317#define ATA_PRIMARY 0x1f0 318#define ATA_SECONDARY 0x170 319#define ATA_PC98_BANK 0x432 320#define ATA_IOSIZE 0x08 321#define ATA_PC98_IOSIZE 0x10 322#define ATA_CTLIOSIZE 0x01 323#define ATA_BMIOSIZE 0x08 324#define ATA_PC98_BANKIOSIZE 0x01 325#define ATA_IOADDR_RID 0 326#define ATA_CTLADDR_RID 1 327#define ATA_BMADDR_RID 0x20 328#define ATA_PC98_CTLADDR_RID 8 329#define ATA_PC98_BANKADDR_RID 9 330#define ATA_IRQ_RID 0 331#define ATA_DEV(unit) ((unit > 0) ? 0x10 : 0) 332#define ATA_CFA_MAGIC1 0x844A 333#define ATA_CFA_MAGIC2 0x848A 334#define ATA_CFA_MAGIC3 0x8400 335#define ATAPI_MAGIC_LSB 0x14 336#define ATAPI_MAGIC_MSB 0xeb 337#define ATAPI_P_READ (ATA_S_DRQ \| ATA_I_IN) 338#define ATAPI_P_WRITE (ATA_S_DRQ) 339#define ATAPI_P_CMDOUT (ATA_S_DRQ \| ATA_I_CMD) 340#define ATAPI_P_DONEDRQ (ATA_S_DRQ \| ATA_I_CMD \| ATA_I_IN) 341#define ATAPI_P_DONE (ATA_I_CMD \| ATA_I_IN) 342#define ATAPI_P_ABORT 0 343#define ATA_INTR_FLAGS (INTR_MPSAFE\|INTR_TYPE_BIO\|INTR_ENTROPY) 344#define ATA_OP_CONTINUES 0 345#define ATA_OP_FINISHED 1 346#define ATA_MAX_28BIT_LBA 268435455UL 347* 348#ifndef ATA_REQUEST_TIMEOUT 349#define ATA_REQUEST_TIMEOUT 10 350#endif 351 352/* structure used for composite atomic operations / 353#define MAX_COMPOSITES 32 / u_int32_t bits / 354struct ata_composite { 355* struct mtx lock; /* control lock / 356* u_int32_t rd_needed; /* needed read subdisks / 357* u_int32_t rd_done; /* done read subdisks / 358* u_int32_t wr_needed; /* needed write subdisks / 359* u_int32_t wr_depend; /* write depends on subdisks / 360* u_int32_t wr_done; /* done write subdisks / 361* struct ata_request request[MAX_COMPOSITES]; 362* u_int32_t residual; /* bytes still to transfer / 363* caddr_t data_1; 364 caddr_t data_2; 365}; 366 367/* structure used to queue an ATA/ATAPI request / 368struct ata_request { 369* device_t dev; /* device handle / 370* device_t parent; /* channel handle / 371* int unit; /* physical unit / 372* union { 373 struct { 374 u_int8_t command; /* command reg / 375* u_int16_t feature; /* feature reg / 376* u_int16_t count; /* count reg / 377* u_int64_t lba; /* lba reg / 378* } ata; 379 struct { 380 u_int8_t ccb[16]; /* ATAPI command block / 381* struct atapi_sense sense; /* ATAPI request sense data / 382* u_int8_t saved_cmd; /* ATAPI saved command / 383* } atapi; 384 } u; 385 u_int32_t bytecount; /* bytes to transfer / 386* u_int32_t transfersize; /* bytes pr transfer / 387* caddr_t data; /* pointer to data buf / 388* u_int32_t tag; /* HW tag of this request / 389* int flags; 390#define ATA_R_CONTROL 0x00000001 391#define ATA_R_READ 0x00000002 392#define ATA_R_WRITE 0x00000004 393#define ATA_R_ATAPI 0x00000008 394#define ATA_R_DMA 0x00000010 395#define ATA_R_QUIET 0x00000020 396#define ATA_R_TIMEOUT 0x00000040 397#define ATA_R_48BIT 0x00000080 398 399#define ATA_R_ORDERED 0x00000100 400#define ATA_R_AT_HEAD 0x00000200 401#define ATA_R_REQUEUE 0x00000400 402#define ATA_R_THREAD 0x00000800 403#define ATA_R_DIRECT 0x00001000 404 405#define ATA_R_ATAPI16 0x00010000 406#define ATA_R_ATAPI_INTR 0x00020000 407 408#define ATA_R_DEBUG 0x10000000 409#define ATA_R_DANGER1 0x20000000 410#define ATA_R_DANGER2 0x40000000 411 412 struct ata_dmaslot dma; / DMA slot of this request / 413* u_int8_t status; /* ATA status / 414* u_int8_t error; /* ATA error / 415* u_int32_t donecount; /* bytes transferred / 416* int result; /* result error code / 417* void (callback)(struct ata_request request); 418 struct sema done; /* request done sema / 419* int retries; /* retry count / 420* int timeout; /* timeout for this cmd / 421* struct callout callout; /* callout management / 422* struct task task; /* task management / 423* struct bio bio; / bio for this request / 424* int this; /* this request ID / 425* struct ata_composite composite; / for composite atomic ops / 426* void driver; / driver specific / 427* TAILQ_ENTRY(ata_request) chain; /* list management / 428#ifdef ATA_CAM 429* union ccb ccb; 430#endif 431}; 432* 433/* define this for debugging request processing / 434#if 0 435#define ATA_DEBUG_RQ(request, string) \ 436* { \ 437 if (request->flags & ATA_R_DEBUG) \ 438 device_printf(request->parent, "req=%p %s " string "\n", \ 439 request, ata_cmd2str(request)); \ 440 } 441#else 442#define ATA_DEBUG_RQ(request, string) 443#endif 444 445 446/* structure describing an ATA/ATAPI device / 447struct ata_device { 448* device_t dev; /* device handle / 449* int unit; /* physical unit / 450#define ATA_MASTER 0x00 451#define ATA_SLAVE 0x01 452#define ATA_PM 0x0f 453* 454 struct ata_params param; /* ata param structure / 455* int mode; /* current transfermode / 456* u_int32_t max_iosize; /* max IO size / 457* int spindown; /* idle spindown timeout / 458* struct callout spindown_timer; 459 int spindown_state; 460 int flags; 461#define ATA_D_USE_CHS 0x0001 462#define ATA_D_MEDIA_CHANGED 0x0002 463#define ATA_D_ENC_PRESENT 0x0004 464}; 465 466/* structure for holding DMA Physical Region Descriptors (PRD) entries / 467struct ata_dma_prdentry { 468* u_int32_t addr; 469 u_int32_t count; 470}; 471 472/* structure used by the setprd function / 473struct ata_dmasetprd_args { 474* void dmatab; 475* int nsegs; 476 int error; 477}; 478 479struct ata_dmaslot { 480 u_int8_t status; /* DMA status / 481* bus_dma_tag_t sg_tag; /* SG list DMA tag / 482* bus_dmamap_t sg_map; /* SG list DMA map / 483* void sg; / DMA transfer table / 484* bus_addr_t sg_bus; /* bus address of dmatab / 485* bus_dma_tag_t data_tag; /* data DMA tag / 486* bus_dmamap_t data_map; /* data DMA map / 487}; 488* 489/* structure holding DMA related information / 490struct ata_dma { 491* bus_dma_tag_t dmatag; /* parent DMA tag / 492* bus_dma_tag_t work_tag; /* workspace DMA tag / 493* bus_dmamap_t work_map; /* workspace DMA map / 494* u_int8_t work; / workspace / 495* bus_addr_t work_bus; /* bus address of dmatab / 496* 497#define ATA_DMA_SLOTS 1 498 int dma_slots; /* DMA slots allocated / 499* struct ata_dmaslot slot[ATA_DMA_SLOTS]; 500 u_int32_t alignment; /* DMA SG list alignment / 501* u_int32_t boundary; /* DMA SG list boundary / 502* u_int32_t segsize; /* DMA SG list segment size / 503* u_int32_t max_iosize; /* DMA data max IO size / 504* u_int64_t max_address; /* highest DMA'able address / 505* int flags; 506#define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress / 507* 508 void (alloc)(device_t dev); 509* void (free)(device_t dev); 510* void (setprd)(void xsc, bus_dma_segment_t segs, int nsegs, int error); 511* int (load)(struct ata_request request, void addr, int nsegs); 512 int (unload)(struct ata_request request); 513 int (start)(struct ata_request request); 514 int (stop)(struct ata_request request); 515 void (reset)(device_t dev); 516}; 517* 518/* structure holding lowlevel functions / 519struct ata_lowlevel { 520* u_int32_t (softreset)(device_t dev, int pmport); 521* int (pm_read)(device_t dev, int port, int reg, u_int32_t result); 522 int (pm_write)(device_t dev, int port, int reg, u_int32_t value); 523* int (status)(device_t dev); 524* int (begin_transaction)(struct ata_request request); 525 int (end_transaction)(struct ata_request request); 526 int (command)(struct ata_request request); 527 void (tf_read)(struct ata_request request); 528 void (tf_write)(struct ata_request request); 529}; 530 531/* structure holding resources for an ATA channel / 532struct ata_resource { 533* struct resource res; 534* int offset; 535}; 536 537#ifdef ATA_CAM 538struct ata_cam_device { 539 u_int revision; 540 int mode; 541 u_int bytecount; 542}; 543#endif 544 545/* structure describing an ATA channel / 546struct ata_channel { 547* device_t dev; /* device handle / 548* int unit; /* physical channel / 549* int attached; /* channel is attached / 550* struct ata_resource r_io[ATA_MAX_RES];/* I/O resources / 551* struct resource r_irq; / interrupt of this channel / 552* void ih; / interrupt handle / 553* struct ata_lowlevel hw; /* lowlevel HW functions / 554* struct ata_dma dma; /* DMA data / functions / 555* int flags; /* channel flags / 556#define ATA_NO_SLAVE 0x01 557#define ATA_USE_16BIT 0x02 558#define ATA_ATAPI_DMA_RO 0x04 559#define ATA_NO_48BIT_DMA 0x08 560#define ATA_ALWAYS_DMASTAT 0x10 561#define ATA_CHECKS_CABLE 0x20 562#define ATA_NO_ATAPI_DMA 0x40 563#define ATA_SATA 0x80 564* 565 int pm_level; /* power management level / 566* int devices; /* what is present / 567#define ATA_ATA_MASTER 0x00000001 568#define ATA_ATA_SLAVE 0x00000002 569#define ATA_PORTMULTIPLIER 0x00008000 570#define ATA_ATAPI_MASTER 0x00010000 571#define ATA_ATAPI_SLAVE 0x00020000 572* 573 struct mtx state_mtx; /* state lock / 574* int state; /* ATA channel state / 575#define ATA_IDLE 0x0000 576#define ATA_ACTIVE 0x0001 577#define ATA_STALL_QUEUE 0x0002 578* 579 struct mtx queue_mtx; /* queue lock / 580* TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue / 581* struct ata_request freezepoint; / composite freezepoint / 582* struct ata_request running; / currently running request / 583* struct task conntask; /* PHY events handling task / 584#ifdef ATA_CAM 585* struct cam_sim sim; 586* struct cam_path path; 587* struct ata_cam_device user[16]; /* User-specified settings / 588* struct ata_cam_device curr[16]; /* Current settings / 589#endif 590}; 591* 592/* disk bay/enclosure related / 593#define ATA_LED_OFF 0x00 594#define ATA_LED_RED 0x01 595#define ATA_LED_GREEN 0x02 596#define ATA_LED_ORANGE 0x03 597#define ATA_LED_MASK 0x03 598* 599/* externs / 600extern int (ata_raid_ioctl_func)(u_long cmd, caddr_t data); 601extern struct intr_config_hook ata_delayed_attach; 602extern devclass_t ata_devclass; 603extern int ata_wc; 604extern int ata_setmax; 605extern int ata_dma_check_80pin; 606* 607/* public prototypes / 608/ ata-all.c: / 609int ata_probe(device_t dev); 610int ata_attach(device_t dev); 611int ata_detach(device_t dev); 612int ata_reinit(device_t dev); 613int ata_suspend(device_t dev); 614int ata_resume(device_t dev); 615void ata_interrupt(void data); 616int ata_device_ioctl(device_t dev, u_long cmd, caddr_t data); 617int ata_getparam(struct ata_device atadev, int init); 618int ata_identify(device_t dev); 619void ata_default_registers(device_t dev); 620void ata_modify_if_48bit(struct ata_request request); 621void ata_udelay(int interval); 622char ata_unit2str(struct ata_device atadev); 623const char ata_mode2str(int mode); 624const char ata_satarev2str(int rev);
625int ata_atapi(device_t dev);	625int ata_atapi(device_t dev, int target);
626int ata_pmode(struct ata_params ap); 627int ata_wmode(struct ata_params ap); 628int ata_umode(struct ata_params ap); 629int ata_limit_mode(device_t dev, int mode, int maxmode); 630void ata_setmode(device_t dev); 631void ata_print_cable(device_t dev, u_int8_t who); 632int ata_check_80pin(device_t dev, int mode); 633#ifdef ATA_CAM 634void ata_cam_begin_transaction(device_t dev, union ccb ccb); 635void ata_cam_end_transaction(device_t dev, struct ata_request request); 636#endif 637 638/* ata-queue.c: / 639int ata_controlcmd(device_t dev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count); 640int ata_atapicmd(device_t dev, u_int8_t ccb, caddr_t data, int count, int flags, int timeout); 641void ata_queue_request(struct ata_request request); 642void ata_start(device_t dev); 643void ata_finish(struct ata_request request); 644void ata_timeout(struct ata_request ); 645void ata_catch_inflight(device_t dev); 646void ata_fail_requests(device_t dev); 647void ata_drop_requests(device_t dev); 648char ata_cmd2str(struct ata_request request); 649* 650/* ata-lowlevel.c: / 651void ata_generic_hw(device_t dev); 652int ata_begin_transaction(struct ata_request ); 653int ata_end_transaction(struct ata_request ); 654void ata_generic_reset(device_t dev); 655int ata_generic_command(struct ata_request request); 656 657/* ata-dma.c: / 658void ata_dmainit(device_t); 659void ata_dmafini(device_t dev); 660* 661/* ata-sata.c: / 662void ata_sata_phy_check_events(device_t dev); 663int ata_sata_scr_read(struct ata_channel ch, int port, int reg, uint32_t val); 664int ata_sata_scr_write(struct ata_channel ch, int port, int reg, uint32_t val); 665int ata_sata_phy_reset(device_t dev, int port, int quick); 666int ata_sata_setmode(device_t dev, int target, int mode); 667int ata_sata_getrev(device_t dev, int target); 668int ata_request2fis_h2d(struct ata_request request, u_int8_t fis); 669void ata_pm_identify(device_t dev); 670 671/* macros for alloc/free of struct ata_request / 672extern uma_zone_t ata_request_zone; 673#define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT \| M_ZERO) 674#define ata_free_request(request) { \ 675* if (!(request->flags & ATA_R_DANGER2)) \ 676 uma_zfree(ata_request_zone, request); \ 677 } 678 679/* macros for alloc/free of struct ata_composite / 680extern uma_zone_t ata_composite_zone; 681#define ata_alloc_composite() uma_zalloc(ata_composite_zone, M_NOWAIT \| M_ZERO) 682#define ata_free_composite(composite) uma_zfree(ata_composite_zone, composite) 683* 684MALLOC_DECLARE(M_ATA); 685 686/* misc newbus defines / 687#define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 688* 689/* macros to hide busspace uglyness / 690#define ATA_INB(res, offset) \ 691* bus_read_1((res), (offset)) 692 693#define ATA_INW(res, offset) \ 694 bus_read_2((res), (offset)) 695#define ATA_INL(res, offset) \ 696 bus_read_4((res), (offset)) 697#define ATA_INSW(res, offset, addr, count) \ 698 bus_read_multi_2((res), (offset), (addr), (count)) 699#define ATA_INSW_STRM(res, offset, addr, count) \ 700 bus_read_multi_stream_2((res), (offset), (addr), (count)) 701#define ATA_INSL(res, offset, addr, count) \ 702 bus_read_multi_4((res), (offset), (addr), (count)) 703#define ATA_INSL_STRM(res, offset, addr, count) \ 704 bus_read_multi_stream_4((res), (offset), (addr), (count)) 705#define ATA_OUTB(res, offset, value) \ 706 bus_write_1((res), (offset), (value)) 707#define ATA_OUTW(res, offset, value) \ 708 bus_write_2((res), (offset), (value)) 709#define ATA_OUTL(res, offset, value) \ 710 bus_write_4((res), (offset), (value)) 711#define ATA_OUTSW(res, offset, addr, count) \ 712 bus_write_multi_2((res), (offset), (addr), (count)) 713#define ATA_OUTSW_STRM(res, offset, addr, count) \ 714 bus_write_multi_stream_2((res), (offset), (addr), (count)) 715#define ATA_OUTSL(res, offset, addr, count) \ 716 bus_write_multi_4((res), (offset), (addr), (count)) 717#define ATA_OUTSL_STRM(res, offset, addr, count) \ 718 bus_write_multi_stream_4((res), (offset), (addr), (count)) 719 720#define ATA_IDX_INB(ch, idx) \ 721 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) 722 723#define ATA_IDX_INW(ch, idx) \ 724 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) 725 726#define ATA_IDX_INL(ch, idx) \ 727 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) 728 729#define ATA_IDX_INSW(ch, idx, addr, count) \ 730 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 731 732#define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 733 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 734 735#define ATA_IDX_INSL(ch, idx, addr, count) \ 736 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 737 738#define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 739 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 740 741#define ATA_IDX_OUTB(ch, idx, value) \ 742 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) 743 744#define ATA_IDX_OUTW(ch, idx, value) \ 745 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) 746 747#define ATA_IDX_OUTL(ch, idx, value) \ 748 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) 749 750#define ATA_IDX_OUTSW(ch, idx, addr, count) \ 751 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 752 753#define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 754 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 755 756#define ATA_IDX_OUTSL(ch, idx, addr, count) \ 757 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 758 759#define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 760 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)	626int ata_pmode(struct ata_params ap); 627int ata_wmode(struct ata_params ap); 628int ata_umode(struct ata_params ap); 629int ata_limit_mode(device_t dev, int mode, int maxmode); 630void ata_setmode(device_t dev); 631void ata_print_cable(device_t dev, u_int8_t who); 632int ata_check_80pin(device_t dev, int mode); 633#ifdef ATA_CAM 634void ata_cam_begin_transaction(device_t dev, union ccb ccb); 635void ata_cam_end_transaction(device_t dev, struct ata_request request); 636#endif 637 638/* ata-queue.c: / 639int ata_controlcmd(device_t dev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count); 640int ata_atapicmd(device_t dev, u_int8_t ccb, caddr_t data, int count, int flags, int timeout); 641void ata_queue_request(struct ata_request request); 642void ata_start(device_t dev); 643void ata_finish(struct ata_request request); 644void ata_timeout(struct ata_request ); 645void ata_catch_inflight(device_t dev); 646void ata_fail_requests(device_t dev); 647void ata_drop_requests(device_t dev); 648char ata_cmd2str(struct ata_request request); 649* 650/* ata-lowlevel.c: / 651void ata_generic_hw(device_t dev); 652int ata_begin_transaction(struct ata_request ); 653int ata_end_transaction(struct ata_request ); 654void ata_generic_reset(device_t dev); 655int ata_generic_command(struct ata_request request); 656 657/* ata-dma.c: / 658void ata_dmainit(device_t); 659void ata_dmafini(device_t dev); 660* 661/* ata-sata.c: / 662void ata_sata_phy_check_events(device_t dev); 663int ata_sata_scr_read(struct ata_channel ch, int port, int reg, uint32_t val); 664int ata_sata_scr_write(struct ata_channel ch, int port, int reg, uint32_t val); 665int ata_sata_phy_reset(device_t dev, int port, int quick); 666int ata_sata_setmode(device_t dev, int target, int mode); 667int ata_sata_getrev(device_t dev, int target); 668int ata_request2fis_h2d(struct ata_request request, u_int8_t fis); 669void ata_pm_identify(device_t dev); 670 671/* macros for alloc/free of struct ata_request / 672extern uma_zone_t ata_request_zone; 673#define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT \| M_ZERO) 674#define ata_free_request(request) { \ 675* if (!(request->flags & ATA_R_DANGER2)) \ 676 uma_zfree(ata_request_zone, request); \ 677 } 678 679/* macros for alloc/free of struct ata_composite / 680extern uma_zone_t ata_composite_zone; 681#define ata_alloc_composite() uma_zalloc(ata_composite_zone, M_NOWAIT \| M_ZERO) 682#define ata_free_composite(composite) uma_zfree(ata_composite_zone, composite) 683* 684MALLOC_DECLARE(M_ATA); 685 686/* misc newbus defines / 687#define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 688* 689/* macros to hide busspace uglyness / 690#define ATA_INB(res, offset) \ 691* bus_read_1((res), (offset)) 692 693#define ATA_INW(res, offset) \ 694 bus_read_2((res), (offset)) 695#define ATA_INL(res, offset) \ 696 bus_read_4((res), (offset)) 697#define ATA_INSW(res, offset, addr, count) \ 698 bus_read_multi_2((res), (offset), (addr), (count)) 699#define ATA_INSW_STRM(res, offset, addr, count) \ 700 bus_read_multi_stream_2((res), (offset), (addr), (count)) 701#define ATA_INSL(res, offset, addr, count) \ 702 bus_read_multi_4((res), (offset), (addr), (count)) 703#define ATA_INSL_STRM(res, offset, addr, count) \ 704 bus_read_multi_stream_4((res), (offset), (addr), (count)) 705#define ATA_OUTB(res, offset, value) \ 706 bus_write_1((res), (offset), (value)) 707#define ATA_OUTW(res, offset, value) \ 708 bus_write_2((res), (offset), (value)) 709#define ATA_OUTL(res, offset, value) \ 710 bus_write_4((res), (offset), (value)) 711#define ATA_OUTSW(res, offset, addr, count) \ 712 bus_write_multi_2((res), (offset), (addr), (count)) 713#define ATA_OUTSW_STRM(res, offset, addr, count) \ 714 bus_write_multi_stream_2((res), (offset), (addr), (count)) 715#define ATA_OUTSL(res, offset, addr, count) \ 716 bus_write_multi_4((res), (offset), (addr), (count)) 717#define ATA_OUTSL_STRM(res, offset, addr, count) \ 718 bus_write_multi_stream_4((res), (offset), (addr), (count)) 719 720#define ATA_IDX_INB(ch, idx) \ 721 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) 722 723#define ATA_IDX_INW(ch, idx) \ 724 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) 725 726#define ATA_IDX_INL(ch, idx) \ 727 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) 728 729#define ATA_IDX_INSW(ch, idx, addr, count) \ 730 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 731 732#define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 733 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 734 735#define ATA_IDX_INSL(ch, idx, addr, count) \ 736 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 737 738#define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 739 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 740 741#define ATA_IDX_OUTB(ch, idx, value) \ 742 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) 743 744#define ATA_IDX_OUTW(ch, idx, value) \ 745 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) 746 747#define ATA_IDX_OUTL(ch, idx, value) \ 748 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) 749 750#define ATA_IDX_OUTSW(ch, idx, addr, count) \ 751 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 752 753#define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 754 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 755 756#define ATA_IDX_OUTSL(ch, idx, addr, count) \ 757 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 758 759#define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 760 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)