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ata-all.c (52918) ata-all.c (53029)
1/*-
2 * Copyright (c) 1998,1999 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
1/*-
2 * Copyright (c) 1998,1999 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: head/sys/dev/ata/ata-all.c 52918 1999-11-06 16:50:21Z sos $
28 * $FreeBSD: head/sys/dev/ata/ata-all.c 53029 1999-11-08 21:36:00Z sos $
29 */
30
31#include "ata.h"
32#include "apm.h"
33#include "isa.h"
34#include "pci.h"
35#include "atadisk.h"
36#include "atapicd.h"

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69#include <dev/ata/ata-all.h>
70#include <dev/ata/ata-disk.h>
71#include <dev/ata/atapi-all.h>
72
73/* misc defines */
74#if SMP == 0
75#define isa_apic_irq(x) x
76#endif
29 */
30
31#include "ata.h"
32#include "apm.h"
33#include "isa.h"
34#include "pci.h"
35#include "atadisk.h"
36#include "atapicd.h"

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69#include <dev/ata/ata-all.h>
70#include <dev/ata/ata-disk.h>
71#include <dev/ata/atapi-all.h>
72
73/* misc defines */
74#if SMP == 0
75#define isa_apic_irq(x) x
76#endif
77#define IOMASK 0xfffffffc /* XXX SOS 0xfffc */
77
78/* prototypes */
79static int32_t ata_probe(int32_t, int32_t, int32_t, device_t, int32_t *);
80static void ataintr(void *);
81static int8_t *active2str(int32_t);
82
83/* local vars */
84static int32_t atanlun = 2;

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258#endif
259
260 if (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) {
261 iobase_1 = IO_WD1;
262 altiobase_1 = iobase_1 + ATA_ALTPORT;
263 irq1 = 14;
264 }
265 else {
78
79/* prototypes */
80static int32_t ata_probe(int32_t, int32_t, int32_t, device_t, int32_t *);
81static void ataintr(void *);
82static int8_t *active2str(int32_t);
83
84/* local vars */
85static int32_t atanlun = 2;

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259#endif
260
261 if (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) {
262 iobase_1 = IO_WD1;
263 altiobase_1 = iobase_1 + ATA_ALTPORT;
264 irq1 = 14;
265 }
266 else {
266 iobase_1 = pci_read_config(dev, 0x10, 4) & 0xfffc;
267 altiobase_1 = pci_read_config(dev, 0x14, 4) & 0xfffc;
268 bmaddr_1 = pci_read_config(dev, 0x20, 4) & 0xfffc;
267 iobase_1 = pci_read_config(dev, 0x10, 4) & IOMASK;
268 altiobase_1 = pci_read_config(dev, 0x14, 4) & IOMASK;
269 bmaddr_1 = pci_read_config(dev, 0x20, 4) & IOMASK;
269 irq1 = pci_read_config(dev, PCI_INTERRUPT_REG, 4) & 0xff;
270 }
271
272 if (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) {
273 iobase_2 = IO_WD2;
274 altiobase_2 = iobase_2 + ATA_ALTPORT;
275 irq2 = 15;
276 }
277 else {
270 irq1 = pci_read_config(dev, PCI_INTERRUPT_REG, 4) & 0xff;
271 }
272
273 if (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) {
274 iobase_2 = IO_WD2;
275 altiobase_2 = iobase_2 + ATA_ALTPORT;
276 irq2 = 15;
277 }
278 else {
278 iobase_2 = pci_read_config(dev, 0x18, 4) & 0xfffc;
279 altiobase_2 = pci_read_config(dev, 0x1c, 4) & 0xfffc;
280 bmaddr_2 = (pci_read_config(dev, 0x20, 4) & 0xfffc) + ATA_BM_OFFSET1;
279 iobase_2 = pci_read_config(dev, 0x18, 4) & IOMASK;
280 altiobase_2 = pci_read_config(dev, 0x1c, 4) & IOMASK;
281 bmaddr_2 = (pci_read_config(dev, 0x20, 4) & IOMASK) + ATA_BM_OFFSET1;
281 irq2 = pci_read_config(dev, PCI_INTERRUPT_REG, 4) & 0xff;
282 }
283
284 /* is this controller busmaster DMA capable ? */
285 if (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) {
286 /* is busmastering support turned on ? */
287 if ((pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4) & 5) == 5) {
288 /* is there a valid port range to connect to ? */
282 irq2 = pci_read_config(dev, PCI_INTERRUPT_REG, 4) & 0xff;
283 }
284
285 /* is this controller busmaster DMA capable ? */
286 if (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) {
287 /* is busmastering support turned on ? */
288 if ((pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4) & 5) == 5) {
289 /* is there a valid port range to connect to ? */
289 if ((bmaddr_1 = pci_read_config(dev, 0x20, 4) & 0xfffc)) {
290 if ((bmaddr_1 = pci_read_config(dev, 0x20, 4) & IOMASK)) {
290 bmaddr_2 = bmaddr_1 + ATA_BM_OFFSET1;
291 printf("ata-pci%d: Busmastering DMA supported\n", unit);
292 }
293 else
294 printf("ata-pci%d: Busmastering DMA not configured\n", unit);
295 }
296 else
297 printf("ata-pci%d: Busmastering DMA not enabled\n", unit);
298 }
299 else {
291 bmaddr_2 = bmaddr_1 + ATA_BM_OFFSET1;
292 printf("ata-pci%d: Busmastering DMA supported\n", unit);
293 }
294 else
295 printf("ata-pci%d: Busmastering DMA not configured\n", unit);
296 }
297 else
298 printf("ata-pci%d: Busmastering DMA not enabled\n", unit);
299 }
300 else {
300 /* the Promise controllers need this to support burst mode */
301 if (type == 0x4d33105a || type == 0x4d38105a)
302 outb(bmaddr_1 + 0x1f, inb(bmaddr_1 + 0x1f) | 0x01);
303
304 /* Promise and HPT366 controllers support busmastering DMA */
305 if (type == 0x4d33105a || type == 0x4d38105a || type == 0x00041103)
301 if (type == 0x4d33105a || type == 0x4d38105a || type == 0x00041103) {
302 /* Promise and HPT366 controllers support busmastering DMA */
306 printf("ata-pci%d: Busmastering DMA supported\n", unit);
303 printf("ata-pci%d: Busmastering DMA supported\n", unit);
307
308 /* we dont know this controller, disable busmastering DMA */
304 }
309 else {
305 else {
306 /* we dont know this controller, disable busmastering DMA */
310 bmaddr_1 = bmaddr_2 = 0;
311 printf("ata-pci%d: Busmastering DMA not supported\n", unit);
312 }
313 }
307 bmaddr_1 = bmaddr_2 = 0;
308 printf("ata-pci%d: Busmastering DMA not supported\n", unit);
309 }
310 }
311
312 /* on the Aladdin activate the ATAPI FIFO */
313 if (type == 0x522910b9) {
314 pci_write_config(dev, 0x53,
315 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
316 }
317
318 /* the Promise controllers needs burst mode to be turned on explicitly */
319 if (type == 0x4d33105a || type == 0x4d38105a)
320 outb(bmaddr_1 + 0x1f, inb(bmaddr_1 + 0x1f) | 0x01);
314
315 /* now probe the addresse found for "real" ATA/ATAPI hardware */
316 lun = 0;
317 if (iobase_1 && ata_probe(iobase_1, altiobase_1, bmaddr_1, dev, &lun)) {
318 scp = atadevices[lun];
319 if (iobase_1 == IO_WD1)
320#ifdef __i386__
321 inthand_add(device_get_nameunit(dev), irq1, ataintr, scp,

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507}
508
509static void
510ataintr(void *data)
511{
512 struct ata_softc *scp =(struct ata_softc *)data;
513
514 /* is this interrupt really for this channel */
321
322 /* now probe the addresse found for "real" ATA/ATAPI hardware */
323 lun = 0;
324 if (iobase_1 && ata_probe(iobase_1, altiobase_1, bmaddr_1, dev, &lun)) {
325 scp = atadevices[lun];
326 if (iobase_1 == IO_WD1)
327#ifdef __i386__
328 inthand_add(device_get_nameunit(dev), irq1, ataintr, scp,

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514}
515
516static void
517ataintr(void *data)
518{
519 struct ata_softc *scp =(struct ata_softc *)data;
520
521 /* is this interrupt really for this channel */
515 if (scp->flags & ATA_DMA_ACTIVE)
516 if (!(ata_dmastatus(scp) & ATA_BMSTAT_INTERRUPT))
517 return;
518 if ((scp->status = inb(scp->ioaddr + ATA_STATUS)) == ATA_S_BUSY)
522 if ((scp->flags & ATA_DMA_ACTIVE) &&
523 !(ata_dmastatus(scp) & ATA_BMSTAT_INTERRUPT))
519 return;
520
524 return;
525
526 if (((scp->status = inb(scp->ioaddr+ATA_STATUS)) & ATA_S_BUSY)==ATA_S_BUSY)
527 return;
528
521 /* find & call the responsible driver to process this interrupt */
522 switch (scp->active) {
523#if NATADISK > 0
524 case ATA_ACTIVE_ATA:
525 if (!scp->running)
526 return;
527 if (ad_interrupt(scp->running) == ATA_OP_CONTINUES)
528 return;
529 break;
530#endif
531#if NATAPICD > 0 || NATAPIFD > 0 || NATAPIST > 0
532 case ATA_ACTIVE_ATAPI:
529 /* find & call the responsible driver to process this interrupt */
530 switch (scp->active) {
531#if NATADISK > 0
532 case ATA_ACTIVE_ATA:
533 if (!scp->running)
534 return;
535 if (ad_interrupt(scp->running) == ATA_OP_CONTINUES)
536 return;
537 break;
538#endif
539#if NATAPICD > 0 || NATAPIFD > 0 || NATAPIST > 0
540 case ATA_ACTIVE_ATAPI:
533 if (!scp->running)
541 if (!scp->running)
534 return;
535 if (atapi_interrupt(scp->running) == ATA_OP_CONTINUES)
536 return;
537 break;
538#endif
539 case ATA_WAIT_INTR:
540 wakeup((caddr_t)scp);
541 break;

--- 362 unchanged lines hidden --- 		542 return;
543 if (atapi_interrupt(scp->running) == ATA_OP_CONTINUES)
544 return;
545 break;
546#endif
547 case ATA_WAIT_INTR:
548 wakeup((caddr_t)scp);
549 break;

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