1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
| 1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
|
32 * $FreeBSD: head/sys/dev/an/if_anreg.h 68692 2000-11-13 23:04:16Z wpaul $
| 32 * $FreeBSD: head/sys/dev/an/if_anreg.h 69771 2000-12-08 19:00:10Z archie $
|
33 */
34
35#define AN_TIMEOUT 65536
36
37/* Default network name: ANY */
38#define AN_DEFAULT_NETNAME "ANY"
39
40/* The nodename must be less than 16 bytes */
41#define AN_DEFAULT_NODENAME "FreeBSD"
42
43#define AN_DEFAULT_IBSS "FreeBSD IBSS"
44
45/*
46 * register space access macros
47 */
48#define CSR_WRITE_2(sc, reg, val) \
49 bus_space_write_2(sc->an_btag, sc->an_bhandle, reg, val)
50
51#define CSR_READ_2(sc, reg) \
52 bus_space_read_2(sc->an_btag, sc->an_bhandle, reg)
53
54#define CSR_WRITE_1(sc, reg, val) \
55 bus_space_write_1(sc->an_btag, sc->an_bhandle, reg, val)
56
57#define CSR_READ_1(sc, reg) \
58 bus_space_read_1(sc->an_btag, sc->an_bhandle, reg)
59
60/*
61 * Size of Aironet I/O space.
62 */
63#define AN_IOSIZ 0x40
64
65/*
66 * Hermes register definitions and what little I know about them.
67 */
68
69/* Hermes command/status registers. */
70#define AN_COMMAND 0x00
71#define AN_PARAM0 0x02
72#define AN_PARAM1 0x04
73#define AN_PARAM2 0x06
74#define AN_STATUS 0x08
75#define AN_RESP0 0x0A
76#define AN_RESP1 0x0C
77#define AN_RESP2 0x0E
78#define AN_LINKSTAT 0x10
79
80/* Command register */
81#define AN_CMD_BUSY 0x8000 /* busy bit */
82#define AN_CMD_NO_ACK 0x0080 /* don't acknowledge command */
83#define AN_CMD_CODE_MASK 0x003F
84#define AN_CMD_QUAL_MASK 0x7F00
85
86/* Command codes */
87#define AN_CMD_NOOP 0x0000 /* no-op */
88#define AN_CMD_ENABLE 0x0001 /* enable */
89#define AN_CMD_DISABLE 0x0002 /* disable */
90#define AN_CMD_FORCE_SYNCLOSS 0x0003 /* force loss of sync */
91#define AN_CMD_FW_RESTART 0x0004 /* firmware resrart */
92#define AN_CMD_HOST_SLEEP 0x0005
93#define AN_CMD_MAGIC_PKT 0x0006
94#define AN_CMD_READCFG 0x0008
95#define AN_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */
96#define AN_CMD_TX 0x000B /* transmit */
97#define AN_CMD_DEALLOC_MEM 0x000C
98#define AN_CMD_NOOP2 0x0010
99#define AN_CMD_ACCESS 0x0021
100#define AN_CMD_ALLOC_BUF 0x0028
101#define AN_CMD_PSP_NODES 0x0030
102#define AN_CMD_SET_PHYREG 0x003E
103#define AN_CMD_TX_TEST 0x003F
104#define AN_CMD_SLEEP 0x0085
105#define AN_CMD_SAVECFG 0x0108
106
107/*
108 * Reclaim qualifier bit, applicable to the
109 * TX command.
110 */
111#define AN_RECLAIM 0x0100 /* reclaim NIC memory */
112
113/*
114 * ACCESS command qualifier bits.
115 */
116#define AN_ACCESS_READ 0x0000
117#define AN_ACCESS_WRITE 0x0100
118
119/*
120 * PROGRAM command qualifier bits.
121 */
122#define AN_PROGRAM_DISABLE 0x0000
123#define AN_PROGRAM_ENABLE_RAM 0x0100
124#define AN_PROGRAM_ENABLE_NVRAM 0x0200
125#define AN_PROGRAM_NVRAM 0x0300
126
127/* Status register values */
128#define AN_STAT_CMD_CODE 0x003F
129#define AN_STAT_CMD_RESULT 0x7F00
130
131/* Linkstat register */
132#define AN_LINKSTAT_ASSOCIATED 0x0400
133#define AN_LINKSTAT_AUTHFAIL 0x0300
134#define AN_LINKSTAT_ASSOC_FAIL 0x8400
135#define AN_LINKSTAT_DISASSOC 0x8200
136#define AN_LINKSTAT_DEAUTH 0x8100
137#define AN_LINKSTAT_SYNCLOST_TSF 0x8004
138#define AN_LINKSTAT_SYNCLOST_HOSTREQ 0x8003
139#define AN_LINKSTAT_SYNCLOST_AVGRETRY 0x8002
140#define AN_LINKSTAT_SYNCLOST_MAXRETRY 0x8001
141#define AN_LINKSTAT_SYNCLOST_MISSBEACON 0x8000
142
143/* memory handle management registers */
144#define AN_RX_FID 0x20
145#define AN_ALLOC_FID 0x22
146#define AN_TX_CMP_FID 0x24
147
148/*
149 * Buffer Access Path (BAP) registers.
150 * These are I/O channels. I believe you can use each one for
151 * any desired purpose independently of the other. In general
152 * though, we use BAP1 for reading and writing LTV records and
153 * reading received data frames, and BAP0 for writing transmit
154 * frames. This is a convention though, not a rule.
155 */
156#define AN_SEL0 0x18
157#define AN_SEL1 0x1A
158#define AN_OFF0 0x1C
159#define AN_OFF1 0x1E
160#define AN_DATA0 0x36
161#define AN_DATA1 0x38
162#define AN_BAP0 AN_DATA0
163#define AN_BAP1 AN_DATA1
164
165#define AN_OFF_BUSY 0x8000
166#define AN_OFF_ERR 0x4000
167#define AN_OFF_DONE 0x2000
168#define AN_OFF_DATAOFF 0x0FFF
169
170/* Event registers */
171#define AN_EVENT_STAT 0x30 /* Event status */
172#define AN_INT_EN 0x32 /* Interrupt enable/disable */
173#define AN_EVENT_ACK 0x34 /* Ack event */
174
175/* Events */
176#define AN_EV_CLR_STUCK_BUSY 0x4000 /* clear stuck busy bit */
177#define AN_EV_WAKEREQUEST 0x2000 /* awaken from PSP mode */
178#define AN_EV_AWAKE 0x0100 /* station woke up from PSP mode*/
179#define AN_EV_LINKSTAT 0x0080 /* link status available */
180#define AN_EV_CMD 0x0010 /* command completed */
181#define AN_EV_ALLOC 0x0008 /* async alloc/reclaim completed */
182#define AN_EV_TX_EXC 0x0004 /* async xmit completed with failure */
183#define AN_EV_TX 0x0002 /* async xmit completed succesfully */
184#define AN_EV_RX 0x0001 /* async rx completed */
185
186#define AN_INTRS \
187 (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_ALLOC|AN_EV_LINKSTAT)
188
189/* Host software registers */
190#define AN_SW0 0x28
191#define AN_SW1 0x2A
192#define AN_SW2 0x2C
193#define AN_SW3 0x2E
194
195#define AN_CNTL 0x14
196
197#define AN_CNTL_AUX_ENA 0xC000
198#define AN_CNTL_AUX_ENA_STAT 0xC000
199#define AN_CNTL_AUX_DIS_STAT 0x0000
200#define AN_CNTL_AUX_ENA_CNTL 0x8000
201#define AN_CNTL_AUX_DIS_CNTL 0x4000
202
203#define AN_AUX_PAGE 0x3A
204#define AN_AUX_OFFSET 0x3C
205#define AN_AUX_DATA 0x3E
206
207/*
208 * Length, Type, Value (LTV) record definitions and RID values.
209 */
210struct an_ltv_gen {
211 u_int16_t an_len;
212 u_int16_t an_type;
213 u_int16_t an_val;
214};
215
216/*
217 * General configuration information.
218 */
219#define AN_RID_GENCONFIG 0xFF10
220struct an_ltv_genconfig {
221 /* General configuration. */
222 u_int16_t an_len; /* 0x00 */
223 u_int16_t an_type; /* XXXX */
224 u_int16_t an_opmode; /* 0x02 */
225 u_int16_t an_rxmode; /* 0x04 */
226 u_int16_t an_fragthresh; /* 0x06 */
227 u_int16_t an_rtsthresh; /* 0x08 */
228 u_int8_t an_macaddr[6]; /* 0x0A */
229 u_int8_t an_rates[8]; /* 0x10 */
230 u_int16_t an_shortretry_limit; /* 0x18 */
231 u_int16_t an_longretry_limit; /* 0x1A */
232 u_int16_t an_tx_msdu_lifetime; /* 0x1C */
233 u_int16_t an_rx_msdu_lifetime; /* 0x1E */
234 u_int16_t an_stationary; /* 0x20 */
235 u_int16_t an_ordering; /* 0x22 */
236 u_int16_t an_devtype; /* 0x24 */
237 u_int16_t an_rsvd0[5]; /* 0x26 */
238 /* Scanning associating. */
239 u_int16_t an_scanmode; /* 0x30 */
240 u_int16_t an_probedelay; /* 0x32 */
241 u_int16_t an_probe_energy_timeout;/* 0x34 */
242 u_int16_t an_probe_response_timeout;/*0x36 */
243 u_int16_t an_beacon_listen_timeout;/*0x38 */
244 u_int16_t an_ibss_join_net_timeout;/*0x3A */
245 u_int16_t an_auth_timeout; /* 0x3C */
246 u_int16_t an_authtype; /* 0x3E */
247 u_int16_t an_assoc_timeout; /* 0x40 */
248 u_int16_t an_specified_ap_timeout;/* 0x42 */
249 u_int16_t an_offline_scan_interval;/*0x44 */
250 u_int16_t an_offline_scan_duration;/*0x46 */
251 u_int16_t an_link_loss_delay; /* 0x48 */
252 u_int16_t an_max_beacon_lost_time;/* 0x4A */
253 u_int16_t an_refresh_interval; /* 0x4C */
254 u_int16_t an_rsvd1; /* 0x4E */
255 /* Power save operation */
256 u_int16_t an_psave_mode; /* 0x50 */
257 u_int16_t an_sleep_for_dtims; /* 0x52 */
258 u_int16_t an_listen_interval; /* 0x54 */
259 u_int16_t an_fast_listen_interval;/* 0x56 */
260 u_int16_t an_listen_decay; /* 0x58 */
261 u_int16_t an_fast_listen_decay; /* 0x5A */
262 u_int16_t an_rsvd2[2]; /* 0x5C */
263 /* Ad-hoc (or AP) operation. */
264 u_int16_t an_beacon_period; /* 0x60 */
265 u_int16_t an_atim_duration; /* 0x62 */
266 u_int16_t an_rsvd3; /* 0x64 */
267 u_int16_t an_ds_channel; /* 0x66 */
268 u_int16_t an_rsvd4; /* 0x68 */
269 u_int16_t an_dtim_period; /* 0x6A */
270 u_int16_t an_rsvd5[2]; /* 0x6C */
271 /* Radio operation. */
272 u_int16_t an_radiotype; /* 0x70 */
273 u_int16_t an_diversity; /* 0x72 */
274 u_int16_t an_tx_power; /* 0x74 */
275 u_int16_t an_rss_thresh; /* 0x76 */
276 u_int16_t an_modulation_type; /* 0x78 */
277 u_int16_t an_short_preamble; /* 0x7A */
278 u_int16_t an_home_product; /* 0x7C */
279 u_int16_t an_rsvd6; /* 0x7E */
280 /* Aironet extensions. */
281 u_int8_t an_nodename[16]; /* 0x80 */
282 u_int16_t an_arl_thresh; /* 0x90 */
283 u_int16_t an_arl_decay; /* 0x92 */
284 u_int16_t an_arl_delay; /* 0x94 */
285 u_int8_t an_rsvd7; /* 0x96 */
286 u_int8_t an_rsvd8; /* 0x97 */
287 u_int8_t an_magic_packet_action; /* 0x98 */
288 u_int8_t an_magic_packet_ctl; /* 0x99 */
289 u_int16_t an_rsvd9;
290};
291
292#define AN_OPMODE_IBSS_ADHOC 0x0000
293#define AN_OPMODE_INFRASTRUCTURE_STATION 0x0001
294#define AN_OPMODE_AP 0x0002
295#define AN_OPMODE_AP_REPEATER 0x0003
296#define AN_OPMODE_UNMODIFIED_PAYLOAD 0x0100
297#define AN_OPMODE_AIRONET_EXTENSIONS 0x0200
298#define AN_OPMODE_AP_EXTENSIONS 0x0400
299
300#define AN_RXMODE_BC_MC_ADDR 0x0000
301#define AN_RXMODE_BC_ADDR 0x0001
302#define AN_RXMODE_ADDR 0x0002
303#define AN_RXMODE_80211_MONITOR_CURBSS 0x0003
304#define AN_RXMODE_80211_MONITOR_ANYBSS 0x0004
305#define AN_RXMODE_LAN_MONITOR_CURBSS 0x0005
306#define AN_RXMODE_NO_8023_HEADER 0x0100
307
308#define AN_RATE_1MBPS 0x0002
309#define AN_RATE_2MBPS 0x0004
310#define AN_RATE_5_5MBPS 0x000B
311#define AN_RATE_11MBPS 0x0016
312
313#define AN_DEVTYPE_PC4500 0x0065
314#define AN_DEVTYPE_PC4800 0x006D
315
316#define AN_SCANMODE_ACTIVE 0x0000
317#define AN_SCANMODE_PASSIVE 0x0001
318#define AN_SCANMODE_AIRONET_ACTIVE 0x0002
319
320#define AN_AUTHTYPE_NONE 0x0000
321#define AN_AUTHTYPE_OPEN 0x0001
322#define AN_AUTHTYPE_SHAREDKEY 0x0002
| 33 */
34
35#define AN_TIMEOUT 65536
36
37/* Default network name: ANY */
38#define AN_DEFAULT_NETNAME "ANY"
39
40/* The nodename must be less than 16 bytes */
41#define AN_DEFAULT_NODENAME "FreeBSD"
42
43#define AN_DEFAULT_IBSS "FreeBSD IBSS"
44
45/*
46 * register space access macros
47 */
48#define CSR_WRITE_2(sc, reg, val) \
49 bus_space_write_2(sc->an_btag, sc->an_bhandle, reg, val)
50
51#define CSR_READ_2(sc, reg) \
52 bus_space_read_2(sc->an_btag, sc->an_bhandle, reg)
53
54#define CSR_WRITE_1(sc, reg, val) \
55 bus_space_write_1(sc->an_btag, sc->an_bhandle, reg, val)
56
57#define CSR_READ_1(sc, reg) \
58 bus_space_read_1(sc->an_btag, sc->an_bhandle, reg)
59
60/*
61 * Size of Aironet I/O space.
62 */
63#define AN_IOSIZ 0x40
64
65/*
66 * Hermes register definitions and what little I know about them.
67 */
68
69/* Hermes command/status registers. */
70#define AN_COMMAND 0x00
71#define AN_PARAM0 0x02
72#define AN_PARAM1 0x04
73#define AN_PARAM2 0x06
74#define AN_STATUS 0x08
75#define AN_RESP0 0x0A
76#define AN_RESP1 0x0C
77#define AN_RESP2 0x0E
78#define AN_LINKSTAT 0x10
79
80/* Command register */
81#define AN_CMD_BUSY 0x8000 /* busy bit */
82#define AN_CMD_NO_ACK 0x0080 /* don't acknowledge command */
83#define AN_CMD_CODE_MASK 0x003F
84#define AN_CMD_QUAL_MASK 0x7F00
85
86/* Command codes */
87#define AN_CMD_NOOP 0x0000 /* no-op */
88#define AN_CMD_ENABLE 0x0001 /* enable */
89#define AN_CMD_DISABLE 0x0002 /* disable */
90#define AN_CMD_FORCE_SYNCLOSS 0x0003 /* force loss of sync */
91#define AN_CMD_FW_RESTART 0x0004 /* firmware resrart */
92#define AN_CMD_HOST_SLEEP 0x0005
93#define AN_CMD_MAGIC_PKT 0x0006
94#define AN_CMD_READCFG 0x0008
95#define AN_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */
96#define AN_CMD_TX 0x000B /* transmit */
97#define AN_CMD_DEALLOC_MEM 0x000C
98#define AN_CMD_NOOP2 0x0010
99#define AN_CMD_ACCESS 0x0021
100#define AN_CMD_ALLOC_BUF 0x0028
101#define AN_CMD_PSP_NODES 0x0030
102#define AN_CMD_SET_PHYREG 0x003E
103#define AN_CMD_TX_TEST 0x003F
104#define AN_CMD_SLEEP 0x0085
105#define AN_CMD_SAVECFG 0x0108
106
107/*
108 * Reclaim qualifier bit, applicable to the
109 * TX command.
110 */
111#define AN_RECLAIM 0x0100 /* reclaim NIC memory */
112
113/*
114 * ACCESS command qualifier bits.
115 */
116#define AN_ACCESS_READ 0x0000
117#define AN_ACCESS_WRITE 0x0100
118
119/*
120 * PROGRAM command qualifier bits.
121 */
122#define AN_PROGRAM_DISABLE 0x0000
123#define AN_PROGRAM_ENABLE_RAM 0x0100
124#define AN_PROGRAM_ENABLE_NVRAM 0x0200
125#define AN_PROGRAM_NVRAM 0x0300
126
127/* Status register values */
128#define AN_STAT_CMD_CODE 0x003F
129#define AN_STAT_CMD_RESULT 0x7F00
130
131/* Linkstat register */
132#define AN_LINKSTAT_ASSOCIATED 0x0400
133#define AN_LINKSTAT_AUTHFAIL 0x0300
134#define AN_LINKSTAT_ASSOC_FAIL 0x8400
135#define AN_LINKSTAT_DISASSOC 0x8200
136#define AN_LINKSTAT_DEAUTH 0x8100
137#define AN_LINKSTAT_SYNCLOST_TSF 0x8004
138#define AN_LINKSTAT_SYNCLOST_HOSTREQ 0x8003
139#define AN_LINKSTAT_SYNCLOST_AVGRETRY 0x8002
140#define AN_LINKSTAT_SYNCLOST_MAXRETRY 0x8001
141#define AN_LINKSTAT_SYNCLOST_MISSBEACON 0x8000
142
143/* memory handle management registers */
144#define AN_RX_FID 0x20
145#define AN_ALLOC_FID 0x22
146#define AN_TX_CMP_FID 0x24
147
148/*
149 * Buffer Access Path (BAP) registers.
150 * These are I/O channels. I believe you can use each one for
151 * any desired purpose independently of the other. In general
152 * though, we use BAP1 for reading and writing LTV records and
153 * reading received data frames, and BAP0 for writing transmit
154 * frames. This is a convention though, not a rule.
155 */
156#define AN_SEL0 0x18
157#define AN_SEL1 0x1A
158#define AN_OFF0 0x1C
159#define AN_OFF1 0x1E
160#define AN_DATA0 0x36
161#define AN_DATA1 0x38
162#define AN_BAP0 AN_DATA0
163#define AN_BAP1 AN_DATA1
164
165#define AN_OFF_BUSY 0x8000
166#define AN_OFF_ERR 0x4000
167#define AN_OFF_DONE 0x2000
168#define AN_OFF_DATAOFF 0x0FFF
169
170/* Event registers */
171#define AN_EVENT_STAT 0x30 /* Event status */
172#define AN_INT_EN 0x32 /* Interrupt enable/disable */
173#define AN_EVENT_ACK 0x34 /* Ack event */
174
175/* Events */
176#define AN_EV_CLR_STUCK_BUSY 0x4000 /* clear stuck busy bit */
177#define AN_EV_WAKEREQUEST 0x2000 /* awaken from PSP mode */
178#define AN_EV_AWAKE 0x0100 /* station woke up from PSP mode*/
179#define AN_EV_LINKSTAT 0x0080 /* link status available */
180#define AN_EV_CMD 0x0010 /* command completed */
181#define AN_EV_ALLOC 0x0008 /* async alloc/reclaim completed */
182#define AN_EV_TX_EXC 0x0004 /* async xmit completed with failure */
183#define AN_EV_TX 0x0002 /* async xmit completed succesfully */
184#define AN_EV_RX 0x0001 /* async rx completed */
185
186#define AN_INTRS \
187 (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_ALLOC|AN_EV_LINKSTAT)
188
189/* Host software registers */
190#define AN_SW0 0x28
191#define AN_SW1 0x2A
192#define AN_SW2 0x2C
193#define AN_SW3 0x2E
194
195#define AN_CNTL 0x14
196
197#define AN_CNTL_AUX_ENA 0xC000
198#define AN_CNTL_AUX_ENA_STAT 0xC000
199#define AN_CNTL_AUX_DIS_STAT 0x0000
200#define AN_CNTL_AUX_ENA_CNTL 0x8000
201#define AN_CNTL_AUX_DIS_CNTL 0x4000
202
203#define AN_AUX_PAGE 0x3A
204#define AN_AUX_OFFSET 0x3C
205#define AN_AUX_DATA 0x3E
206
207/*
208 * Length, Type, Value (LTV) record definitions and RID values.
209 */
210struct an_ltv_gen {
211 u_int16_t an_len;
212 u_int16_t an_type;
213 u_int16_t an_val;
214};
215
216/*
217 * General configuration information.
218 */
219#define AN_RID_GENCONFIG 0xFF10
220struct an_ltv_genconfig {
221 /* General configuration. */
222 u_int16_t an_len; /* 0x00 */
223 u_int16_t an_type; /* XXXX */
224 u_int16_t an_opmode; /* 0x02 */
225 u_int16_t an_rxmode; /* 0x04 */
226 u_int16_t an_fragthresh; /* 0x06 */
227 u_int16_t an_rtsthresh; /* 0x08 */
228 u_int8_t an_macaddr[6]; /* 0x0A */
229 u_int8_t an_rates[8]; /* 0x10 */
230 u_int16_t an_shortretry_limit; /* 0x18 */
231 u_int16_t an_longretry_limit; /* 0x1A */
232 u_int16_t an_tx_msdu_lifetime; /* 0x1C */
233 u_int16_t an_rx_msdu_lifetime; /* 0x1E */
234 u_int16_t an_stationary; /* 0x20 */
235 u_int16_t an_ordering; /* 0x22 */
236 u_int16_t an_devtype; /* 0x24 */
237 u_int16_t an_rsvd0[5]; /* 0x26 */
238 /* Scanning associating. */
239 u_int16_t an_scanmode; /* 0x30 */
240 u_int16_t an_probedelay; /* 0x32 */
241 u_int16_t an_probe_energy_timeout;/* 0x34 */
242 u_int16_t an_probe_response_timeout;/*0x36 */
243 u_int16_t an_beacon_listen_timeout;/*0x38 */
244 u_int16_t an_ibss_join_net_timeout;/*0x3A */
245 u_int16_t an_auth_timeout; /* 0x3C */
246 u_int16_t an_authtype; /* 0x3E */
247 u_int16_t an_assoc_timeout; /* 0x40 */
248 u_int16_t an_specified_ap_timeout;/* 0x42 */
249 u_int16_t an_offline_scan_interval;/*0x44 */
250 u_int16_t an_offline_scan_duration;/*0x46 */
251 u_int16_t an_link_loss_delay; /* 0x48 */
252 u_int16_t an_max_beacon_lost_time;/* 0x4A */
253 u_int16_t an_refresh_interval; /* 0x4C */
254 u_int16_t an_rsvd1; /* 0x4E */
255 /* Power save operation */
256 u_int16_t an_psave_mode; /* 0x50 */
257 u_int16_t an_sleep_for_dtims; /* 0x52 */
258 u_int16_t an_listen_interval; /* 0x54 */
259 u_int16_t an_fast_listen_interval;/* 0x56 */
260 u_int16_t an_listen_decay; /* 0x58 */
261 u_int16_t an_fast_listen_decay; /* 0x5A */
262 u_int16_t an_rsvd2[2]; /* 0x5C */
263 /* Ad-hoc (or AP) operation. */
264 u_int16_t an_beacon_period; /* 0x60 */
265 u_int16_t an_atim_duration; /* 0x62 */
266 u_int16_t an_rsvd3; /* 0x64 */
267 u_int16_t an_ds_channel; /* 0x66 */
268 u_int16_t an_rsvd4; /* 0x68 */
269 u_int16_t an_dtim_period; /* 0x6A */
270 u_int16_t an_rsvd5[2]; /* 0x6C */
271 /* Radio operation. */
272 u_int16_t an_radiotype; /* 0x70 */
273 u_int16_t an_diversity; /* 0x72 */
274 u_int16_t an_tx_power; /* 0x74 */
275 u_int16_t an_rss_thresh; /* 0x76 */
276 u_int16_t an_modulation_type; /* 0x78 */
277 u_int16_t an_short_preamble; /* 0x7A */
278 u_int16_t an_home_product; /* 0x7C */
279 u_int16_t an_rsvd6; /* 0x7E */
280 /* Aironet extensions. */
281 u_int8_t an_nodename[16]; /* 0x80 */
282 u_int16_t an_arl_thresh; /* 0x90 */
283 u_int16_t an_arl_decay; /* 0x92 */
284 u_int16_t an_arl_delay; /* 0x94 */
285 u_int8_t an_rsvd7; /* 0x96 */
286 u_int8_t an_rsvd8; /* 0x97 */
287 u_int8_t an_magic_packet_action; /* 0x98 */
288 u_int8_t an_magic_packet_ctl; /* 0x99 */
289 u_int16_t an_rsvd9;
290};
291
292#define AN_OPMODE_IBSS_ADHOC 0x0000
293#define AN_OPMODE_INFRASTRUCTURE_STATION 0x0001
294#define AN_OPMODE_AP 0x0002
295#define AN_OPMODE_AP_REPEATER 0x0003
296#define AN_OPMODE_UNMODIFIED_PAYLOAD 0x0100
297#define AN_OPMODE_AIRONET_EXTENSIONS 0x0200
298#define AN_OPMODE_AP_EXTENSIONS 0x0400
299
300#define AN_RXMODE_BC_MC_ADDR 0x0000
301#define AN_RXMODE_BC_ADDR 0x0001
302#define AN_RXMODE_ADDR 0x0002
303#define AN_RXMODE_80211_MONITOR_CURBSS 0x0003
304#define AN_RXMODE_80211_MONITOR_ANYBSS 0x0004
305#define AN_RXMODE_LAN_MONITOR_CURBSS 0x0005
306#define AN_RXMODE_NO_8023_HEADER 0x0100
307
308#define AN_RATE_1MBPS 0x0002
309#define AN_RATE_2MBPS 0x0004
310#define AN_RATE_5_5MBPS 0x000B
311#define AN_RATE_11MBPS 0x0016
312
313#define AN_DEVTYPE_PC4500 0x0065
314#define AN_DEVTYPE_PC4800 0x006D
315
316#define AN_SCANMODE_ACTIVE 0x0000
317#define AN_SCANMODE_PASSIVE 0x0001
318#define AN_SCANMODE_AIRONET_ACTIVE 0x0002
319
320#define AN_AUTHTYPE_NONE 0x0000
321#define AN_AUTHTYPE_OPEN 0x0001
322#define AN_AUTHTYPE_SHAREDKEY 0x0002
|
323#define AN_AUTHTYPE_EXCLUDE_UNENCRYPTED 0x0004
| 323#define AN_AUTHTYPE_PRIVACY_IN_USE 0x0100
324#define AN_AUTHTYPE_ALLOW_UNENCRYPTED 0x0200
|
324
| 325
|
| 326
|
325#define AN_PSAVE_NONE 0x0000
326#define AN_PSAVE_CAM 0x0001
327#define AN_PSAVE_PSP 0x0002
328#define AN_PSAVE_PSP_CAM 0x0003
329
330#define AN_RADIOTYPE_80211_FH 0x0001
331#define AN_RADIOTYPE_80211_DS 0x0002
332#define AN_RADIOTYPE_LM2000_DS 0x0004
333
334#define AN_DIVERSITY_FACTORY_DEFAULT 0x0000
335#define AN_DIVERSITY_ANTENNA_1_ONLY 0x0001
336#define AN_DIVERSITY_ANTENNA_2_ONLY 0x0002
337#define AN_DIVERSITY_ANTENNA_1_AND_2 0x0003
338
339#define AN_TXPOWER_FACTORY_DEFAULT 0x0000
340#define AN_TXPOWER_50MW 50
341#define AN_TXPOWER_100MW 100
342#define AN_TXPOWER_250MW 250
343
344/*
345 * Valid SSID list. You can specify up to three SSIDs denoting
346 * the service sets that you want to join. The first SSID always
347 * defaults to "tsunami" which is a handy way to detect the
348 * card.
349 */
350#define AN_RID_SSIDLIST 0xFF11
351struct an_ltv_ssidlist {
352 u_int16_t an_len;
353 u_int16_t an_type;
354 u_int16_t an_ssid1_len;
355 char an_ssid1[32];
356 u_int16_t an_ssid2_len;
357 char an_ssid2[32];
358 u_int16_t an_ssid3_len;
359 char an_ssid3[32];
360};
361
362#define AN_DEF_SSID_LEN 7
363#define AN_DEF_SSID "tsunami"
364
365/*
366 * Valid AP list.
367 */
368#define AN_RID_APLIST 0xFF12
369struct an_ltv_aplist {
370 u_int16_t an_len;
371 u_int16_t an_type;
372 u_int8_t an_ap1[8];
373 u_int8_t an_ap2[8];
374 u_int8_t an_ap3[8];
375 u_int8_t an_ap4[8];
376};
377
378/*
379 * Driver name.
380 */
381#define AN_RID_DRVNAME 0xFF13
382struct an_ltv_drvname {
383 u_int16_t an_len;
384 u_int16_t an_type;
385 u_int8_t an_drvname[16];
386};
387
388/*
389 * Frame encapsulation.
390 */
391#define AN_RID_ENCAP 0xFF14
392struct an_rid_encap {
393 u_int16_t an_len;
394 u_int16_t an_type;
395 u_int16_t an_ethertype_default;
396 u_int16_t an_action_default;
397 u_int16_t an_ethertype0;
398 u_int16_t an_action0;
399 u_int16_t an_ethertype1;
400 u_int16_t an_action1;
401 u_int16_t an_ethertype2;
402 u_int16_t an_action2;
403 u_int16_t an_ethertype3;
404 u_int16_t an_action3;
405 u_int16_t an_ethertype4;
406 u_int16_t an_action4;
407 u_int16_t an_ethertype5;
408 u_int16_t an_action5;
409 u_int16_t an_ethertype6;
410 u_int16_t an_action6;
411};
412
413#define AN_ENCAP_ACTION_RX 0x0001
414#define AN_ENCAP_ACTION_TX 0x0002
415
416#define AN_RXENCAP_NONE 0x0000
417#define AN_RXENCAP_RFC1024 0x0001
418
419#define AN_TXENCAP_RFC1024 0x0000
420#define AN_TXENCAP_80211 0x0002
421
422#define AN_RID_WEP_TEMP 0xFF15
423#define AN_RID_WEP_PERM 0xFF16
424
425/*
426 * Actual config, same structure as general config (read only).
427 */
428#define AN_RID_ACTUALCFG 0xFF20
429
430/*
431 * Card capabilities (read only).
432 */
433#define AN_RID_CAPABILITIES 0xFF00
434struct an_ltv_caps {
435 u_int16_t an_len; /* 0x00 */
436 u_int16_t an_type; /* XXXX */
437 u_int8_t an_oui[3]; /* 0x02 */
438 u_int8_t an_rsvd0; /* 0x05 */
439 u_int16_t an_prodnum; /* 0x06 */
440 u_int8_t an_manufname[32]; /* 0x08 */
441 u_int8_t an_prodname[16]; /* 0x28 */
442 u_int8_t an_prodvers[8]; /* 0x38 */
443 u_int8_t an_oemaddr[6]; /* 0x40 */
444 u_int8_t an_aironetaddr[6]; /* 0x46 */
445 u_int16_t an_radiotype; /* 0x4C */
446 u_int16_t an_regdomain; /* 0x4E */
447 u_int8_t an_callid[6]; /* 0x50 */
448 u_int8_t an_rates[8]; /* 0x56 */
449 u_int8_t an_rx_diversity; /* 0x5E */
450 u_int8_t an_tx_diversity; /* 0x5F */
451 u_int16_t an_tx_powerlevels[8]; /* 0x60 */
452 u_int16_t an_hwrev; /* 0x70 */
453 u_int16_t an_hwcaps; /* 0x72 */
454 u_int16_t an_temprange; /* 0x74 */
455 u_int16_t an_fwrev; /* 0x76 */
456 u_int16_t an_fwsubrev; /* 0x78 */
457 u_int16_t an_ifacerev; /* 0x7A */
458 u_int16_t an_softcaps; /* 0x7C */
459 u_int16_t an_bootblockrev; /* 0x7E */
460 u_int16_t an_req_hw_support; /* 0x80 */
461};
462
463/*
464 * Access point (read only)
465 */
466#define AN_RID_APINFO 0xFF01
467struct an_ltv_apinfo {
468 u_int16_t an_len;
469 u_int16_t an_type;
470 u_int16_t an_tim_addr;
471 u_int16_t an_airo_addr;
472};
473
474/*
475 * Radio info (read only).
476 */
477#define AN_RID_RADIOINFO 0xFF02
478struct an_ltv_radioinfo {
479 u_int16_t an_len;
480 u_int16_t an_type;
481 /* ??? */
482};
483
484/*
485 * Status (read only). Note: the manual claims this RID is 108 bytes
486 * long (0x6A is the last datum, which is 2 bytes long) however when
487 * this RID is read from the NIC, it returns a length of 110. To be
488 * on the safe side, this structure is padded with an extra 16-bit
489 * word. (There is a misprint in the manual which says the macaddr
490 * field is 8 bytes long.)
491 *
492 * Also, the channel_set and current_channel fields appear to be
493 * reversed. Either that, or the hop_period field is unused.
494 */
495#define AN_RID_STATUS 0xFF50
496struct an_ltv_status {
497 u_int16_t an_len; /* 0x00 */
498 u_int16_t an_type; /* 0xXX */
499 u_int8_t an_macaddr[6]; /* 0x02 */
500 u_int16_t an_opmode; /* 0x08 */
501 u_int16_t an_errcode; /* 0x0A */
502 u_int16_t an_cur_signal_strength; /* 0x0C */
503 u_int16_t an_ssidlen; /* 0x0E */
504 u_int8_t an_ssid[32]; /* 0x10 */
505 u_int8_t an_ap_name[16]; /* 0x30 */
506 u_int8_t an_cur_bssid[6]; /* 0x40 */
507 u_int8_t an_prev_bssid1[6]; /* 0x46 */
508 u_int8_t an_prev_bssid2[6]; /* 0x4C */
509 u_int8_t an_prev_bssid3[6]; /* 0x52 */
510 u_int16_t an_beacon_period; /* 0x58 */
511 u_int16_t an_dtim_period; /* 0x5A */
512 u_int16_t an_atim_duration; /* 0x5C */
513 u_int16_t an_hop_period; /* 0x5E */
514 u_int16_t an_cur_channel; /* 0x62 */
515 u_int16_t an_channel_set; /* 0x60 */
516 u_int16_t an_hops_to_backbone; /* 0x64 */
517 u_int16_t an_ap_total_load; /* 0x66 */
518 u_int16_t an_our_generated_load; /* 0x68 */
519 u_int16_t an_accumulated_arl; /* 0x6A */
520 u_int16_t an_cur_signal_quality; /* 0x6C */
521 u_int16_t an_current_tx_rate; /* 0x6E */
522 u_int16_t an_ap_device; /* 0x70 */
523 u_int16_t an_normalized_rssi; /* 0x72 */
524 u_int16_t an_short_pre_in_use; /* 0x74 */
525 u_int8_t an_ap_ip_addr[4]; /* 0x76 */
526 u_int16_t an_max_noise_prev_sec; /* 0x7A */
527 u_int16_t an_avg_noise_prev_min; /* 0x7C */
528 u_int16_t an_max_noise_prev_min; /* 0x7E */
529 u_int16_t an_spare[2];
530};
531
532#define AN_STATUS_OPMODE_CONFIGURED 0x0001
533#define AN_STATUS_OPMODE_MAC_ENABLED 0x0002
534#define AN_STATUS_OPMODE_RX_ENABLED 0x0004
535#define AN_STATUS_OPMODE_IN_SYNC 0x0010
536#define AN_STATUS_OPMODE_ASSOCIATED 0x0020
537#define AN_STATUS_OPMODE_ERROR 0x8000
538
539
540/*
541 * Statistics
542 */
543#define AN_RID_16BITS_CUM 0xFF60 /* Cumulative 16-bit stats counters */
544#define AN_RID_16BITS_DELTA 0xFF61 /* 16-bit stats (since last clear) */
545#define AN_RID_16BITS_DELTACLR 0xFF62 /* 16-bit stats, clear on read */
546#define AN_RID_32BITS_CUM 0xFF68 /* Cumulative 32-bit stats counters */
547#define AN_RID_32BITS_DELTA 0xFF69 /* 32-bit stats (since last clear) */
548#define AN_RID_32BITS_DELTACLR 0xFF6A /* 32-bit stats, clear on read */
549
550/*
551 * Grrr. The manual says the statistics record is 384 bytes in length,
552 * but the card says the record is 404 bytes. There's some padding left
553 * at the end of this structure to account for any discrepancies.
554 */
555struct an_ltv_stats {
556 u_int16_t an_fudge;
557 u_int16_t an_len; /* 0x00 */
558 u_int16_t an_type; /* 0xXX */
559 u_int16_t an_spacer; /* 0x02 */
560 u_int32_t an_rx_overruns; /* 0x04 */
561 u_int32_t an_rx_plcp_csum_errs; /* 0x08 */
562 u_int32_t an_rx_plcp_format_errs; /* 0x0C */
563 u_int32_t an_rx_plcp_len_errs; /* 0x10 */
564 u_int32_t an_rx_mac_crc_errs; /* 0x14 */
565 u_int32_t an_rx_mac_crc_ok; /* 0x18 */
566 u_int32_t an_rx_wep_errs; /* 0x1C */
567 u_int32_t an_rx_wep_ok; /* 0x20 */
568 u_int32_t an_retry_long; /* 0x24 */
569 u_int32_t an_retry_short; /* 0x28 */
570 u_int32_t an_retry_max; /* 0x2C */
571 u_int32_t an_no_ack; /* 0x30 */
572 u_int32_t an_no_cts; /* 0x34 */
573 u_int32_t an_rx_ack_ok; /* 0x38 */
574 u_int32_t an_rx_cts_ok; /* 0x3C */
575 u_int32_t an_tx_ack_ok; /* 0x40 */
576 u_int32_t an_tx_rts_ok; /* 0x44 */
577 u_int32_t an_tx_cts_ok; /* 0x48 */
578 u_int32_t an_tx_lmac_mcasts; /* 0x4C */
579 u_int32_t an_tx_lmac_bcasts; /* 0x50 */
580 u_int32_t an_tx_lmac_ucast_frags; /* 0x54 */
581 u_int32_t an_tx_lmac_ucasts; /* 0x58 */
582 u_int32_t an_tx_beacons; /* 0x5C */
583 u_int32_t an_rx_beacons; /* 0x60 */
584 u_int32_t an_tx_single_cols; /* 0x64 */
585 u_int32_t an_tx_multi_cols; /* 0x68 */
586 u_int32_t an_tx_defers_no; /* 0x6C */
587 u_int32_t an_tx_defers_prot; /* 0x70 */
588 u_int32_t an_tx_defers_energy; /* 0x74 */
589 u_int32_t an_rx_dups; /* 0x78 */
590 u_int32_t an_rx_partial; /* 0x7C */
591 u_int32_t an_tx_too_old; /* 0x80 */
592 u_int32_t an_rx_too_old; /* 0x84 */
593 u_int32_t an_lostsync_max_retries;/* 0x88 */
594 u_int32_t an_lostsync_missed_beacons;/* 0x8C */
595 u_int32_t an_lostsync_arl_exceeded;/*0x90 */
596 u_int32_t an_lostsync_deauthed; /* 0x94 */
597 u_int32_t an_lostsync_disassociated;/*0x98 */
598 u_int32_t an_lostsync_tsf_timing; /* 0x9C */
599 u_int32_t an_tx_host_mcasts; /* 0xA0 */
600 u_int32_t an_tx_host_bcasts; /* 0xA4 */
601 u_int32_t an_tx_host_ucasts; /* 0xA8 */
602 u_int32_t an_tx_host_failed; /* 0xAC */
603 u_int32_t an_rx_host_mcasts; /* 0xB0 */
604 u_int32_t an_rx_host_bcasts; /* 0xB4 */
605 u_int32_t an_rx_host_ucasts; /* 0xB8 */
606 u_int32_t an_rx_host_discarded; /* 0xBC */
607 u_int32_t an_tx_hmac_mcasts; /* 0xC0 */
608 u_int32_t an_tx_hmac_bcasts; /* 0xC4 */
609 u_int32_t an_tx_hmac_ucasts; /* 0xC8 */
610 u_int32_t an_tx_hmac_failed; /* 0xCC */
611 u_int32_t an_rx_hmac_mcasts; /* 0xD0 */
612 u_int32_t an_rx_hmac_bcasts; /* 0xD4 */
613 u_int32_t an_rx_hmac_ucasts; /* 0xD8 */
614 u_int32_t an_rx_hmac_discarded; /* 0xDC */
615 u_int32_t an_tx_hmac_accepted; /* 0xE0 */
616 u_int32_t an_ssid_mismatches; /* 0xE4 */
617 u_int32_t an_ap_mismatches; /* 0xE8 */
618 u_int32_t an_rates_mismatches; /* 0xEC */
619 u_int32_t an_auth_rejects; /* 0xF0 */
620 u_int32_t an_auth_timeouts; /* 0xF4 */
621 u_int32_t an_assoc_rejects; /* 0xF8 */
622 u_int32_t an_assoc_timeouts; /* 0xFC */
623 u_int32_t an_reason_outside_table;/* 0x100 */
624 u_int32_t an_reason1; /* 0x104 */
625 u_int32_t an_reason2; /* 0x108 */
626 u_int32_t an_reason3; /* 0x10C */
627 u_int32_t an_reason4; /* 0x110 */
628 u_int32_t an_reason5; /* 0x114 */
629 u_int32_t an_reason6; /* 0x118 */
630 u_int32_t an_reason7; /* 0x11C */
631 u_int32_t an_reason8; /* 0x120 */
632 u_int32_t an_reason9; /* 0x124 */
633 u_int32_t an_reason10; /* 0x128 */
634 u_int32_t an_reason11; /* 0x12C */
635 u_int32_t an_reason12; /* 0x130 */
636 u_int32_t an_reason13; /* 0x134 */
637 u_int32_t an_reason14; /* 0x138 */
638 u_int32_t an_reason15; /* 0x13C */
639 u_int32_t an_reason16; /* 0x140 */
640 u_int32_t an_reason17; /* 0x144 */
641 u_int32_t an_reason18; /* 0x148 */
642 u_int32_t an_reason19; /* 0x14C */
643 u_int32_t an_rx_mgmt_pkts; /* 0x150 */
644 u_int32_t an_tx_mgmt_pkts; /* 0x154 */
645 u_int32_t an_rx_refresh_pkts; /* 0x158 */
646 u_int32_t an_tx_refresh_pkts; /* 0x15C */
647 u_int32_t an_rx_poll_pkts; /* 0x160 */
648 u_int32_t an_tx_poll_pkts; /* 0x164 */
649 u_int32_t an_host_retries; /* 0x168 */
650 u_int32_t an_lostsync_hostreq; /* 0x16C */
651 u_int32_t an_host_tx_bytes; /* 0x170 */
652 u_int32_t an_host_rx_bytes; /* 0x174 */
653 u_int32_t an_uptime_usecs; /* 0x178 */
654 u_int32_t an_uptime_secs; /* 0x17C */
655 u_int32_t an_lostsync_better_ap; /* 0x180 */
656 u_int32_t an_rsvd[10];
657};
658
659/*
660 * Volatile WEP Key
661 */
662#define AN_RID_WEP_VOLATILE 0xFF15 /* Volatile WEP Key */
663struct an_ltv_wepkey {
664 u_int16_t an_len; /* 0x00 */
665 u_int16_t an_type; /* 0xXX */
666 u_int16_t an_key_index; /* 0x02 */
667 u_int8_t an_mac_addr[6]; /* 0x04 */
668 u_int16_t an_key_len; /* 0x0A */
669 u_int8_t an_key[13]; /* 0x0C */
670};
671
672/*
673 * Persistent WEP Key
674 */
675#define AN_RID_WEP_PERSISTENT 0xFF16 /* Persistent WEP Key */
676
677
678/*
679 * Receive frame structure.
680 */
681struct an_rxframe {
682 u_int32_t an_rx_time; /* 0x00 */
683 u_int16_t an_rx_status; /* 0x04 */
684 u_int16_t an_rx_payload_len; /* 0x06 */
685 u_int8_t an_rsvd0; /* 0x08 */
686 u_int8_t an_rx_signal_strength; /* 0x09 */
687 u_int8_t an_rx_rate; /* 0x0A */
688 u_int8_t an_rx_chan; /* 0x0B */
689 u_int8_t an_rx_assoc_cnt; /* 0x0C */
690 u_int8_t an_rsvd1[3]; /* 0x0D */
691 u_int8_t an_plcp_hdr[4]; /* 0x10 */
692 u_int16_t an_frame_ctl; /* 0x14 */
693 u_int16_t an_duration; /* 0x16 */
694 u_int8_t an_addr1[6]; /* 0x18 */
695 u_int8_t an_addr2[6]; /* 0x1E */
696 u_int8_t an_addr3[6]; /* 0x24 */
697 u_int16_t an_seq_ctl; /* 0x2A */
698 u_int8_t an_addr4[6]; /* 0x2C */
699 u_int16_t an_gaplen; /* 0x32 */
700};
701
702#define AN_RXGAP_MAX 8
703
704/*
705 * Transmit frame structure.
706 */
707struct an_txframe {
708 u_int32_t an_tx_sw; /* 0x00 */
709 u_int16_t an_tx_status; /* 0x04 */
710 u_int16_t an_tx_payload_len; /* 0x06 */
711 u_int16_t an_tx_ctl; /* 0x08 */
712 u_int16_t an_tx_assoc_id; /* 0x0A */
713 u_int16_t an_tx_retry; /* 0x0C */
714 u_int8_t an_tx_assoc_cnt; /* 0x0E */
715 u_int8_t an_tx_rate; /* 0x0F */
716 u_int8_t an_tx_max_long_retries; /* 0x10 */
717 u_int8_t an_tx_max_short_retries; /*0x11 */
718 u_int8_t an_rsvd0[2]; /* 0x12 */
719 u_int16_t an_frame_ctl; /* 0x14 */
720 u_int16_t an_duration; /* 0x16 */
721 u_int8_t an_addr1[6]; /* 0x18 */
722 u_int8_t an_addr2[6]; /* 0x1E */
723 u_int8_t an_addr3[6]; /* 0x24 */
724 u_int16_t an_seq_ctl; /* 0x2A */
725 u_int8_t an_addr4[6]; /* 0x2C */
726 u_int16_t an_gaplen; /* 0x32 */
727};
728
729struct an_rxframe_802_3 {
730 u_int16_t an_rx_802_3_status; /* 0x34 */
731 u_int16_t an_rx_802_3_payload_len;/* 0x36 */
732 u_int8_t an_rx_dst_addr[6]; /* 0x38 */
733 u_int8_t an_rx_src_addr[6]; /* 0x3E */
734};
735#define AN_RXGAP_MAX 8
736
737
738struct an_txframe_802_3 {
739/*
740 * Transmit 802.3 header structure.
741 */
742 u_int16_t an_tx_802_3_status; /* 0x34 */
743 u_int16_t an_tx_802_3_payload_len;/* 0x36 */
744 u_int8_t an_tx_dst_addr[6]; /* 0x38 */
745 u_int8_t an_tx_src_addr[6]; /* 0x3E */
746};
747
748#define AN_TXSTAT_EXCESS_RETRY 0x0002
749#define AN_TXSTAT_LIFE_EXCEEDED 0x0004
750#define AN_TXSTAT_AID_FAIL 0x0008
751#define AN_TXSTAT_MAC_DISABLED 0x0010
752#define AN_TXSTAT_ASSOC_LOST 0x0020
753
754#define AN_TXCTL_RSVD 0x0001
755#define AN_TXCTL_TXOK_INTR 0x0002
756#define AN_TXCTL_TXERR_INTR 0x0004
757#define AN_TXCTL_HEADER_TYPE 0x0008
758#define AN_TXCTL_PAYLOAD_TYPE 0x0010
759#define AN_TXCTL_NORELEASE 0x0020
760#define AN_TXCTL_NORETRIES 0x0040
761#define AN_TXCTL_CLEAR_AID 0x0080
762#define AN_TXCTL_STRICT_ORDER 0x0100
763#define AN_TXCTL_USE_RTS 0x0200
764
765#define AN_HEADERTYPE_8023 0x0000
766#define AN_HEADERTYPE_80211 0x0008
767
768#define AN_PAYLOADTYPE_ETHER 0x0000
769#define AN_PAYLOADTYPE_LLC 0x0010
770
771#define AN_TXCTL_80211 \
772 (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_80211| \
773 AN_PAYLOADTYPE_LLC|AN_TXCTL_NORELEASE)
774
775#define AN_TXCTL_8023 \
776 (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_8023| \
777 AN_PAYLOADTYPE_ETHER|AN_TXCTL_NORELEASE)
778
779#define AN_TXGAP_80211 0
780#define AN_TXGAP_8023 0
781
782struct an_802_3_hdr {
783 u_int16_t an_8023_status;
784 u_int16_t an_8023_payload_len;
785 u_int8_t an_8023_dst_addr[6];
786 u_int8_t an_8023_src_addr[6];
787 u_int16_t an_8023_dat[3]; /* SNAP header */
788 u_int16_t an_8023_type;
789};
790
791struct an_snap_hdr {
792 u_int16_t an_snap_dat[3]; /* SNAP header */
793 u_int16_t an_snap_type;
794};
795
796#define AN_TX_RING_CNT 4
797#define AN_INC(x, y) (x) = (x + 1) % y
798
799struct an_tx_ring_data {
800 u_int16_t an_tx_fids[AN_TX_RING_CNT];
801 u_int16_t an_tx_ring[AN_TX_RING_CNT];
802 int an_tx_prod;
803 int an_tx_cons;
804};
805
806struct an_softc {
807 struct arpcom arpcom;
808
809 int an_unit;
810
811 int port_rid; /* resource id for port range */
812 struct resource* port_res; /* resource for port range */
813 int irq_rid; /* resource id for irq */
814 struct resource* irq_res; /* resource for irq */
815 void* irq_handle; /* handle for irq handler */
816
817 bus_space_handle_t an_bhandle_p;
818 bus_space_handle_t an_bhandle;
819 bus_space_tag_t an_btag;
820 struct an_ltv_genconfig an_config;
821 struct an_ltv_caps an_caps;
822 struct an_ltv_ssidlist an_ssidlist;
823 struct an_ltv_aplist an_aplist;
824 struct an_ltv_key an_temp_keys;
825 struct an_ltv_key an_perm_keys;
826 int an_tx_rate;
827 int an_rxmode;
828 int an_gone;
829 int an_if_flags;
830 u_int8_t an_txbuf[1536];
831 struct an_tx_ring_data an_rdata;
832 struct an_ltv_stats an_stats;
833 struct an_ltv_status an_status;
834 u_int8_t an_associated;
835#ifdef ANCACHE
836 int an_sigitems;
837 struct an_sigcache an_sigcache[MAXANCACHE];
838 int an_nextitem;
839#endif
840 struct callout_handle an_stat_ch;
841 struct mtx an_mtx;
842 device_t an_dev;
843};
844
845#define AN_LOCK(_sc) mtx_enter(&(_sc)->an_mtx, MTX_DEF)
846#define AN_UNLOCK(_sc) mtx_exit(&(_sc)->an_mtx, MTX_DEF)
847
848void an_release_resources __P((device_t));
849int an_alloc_port __P((device_t, int, int));
850int an_alloc_memory __P((device_t, int, int));
851int an_alloc_irq __P((device_t, int, int));
852int an_probe __P((device_t));
853void an_shutdown __P((device_t));
854int an_attach __P((struct an_softc *, int, int));
855void an_stop __P((struct an_softc *));
856
857driver_intr_t an_intr;
858
859#define AN_802_3_OFFSET 0x2E
860#define AN_802_11_OFFSET 0x44
861#define AN_802_11_OFFSET_RAW 0x3C
862
863#define AN_STAT_BADCRC 0x0001
864#define AN_STAT_UNDECRYPTABLE 0x0002
865#define AN_STAT_ERRSTAT 0x0003
866#define AN_STAT_MAC_PORT 0x0700
867#define AN_STAT_1042 0x2000 /* RFC1042 encoded */
868#define AN_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */
869#define AN_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */
870#define AN_RXSTAT_MSG_TYPE 0xE000
871
872#define AN_ENC_TX_802_3 0x00
873#define AN_ENC_TX_802_11 0x11
874#define AN_ENC_TX_E_II 0x0E
875
876#define AN_ENC_TX_1042 0x00
877#define AN_ENC_TX_TUNNEL 0xF8
878
879#define AN_TXCNTL_MACPORT 0x00FF
880#define AN_TXCNTL_STRUCTTYPE 0xFF00
881
882/*
883 * SNAP (sub-network access protocol) constants for transmission
884 * of IP datagrams over IEEE 802 networks, taken from RFC1042.
885 * We need these for the LLC/SNAP header fields in the TX/RX frame
886 * structure.
887 */
888#define AN_SNAP_K1 0xaa /* assigned global SAP for SNAP */
889#define AN_SNAP_K2 0x00
890#define AN_SNAP_CONTROL 0x03 /* unnumbered information format */
891#define AN_SNAP_WORD0 (AN_SNAP_K1 | (AN_SNAP_K1 << 8))
892#define AN_SNAP_WORD1 (AN_SNAP_K2 | (AN_SNAP_CONTROL << 8))
893#define AN_SNAPHDR_LEN 0x6
894
895
| 327#define AN_PSAVE_NONE 0x0000
328#define AN_PSAVE_CAM 0x0001
329#define AN_PSAVE_PSP 0x0002
330#define AN_PSAVE_PSP_CAM 0x0003
331
332#define AN_RADIOTYPE_80211_FH 0x0001
333#define AN_RADIOTYPE_80211_DS 0x0002
334#define AN_RADIOTYPE_LM2000_DS 0x0004
335
336#define AN_DIVERSITY_FACTORY_DEFAULT 0x0000
337#define AN_DIVERSITY_ANTENNA_1_ONLY 0x0001
338#define AN_DIVERSITY_ANTENNA_2_ONLY 0x0002
339#define AN_DIVERSITY_ANTENNA_1_AND_2 0x0003
340
341#define AN_TXPOWER_FACTORY_DEFAULT 0x0000
342#define AN_TXPOWER_50MW 50
343#define AN_TXPOWER_100MW 100
344#define AN_TXPOWER_250MW 250
345
346/*
347 * Valid SSID list. You can specify up to three SSIDs denoting
348 * the service sets that you want to join. The first SSID always
349 * defaults to "tsunami" which is a handy way to detect the
350 * card.
351 */
352#define AN_RID_SSIDLIST 0xFF11
353struct an_ltv_ssidlist {
354 u_int16_t an_len;
355 u_int16_t an_type;
356 u_int16_t an_ssid1_len;
357 char an_ssid1[32];
358 u_int16_t an_ssid2_len;
359 char an_ssid2[32];
360 u_int16_t an_ssid3_len;
361 char an_ssid3[32];
362};
363
364#define AN_DEF_SSID_LEN 7
365#define AN_DEF_SSID "tsunami"
366
367/*
368 * Valid AP list.
369 */
370#define AN_RID_APLIST 0xFF12
371struct an_ltv_aplist {
372 u_int16_t an_len;
373 u_int16_t an_type;
374 u_int8_t an_ap1[8];
375 u_int8_t an_ap2[8];
376 u_int8_t an_ap3[8];
377 u_int8_t an_ap4[8];
378};
379
380/*
381 * Driver name.
382 */
383#define AN_RID_DRVNAME 0xFF13
384struct an_ltv_drvname {
385 u_int16_t an_len;
386 u_int16_t an_type;
387 u_int8_t an_drvname[16];
388};
389
390/*
391 * Frame encapsulation.
392 */
393#define AN_RID_ENCAP 0xFF14
394struct an_rid_encap {
395 u_int16_t an_len;
396 u_int16_t an_type;
397 u_int16_t an_ethertype_default;
398 u_int16_t an_action_default;
399 u_int16_t an_ethertype0;
400 u_int16_t an_action0;
401 u_int16_t an_ethertype1;
402 u_int16_t an_action1;
403 u_int16_t an_ethertype2;
404 u_int16_t an_action2;
405 u_int16_t an_ethertype3;
406 u_int16_t an_action3;
407 u_int16_t an_ethertype4;
408 u_int16_t an_action4;
409 u_int16_t an_ethertype5;
410 u_int16_t an_action5;
411 u_int16_t an_ethertype6;
412 u_int16_t an_action6;
413};
414
415#define AN_ENCAP_ACTION_RX 0x0001
416#define AN_ENCAP_ACTION_TX 0x0002
417
418#define AN_RXENCAP_NONE 0x0000
419#define AN_RXENCAP_RFC1024 0x0001
420
421#define AN_TXENCAP_RFC1024 0x0000
422#define AN_TXENCAP_80211 0x0002
423
424#define AN_RID_WEP_TEMP 0xFF15
425#define AN_RID_WEP_PERM 0xFF16
426
427/*
428 * Actual config, same structure as general config (read only).
429 */
430#define AN_RID_ACTUALCFG 0xFF20
431
432/*
433 * Card capabilities (read only).
434 */
435#define AN_RID_CAPABILITIES 0xFF00
436struct an_ltv_caps {
437 u_int16_t an_len; /* 0x00 */
438 u_int16_t an_type; /* XXXX */
439 u_int8_t an_oui[3]; /* 0x02 */
440 u_int8_t an_rsvd0; /* 0x05 */
441 u_int16_t an_prodnum; /* 0x06 */
442 u_int8_t an_manufname[32]; /* 0x08 */
443 u_int8_t an_prodname[16]; /* 0x28 */
444 u_int8_t an_prodvers[8]; /* 0x38 */
445 u_int8_t an_oemaddr[6]; /* 0x40 */
446 u_int8_t an_aironetaddr[6]; /* 0x46 */
447 u_int16_t an_radiotype; /* 0x4C */
448 u_int16_t an_regdomain; /* 0x4E */
449 u_int8_t an_callid[6]; /* 0x50 */
450 u_int8_t an_rates[8]; /* 0x56 */
451 u_int8_t an_rx_diversity; /* 0x5E */
452 u_int8_t an_tx_diversity; /* 0x5F */
453 u_int16_t an_tx_powerlevels[8]; /* 0x60 */
454 u_int16_t an_hwrev; /* 0x70 */
455 u_int16_t an_hwcaps; /* 0x72 */
456 u_int16_t an_temprange; /* 0x74 */
457 u_int16_t an_fwrev; /* 0x76 */
458 u_int16_t an_fwsubrev; /* 0x78 */
459 u_int16_t an_ifacerev; /* 0x7A */
460 u_int16_t an_softcaps; /* 0x7C */
461 u_int16_t an_bootblockrev; /* 0x7E */
462 u_int16_t an_req_hw_support; /* 0x80 */
463};
464
465/*
466 * Access point (read only)
467 */
468#define AN_RID_APINFO 0xFF01
469struct an_ltv_apinfo {
470 u_int16_t an_len;
471 u_int16_t an_type;
472 u_int16_t an_tim_addr;
473 u_int16_t an_airo_addr;
474};
475
476/*
477 * Radio info (read only).
478 */
479#define AN_RID_RADIOINFO 0xFF02
480struct an_ltv_radioinfo {
481 u_int16_t an_len;
482 u_int16_t an_type;
483 /* ??? */
484};
485
486/*
487 * Status (read only). Note: the manual claims this RID is 108 bytes
488 * long (0x6A is the last datum, which is 2 bytes long) however when
489 * this RID is read from the NIC, it returns a length of 110. To be
490 * on the safe side, this structure is padded with an extra 16-bit
491 * word. (There is a misprint in the manual which says the macaddr
492 * field is 8 bytes long.)
493 *
494 * Also, the channel_set and current_channel fields appear to be
495 * reversed. Either that, or the hop_period field is unused.
496 */
497#define AN_RID_STATUS 0xFF50
498struct an_ltv_status {
499 u_int16_t an_len; /* 0x00 */
500 u_int16_t an_type; /* 0xXX */
501 u_int8_t an_macaddr[6]; /* 0x02 */
502 u_int16_t an_opmode; /* 0x08 */
503 u_int16_t an_errcode; /* 0x0A */
504 u_int16_t an_cur_signal_strength; /* 0x0C */
505 u_int16_t an_ssidlen; /* 0x0E */
506 u_int8_t an_ssid[32]; /* 0x10 */
507 u_int8_t an_ap_name[16]; /* 0x30 */
508 u_int8_t an_cur_bssid[6]; /* 0x40 */
509 u_int8_t an_prev_bssid1[6]; /* 0x46 */
510 u_int8_t an_prev_bssid2[6]; /* 0x4C */
511 u_int8_t an_prev_bssid3[6]; /* 0x52 */
512 u_int16_t an_beacon_period; /* 0x58 */
513 u_int16_t an_dtim_period; /* 0x5A */
514 u_int16_t an_atim_duration; /* 0x5C */
515 u_int16_t an_hop_period; /* 0x5E */
516 u_int16_t an_cur_channel; /* 0x62 */
517 u_int16_t an_channel_set; /* 0x60 */
518 u_int16_t an_hops_to_backbone; /* 0x64 */
519 u_int16_t an_ap_total_load; /* 0x66 */
520 u_int16_t an_our_generated_load; /* 0x68 */
521 u_int16_t an_accumulated_arl; /* 0x6A */
522 u_int16_t an_cur_signal_quality; /* 0x6C */
523 u_int16_t an_current_tx_rate; /* 0x6E */
524 u_int16_t an_ap_device; /* 0x70 */
525 u_int16_t an_normalized_rssi; /* 0x72 */
526 u_int16_t an_short_pre_in_use; /* 0x74 */
527 u_int8_t an_ap_ip_addr[4]; /* 0x76 */
528 u_int16_t an_max_noise_prev_sec; /* 0x7A */
529 u_int16_t an_avg_noise_prev_min; /* 0x7C */
530 u_int16_t an_max_noise_prev_min; /* 0x7E */
531 u_int16_t an_spare[2];
532};
533
534#define AN_STATUS_OPMODE_CONFIGURED 0x0001
535#define AN_STATUS_OPMODE_MAC_ENABLED 0x0002
536#define AN_STATUS_OPMODE_RX_ENABLED 0x0004
537#define AN_STATUS_OPMODE_IN_SYNC 0x0010
538#define AN_STATUS_OPMODE_ASSOCIATED 0x0020
539#define AN_STATUS_OPMODE_ERROR 0x8000
540
541
542/*
543 * Statistics
544 */
545#define AN_RID_16BITS_CUM 0xFF60 /* Cumulative 16-bit stats counters */
546#define AN_RID_16BITS_DELTA 0xFF61 /* 16-bit stats (since last clear) */
547#define AN_RID_16BITS_DELTACLR 0xFF62 /* 16-bit stats, clear on read */
548#define AN_RID_32BITS_CUM 0xFF68 /* Cumulative 32-bit stats counters */
549#define AN_RID_32BITS_DELTA 0xFF69 /* 32-bit stats (since last clear) */
550#define AN_RID_32BITS_DELTACLR 0xFF6A /* 32-bit stats, clear on read */
551
552/*
553 * Grrr. The manual says the statistics record is 384 bytes in length,
554 * but the card says the record is 404 bytes. There's some padding left
555 * at the end of this structure to account for any discrepancies.
556 */
557struct an_ltv_stats {
558 u_int16_t an_fudge;
559 u_int16_t an_len; /* 0x00 */
560 u_int16_t an_type; /* 0xXX */
561 u_int16_t an_spacer; /* 0x02 */
562 u_int32_t an_rx_overruns; /* 0x04 */
563 u_int32_t an_rx_plcp_csum_errs; /* 0x08 */
564 u_int32_t an_rx_plcp_format_errs; /* 0x0C */
565 u_int32_t an_rx_plcp_len_errs; /* 0x10 */
566 u_int32_t an_rx_mac_crc_errs; /* 0x14 */
567 u_int32_t an_rx_mac_crc_ok; /* 0x18 */
568 u_int32_t an_rx_wep_errs; /* 0x1C */
569 u_int32_t an_rx_wep_ok; /* 0x20 */
570 u_int32_t an_retry_long; /* 0x24 */
571 u_int32_t an_retry_short; /* 0x28 */
572 u_int32_t an_retry_max; /* 0x2C */
573 u_int32_t an_no_ack; /* 0x30 */
574 u_int32_t an_no_cts; /* 0x34 */
575 u_int32_t an_rx_ack_ok; /* 0x38 */
576 u_int32_t an_rx_cts_ok; /* 0x3C */
577 u_int32_t an_tx_ack_ok; /* 0x40 */
578 u_int32_t an_tx_rts_ok; /* 0x44 */
579 u_int32_t an_tx_cts_ok; /* 0x48 */
580 u_int32_t an_tx_lmac_mcasts; /* 0x4C */
581 u_int32_t an_tx_lmac_bcasts; /* 0x50 */
582 u_int32_t an_tx_lmac_ucast_frags; /* 0x54 */
583 u_int32_t an_tx_lmac_ucasts; /* 0x58 */
584 u_int32_t an_tx_beacons; /* 0x5C */
585 u_int32_t an_rx_beacons; /* 0x60 */
586 u_int32_t an_tx_single_cols; /* 0x64 */
587 u_int32_t an_tx_multi_cols; /* 0x68 */
588 u_int32_t an_tx_defers_no; /* 0x6C */
589 u_int32_t an_tx_defers_prot; /* 0x70 */
590 u_int32_t an_tx_defers_energy; /* 0x74 */
591 u_int32_t an_rx_dups; /* 0x78 */
592 u_int32_t an_rx_partial; /* 0x7C */
593 u_int32_t an_tx_too_old; /* 0x80 */
594 u_int32_t an_rx_too_old; /* 0x84 */
595 u_int32_t an_lostsync_max_retries;/* 0x88 */
596 u_int32_t an_lostsync_missed_beacons;/* 0x8C */
597 u_int32_t an_lostsync_arl_exceeded;/*0x90 */
598 u_int32_t an_lostsync_deauthed; /* 0x94 */
599 u_int32_t an_lostsync_disassociated;/*0x98 */
600 u_int32_t an_lostsync_tsf_timing; /* 0x9C */
601 u_int32_t an_tx_host_mcasts; /* 0xA0 */
602 u_int32_t an_tx_host_bcasts; /* 0xA4 */
603 u_int32_t an_tx_host_ucasts; /* 0xA8 */
604 u_int32_t an_tx_host_failed; /* 0xAC */
605 u_int32_t an_rx_host_mcasts; /* 0xB0 */
606 u_int32_t an_rx_host_bcasts; /* 0xB4 */
607 u_int32_t an_rx_host_ucasts; /* 0xB8 */
608 u_int32_t an_rx_host_discarded; /* 0xBC */
609 u_int32_t an_tx_hmac_mcasts; /* 0xC0 */
610 u_int32_t an_tx_hmac_bcasts; /* 0xC4 */
611 u_int32_t an_tx_hmac_ucasts; /* 0xC8 */
612 u_int32_t an_tx_hmac_failed; /* 0xCC */
613 u_int32_t an_rx_hmac_mcasts; /* 0xD0 */
614 u_int32_t an_rx_hmac_bcasts; /* 0xD4 */
615 u_int32_t an_rx_hmac_ucasts; /* 0xD8 */
616 u_int32_t an_rx_hmac_discarded; /* 0xDC */
617 u_int32_t an_tx_hmac_accepted; /* 0xE0 */
618 u_int32_t an_ssid_mismatches; /* 0xE4 */
619 u_int32_t an_ap_mismatches; /* 0xE8 */
620 u_int32_t an_rates_mismatches; /* 0xEC */
621 u_int32_t an_auth_rejects; /* 0xF0 */
622 u_int32_t an_auth_timeouts; /* 0xF4 */
623 u_int32_t an_assoc_rejects; /* 0xF8 */
624 u_int32_t an_assoc_timeouts; /* 0xFC */
625 u_int32_t an_reason_outside_table;/* 0x100 */
626 u_int32_t an_reason1; /* 0x104 */
627 u_int32_t an_reason2; /* 0x108 */
628 u_int32_t an_reason3; /* 0x10C */
629 u_int32_t an_reason4; /* 0x110 */
630 u_int32_t an_reason5; /* 0x114 */
631 u_int32_t an_reason6; /* 0x118 */
632 u_int32_t an_reason7; /* 0x11C */
633 u_int32_t an_reason8; /* 0x120 */
634 u_int32_t an_reason9; /* 0x124 */
635 u_int32_t an_reason10; /* 0x128 */
636 u_int32_t an_reason11; /* 0x12C */
637 u_int32_t an_reason12; /* 0x130 */
638 u_int32_t an_reason13; /* 0x134 */
639 u_int32_t an_reason14; /* 0x138 */
640 u_int32_t an_reason15; /* 0x13C */
641 u_int32_t an_reason16; /* 0x140 */
642 u_int32_t an_reason17; /* 0x144 */
643 u_int32_t an_reason18; /* 0x148 */
644 u_int32_t an_reason19; /* 0x14C */
645 u_int32_t an_rx_mgmt_pkts; /* 0x150 */
646 u_int32_t an_tx_mgmt_pkts; /* 0x154 */
647 u_int32_t an_rx_refresh_pkts; /* 0x158 */
648 u_int32_t an_tx_refresh_pkts; /* 0x15C */
649 u_int32_t an_rx_poll_pkts; /* 0x160 */
650 u_int32_t an_tx_poll_pkts; /* 0x164 */
651 u_int32_t an_host_retries; /* 0x168 */
652 u_int32_t an_lostsync_hostreq; /* 0x16C */
653 u_int32_t an_host_tx_bytes; /* 0x170 */
654 u_int32_t an_host_rx_bytes; /* 0x174 */
655 u_int32_t an_uptime_usecs; /* 0x178 */
656 u_int32_t an_uptime_secs; /* 0x17C */
657 u_int32_t an_lostsync_better_ap; /* 0x180 */
658 u_int32_t an_rsvd[10];
659};
660
661/*
662 * Volatile WEP Key
663 */
664#define AN_RID_WEP_VOLATILE 0xFF15 /* Volatile WEP Key */
665struct an_ltv_wepkey {
666 u_int16_t an_len; /* 0x00 */
667 u_int16_t an_type; /* 0xXX */
668 u_int16_t an_key_index; /* 0x02 */
669 u_int8_t an_mac_addr[6]; /* 0x04 */
670 u_int16_t an_key_len; /* 0x0A */
671 u_int8_t an_key[13]; /* 0x0C */
672};
673
674/*
675 * Persistent WEP Key
676 */
677#define AN_RID_WEP_PERSISTENT 0xFF16 /* Persistent WEP Key */
678
679
680/*
681 * Receive frame structure.
682 */
683struct an_rxframe {
684 u_int32_t an_rx_time; /* 0x00 */
685 u_int16_t an_rx_status; /* 0x04 */
686 u_int16_t an_rx_payload_len; /* 0x06 */
687 u_int8_t an_rsvd0; /* 0x08 */
688 u_int8_t an_rx_signal_strength; /* 0x09 */
689 u_int8_t an_rx_rate; /* 0x0A */
690 u_int8_t an_rx_chan; /* 0x0B */
691 u_int8_t an_rx_assoc_cnt; /* 0x0C */
692 u_int8_t an_rsvd1[3]; /* 0x0D */
693 u_int8_t an_plcp_hdr[4]; /* 0x10 */
694 u_int16_t an_frame_ctl; /* 0x14 */
695 u_int16_t an_duration; /* 0x16 */
696 u_int8_t an_addr1[6]; /* 0x18 */
697 u_int8_t an_addr2[6]; /* 0x1E */
698 u_int8_t an_addr3[6]; /* 0x24 */
699 u_int16_t an_seq_ctl; /* 0x2A */
700 u_int8_t an_addr4[6]; /* 0x2C */
701 u_int16_t an_gaplen; /* 0x32 */
702};
703
704#define AN_RXGAP_MAX 8
705
706/*
707 * Transmit frame structure.
708 */
709struct an_txframe {
710 u_int32_t an_tx_sw; /* 0x00 */
711 u_int16_t an_tx_status; /* 0x04 */
712 u_int16_t an_tx_payload_len; /* 0x06 */
713 u_int16_t an_tx_ctl; /* 0x08 */
714 u_int16_t an_tx_assoc_id; /* 0x0A */
715 u_int16_t an_tx_retry; /* 0x0C */
716 u_int8_t an_tx_assoc_cnt; /* 0x0E */
717 u_int8_t an_tx_rate; /* 0x0F */
718 u_int8_t an_tx_max_long_retries; /* 0x10 */
719 u_int8_t an_tx_max_short_retries; /*0x11 */
720 u_int8_t an_rsvd0[2]; /* 0x12 */
721 u_int16_t an_frame_ctl; /* 0x14 */
722 u_int16_t an_duration; /* 0x16 */
723 u_int8_t an_addr1[6]; /* 0x18 */
724 u_int8_t an_addr2[6]; /* 0x1E */
725 u_int8_t an_addr3[6]; /* 0x24 */
726 u_int16_t an_seq_ctl; /* 0x2A */
727 u_int8_t an_addr4[6]; /* 0x2C */
728 u_int16_t an_gaplen; /* 0x32 */
729};
730
731struct an_rxframe_802_3 {
732 u_int16_t an_rx_802_3_status; /* 0x34 */
733 u_int16_t an_rx_802_3_payload_len;/* 0x36 */
734 u_int8_t an_rx_dst_addr[6]; /* 0x38 */
735 u_int8_t an_rx_src_addr[6]; /* 0x3E */
736};
737#define AN_RXGAP_MAX 8
738
739
740struct an_txframe_802_3 {
741/*
742 * Transmit 802.3 header structure.
743 */
744 u_int16_t an_tx_802_3_status; /* 0x34 */
745 u_int16_t an_tx_802_3_payload_len;/* 0x36 */
746 u_int8_t an_tx_dst_addr[6]; /* 0x38 */
747 u_int8_t an_tx_src_addr[6]; /* 0x3E */
748};
749
750#define AN_TXSTAT_EXCESS_RETRY 0x0002
751#define AN_TXSTAT_LIFE_EXCEEDED 0x0004
752#define AN_TXSTAT_AID_FAIL 0x0008
753#define AN_TXSTAT_MAC_DISABLED 0x0010
754#define AN_TXSTAT_ASSOC_LOST 0x0020
755
756#define AN_TXCTL_RSVD 0x0001
757#define AN_TXCTL_TXOK_INTR 0x0002
758#define AN_TXCTL_TXERR_INTR 0x0004
759#define AN_TXCTL_HEADER_TYPE 0x0008
760#define AN_TXCTL_PAYLOAD_TYPE 0x0010
761#define AN_TXCTL_NORELEASE 0x0020
762#define AN_TXCTL_NORETRIES 0x0040
763#define AN_TXCTL_CLEAR_AID 0x0080
764#define AN_TXCTL_STRICT_ORDER 0x0100
765#define AN_TXCTL_USE_RTS 0x0200
766
767#define AN_HEADERTYPE_8023 0x0000
768#define AN_HEADERTYPE_80211 0x0008
769
770#define AN_PAYLOADTYPE_ETHER 0x0000
771#define AN_PAYLOADTYPE_LLC 0x0010
772
773#define AN_TXCTL_80211 \
774 (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_80211| \
775 AN_PAYLOADTYPE_LLC|AN_TXCTL_NORELEASE)
776
777#define AN_TXCTL_8023 \
778 (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_8023| \
779 AN_PAYLOADTYPE_ETHER|AN_TXCTL_NORELEASE)
780
781#define AN_TXGAP_80211 0
782#define AN_TXGAP_8023 0
783
784struct an_802_3_hdr {
785 u_int16_t an_8023_status;
786 u_int16_t an_8023_payload_len;
787 u_int8_t an_8023_dst_addr[6];
788 u_int8_t an_8023_src_addr[6];
789 u_int16_t an_8023_dat[3]; /* SNAP header */
790 u_int16_t an_8023_type;
791};
792
793struct an_snap_hdr {
794 u_int16_t an_snap_dat[3]; /* SNAP header */
795 u_int16_t an_snap_type;
796};
797
798#define AN_TX_RING_CNT 4
799#define AN_INC(x, y) (x) = (x + 1) % y
800
801struct an_tx_ring_data {
802 u_int16_t an_tx_fids[AN_TX_RING_CNT];
803 u_int16_t an_tx_ring[AN_TX_RING_CNT];
804 int an_tx_prod;
805 int an_tx_cons;
806};
807
808struct an_softc {
809 struct arpcom arpcom;
810
811 int an_unit;
812
813 int port_rid; /* resource id for port range */
814 struct resource* port_res; /* resource for port range */
815 int irq_rid; /* resource id for irq */
816 struct resource* irq_res; /* resource for irq */
817 void* irq_handle; /* handle for irq handler */
818
819 bus_space_handle_t an_bhandle_p;
820 bus_space_handle_t an_bhandle;
821 bus_space_tag_t an_btag;
822 struct an_ltv_genconfig an_config;
823 struct an_ltv_caps an_caps;
824 struct an_ltv_ssidlist an_ssidlist;
825 struct an_ltv_aplist an_aplist;
826 struct an_ltv_key an_temp_keys;
827 struct an_ltv_key an_perm_keys;
828 int an_tx_rate;
829 int an_rxmode;
830 int an_gone;
831 int an_if_flags;
832 u_int8_t an_txbuf[1536];
833 struct an_tx_ring_data an_rdata;
834 struct an_ltv_stats an_stats;
835 struct an_ltv_status an_status;
836 u_int8_t an_associated;
837#ifdef ANCACHE
838 int an_sigitems;
839 struct an_sigcache an_sigcache[MAXANCACHE];
840 int an_nextitem;
841#endif
842 struct callout_handle an_stat_ch;
843 struct mtx an_mtx;
844 device_t an_dev;
845};
846
847#define AN_LOCK(_sc) mtx_enter(&(_sc)->an_mtx, MTX_DEF)
848#define AN_UNLOCK(_sc) mtx_exit(&(_sc)->an_mtx, MTX_DEF)
849
850void an_release_resources __P((device_t));
851int an_alloc_port __P((device_t, int, int));
852int an_alloc_memory __P((device_t, int, int));
853int an_alloc_irq __P((device_t, int, int));
854int an_probe __P((device_t));
855void an_shutdown __P((device_t));
856int an_attach __P((struct an_softc *, int, int));
857void an_stop __P((struct an_softc *));
858
859driver_intr_t an_intr;
860
861#define AN_802_3_OFFSET 0x2E
862#define AN_802_11_OFFSET 0x44
863#define AN_802_11_OFFSET_RAW 0x3C
864
865#define AN_STAT_BADCRC 0x0001
866#define AN_STAT_UNDECRYPTABLE 0x0002
867#define AN_STAT_ERRSTAT 0x0003
868#define AN_STAT_MAC_PORT 0x0700
869#define AN_STAT_1042 0x2000 /* RFC1042 encoded */
870#define AN_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */
871#define AN_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */
872#define AN_RXSTAT_MSG_TYPE 0xE000
873
874#define AN_ENC_TX_802_3 0x00
875#define AN_ENC_TX_802_11 0x11
876#define AN_ENC_TX_E_II 0x0E
877
878#define AN_ENC_TX_1042 0x00
879#define AN_ENC_TX_TUNNEL 0xF8
880
881#define AN_TXCNTL_MACPORT 0x00FF
882#define AN_TXCNTL_STRUCTTYPE 0xFF00
883
884/*
885 * SNAP (sub-network access protocol) constants for transmission
886 * of IP datagrams over IEEE 802 networks, taken from RFC1042.
887 * We need these for the LLC/SNAP header fields in the TX/RX frame
888 * structure.
889 */
890#define AN_SNAP_K1 0xaa /* assigned global SAP for SNAP */
891#define AN_SNAP_K2 0x00
892#define AN_SNAP_CONTROL 0x03 /* unnumbered information format */
893#define AN_SNAP_WORD0 (AN_SNAP_K1 | (AN_SNAP_K1 << 8))
894#define AN_SNAP_WORD1 (AN_SNAP_K2 | (AN_SNAP_CONTROL << 8))
895#define AN_SNAPHDR_LEN 0x6
896
897
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