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ahd_pci.c (123019) ahd_pci.c (123579)
1/*
2 * FreeBSD, PCI product support functions
3 *
4 * Copyright (c) 1995-2001 Justin T. Gibbs
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
1/*
2 * FreeBSD, PCI product support functions
3 *
4 * Copyright (c) 1995-2001 Justin T. Gibbs
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $Id: ahd_pci.c,v 1.13 2003/11/03 09:22:17 dfr Exp $
31 * $Id: //depot/aic7xxx/freebsd/dev/aic7xxx/ahd_pci.c#17 $
32 */
33
34#include <sys/cdefs.h>
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/aic7xxx/ahd_pci.c 123019 2003-11-28 05:28:29Z imp $");
35__FBSDID("$FreeBSD: head/sys/dev/aic7xxx/ahd_pci.c 123579 2003-12-17 00:02:10Z gibbs $");
36
37#include <dev/aic7xxx/aic79xx_osm.h>
38
36
37#include <dev/aic7xxx/aic79xx_osm.h>
38
39#define AHD_PCI_IOADDR0 PCIR_BAR(0) /* Primary I/O BAR */
40#define AHD_PCI_MEMADDR PCIR_BAR(1) /* Mem I/O Address */
41#define AHD_PCI_IOADDR1 PCIR_BAR(3) /* Secondary I/O BAR */
42
43static int ahd_pci_probe(device_t dev);
44static int ahd_pci_attach(device_t dev);
45
46static device_method_t ahd_pci_device_methods[] = {
47 /* Device interface */
48 DEVMETHOD(device_probe, ahd_pci_probe),
49 DEVMETHOD(device_attach, ahd_pci_attach),
50 DEVMETHOD(device_detach, ahd_detach),

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108 * Should we bother disabling 39Bit addressing
109 * based on installed memory?
110 */
111 if (sizeof(bus_addr_t) > 4)
112 ahd->flags |= AHD_39BIT_ADDRESSING;
113
114 /* Allocate a dmatag for our SCB DMA maps */
115 /* XXX Should be a child of the PCI bus dma tag */
39static int ahd_pci_probe(device_t dev);
40static int ahd_pci_attach(device_t dev);
41
42static device_method_t ahd_pci_device_methods[] = {
43 /* Device interface */
44 DEVMETHOD(device_probe, ahd_pci_probe),
45 DEVMETHOD(device_attach, ahd_pci_attach),
46 DEVMETHOD(device_detach, ahd_detach),

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104 * Should we bother disabling 39Bit addressing
105 * based on installed memory?
106 */
107 if (sizeof(bus_addr_t) > 4)
108 ahd->flags |= AHD_39BIT_ADDRESSING;
109
110 /* Allocate a dmatag for our SCB DMA maps */
111 /* XXX Should be a child of the PCI bus dma tag */
116 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
112 error = aic_dma_tag_create(ahd, /*parent*/NULL, /*alignment*/1,
117 /*boundary*/0,
118 (ahd->flags & AHD_39BIT_ADDRESSING)
113 /*boundary*/0,
114 (ahd->flags & AHD_39BIT_ADDRESSING)
119 ? 0x7FFFFFFFFFLL
115 ? 0x7FFFFFFFFF
120 : BUS_SPACE_MAXADDR_32BIT,
121 /*highaddr*/BUS_SPACE_MAXADDR,
122 /*filter*/NULL, /*filterarg*/NULL,
123 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
124 /*nsegments*/AHD_NSEG,
125 /*maxsegsz*/AHD_MAXTRANSFER_SIZE,
126 /*flags*/0,
116 : BUS_SPACE_MAXADDR_32BIT,
117 /*highaddr*/BUS_SPACE_MAXADDR,
118 /*filter*/NULL, /*filterarg*/NULL,
119 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
120 /*nsegments*/AHD_NSEG,
121 /*maxsegsz*/AHD_MAXTRANSFER_SIZE,
122 /*flags*/0,
127 /*lockfunc*/busdma_lock_mutex,
128 /*lockarg*/&Giant,
129 &ahd->parent_dmat);
130
131 if (error != 0) {
132 printf("ahd_pci_attach: Could not allocate DMA tag "
133 "- error %d\n", error);
134 ahd_free(ahd);
135 return (ENOMEM);
136 }

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151 struct resource *regs;
152 struct resource *regs2;
153 u_int command;
154 int regs_type;
155 int regs_id;
156 int regs_id2;
157 int allow_memio;
158
123 &ahd->parent_dmat);
124
125 if (error != 0) {
126 printf("ahd_pci_attach: Could not allocate DMA tag "
127 "- error %d\n", error);
128 ahd_free(ahd);
129 return (ENOMEM);
130 }

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145 struct resource *regs;
146 struct resource *regs2;
147 u_int command;
148 int regs_type;
149 int regs_id;
150 int regs_id2;
151 int allow_memio;
152
159 command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1);
153 command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1);
160 regs = NULL;
161 regs2 = NULL;
162 regs_type = 0;
163 regs_id = 0;
164
165 /* Retrieve the per-device 'allow_memio' hint */
166 if (resource_int_value(device_get_name(ahd->dev_softc),
167 device_get_unit(ahd->dev_softc),

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193 * Do a quick test to see if memory mapped
194 * I/O is functioning correctly.
195 */
196 if (error != 0
197 || ahd_pci_test_register_access(ahd) != 0) {
198 device_printf(ahd->dev_softc,
199 "PCI Device %d:%d:%d failed memory "
200 "mapped test. Using PIO.\n",
154 regs = NULL;
155 regs2 = NULL;
156 regs_type = 0;
157 regs_id = 0;
158
159 /* Retrieve the per-device 'allow_memio' hint */
160 if (resource_int_value(device_get_name(ahd->dev_softc),
161 device_get_unit(ahd->dev_softc),

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187 * Do a quick test to see if memory mapped
188 * I/O is functioning correctly.
189 */
190 if (error != 0
191 || ahd_pci_test_register_access(ahd) != 0) {
192 device_printf(ahd->dev_softc,
193 "PCI Device %d:%d:%d failed memory "
194 "mapped test. Using PIO.\n",
201 ahd_get_pci_bus(ahd->dev_softc),
202 ahd_get_pci_slot(ahd->dev_softc),
203 ahd_get_pci_function(ahd->dev_softc));
195 aic_get_pci_bus(ahd->dev_softc),
196 aic_get_pci_slot(ahd->dev_softc),
197 aic_get_pci_function(ahd->dev_softc));
204 bus_release_resource(ahd->dev_softc, regs_type,
205 regs_id, regs);
206 regs = NULL;
207 } else {
208 command &= ~PCIM_CMD_PORTEN;
198 bus_release_resource(ahd->dev_softc, regs_type,
199 regs_id, regs);
200 regs = NULL;
201 } else {
202 command &= ~PCIM_CMD_PORTEN;
209 ahd_pci_write_config(ahd->dev_softc,
203 aic_pci_write_config(ahd->dev_softc,
210 PCIR_COMMAND,
211 command, /*bytes*/1);
212 }
213 }
214 }
215 if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
216 regs_type = SYS_RES_IOPORT;
217 regs_id = AHD_PCI_IOADDR0;

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232 if (regs2 == NULL) {
233 device_printf(ahd->dev_softc,
234 "can't allocate register resources\n");
235 return (ENOMEM);
236 }
237 ahd->tags[1] = rman_get_bustag(regs2);
238 ahd->bshs[1] = rman_get_bushandle(regs2);
239 command &= ~PCIM_CMD_MEMEN;
204 PCIR_COMMAND,
205 command, /*bytes*/1);
206 }
207 }
208 }
209 if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
210 regs_type = SYS_RES_IOPORT;
211 regs_id = AHD_PCI_IOADDR0;

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226 if (regs2 == NULL) {
227 device_printf(ahd->dev_softc,
228 "can't allocate register resources\n");
229 return (ENOMEM);
230 }
231 ahd->tags[1] = rman_get_bustag(regs2);
232 ahd->bshs[1] = rman_get_bushandle(regs2);
233 command &= ~PCIM_CMD_MEMEN;
240 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
234 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
241 command, /*bytes*/1);
242 ahd->platform_data->regs_res_type[1] = regs_type;
243 ahd->platform_data->regs_res_id[1] = regs_id2;
244 ahd->platform_data->regs[1] = regs2;
245 }
246 ahd->platform_data->regs_res_type[0] = regs_type;
247 ahd->platform_data->regs_res_id[0] = regs_id;
248 ahd->platform_data->regs[0] = regs;

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258 ahd->platform_data->irq =
259 bus_alloc_resource(ahd->dev_softc, SYS_RES_IRQ, &zero,
260 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
261 if (ahd->platform_data->irq == NULL)
262 return (ENOMEM);
263 ahd->platform_data->irq_res_type = SYS_RES_IRQ;
264 return (ahd_map_int(ahd));
265}
235 command, /*bytes*/1);
236 ahd->platform_data->regs_res_type[1] = regs_type;
237 ahd->platform_data->regs_res_id[1] = regs_id2;
238 ahd->platform_data->regs[1] = regs2;
239 }
240 ahd->platform_data->regs_res_type[0] = regs_type;
241 ahd->platform_data->regs_res_id[0] = regs_id;
242 ahd->platform_data->regs[0] = regs;

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252 ahd->platform_data->irq =
253 bus_alloc_resource(ahd->dev_softc, SYS_RES_IRQ, &zero,
254 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
255 if (ahd->platform_data->irq == NULL)
256 return (ENOMEM);
257 ahd->platform_data->irq_res_type = SYS_RES_IRQ;
258 return (ahd_map_int(ahd));
259}
266
267void
268ahd_power_state_change(struct ahd_softc *ahd, ahd_power_state new_state)
269{
270 uint32_t cap;
271 u_int cap_offset;
272
273 /*
274 * Traverse the capability list looking for
275 * the power management capability.
276 */
277 cap = 0;
278 cap_offset = ahd_pci_read_config(ahd->dev_softc,
279 PCIR_CAP_PTR, /*bytes*/1);
280 while (cap_offset != 0) {
281
282 cap = ahd_pci_read_config(ahd->dev_softc,
283 cap_offset, /*bytes*/4);
284 if ((cap & 0xFF) == 1
285 && ((cap >> 16) & 0x3) > 0) {
286 uint32_t pm_control;
287
288 pm_control = ahd_pci_read_config(ahd->dev_softc,
289 cap_offset + 4,
290 /*bytes*/2);
291 pm_control &= ~0x3;
292 pm_control |= new_state;
293 ahd_pci_write_config(ahd->dev_softc,
294 cap_offset + 4,
295 pm_control, /*bytes*/2);
296 break;
297 }
298 cap_offset = (cap >> 8) & 0xFF;
299 }
300}