1/*-
2 * Copyright (c) 2000 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2000 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
|
46
47#include <vm/vm.h>
48#include <vm/vm_object.h>
49#include <vm/pmap.h>
50
51#define REG_GARTCTRL 0
52#define REG_APSIZE 1
53#define REG_ATTBASE 2
54
55struct agp_via_softc {
56 struct agp_softc agp;
57 u_int32_t initial_aperture; /* aperture size at startup */
58 struct agp_gatt *gatt;
59 int *regs;
60};
61
62static int via_v2_regs[] = { AGP_VIA_GARTCTRL, AGP_VIA_APSIZE,
63 AGP_VIA_ATTBASE };
64static int via_v3_regs[] = { AGP3_VIA_GARTCTRL, AGP3_VIA_APSIZE,
65 AGP3_VIA_ATTBASE };
66
67static const char*
68agp_via_match(device_t dev)
69{
70 if (pci_get_class(dev) != PCIC_BRIDGE
71 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
72 return NULL;
73
74 if (agp_find_caps(dev) == 0)
75 return NULL;
76
77 switch (pci_get_devid(dev)) {
78 case 0x01981106:
79 return ("VIA 8763 (P4X600) host to PCI bridge");
80 case 0x02591106:
81 return ("VIA PM800/PN800/PM880/PN880 host to PCI bridge");
82 case 0x02691106:
83 return ("VIA KT880 host to PCI bridge");
84 case 0x02961106:
85 return ("VIA 3296 (P4M800) host to PCI bridge");
86 case 0x03051106:
87 return ("VIA 82C8363 (Apollo KT133x/KM133) host to PCI bridge");
88 case 0x03241106:
89 return ("VIA VT3324 (CX700) host to PCI bridge");
90 case 0x03911106:
91 return ("VIA 8371 (Apollo KX133) host to PCI bridge");
92 case 0x05011106:
93 return ("VIA 8501 (Apollo MVP4) host to PCI bridge");
94 case 0x05971106:
95 return ("VIA 82C597 (Apollo VP3) host to PCI bridge");
96 case 0x05981106:
97 return ("VIA 82C598 (Apollo MVP3) host to PCI bridge");
98 case 0x06011106:
99 return ("VIA 8601 (Apollo ProMedia/PLE133Ta) host to PCI bridge");
100 case 0x06051106:
101 return ("VIA 82C694X (Apollo Pro 133A) host to PCI bridge");
102 case 0x06911106:
103 return ("VIA 82C691 (Apollo Pro) host to PCI bridge");
104 case 0x30911106:
105 return ("VIA 8633 (Pro 266) host to PCI bridge");
106 case 0x30991106:
107 return ("VIA 8367 (KT266/KY266x/KT333) host to PCI bridge");
108 case 0x31011106:
109 return ("VIA 8653 (Pro266T) host to PCI bridge");
110 case 0x31121106:
111 return ("VIA 8361 (KLE133) host to PCI bridge");
112 case 0x31161106:
113 return ("VIA XM266 (PM266/KM266) host to PCI bridge");
114 case 0x31231106:
115 return ("VIA 862x (CLE266) host to PCI bridge");
116 case 0x31281106:
117 return ("VIA 8753 (P4X266) host to PCI bridge");
118 case 0x31481106:
119 return ("VIA 8703 (P4M266x/P4N266) host to PCI bridge");
120 case 0x31561106:
121 return ("VIA XN266 (Apollo Pro266) host to PCI bridge");
122 case 0x31681106:
123 return ("VIA 8754 (PT800) host to PCI bridge");
124 case 0x31891106:
125 return ("VIA 8377 (Apollo KT400/KT400A/KT600) host to PCI bridge");
126 case 0x32051106:
127 return ("VIA 8235/8237 (Apollo KM400/KM400A) host to PCI bridge");
128 case 0x32081106:
129 return ("VIA 8783 (PT890) host to PCI bridge");
130 case 0x32581106:
131 return ("VIA PT880 host to PCI bridge");
132 case 0xb1981106:
133 return ("VIA VT83xx/VT87xx/KTxxx/Px8xx host to PCI bridge");
134 };
135
136 return NULL;
137}
138
139static int
140agp_via_probe(device_t dev)
141{
142 const char *desc;
143
144 if (resource_disabled("agp", device_get_unit(dev)))
145 return (ENXIO);
146 desc = agp_via_match(dev);
147 if (desc) {
148 device_set_desc(dev, desc);
149 return BUS_PROBE_DEFAULT;
150 }
151
152 return ENXIO;
153}
154
155static int
156agp_via_attach(device_t dev)
157{
158 struct agp_via_softc *sc = device_get_softc(dev);
159 struct agp_gatt *gatt;
160 int error;
161 u_int32_t agpsel;
162
163 /* XXX: This should be keying off of whether the bridge is AGP3 capable,
164 * rather than a bunch of device ids for chipsets that happen to do 8x.
165 */
166 switch (pci_get_devid(dev)) {
167 case 0x01981106:
168 case 0x02591106:
169 case 0x02691106:
170 case 0x02961106:
171 case 0x03241106:
172 case 0x31231106:
173 case 0x31681106:
174 case 0x31891106:
175 case 0x32051106:
176 case 0x32581106:
177 case 0xb1981106:
178 /* The newer VIA chipsets will select the AGP version based on
179 * what AGP versions the card supports. We still have to
180 * program it using the v2 registers if it has chosen to use
181 * compatibility mode.
182 */
183 agpsel = pci_read_config(dev, AGP_VIA_AGPSEL, 1);
184 if ((agpsel & (1 << 1)) == 0)
185 sc->regs = via_v3_regs;
186 else
187 sc->regs = via_v2_regs;
188 break;
189 default:
190 sc->regs = via_v2_regs;
191 break;
192 }
193
194 error = agp_generic_attach(dev);
195 if (error)
196 return error;
197
198 sc->initial_aperture = AGP_GET_APERTURE(dev);
199
200 for (;;) {
201 gatt = agp_alloc_gatt(dev);
202 if (gatt)
203 break;
204
205 /*
206 * Probably contigmalloc failure. Try reducing the
207 * aperture so that the gatt size reduces.
208 */
209 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
210 agp_generic_detach(dev);
211 return ENOMEM;
212 }
213 }
214 sc->gatt = gatt;
215
216 if (sc->regs == via_v2_regs) {
217 /* Install the gatt. */
218 pci_write_config(dev, sc->regs[REG_ATTBASE], gatt->ag_physical | 3, 4);
219
220 /* Enable the aperture. */
221 pci_write_config(dev, sc->regs[REG_GARTCTRL], 0x0f, 4);
222 } else {
223 u_int32_t gartctrl;
224
225 /* Install the gatt. */
226 pci_write_config(dev, sc->regs[REG_ATTBASE], gatt->ag_physical, 4);
227
228 /* Enable the aperture. */
229 gartctrl = pci_read_config(dev, sc->regs[REG_ATTBASE], 4);
230 pci_write_config(dev, sc->regs[REG_GARTCTRL], gartctrl | (3 << 7), 4);
231 }
232
233 device_printf(dev, "aperture size is %dM\n",
234 sc->initial_aperture / 1024 / 1024);
235
236 return 0;
237}
238
239static int
240agp_via_detach(device_t dev)
241{
242 struct agp_via_softc *sc = device_get_softc(dev);
243
244 agp_free_cdev(dev);
245
246 pci_write_config(dev, sc->regs[REG_GARTCTRL], 0, 4);
247 pci_write_config(dev, sc->regs[REG_ATTBASE], 0, 4);
248 AGP_SET_APERTURE(dev, sc->initial_aperture);
249 agp_free_gatt(sc->gatt);
250 agp_free_res(dev);
251
252 return 0;
253}
254
255static u_int32_t
256agp_via_get_aperture(device_t dev)
257{
258 struct agp_via_softc *sc = device_get_softc(dev);
259 u_int32_t apsize;
260
261 if (sc->regs == via_v2_regs) {
262 apsize = pci_read_config(dev, sc->regs[REG_APSIZE], 1) & 0x1f;
263
264 /*
265 * The size is determined by the number of low bits of
266 * register APBASE which are forced to zero. The low 20 bits
267 * are always forced to zero and each zero bit in the apsize
268 * field just read forces the corresponding bit in the 27:20
269 * to be zero. We calculate the aperture size accordingly.
270 */
271 return (((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1;
272 } else {
273 apsize = pci_read_config(dev, sc->regs[REG_APSIZE], 2) & 0xfff;
274 switch (apsize) {
275 case 0x800:
276 return 0x80000000;
277 case 0xc00:
278 return 0x40000000;
279 case 0xe00:
280 return 0x20000000;
281 case 0xf00:
282 return 0x10000000;
283 case 0xf20:
284 return 0x08000000;
285 case 0xf30:
286 return 0x04000000;
287 case 0xf38:
288 return 0x02000000;
289 default:
290 device_printf(dev, "Invalid aperture setting 0x%x",
291 pci_read_config(dev, sc->regs[REG_APSIZE], 2));
292 return 0;
293 }
294 }
295}
296
297static int
298agp_via_set_aperture(device_t dev, u_int32_t aperture)
299{
300 struct agp_via_softc *sc = device_get_softc(dev);
301 u_int32_t apsize, key, val;
302
303 if (sc->regs == via_v2_regs) {
304 /*
305 * Reverse the magic from get_aperture.
306 */
307 apsize = ((aperture - 1) >> 20) ^ 0xff;
308
309 /*
310 * Double check for sanity.
311 */
312 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
313 return EINVAL;
314
315 pci_write_config(dev, sc->regs[REG_APSIZE], apsize, 1);
316 } else {
317 switch (aperture) {
318 case 0x80000000:
319 key = 0x800;
320 break;
321 case 0x40000000:
322 key = 0xc00;
323 break;
324 case 0x20000000:
325 key = 0xe00;
326 break;
327 case 0x10000000:
328 key = 0xf00;
329 break;
330 case 0x08000000:
331 key = 0xf20;
332 break;
333 case 0x04000000:
334 key = 0xf30;
335 break;
336 case 0x02000000:
337 key = 0xf38;
338 break;
339 default:
340 device_printf(dev, "Invalid aperture size (%dMb)\n",
341 aperture / 1024 / 1024);
342 return EINVAL;
343 }
344 val = pci_read_config(dev, sc->regs[REG_APSIZE], 2);
345 pci_write_config(dev, sc->regs[REG_APSIZE],
346 ((val & ~0xfff) | key), 2);
347 }
348 return 0;
349}
350
351static int
352agp_via_bind_page(device_t dev, int offset, vm_offset_t physical)
353{
354 struct agp_via_softc *sc = device_get_softc(dev);
355
356 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
357 return EINVAL;
358
359 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical;
360 return 0;
361}
362
363static int
364agp_via_unbind_page(device_t dev, int offset)
365{
366 struct agp_via_softc *sc = device_get_softc(dev);
367
368 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
369 return EINVAL;
370
371 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
372 return 0;
373}
374
375static void
376agp_via_flush_tlb(device_t dev)
377{
378 struct agp_via_softc *sc = device_get_softc(dev);
379 u_int32_t gartctrl;
380
381 if (sc->regs == via_v2_regs) {
382 pci_write_config(dev, sc->regs[REG_GARTCTRL], 0x8f, 4);
383 pci_write_config(dev, sc->regs[REG_GARTCTRL], 0x0f, 4);
384 } else {
385 gartctrl = pci_read_config(dev, sc->regs[REG_GARTCTRL], 4);
386 pci_write_config(dev, sc->regs[REG_GARTCTRL], gartctrl &
387 ~(1 << 7), 4);
388 pci_write_config(dev, sc->regs[REG_GARTCTRL], gartctrl, 4);
389 }
390
391}
392
393static device_method_t agp_via_methods[] = {
394 /* Device interface */
395 DEVMETHOD(device_probe, agp_via_probe),
396 DEVMETHOD(device_attach, agp_via_attach),
397 DEVMETHOD(device_detach, agp_via_detach),
398 DEVMETHOD(device_shutdown, bus_generic_shutdown),
399 DEVMETHOD(device_suspend, bus_generic_suspend),
400 DEVMETHOD(device_resume, bus_generic_resume),
401
402 /* AGP interface */
403 DEVMETHOD(agp_get_aperture, agp_via_get_aperture),
404 DEVMETHOD(agp_set_aperture, agp_via_set_aperture),
405 DEVMETHOD(agp_bind_page, agp_via_bind_page),
406 DEVMETHOD(agp_unbind_page, agp_via_unbind_page),
407 DEVMETHOD(agp_flush_tlb, agp_via_flush_tlb),
408 DEVMETHOD(agp_enable, agp_generic_enable),
409 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
410 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
411 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
412 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
413
414 { 0, 0 }
415};
416
417static driver_t agp_via_driver = {
418 "agp",
419 agp_via_methods,
420 sizeof(struct agp_via_softc),
421};
422
423static devclass_t agp_devclass;
424
425DRIVER_MODULE(agp_via, hostb, agp_via_driver, agp_devclass, 0, 0);
426MODULE_DEPEND(agp_via, agp, 1, 1, 1);
427MODULE_DEPEND(agp_via, pci, 1, 1, 1);
| 46
47#include <vm/vm.h>
48#include <vm/vm_object.h>
49#include <vm/pmap.h>
50
51#define REG_GARTCTRL 0
52#define REG_APSIZE 1
53#define REG_ATTBASE 2
54
55struct agp_via_softc {
56 struct agp_softc agp;
57 u_int32_t initial_aperture; /* aperture size at startup */
58 struct agp_gatt *gatt;
59 int *regs;
60};
61
62static int via_v2_regs[] = { AGP_VIA_GARTCTRL, AGP_VIA_APSIZE,
63 AGP_VIA_ATTBASE };
64static int via_v3_regs[] = { AGP3_VIA_GARTCTRL, AGP3_VIA_APSIZE,
65 AGP3_VIA_ATTBASE };
66
67static const char*
68agp_via_match(device_t dev)
69{
70 if (pci_get_class(dev) != PCIC_BRIDGE
71 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
72 return NULL;
73
74 if (agp_find_caps(dev) == 0)
75 return NULL;
76
77 switch (pci_get_devid(dev)) {
78 case 0x01981106:
79 return ("VIA 8763 (P4X600) host to PCI bridge");
80 case 0x02591106:
81 return ("VIA PM800/PN800/PM880/PN880 host to PCI bridge");
82 case 0x02691106:
83 return ("VIA KT880 host to PCI bridge");
84 case 0x02961106:
85 return ("VIA 3296 (P4M800) host to PCI bridge");
86 case 0x03051106:
87 return ("VIA 82C8363 (Apollo KT133x/KM133) host to PCI bridge");
88 case 0x03241106:
89 return ("VIA VT3324 (CX700) host to PCI bridge");
90 case 0x03911106:
91 return ("VIA 8371 (Apollo KX133) host to PCI bridge");
92 case 0x05011106:
93 return ("VIA 8501 (Apollo MVP4) host to PCI bridge");
94 case 0x05971106:
95 return ("VIA 82C597 (Apollo VP3) host to PCI bridge");
96 case 0x05981106:
97 return ("VIA 82C598 (Apollo MVP3) host to PCI bridge");
98 case 0x06011106:
99 return ("VIA 8601 (Apollo ProMedia/PLE133Ta) host to PCI bridge");
100 case 0x06051106:
101 return ("VIA 82C694X (Apollo Pro 133A) host to PCI bridge");
102 case 0x06911106:
103 return ("VIA 82C691 (Apollo Pro) host to PCI bridge");
104 case 0x30911106:
105 return ("VIA 8633 (Pro 266) host to PCI bridge");
106 case 0x30991106:
107 return ("VIA 8367 (KT266/KY266x/KT333) host to PCI bridge");
108 case 0x31011106:
109 return ("VIA 8653 (Pro266T) host to PCI bridge");
110 case 0x31121106:
111 return ("VIA 8361 (KLE133) host to PCI bridge");
112 case 0x31161106:
113 return ("VIA XM266 (PM266/KM266) host to PCI bridge");
114 case 0x31231106:
115 return ("VIA 862x (CLE266) host to PCI bridge");
116 case 0x31281106:
117 return ("VIA 8753 (P4X266) host to PCI bridge");
118 case 0x31481106:
119 return ("VIA 8703 (P4M266x/P4N266) host to PCI bridge");
120 case 0x31561106:
121 return ("VIA XN266 (Apollo Pro266) host to PCI bridge");
122 case 0x31681106:
123 return ("VIA 8754 (PT800) host to PCI bridge");
124 case 0x31891106:
125 return ("VIA 8377 (Apollo KT400/KT400A/KT600) host to PCI bridge");
126 case 0x32051106:
127 return ("VIA 8235/8237 (Apollo KM400/KM400A) host to PCI bridge");
128 case 0x32081106:
129 return ("VIA 8783 (PT890) host to PCI bridge");
130 case 0x32581106:
131 return ("VIA PT880 host to PCI bridge");
132 case 0xb1981106:
133 return ("VIA VT83xx/VT87xx/KTxxx/Px8xx host to PCI bridge");
134 };
135
136 return NULL;
137}
138
139static int
140agp_via_probe(device_t dev)
141{
142 const char *desc;
143
144 if (resource_disabled("agp", device_get_unit(dev)))
145 return (ENXIO);
146 desc = agp_via_match(dev);
147 if (desc) {
148 device_set_desc(dev, desc);
149 return BUS_PROBE_DEFAULT;
150 }
151
152 return ENXIO;
153}
154
155static int
156agp_via_attach(device_t dev)
157{
158 struct agp_via_softc *sc = device_get_softc(dev);
159 struct agp_gatt *gatt;
160 int error;
161 u_int32_t agpsel;
162
163 /* XXX: This should be keying off of whether the bridge is AGP3 capable,
164 * rather than a bunch of device ids for chipsets that happen to do 8x.
165 */
166 switch (pci_get_devid(dev)) {
167 case 0x01981106:
168 case 0x02591106:
169 case 0x02691106:
170 case 0x02961106:
171 case 0x03241106:
172 case 0x31231106:
173 case 0x31681106:
174 case 0x31891106:
175 case 0x32051106:
176 case 0x32581106:
177 case 0xb1981106:
178 /* The newer VIA chipsets will select the AGP version based on
179 * what AGP versions the card supports. We still have to
180 * program it using the v2 registers if it has chosen to use
181 * compatibility mode.
182 */
183 agpsel = pci_read_config(dev, AGP_VIA_AGPSEL, 1);
184 if ((agpsel & (1 << 1)) == 0)
185 sc->regs = via_v3_regs;
186 else
187 sc->regs = via_v2_regs;
188 break;
189 default:
190 sc->regs = via_v2_regs;
191 break;
192 }
193
194 error = agp_generic_attach(dev);
195 if (error)
196 return error;
197
198 sc->initial_aperture = AGP_GET_APERTURE(dev);
199
200 for (;;) {
201 gatt = agp_alloc_gatt(dev);
202 if (gatt)
203 break;
204
205 /*
206 * Probably contigmalloc failure. Try reducing the
207 * aperture so that the gatt size reduces.
208 */
209 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
210 agp_generic_detach(dev);
211 return ENOMEM;
212 }
213 }
214 sc->gatt = gatt;
215
216 if (sc->regs == via_v2_regs) {
217 /* Install the gatt. */
218 pci_write_config(dev, sc->regs[REG_ATTBASE], gatt->ag_physical | 3, 4);
219
220 /* Enable the aperture. */
221 pci_write_config(dev, sc->regs[REG_GARTCTRL], 0x0f, 4);
222 } else {
223 u_int32_t gartctrl;
224
225 /* Install the gatt. */
226 pci_write_config(dev, sc->regs[REG_ATTBASE], gatt->ag_physical, 4);
227
228 /* Enable the aperture. */
229 gartctrl = pci_read_config(dev, sc->regs[REG_ATTBASE], 4);
230 pci_write_config(dev, sc->regs[REG_GARTCTRL], gartctrl | (3 << 7), 4);
231 }
232
233 device_printf(dev, "aperture size is %dM\n",
234 sc->initial_aperture / 1024 / 1024);
235
236 return 0;
237}
238
239static int
240agp_via_detach(device_t dev)
241{
242 struct agp_via_softc *sc = device_get_softc(dev);
243
244 agp_free_cdev(dev);
245
246 pci_write_config(dev, sc->regs[REG_GARTCTRL], 0, 4);
247 pci_write_config(dev, sc->regs[REG_ATTBASE], 0, 4);
248 AGP_SET_APERTURE(dev, sc->initial_aperture);
249 agp_free_gatt(sc->gatt);
250 agp_free_res(dev);
251
252 return 0;
253}
254
255static u_int32_t
256agp_via_get_aperture(device_t dev)
257{
258 struct agp_via_softc *sc = device_get_softc(dev);
259 u_int32_t apsize;
260
261 if (sc->regs == via_v2_regs) {
262 apsize = pci_read_config(dev, sc->regs[REG_APSIZE], 1) & 0x1f;
263
264 /*
265 * The size is determined by the number of low bits of
266 * register APBASE which are forced to zero. The low 20 bits
267 * are always forced to zero and each zero bit in the apsize
268 * field just read forces the corresponding bit in the 27:20
269 * to be zero. We calculate the aperture size accordingly.
270 */
271 return (((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1;
272 } else {
273 apsize = pci_read_config(dev, sc->regs[REG_APSIZE], 2) & 0xfff;
274 switch (apsize) {
275 case 0x800:
276 return 0x80000000;
277 case 0xc00:
278 return 0x40000000;
279 case 0xe00:
280 return 0x20000000;
281 case 0xf00:
282 return 0x10000000;
283 case 0xf20:
284 return 0x08000000;
285 case 0xf30:
286 return 0x04000000;
287 case 0xf38:
288 return 0x02000000;
289 default:
290 device_printf(dev, "Invalid aperture setting 0x%x",
291 pci_read_config(dev, sc->regs[REG_APSIZE], 2));
292 return 0;
293 }
294 }
295}
296
297static int
298agp_via_set_aperture(device_t dev, u_int32_t aperture)
299{
300 struct agp_via_softc *sc = device_get_softc(dev);
301 u_int32_t apsize, key, val;
302
303 if (sc->regs == via_v2_regs) {
304 /*
305 * Reverse the magic from get_aperture.
306 */
307 apsize = ((aperture - 1) >> 20) ^ 0xff;
308
309 /*
310 * Double check for sanity.
311 */
312 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
313 return EINVAL;
314
315 pci_write_config(dev, sc->regs[REG_APSIZE], apsize, 1);
316 } else {
317 switch (aperture) {
318 case 0x80000000:
319 key = 0x800;
320 break;
321 case 0x40000000:
322 key = 0xc00;
323 break;
324 case 0x20000000:
325 key = 0xe00;
326 break;
327 case 0x10000000:
328 key = 0xf00;
329 break;
330 case 0x08000000:
331 key = 0xf20;
332 break;
333 case 0x04000000:
334 key = 0xf30;
335 break;
336 case 0x02000000:
337 key = 0xf38;
338 break;
339 default:
340 device_printf(dev, "Invalid aperture size (%dMb)\n",
341 aperture / 1024 / 1024);
342 return EINVAL;
343 }
344 val = pci_read_config(dev, sc->regs[REG_APSIZE], 2);
345 pci_write_config(dev, sc->regs[REG_APSIZE],
346 ((val & ~0xfff) | key), 2);
347 }
348 return 0;
349}
350
351static int
352agp_via_bind_page(device_t dev, int offset, vm_offset_t physical)
353{
354 struct agp_via_softc *sc = device_get_softc(dev);
355
356 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
357 return EINVAL;
358
359 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical;
360 return 0;
361}
362
363static int
364agp_via_unbind_page(device_t dev, int offset)
365{
366 struct agp_via_softc *sc = device_get_softc(dev);
367
368 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
369 return EINVAL;
370
371 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
372 return 0;
373}
374
375static void
376agp_via_flush_tlb(device_t dev)
377{
378 struct agp_via_softc *sc = device_get_softc(dev);
379 u_int32_t gartctrl;
380
381 if (sc->regs == via_v2_regs) {
382 pci_write_config(dev, sc->regs[REG_GARTCTRL], 0x8f, 4);
383 pci_write_config(dev, sc->regs[REG_GARTCTRL], 0x0f, 4);
384 } else {
385 gartctrl = pci_read_config(dev, sc->regs[REG_GARTCTRL], 4);
386 pci_write_config(dev, sc->regs[REG_GARTCTRL], gartctrl &
387 ~(1 << 7), 4);
388 pci_write_config(dev, sc->regs[REG_GARTCTRL], gartctrl, 4);
389 }
390
391}
392
393static device_method_t agp_via_methods[] = {
394 /* Device interface */
395 DEVMETHOD(device_probe, agp_via_probe),
396 DEVMETHOD(device_attach, agp_via_attach),
397 DEVMETHOD(device_detach, agp_via_detach),
398 DEVMETHOD(device_shutdown, bus_generic_shutdown),
399 DEVMETHOD(device_suspend, bus_generic_suspend),
400 DEVMETHOD(device_resume, bus_generic_resume),
401
402 /* AGP interface */
403 DEVMETHOD(agp_get_aperture, agp_via_get_aperture),
404 DEVMETHOD(agp_set_aperture, agp_via_set_aperture),
405 DEVMETHOD(agp_bind_page, agp_via_bind_page),
406 DEVMETHOD(agp_unbind_page, agp_via_unbind_page),
407 DEVMETHOD(agp_flush_tlb, agp_via_flush_tlb),
408 DEVMETHOD(agp_enable, agp_generic_enable),
409 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
410 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
411 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
412 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
413
414 { 0, 0 }
415};
416
417static driver_t agp_via_driver = {
418 "agp",
419 agp_via_methods,
420 sizeof(struct agp_via_softc),
421};
422
423static devclass_t agp_devclass;
424
425DRIVER_MODULE(agp_via, hostb, agp_via_driver, agp_devclass, 0, 0);
426MODULE_DEPEND(agp_via, agp, 1, 1, 1);
427MODULE_DEPEND(agp_via, pci, 1, 1, 1);
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