58
59#include <vm/vm.h>
60#include <vm/vm_object.h>
61#include <vm/pmap.h>
62
63#include <machine/bus.h>
64#include <machine/resource.h>
65#include <sys/rman.h>
66
67#define NVIDIA_VENDORID 0x10de
68#define NVIDIA_DEVICEID_NFORCE 0x01a4
69#define NVIDIA_DEVICEID_NFORCE2 0x01e0
70
71struct agp_nvidia_softc {
72 struct agp_softc agp;
73 u_int32_t initial_aperture; /* aperture size at startup */
74 struct agp_gatt * gatt;
75
76 device_t dev; /* AGP Controller */
77 device_t mc1_dev; /* Memory Controller */
78 device_t mc2_dev; /* Memory Controller */
79 device_t bdev; /* Bridge */
80
81 u_int32_t wbc_mask;
82 int num_dirs;
83 int num_active_entries;
84 off_t pg_offset;
85};
86
87static const char *agp_nvidia_match(device_t dev);
88static int agp_nvidia_probe(device_t);
89static int agp_nvidia_attach(device_t);
90static int agp_nvidia_detach(device_t);
91static u_int32_t agp_nvidia_get_aperture(device_t);
92static int agp_nvidia_set_aperture(device_t, u_int32_t);
93static int agp_nvidia_bind_page(device_t, int, vm_offset_t);
94static int agp_nvidia_unbind_page(device_t, int);
95
96static int nvidia_init_iorr(u_int32_t, u_int32_t);
97
98static const char *
99agp_nvidia_match (device_t dev)
100{
101 if (pci_get_class(dev) != PCIC_BRIDGE ||
102 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
103 pci_get_vendor(dev) != NVIDIA_VENDORID)
104 return (NULL);
105
106 switch (pci_get_device(dev)) {
107 case NVIDIA_DEVICEID_NFORCE:
108 return ("NVIDIA nForce AGP Controller");
109 case NVIDIA_DEVICEID_NFORCE2:
110 return ("NVIDIA nForce2 AGP Controller");
111 }
112 return (NULL);
113}
114
115static int
116agp_nvidia_probe (device_t dev)
117{
118 const char *desc;
119
120 if (resource_disabled("agp", device_get_unit(dev)))
121 return (ENXIO);
122 desc = agp_nvidia_match(dev);
123 if (desc) {
124 device_set_desc(dev, desc);
125 return (BUS_PROBE_DEFAULT);
126 }
127 return (ENXIO);
128}
129
130static int
131agp_nvidia_attach (device_t dev)
132{
133 struct agp_nvidia_softc *sc = device_get_softc(dev);
134 struct agp_gatt *gatt;
135 u_int32_t apbase;
136 u_int32_t aplimit;
137 u_int32_t temp;
138 int size;
139 int i;
140 int error;
141
142 switch (pci_get_device(dev)) {
143 case NVIDIA_DEVICEID_NFORCE:
144 sc->wbc_mask = 0x00010000;
145 break;
146 case NVIDIA_DEVICEID_NFORCE2:
147 sc->wbc_mask = 0x80000000;
148 break;
149 default:
150 device_printf(dev, "Bad chip id\n");
151 return (ENODEV);
152 }
153
154 /* AGP Controller */
155 sc->dev = dev;
156
157 /* Memory Controller 1 */
158 sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1);
159 if (sc->mc1_dev == NULL) {
160 device_printf(dev,
161 "Unable to find NVIDIA Memory Controller 1.\n");
162 return (ENODEV);
163 }
164
165 /* Memory Controller 2 */
166 sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2);
167 if (sc->mc2_dev == NULL) {
168 device_printf(dev,
169 "Unable to find NVIDIA Memory Controller 2.\n");
170 return (ENODEV);
171 }
172
173 /* AGP Host to PCI Bridge */
174 sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0);
175 if (sc->bdev == NULL) {
176 device_printf(dev,
177 "Unable to find NVIDIA AGP Host to PCI Bridge.\n");
178 return (ENODEV);
179 }
180
181 error = agp_generic_attach(dev);
182 if (error)
183 return (error);
184
185 sc->initial_aperture = AGP_GET_APERTURE(dev);
186
187 for (;;) {
188 gatt = agp_alloc_gatt(dev);
189 if (gatt)
190 break;
191 /*
192 * Probably contigmalloc failure. Try reducing the
193 * aperture so that the gatt size reduces.
194 */
195 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
196 goto fail;
197 }
198 sc->gatt = gatt;
199
200 apbase = rman_get_start(sc->agp.as_aperture);
201 aplimit = apbase + AGP_GET_APERTURE(dev) - 1;
202 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4);
203 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4);
204 pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4);
205 pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4);
206
207 error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev));
208 if (error) {
209 device_printf(dev, "Failed to setup IORRs\n");
210 goto fail;
211 }
212
213 /* directory size is 64k */
214 size = AGP_GET_APERTURE(dev) / 1024 / 1024;
215 sc->num_dirs = size / 64;
216 sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
217 sc->pg_offset = 0;
218 if (sc->num_dirs == 0) {
219 sc->num_dirs = 1;
220 sc->num_active_entries /= (64 / size);
221 sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
222 ~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE;
223 }
224
225 /* (G)ATT Base Address */
226 for (i = 0; i < 8; i++) {
227 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i),
228 (sc->gatt->ag_physical +
229 (i % sc->num_dirs) * 64 * 1024) | 1, 4);
230 }
231
232 /* GTLB Control */
233 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
234 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4);
235
236 /* GART Control */
237 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
238 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4);
239
240 return (0);
241fail:
242 agp_generic_detach(dev);
243 return (ENOMEM);
244}
245
246static int
247agp_nvidia_detach (device_t dev)
248{
249 struct agp_nvidia_softc *sc = device_get_softc(dev);
250 u_int32_t temp;
251
252 agp_free_cdev(dev);
253
254 /* GART Control */
255 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
256 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4);
257
258 /* GTLB Control */
259 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
260 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4);
261
262 /* Put the aperture back the way it started. */
263 AGP_SET_APERTURE(dev, sc->initial_aperture);
264
265 /* restore iorr for previous aperture size */
266 nvidia_init_iorr(rman_get_start(sc->agp.as_aperture),
267 sc->initial_aperture);
268
269 agp_free_gatt(sc->gatt);
270 agp_free_res(dev);
271
272 return (0);
273}
274
275static u_int32_t
276agp_nvidia_get_aperture(device_t dev)
277{
278 switch (pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f) {
279 case 0: return (512 * 1024 * 1024); break;
280 case 8: return (256 * 1024 * 1024); break;
281 case 12: return (128 * 1024 * 1024); break;
282 case 14: return (64 * 1024 * 1024); break;
283 case 15: return (32 * 1024 * 1024); break;
284 default:
285 device_printf(dev, "Invalid aperture setting 0x%x",
286 pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1));
287 return 0;
288 }
289}
290
291static int
292agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
293{
294 u_int8_t val;
295 u_int8_t key;
296
297 switch (aperture) {
298 case (512 * 1024 * 1024): key = 0; break;
299 case (256 * 1024 * 1024): key = 8; break;
300 case (128 * 1024 * 1024): key = 12; break;
301 case (64 * 1024 * 1024): key = 14; break;
302 case (32 * 1024 * 1024): key = 15; break;
303 default:
304 device_printf(dev, "Invalid aperture size (%dMb)\n",
305 aperture / 1024 / 1024);
306 return (EINVAL);
307 }
308 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
309 pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
310
311 return (0);
312}
313
314static int
315agp_nvidia_bind_page(device_t dev, int offset, vm_offset_t physical)
316{
317 struct agp_nvidia_softc *sc = device_get_softc(dev);
318 u_int32_t index;
319
320 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
321 return (EINVAL);
322
323 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
324 sc->gatt->ag_virtual[index] = physical | 1;
325
326 return (0);
327}
328
329static int
330agp_nvidia_unbind_page(device_t dev, int offset)
331{
332 struct agp_nvidia_softc *sc = device_get_softc(dev);
333 u_int32_t index;
334
335 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
336 return (EINVAL);
337
338 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
339 sc->gatt->ag_virtual[index] = 0;
340
341 return (0);
342}
343
344static int
345agp_nvidia_flush_tlb (device_t dev, int offset)
346{
347 struct agp_nvidia_softc *sc;
348 u_int32_t wbc_reg, temp;
349 volatile u_int32_t *ag_virtual;
350 int i;
351
352 sc = (struct agp_nvidia_softc *)device_get_softc(dev);
353
354 if (sc->wbc_mask) {
355 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
356 wbc_reg |= sc->wbc_mask;
357 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4);
358
359 /* Wait no more than 3 seconds. */
360 for (i = 0; i < 3000; i++) {
361 wbc_reg = pci_read_config(sc->mc1_dev,
362 AGP_NVIDIA_1_WBC, 4);
363 if ((sc->wbc_mask & wbc_reg) == 0)
364 break;
365 else
366 DELAY(1000);
367 }
368 if (i == 3000)
369 device_printf(dev,
370 "TLB flush took more than 3 seconds.\n");
371 }
372
373 ag_virtual = (volatile u_int32_t *)sc->gatt->ag_virtual;
374
375 /* Flush TLB entries. */
376 for(i = 0; i < 32 + 1; i++)
377 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
378 for(i = 0; i < 32 + 1; i++)
379 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
380
381 return (0);
382}
383
384#define SYSCFG 0xC0010010
385#define IORR_BASE0 0xC0010016
386#define IORR_MASK0 0xC0010017
387#define AMD_K7_NUM_IORR 2
388
389static int
390nvidia_init_iorr(u_int32_t addr, u_int32_t size)
391{
392 quad_t base, mask, sys;
393 u_int32_t iorr_addr, free_iorr_addr;
394
395 /* Find the iorr that is already used for the addr */
396 /* If not found, determine the uppermost available iorr */
397 free_iorr_addr = AMD_K7_NUM_IORR;
398 for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
399 base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
400 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
401
402 if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
403 break;
404
405 if ((mask & 0x00000800ULL) == 0)
406 free_iorr_addr = iorr_addr;
407 }
408
409 if (iorr_addr >= AMD_K7_NUM_IORR) {
410 iorr_addr = free_iorr_addr;
411 if (iorr_addr >= AMD_K7_NUM_IORR)
412 return (EINVAL);
413 }
414
415 base = (addr & ~0xfff) | 0x18;
416 mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800;
417 wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
418 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
419
420 sys = rdmsr(SYSCFG);
421 sys |= 0x00100000ULL;
422 wrmsr(SYSCFG, sys);
423
424 return (0);
425}
426
427static device_method_t agp_nvidia_methods[] = {
428 /* Device interface */
429 DEVMETHOD(device_probe, agp_nvidia_probe),
430 DEVMETHOD(device_attach, agp_nvidia_attach),
431 DEVMETHOD(device_detach, agp_nvidia_detach),
432 DEVMETHOD(device_shutdown, bus_generic_shutdown),
433 DEVMETHOD(device_suspend, bus_generic_suspend),
434 DEVMETHOD(device_resume, bus_generic_resume),
435
436 /* AGP interface */
437 DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture),
438 DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture),
439 DEVMETHOD(agp_bind_page, agp_nvidia_bind_page),
440 DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page),
441 DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb),
442
443 DEVMETHOD(agp_enable, agp_generic_enable),
444 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
445 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
446 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
447 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
448
449 { 0, 0 }
450};
451
452static driver_t agp_nvidia_driver = {
453 "agp",
454 agp_nvidia_methods,
455 sizeof(struct agp_nvidia_softc),
456};
457
458static devclass_t agp_devclass;
459
460DRIVER_MODULE(agp_nvidia, hostb, agp_nvidia_driver, agp_devclass, 0, 0);
461MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1);
462MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);
| 58
59#include <vm/vm.h>
60#include <vm/vm_object.h>
61#include <vm/pmap.h>
62
63#include <machine/bus.h>
64#include <machine/resource.h>
65#include <sys/rman.h>
66
67#define NVIDIA_VENDORID 0x10de
68#define NVIDIA_DEVICEID_NFORCE 0x01a4
69#define NVIDIA_DEVICEID_NFORCE2 0x01e0
70
71struct agp_nvidia_softc {
72 struct agp_softc agp;
73 u_int32_t initial_aperture; /* aperture size at startup */
74 struct agp_gatt * gatt;
75
76 device_t dev; /* AGP Controller */
77 device_t mc1_dev; /* Memory Controller */
78 device_t mc2_dev; /* Memory Controller */
79 device_t bdev; /* Bridge */
80
81 u_int32_t wbc_mask;
82 int num_dirs;
83 int num_active_entries;
84 off_t pg_offset;
85};
86
87static const char *agp_nvidia_match(device_t dev);
88static int agp_nvidia_probe(device_t);
89static int agp_nvidia_attach(device_t);
90static int agp_nvidia_detach(device_t);
91static u_int32_t agp_nvidia_get_aperture(device_t);
92static int agp_nvidia_set_aperture(device_t, u_int32_t);
93static int agp_nvidia_bind_page(device_t, int, vm_offset_t);
94static int agp_nvidia_unbind_page(device_t, int);
95
96static int nvidia_init_iorr(u_int32_t, u_int32_t);
97
98static const char *
99agp_nvidia_match (device_t dev)
100{
101 if (pci_get_class(dev) != PCIC_BRIDGE ||
102 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
103 pci_get_vendor(dev) != NVIDIA_VENDORID)
104 return (NULL);
105
106 switch (pci_get_device(dev)) {
107 case NVIDIA_DEVICEID_NFORCE:
108 return ("NVIDIA nForce AGP Controller");
109 case NVIDIA_DEVICEID_NFORCE2:
110 return ("NVIDIA nForce2 AGP Controller");
111 }
112 return (NULL);
113}
114
115static int
116agp_nvidia_probe (device_t dev)
117{
118 const char *desc;
119
120 if (resource_disabled("agp", device_get_unit(dev)))
121 return (ENXIO);
122 desc = agp_nvidia_match(dev);
123 if (desc) {
124 device_set_desc(dev, desc);
125 return (BUS_PROBE_DEFAULT);
126 }
127 return (ENXIO);
128}
129
130static int
131agp_nvidia_attach (device_t dev)
132{
133 struct agp_nvidia_softc *sc = device_get_softc(dev);
134 struct agp_gatt *gatt;
135 u_int32_t apbase;
136 u_int32_t aplimit;
137 u_int32_t temp;
138 int size;
139 int i;
140 int error;
141
142 switch (pci_get_device(dev)) {
143 case NVIDIA_DEVICEID_NFORCE:
144 sc->wbc_mask = 0x00010000;
145 break;
146 case NVIDIA_DEVICEID_NFORCE2:
147 sc->wbc_mask = 0x80000000;
148 break;
149 default:
150 device_printf(dev, "Bad chip id\n");
151 return (ENODEV);
152 }
153
154 /* AGP Controller */
155 sc->dev = dev;
156
157 /* Memory Controller 1 */
158 sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1);
159 if (sc->mc1_dev == NULL) {
160 device_printf(dev,
161 "Unable to find NVIDIA Memory Controller 1.\n");
162 return (ENODEV);
163 }
164
165 /* Memory Controller 2 */
166 sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2);
167 if (sc->mc2_dev == NULL) {
168 device_printf(dev,
169 "Unable to find NVIDIA Memory Controller 2.\n");
170 return (ENODEV);
171 }
172
173 /* AGP Host to PCI Bridge */
174 sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0);
175 if (sc->bdev == NULL) {
176 device_printf(dev,
177 "Unable to find NVIDIA AGP Host to PCI Bridge.\n");
178 return (ENODEV);
179 }
180
181 error = agp_generic_attach(dev);
182 if (error)
183 return (error);
184
185 sc->initial_aperture = AGP_GET_APERTURE(dev);
186
187 for (;;) {
188 gatt = agp_alloc_gatt(dev);
189 if (gatt)
190 break;
191 /*
192 * Probably contigmalloc failure. Try reducing the
193 * aperture so that the gatt size reduces.
194 */
195 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
196 goto fail;
197 }
198 sc->gatt = gatt;
199
200 apbase = rman_get_start(sc->agp.as_aperture);
201 aplimit = apbase + AGP_GET_APERTURE(dev) - 1;
202 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4);
203 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4);
204 pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4);
205 pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4);
206
207 error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev));
208 if (error) {
209 device_printf(dev, "Failed to setup IORRs\n");
210 goto fail;
211 }
212
213 /* directory size is 64k */
214 size = AGP_GET_APERTURE(dev) / 1024 / 1024;
215 sc->num_dirs = size / 64;
216 sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
217 sc->pg_offset = 0;
218 if (sc->num_dirs == 0) {
219 sc->num_dirs = 1;
220 sc->num_active_entries /= (64 / size);
221 sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
222 ~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE;
223 }
224
225 /* (G)ATT Base Address */
226 for (i = 0; i < 8; i++) {
227 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i),
228 (sc->gatt->ag_physical +
229 (i % sc->num_dirs) * 64 * 1024) | 1, 4);
230 }
231
232 /* GTLB Control */
233 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
234 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4);
235
236 /* GART Control */
237 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
238 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4);
239
240 return (0);
241fail:
242 agp_generic_detach(dev);
243 return (ENOMEM);
244}
245
246static int
247agp_nvidia_detach (device_t dev)
248{
249 struct agp_nvidia_softc *sc = device_get_softc(dev);
250 u_int32_t temp;
251
252 agp_free_cdev(dev);
253
254 /* GART Control */
255 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
256 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4);
257
258 /* GTLB Control */
259 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
260 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4);
261
262 /* Put the aperture back the way it started. */
263 AGP_SET_APERTURE(dev, sc->initial_aperture);
264
265 /* restore iorr for previous aperture size */
266 nvidia_init_iorr(rman_get_start(sc->agp.as_aperture),
267 sc->initial_aperture);
268
269 agp_free_gatt(sc->gatt);
270 agp_free_res(dev);
271
272 return (0);
273}
274
275static u_int32_t
276agp_nvidia_get_aperture(device_t dev)
277{
278 switch (pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f) {
279 case 0: return (512 * 1024 * 1024); break;
280 case 8: return (256 * 1024 * 1024); break;
281 case 12: return (128 * 1024 * 1024); break;
282 case 14: return (64 * 1024 * 1024); break;
283 case 15: return (32 * 1024 * 1024); break;
284 default:
285 device_printf(dev, "Invalid aperture setting 0x%x",
286 pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1));
287 return 0;
288 }
289}
290
291static int
292agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
293{
294 u_int8_t val;
295 u_int8_t key;
296
297 switch (aperture) {
298 case (512 * 1024 * 1024): key = 0; break;
299 case (256 * 1024 * 1024): key = 8; break;
300 case (128 * 1024 * 1024): key = 12; break;
301 case (64 * 1024 * 1024): key = 14; break;
302 case (32 * 1024 * 1024): key = 15; break;
303 default:
304 device_printf(dev, "Invalid aperture size (%dMb)\n",
305 aperture / 1024 / 1024);
306 return (EINVAL);
307 }
308 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
309 pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
310
311 return (0);
312}
313
314static int
315agp_nvidia_bind_page(device_t dev, int offset, vm_offset_t physical)
316{
317 struct agp_nvidia_softc *sc = device_get_softc(dev);
318 u_int32_t index;
319
320 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
321 return (EINVAL);
322
323 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
324 sc->gatt->ag_virtual[index] = physical | 1;
325
326 return (0);
327}
328
329static int
330agp_nvidia_unbind_page(device_t dev, int offset)
331{
332 struct agp_nvidia_softc *sc = device_get_softc(dev);
333 u_int32_t index;
334
335 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
336 return (EINVAL);
337
338 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
339 sc->gatt->ag_virtual[index] = 0;
340
341 return (0);
342}
343
344static int
345agp_nvidia_flush_tlb (device_t dev, int offset)
346{
347 struct agp_nvidia_softc *sc;
348 u_int32_t wbc_reg, temp;
349 volatile u_int32_t *ag_virtual;
350 int i;
351
352 sc = (struct agp_nvidia_softc *)device_get_softc(dev);
353
354 if (sc->wbc_mask) {
355 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
356 wbc_reg |= sc->wbc_mask;
357 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4);
358
359 /* Wait no more than 3 seconds. */
360 for (i = 0; i < 3000; i++) {
361 wbc_reg = pci_read_config(sc->mc1_dev,
362 AGP_NVIDIA_1_WBC, 4);
363 if ((sc->wbc_mask & wbc_reg) == 0)
364 break;
365 else
366 DELAY(1000);
367 }
368 if (i == 3000)
369 device_printf(dev,
370 "TLB flush took more than 3 seconds.\n");
371 }
372
373 ag_virtual = (volatile u_int32_t *)sc->gatt->ag_virtual;
374
375 /* Flush TLB entries. */
376 for(i = 0; i < 32 + 1; i++)
377 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
378 for(i = 0; i < 32 + 1; i++)
379 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
380
381 return (0);
382}
383
384#define SYSCFG 0xC0010010
385#define IORR_BASE0 0xC0010016
386#define IORR_MASK0 0xC0010017
387#define AMD_K7_NUM_IORR 2
388
389static int
390nvidia_init_iorr(u_int32_t addr, u_int32_t size)
391{
392 quad_t base, mask, sys;
393 u_int32_t iorr_addr, free_iorr_addr;
394
395 /* Find the iorr that is already used for the addr */
396 /* If not found, determine the uppermost available iorr */
397 free_iorr_addr = AMD_K7_NUM_IORR;
398 for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
399 base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
400 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
401
402 if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
403 break;
404
405 if ((mask & 0x00000800ULL) == 0)
406 free_iorr_addr = iorr_addr;
407 }
408
409 if (iorr_addr >= AMD_K7_NUM_IORR) {
410 iorr_addr = free_iorr_addr;
411 if (iorr_addr >= AMD_K7_NUM_IORR)
412 return (EINVAL);
413 }
414
415 base = (addr & ~0xfff) | 0x18;
416 mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800;
417 wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
418 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
419
420 sys = rdmsr(SYSCFG);
421 sys |= 0x00100000ULL;
422 wrmsr(SYSCFG, sys);
423
424 return (0);
425}
426
427static device_method_t agp_nvidia_methods[] = {
428 /* Device interface */
429 DEVMETHOD(device_probe, agp_nvidia_probe),
430 DEVMETHOD(device_attach, agp_nvidia_attach),
431 DEVMETHOD(device_detach, agp_nvidia_detach),
432 DEVMETHOD(device_shutdown, bus_generic_shutdown),
433 DEVMETHOD(device_suspend, bus_generic_suspend),
434 DEVMETHOD(device_resume, bus_generic_resume),
435
436 /* AGP interface */
437 DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture),
438 DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture),
439 DEVMETHOD(agp_bind_page, agp_nvidia_bind_page),
440 DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page),
441 DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb),
442
443 DEVMETHOD(agp_enable, agp_generic_enable),
444 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
445 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
446 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
447 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
448
449 { 0, 0 }
450};
451
452static driver_t agp_nvidia_driver = {
453 "agp",
454 agp_nvidia_methods,
455 sizeof(struct agp_nvidia_softc),
456};
457
458static devclass_t agp_devclass;
459
460DRIVER_MODULE(agp_nvidia, hostb, agp_nvidia_driver, agp_devclass, 0, 0);
461MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1);
462MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);
|