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agp_intel.c (165811) agp_intel.c (165815)
1/*-
2 * Copyright (c) 2000 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2000 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/agp/agp_intel.c 165811 2007-01-05 20:06:40Z jkim $");
28__FBSDID("$FreeBSD: head/sys/dev/agp/agp_intel.c 165815 2007-01-05 22:55:19Z jkim $");
29
30#include "opt_bus.h"
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/malloc.h>
35#include <sys/kernel.h>
36#include <sys/module.h>

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152 */
153 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
154 break;
155 default:
156 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
157 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4);
158 }
159
29
30#include "opt_bus.h"
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/malloc.h>
35#include <sys/kernel.h>
36#include <sys/module.h>

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152 */
153 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
154 break;
155 default:
156 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
157 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4);
158 }
159
160 /* Enable things, clear errors etc. */
160 /* Enable aperture accesses. */
161 switch (type) {
161 switch (type) {
162 case 0x1a218086: /* i840 */
163 case 0x25308086: /* i850 */
164 case 0x25318086: /* i860 */
165 pci_write_config(dev, AGP_INTEL_MCHCFG,
166 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
167 | (1 << 9)), 2);
168 break;
169 case 0x25008086: /* i820 */
170 case 0x25018086: /* i820 */
171 pci_write_config(dev, AGP_INTEL_I820_RDCR,
172 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
173 | (1 << 1)), 1);
174 break;
175 case 0x1a308086: /* i845 */
162 case 0x25008086: /* i820 */
163 case 0x25018086: /* i820 */
164 pci_write_config(dev, AGP_INTEL_I820_RDCR,
165 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
166 | (1 << 1)), 1);
167 break;
168 case 0x1a308086: /* i845 */
169 case 0x25608086: /* i845G */
176 case 0x33408086: /* i855 */
177 case 0x35808086: /* i855GM */
170 case 0x33408086: /* i855 */
171 case 0x35808086: /* i855GM */
178 case 0x255d8086: /* E7205 */
179 case 0x25508086: /* E7505 */
180 case 0x25708086: /* i865 */
181 case 0x25788086: /* i875P */
172 case 0x25708086: /* i865 */
173 case 0x25788086: /* i875P */
182 case 0x25608086: /* i845G */
183 pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
184 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
174 pci_write_config(dev, AGP_INTEL_I845_AGPM,
175 (pci_read_config(dev, AGP_INTEL_I845_AGPM, 1)
185 | (1 << 1)), 1);
186 break;
176 | (1 << 1)), 1);
177 break;
178 case 0x1a218086: /* i840 */
179 case 0x25308086: /* i850 */
180 case 0x25318086: /* i860 */
181 case 0x255d8086: /* E7205 */
182 case 0x25508086: /* E7505 */
183 pci_write_config(dev, AGP_INTEL_MCHCFG,
184 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
185 | (1 << 9)), 2);
186 break;
187 default: /* Intel Generic (maybe) */
188 pci_write_config(dev, AGP_INTEL_NBXCFG,
189 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
190 & ~(1 << 10)) | (1 << 9), 4);
191 }
192
187 default: /* Intel Generic (maybe) */
188 pci_write_config(dev, AGP_INTEL_NBXCFG,
189 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
190 & ~(1 << 10)) | (1 << 9), 4);
191 }
192
193 /* Clear errors. */
193 switch (type) {
194 case 0x1a218086: /* i840 */
195 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
196 break;
197 case 0x25008086: /* i820 */
198 case 0x25018086: /* i820 */
199 case 0x1a308086: /* i845 */
194 switch (type) {
195 case 0x1a218086: /* i840 */
196 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
197 break;
198 case 0x25008086: /* i820 */
199 case 0x25018086: /* i820 */
200 case 0x1a308086: /* i845 */
201 case 0x25608086: /* i845G */
200 case 0x25308086: /* i850 */
201 case 0x33408086: /* i855 */
202 case 0x25308086: /* i850 */
203 case 0x33408086: /* i855 */
202 case 0x255d8086: /* E7205 */
203 case 0x25508086: /* E7505 */
204 case 0x25318086: /* i860 */
205 case 0x25708086: /* i865 */
206 case 0x25788086: /* i875P */
204 case 0x25318086: /* i860 */
205 case 0x25708086: /* i865 */
206 case 0x25788086: /* i875P */
207 case 0x25608086: /* i845G */
207 case 0x255d8086: /* E7205 */
208 case 0x25508086: /* E7505 */
208 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
209 break;
210 default: /* Intel Generic (maybe) */
211 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
212 }
213}
214
215static int

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254
255 return (0);
256}
257
258static int
259agp_intel_detach(device_t dev)
260{
261 struct agp_intel_softc *sc;
209 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
210 break;
211 default: /* Intel Generic (maybe) */
212 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
213 }
214}
215
216static int

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255
256 return (0);
257}
258
259static int
260agp_intel_detach(device_t dev)
261{
262 struct agp_intel_softc *sc;
263 u_int32_t reg;
262 int error;
263
264 sc = device_get_softc(dev);
265
266 error = agp_generic_detach(dev);
267 if (error)
268 return (error);
269
264 int error;
265
266 sc = device_get_softc(dev);
267
268 error = agp_generic_detach(dev);
269 if (error)
270 return (error);
271
272 /* Disable aperture accesses. */
270 switch (pci_get_devid(dev)) {
273 switch (pci_get_devid(dev)) {
271 case 0x1a218086: /* i840 */
272 case 0x25308086: /* i850 */
273 case 0x25318086: /* i860 */
274 printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
275 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
276 & ~(1 << 9)));
277 pci_write_config(dev, AGP_INTEL_MCHCFG,
278 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
279 & ~(1 << 9)), 2);
280 /* FALLTHRU */
281 case 0x25008086: /* i820 */
282 case 0x25018086: /* i820 */
274 case 0x25008086: /* i820 */
275 case 0x25018086: /* i820 */
283 printf("%s: set RDCR to %x\n", __func__, (unsigned)
284 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
285 & ~(1 << 1)));
286 pci_write_config(dev, AGP_INTEL_I820_RDCR,
287 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
288 & ~(1 << 1)), 1);
289 /* FALLTHRU */
276 reg = pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) & ~(1 << 1);
277 printf("%s: set RDCR to %02x\n", __func__, reg & 0xff);
278 pci_write_config(dev, AGP_INTEL_I820_RDCR, reg, 1);
279 break;
290 case 0x1a308086: /* i845 */
291 case 0x25608086: /* i845G */
292 case 0x33408086: /* i855 */
293 case 0x35808086: /* i855GM */
280 case 0x1a308086: /* i845 */
281 case 0x25608086: /* i845G */
282 case 0x33408086: /* i855 */
283 case 0x35808086: /* i855GM */
294 case 0x255d8086: /* E7205 */
295 case 0x25508086: /* E7505 */
296 case 0x25708086: /* i865 */
297 case 0x25788086: /* i875P */
284 case 0x25708086: /* i865 */
285 case 0x25788086: /* i875P */
298 printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
299 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
300 & ~(1 << 1)));
301 pci_write_config(dev, AGP_INTEL_MCHCFG,
302 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
303 & ~(1 << 1)), 1);
304 /* FALLTHRU */
286 reg = pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) & ~(1 << 1);
287 printf("%s: set AGPM to %02x\n", __func__, reg & 0xff);
288 pci_write_config(dev, AGP_INTEL_I845_AGPM, reg, 1);
289 break;
290 case 0x1a218086: /* i840 */
291 case 0x25308086: /* i850 */
292 case 0x25318086: /* i860 */
293 case 0x255d8086: /* E7205 */
294 case 0x25508086: /* E7505 */
295 reg = pci_read_config(dev, AGP_INTEL_MCHCFG, 2) & ~(1 << 9);
296 printf("%s: set MCHCFG to %x04\n", __func__, reg & 0xffff);
297 pci_write_config(dev, AGP_INTEL_MCHCFG, reg, 2);
298 break;
305 default: /* Intel Generic (maybe) */
299 default: /* Intel Generic (maybe) */
306 printf("%s: set NBXCFG to %x\n", __func__,
307 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
308 & ~(1 << 9)));
309 pci_write_config(dev, AGP_INTEL_NBXCFG,
310 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
311 & ~(1 << 9)), 4);
300 reg = pci_read_config(dev, AGP_INTEL_NBXCFG, 4) & ~(1 << 9);
301 printf("%s: set NBXCFG to %08x\n", __func__, reg);
302 pci_write_config(dev, AGP_INTEL_NBXCFG, reg, 4);
312 }
313 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
314 AGP_SET_APERTURE(dev, sc->initial_aperture);
315 agp_free_gatt(sc->gatt);
316
317 return (0);
318}
319

--- 124 unchanged lines hidden --- 		303 }
304 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
305 AGP_SET_APERTURE(dev, sc->initial_aperture);
306 agp_free_gatt(sc->gatt);
307
308 return (0);
309}
310

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