1/*-
2 * Device probe and attach routines for the following
3 * Advanced Systems Inc. SCSI controllers:
4 *
5 * ABP[3]940UW - Bus-Master PCI Ultra-Wide (253 CDB)
6 * ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB/Channel)
7 * ABP970UW - Bus-Master PCI Ultra-Wide (253 CDB)
8 * ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
9 * ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
10 *
11 * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
12 * All rights reserved.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions, and the following disclaimer,
19 * without modification.
20 * 2. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36#include <sys/cdefs.h>
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38
39#include <sys/param.h>
40#include <sys/systm.h>
41#include <sys/kernel.h>
42#include <sys/module.h>
43#include <sys/lock.h>
44#include <sys/mutex.h>
45#include <sys/bus.h>
46
47#include <machine/bus.h>
48#include <machine/resource.h>
49
50#include <sys/rman.h>
51
52#include <dev/pci/pcireg.h>
53#include <dev/pci/pcivar.h>
54
55#include <cam/cam.h>
56#include <cam/scsi/scsi_all.h>
57
58#include <dev/advansys/adwvar.h>
59#include <dev/advansys/adwlib.h>
60#include <dev/advansys/adwmcode.h>
61
62#define ADW_PCI_IOBASE PCIR_BAR(0) /* I/O Address */
63#define ADW_PCI_MEMBASE PCIR_BAR(1) /* Mem I/O Address */
64
65#define PCI_ID_ADVANSYS_3550 0x230010CD00000000ull
66#define PCI_ID_ADVANSYS_38C0800_REV1 0x250010CD00000000ull
67#define PCI_ID_ADVANSYS_38C1600_REV1 0x270010CD00000000ull
68#define PCI_ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
69#define PCI_ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
70
71struct adw_pci_identity;
72typedef int (adw_device_setup_t)(device_t, struct adw_pci_identity *,
73 struct adw_softc *adw);
74
75struct adw_pci_identity {
76 u_int64_t full_id;
77 u_int64_t id_mask;
78 char *name;
79 adw_device_setup_t *setup;
80 const struct adw_mcode *mcode_data;
81 const struct adw_eeprom *default_eeprom;
82};
83
84static adw_device_setup_t adw_asc3550_setup;
85static adw_device_setup_t adw_asc38C0800_setup;
86#ifdef NOTYET
87static adw_device_setup_t adw_asc38C1600_setup;
88#endif
89
90struct adw_pci_identity adw_pci_ident_table[] =
91{
92 /* asc3550 based controllers */
93 {
94 PCI_ID_ADVANSYS_3550,
95 PCI_ID_DEV_VENDOR_MASK,
96 "AdvanSys 3550 Ultra SCSI Adapter",
97 adw_asc3550_setup,
98 &adw_asc3550_mcode_data,
99 &adw_asc3550_default_eeprom
100 },
101 /* asc38C0800 based controllers */
102 {
103 PCI_ID_ADVANSYS_38C0800_REV1,
104 PCI_ID_DEV_VENDOR_MASK,
105 "AdvanSys 38C0800 Ultra2 SCSI Adapter",
106 adw_asc38C0800_setup,
107 &adw_asc38C0800_mcode_data,
108 &adw_asc38C0800_default_eeprom
109 },
110#ifdef NOTYET
111 /* XXX Disabled until I have hardware to test with */
112 /* asc38C1600 based controllers */
113 {
114 PCI_ID_ADVANSYS_38C1600_REV1,
115 PCI_ID_DEV_VENDOR_MASK,
116 "AdvanSys 38C1600 Ultra160 SCSI Adapter",
117 adw_asc38C1600_setup,
118 NULL, /* None provided by vendor thus far */
119 NULL /* None provided by vendor thus far */
120 }
121#endif
122};
123
124static const int adw_num_pci_devs =
125 sizeof(adw_pci_ident_table) / sizeof(*adw_pci_ident_table);
126
127#define ADW_PCI_MAX_DMA_ADDR (0xFFFFFFFFUL)
128#define ADW_PCI_MAX_DMA_COUNT (0xFFFFFFFFUL)
129
130static int adw_pci_probe(device_t dev);
131static int adw_pci_attach(device_t dev);
132
133static device_method_t adw_pci_methods[] = {
134 /* Device interface */
135 DEVMETHOD(device_probe, adw_pci_probe),
136 DEVMETHOD(device_attach, adw_pci_attach),
137 { 0, 0 }
138};
139
140static driver_t adw_pci_driver = {
141 "adw",
142 adw_pci_methods,
143 sizeof(struct adw_softc)
144};
145
146static devclass_t adw_devclass;
147
148DRIVER_MODULE(adw, pci, adw_pci_driver, adw_devclass, 0, 0);
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150
151static __inline u_int64_t
152adw_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
153{
154 u_int64_t id;
155
156 id = subvendor
157 | (subdevice << 16)
158 | ((u_int64_t)vendor << 32)
159 | ((u_int64_t)device << 48);
160
161 return (id);
162}
163
164static struct adw_pci_identity *
165adw_find_pci_device(device_t dev)
166{
167 u_int64_t full_id;
168 struct adw_pci_identity *entry;
169 u_int i;
170
171 full_id = adw_compose_id(pci_get_device(dev),
172 pci_get_vendor(dev),
173 pci_get_subdevice(dev),
174 pci_get_subvendor(dev));
175
176 for (i = 0; i < adw_num_pci_devs; i++) {
177 entry = &adw_pci_ident_table[i];
178 if (entry->full_id == (full_id & entry->id_mask))
179 return (entry);
180 }
181 return (NULL);
182}
183
184static int
185adw_pci_probe(device_t dev)
186{
187 struct adw_pci_identity *entry;
188
189 entry = adw_find_pci_device(dev);
190 if (entry != NULL) {
191 device_set_desc(dev, entry->name);
192 return (BUS_PROBE_DEFAULT);
193 }
194 return (ENXIO);
195}
196
197static int
198adw_pci_attach(device_t dev)
199{
200 struct adw_softc *adw;
201 struct adw_pci_identity *entry;
202 u_int32_t command;
203 struct resource *regs;
204 int regs_type;
205 int regs_id;
206 int error;
207 int zero;
208
209 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
210 entry = adw_find_pci_device(dev);
211 if (entry == NULL)
212 return (ENXIO);
213 regs = NULL;
214 regs_type = 0;
215 regs_id = 0;
216#ifdef ADW_ALLOW_MEMIO
217 if ((command & PCIM_CMD_MEMEN) != 0) {
218 regs_type = SYS_RES_MEMORY;
219 regs_id = ADW_PCI_MEMBASE;
220 regs = bus_alloc_resource_any(dev, regs_type,
221 ®s_id, RF_ACTIVE);
222 }
223#endif
224 if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
225 regs_type = SYS_RES_IOPORT;
226 regs_id = ADW_PCI_IOBASE;
227 regs = bus_alloc_resource_any(dev, regs_type,
228 ®s_id, RF_ACTIVE);
229 }
230
231 if (regs == NULL) {
232 device_printf(dev, "can't allocate register resources\n");
233 return (ENOMEM);
234 }
235
236 adw = adw_alloc(dev, regs, regs_type, regs_id);
237 if (adw == NULL)
238 return(ENOMEM);
239
240 /*
241 * Now that we have access to our registers, just verify that
242 * this really is an AdvanSys device.
243 */
244 if (adw_find_signature(adw) == 0) {
245 adw_free(adw);
246 return (ENXIO);
247 }
248
249 adw_reset_chip(adw);
250
251 error = entry->setup(dev, entry, adw);
252
253 if (error != 0)
254 return (error);
255
256 /* Ensure busmastering is enabled */
257 command |= PCIM_CMD_BUSMASTEREN;
258 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
259
260 /* Allocate a dmatag for our transfer DMA maps */
261 /* XXX Should be a child of the PCI bus dma tag */
262 error = bus_dma_tag_create(
263 /* parent */ NULL,
264 /* alignment */ 1,
265 /* boundary */ 0,
266 /* lowaddr */ ADW_PCI_MAX_DMA_ADDR,
267 /* highaddr */ BUS_SPACE_MAXADDR,
268 /* filter */ NULL,
269 /* filterarg */ NULL,
270 /* maxsize */ BUS_SPACE_MAXSIZE_32BIT,
271 /* nsegments */ ~0,
272 /* maxsegsz */ ADW_PCI_MAX_DMA_COUNT,
273 /* flags */ 0,
274 /* lockfunc */ busdma_lock_mutex,
275 /* lockarg */ &Giant,
276 &adw->parent_dmat);
277
278 adw->init_level++;
279
280 if (error != 0) {
281 printf("%s: Could not allocate DMA tag - error %d\n",
282 adw_name(adw), error);
283 adw_free(adw);
284 return (error);
285 }
286
287 adw->init_level++;
288
289 error = adw_init(adw);
290 if (error != 0) {
291 adw_free(adw);
292 return (error);
293 }
294
295 /*
296 * If the PCI Configuration Command Register "Parity Error Response
297 * Control" Bit was clear (0), then set the microcode variable
298 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
299 * to ignore DMA parity errors.
300 */
301 if ((command & PCIM_CMD_PERRESPEN) == 0)
302 adw_lram_write_16(adw, ADW_MC_CONTROL_FLAG,
303 adw_lram_read_16(adw, ADW_MC_CONTROL_FLAG)
304 | ADW_MC_CONTROL_IGN_PERR);
305
306 zero = 0;
307 adw->irq_res_type = SYS_RES_IRQ;
308 adw->irq = bus_alloc_resource_any(dev, adw->irq_res_type, &zero,
309 RF_ACTIVE | RF_SHAREABLE);
310 if (adw->irq == NULL) {
311 adw_free(adw);
312 return (ENOMEM);
313 }
314
315 error = adw_attach(adw);
316 if (error != 0)
317 adw_free(adw);
318 return (error);
319}
320
321static int
322adw_generic_setup(device_t dev, struct adw_pci_identity *entry,
323 struct adw_softc *adw)
324{
325 adw->channel = pci_get_function(dev) == 1 ? 'B' : 'A';
326 adw->chip = ADW_CHIP_NONE;
327 adw->features = ADW_FENONE;
328 adw->flags = ADW_FNONE;
329 adw->mcode_data = entry->mcode_data;
330 adw->default_eeprom = entry->default_eeprom;
331 return (0);
332}
333
334static int
335adw_asc3550_setup(device_t dev, struct adw_pci_identity *entry,
336 struct adw_softc *adw)
337{
338 int error;
339
340 error = adw_generic_setup(dev, entry, adw);
341 if (error != 0)
342 return (error);
343 adw->chip = ADW_CHIP_ASC3550;
344 adw->features = ADW_ASC3550_FE;
345 adw->memsize = ADW_3550_MEMSIZE;
346 /*
347 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits
348 * sets a FIFO threshold of 128 bytes. This register is
349 * only accessible to the host.
350 */
351 adw_outb(adw, ADW_DMA_CFG0,
352 ADW_DMA_CFG0_START_CTL_EM_FU|ADW_DMA_CFG0_READ_CMD_MRM);
353 adw_outb(adw, ADW_MEM_CFG,
354 adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_8KB);
355 return (0);
356}
357
358static int
359adw_asc38C0800_setup(device_t dev, struct adw_pci_identity *entry,
360 struct adw_softc *adw)
361{
362 int error;
363
364 error = adw_generic_setup(dev, entry, adw);
365 if (error != 0)
366 return (error);
367 /*
368 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and
369 * START_CTL_TH [3:2] bits for the default FIFO threshold.
370 *
371 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
372 *
373 * For DMA Errata #4 set the BC_THRESH_ENB bit.
374 */
375 adw_outb(adw, ADW_DMA_CFG0,
376 ADW_DMA_CFG0_BC_THRESH_ENB|ADW_DMA_CFG0_FIFO_THRESH_80B
377 |ADW_DMA_CFG0_START_CTL_TH|ADW_DMA_CFG0_READ_CMD_MRM);
378 adw_outb(adw, ADW_MEM_CFG,
379 adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_16KB);
380 adw->chip = ADW_CHIP_ASC38C0800;
381 adw->features = ADW_ASC38C0800_FE;
382 adw->memsize = ADW_38C0800_MEMSIZE;
383 return (error);
384}
385
386#ifdef NOTYET
387static int
388adw_asc38C1600_setup(device_t dev, struct adw_pci_identity *entry,
389 struct adw_softc *adw)
390{
391 int error;
392
393 error = adw_generic_setup(dev, entry, adw);
394 if (error != 0)
395 return (error);
396 adw->chip = ADW_CHIP_ASC38C1600;
397 adw->features = ADW_ASC38C1600_FE;
398 adw->memsize = ADW_38C1600_MEMSIZE;
399 return (error);
400}
401#endif
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