1/*-
2 * Device probe and attach routines for the following
3 * Advanced Systems Inc. SCSI controllers:
4 *
5 * ABP[3]940UW - Bus-Master PCI Ultra-Wide (253 CDB)
6 * ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB/Channel)
7 * ABP970UW - Bus-Master PCI Ultra-Wide (253 CDB)
8 * ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
9 * ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
10 *
11 * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
12 * All rights reserved.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions, and the following disclaimer,
19 * without modification.
20 * 2. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36#include <sys/cdefs.h>
| 1/*-
2 * Device probe and attach routines for the following
3 * Advanced Systems Inc. SCSI controllers:
4 *
5 * ABP[3]940UW - Bus-Master PCI Ultra-Wide (253 CDB)
6 * ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB/Channel)
7 * ABP970UW - Bus-Master PCI Ultra-Wide (253 CDB)
8 * ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
9 * ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
10 *
11 * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
12 * All rights reserved.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions, and the following disclaimer,
19 * without modification.
20 * 2. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36#include <sys/cdefs.h>
|
38
39#include <sys/param.h>
40#include <sys/systm.h>
41#include <sys/kernel.h>
42#include <sys/module.h>
43#include <sys/lock.h>
44#include <sys/mutex.h>
45#include <sys/bus.h>
46
47#include <machine/bus.h>
48#include <machine/resource.h>
49
50#include <sys/rman.h>
51
52#include <dev/pci/pcireg.h>
53#include <dev/pci/pcivar.h>
54
55#include <cam/cam.h>
56#include <cam/scsi/scsi_all.h>
57
58#include <dev/advansys/adwvar.h>
59#include <dev/advansys/adwlib.h>
60#include <dev/advansys/adwmcode.h>
61
62#define ADW_PCI_IOBASE PCIR_BAR(0) /* I/O Address */
63#define ADW_PCI_MEMBASE PCIR_BAR(1) /* Mem I/O Address */
64
65#define PCI_ID_ADVANSYS_3550 0x230010CD00000000ull
66#define PCI_ID_ADVANSYS_38C0800_REV1 0x250010CD00000000ull
67#define PCI_ID_ADVANSYS_38C1600_REV1 0x270010CD00000000ull
68#define PCI_ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
69#define PCI_ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
70
71struct adw_pci_identity;
72typedef int (adw_device_setup_t)(device_t, struct adw_pci_identity *,
73 struct adw_softc *adw);
74
75struct adw_pci_identity {
76 u_int64_t full_id;
77 u_int64_t id_mask;
78 char *name;
79 adw_device_setup_t *setup;
80 const struct adw_mcode *mcode_data;
81 const struct adw_eeprom *default_eeprom;
82};
83
84static adw_device_setup_t adw_asc3550_setup;
85static adw_device_setup_t adw_asc38C0800_setup;
86#ifdef NOTYET
87static adw_device_setup_t adw_asc38C1600_setup;
88#endif
89
90struct adw_pci_identity adw_pci_ident_table[] =
91{
92 /* asc3550 based controllers */
93 {
94 PCI_ID_ADVANSYS_3550,
95 PCI_ID_DEV_VENDOR_MASK,
96 "AdvanSys 3550 Ultra SCSI Adapter",
97 adw_asc3550_setup,
98 &adw_asc3550_mcode_data,
99 &adw_asc3550_default_eeprom
100 },
101 /* asc38C0800 based controllers */
102 {
103 PCI_ID_ADVANSYS_38C0800_REV1,
104 PCI_ID_DEV_VENDOR_MASK,
105 "AdvanSys 38C0800 Ultra2 SCSI Adapter",
106 adw_asc38C0800_setup,
107 &adw_asc38C0800_mcode_data,
108 &adw_asc38C0800_default_eeprom
109 },
| 38
39#include <sys/param.h>
40#include <sys/systm.h>
41#include <sys/kernel.h>
42#include <sys/module.h>
43#include <sys/lock.h>
44#include <sys/mutex.h>
45#include <sys/bus.h>
46
47#include <machine/bus.h>
48#include <machine/resource.h>
49
50#include <sys/rman.h>
51
52#include <dev/pci/pcireg.h>
53#include <dev/pci/pcivar.h>
54
55#include <cam/cam.h>
56#include <cam/scsi/scsi_all.h>
57
58#include <dev/advansys/adwvar.h>
59#include <dev/advansys/adwlib.h>
60#include <dev/advansys/adwmcode.h>
61
62#define ADW_PCI_IOBASE PCIR_BAR(0) /* I/O Address */
63#define ADW_PCI_MEMBASE PCIR_BAR(1) /* Mem I/O Address */
64
65#define PCI_ID_ADVANSYS_3550 0x230010CD00000000ull
66#define PCI_ID_ADVANSYS_38C0800_REV1 0x250010CD00000000ull
67#define PCI_ID_ADVANSYS_38C1600_REV1 0x270010CD00000000ull
68#define PCI_ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
69#define PCI_ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
70
71struct adw_pci_identity;
72typedef int (adw_device_setup_t)(device_t, struct adw_pci_identity *,
73 struct adw_softc *adw);
74
75struct adw_pci_identity {
76 u_int64_t full_id;
77 u_int64_t id_mask;
78 char *name;
79 adw_device_setup_t *setup;
80 const struct adw_mcode *mcode_data;
81 const struct adw_eeprom *default_eeprom;
82};
83
84static adw_device_setup_t adw_asc3550_setup;
85static adw_device_setup_t adw_asc38C0800_setup;
86#ifdef NOTYET
87static adw_device_setup_t adw_asc38C1600_setup;
88#endif
89
90struct adw_pci_identity adw_pci_ident_table[] =
91{
92 /* asc3550 based controllers */
93 {
94 PCI_ID_ADVANSYS_3550,
95 PCI_ID_DEV_VENDOR_MASK,
96 "AdvanSys 3550 Ultra SCSI Adapter",
97 adw_asc3550_setup,
98 &adw_asc3550_mcode_data,
99 &adw_asc3550_default_eeprom
100 },
101 /* asc38C0800 based controllers */
102 {
103 PCI_ID_ADVANSYS_38C0800_REV1,
104 PCI_ID_DEV_VENDOR_MASK,
105 "AdvanSys 38C0800 Ultra2 SCSI Adapter",
106 adw_asc38C0800_setup,
107 &adw_asc38C0800_mcode_data,
108 &adw_asc38C0800_default_eeprom
109 },
|
111 /* XXX Disabled until I have hardware to test with */
112 /* asc38C1600 based controllers */
113 {
114 PCI_ID_ADVANSYS_38C1600_REV1,
115 PCI_ID_DEV_VENDOR_MASK,
116 "AdvanSys 38C1600 Ultra160 SCSI Adapter",
117 adw_asc38C1600_setup,
118 NULL, /* None provided by vendor thus far */
119 NULL /* None provided by vendor thus far */
120 }
121#endif
122};
123
124static const int adw_num_pci_devs =
125 sizeof(adw_pci_ident_table) / sizeof(*adw_pci_ident_table);
126
127#define ADW_PCI_MAX_DMA_ADDR (0xFFFFFFFFUL)
128#define ADW_PCI_MAX_DMA_COUNT (0xFFFFFFFFUL)
129
130static int adw_pci_probe(device_t dev);
131static int adw_pci_attach(device_t dev);
132
133static device_method_t adw_pci_methods[] = {
134 /* Device interface */
135 DEVMETHOD(device_probe, adw_pci_probe),
136 DEVMETHOD(device_attach, adw_pci_attach),
137 { 0, 0 }
138};
139
140static driver_t adw_pci_driver = {
141 "adw",
142 adw_pci_methods,
143 sizeof(struct adw_softc)
144};
145
146static devclass_t adw_devclass;
147
148DRIVER_MODULE(adw, pci, adw_pci_driver, adw_devclass, 0, 0);
149
150static __inline u_int64_t
151adw_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
152{
153 u_int64_t id;
154
155 id = subvendor
156 | (subdevice << 16)
157 | ((u_int64_t)vendor << 32)
158 | ((u_int64_t)device << 48);
159
160 return (id);
161}
162
163static struct adw_pci_identity *
164adw_find_pci_device(device_t dev)
165{
166 u_int64_t full_id;
167 struct adw_pci_identity *entry;
168 u_int i;
169
170 full_id = adw_compose_id(pci_get_device(dev),
171 pci_get_vendor(dev),
172 pci_get_subdevice(dev),
173 pci_get_subvendor(dev));
174
175 for (i = 0; i < adw_num_pci_devs; i++) {
176 entry = &adw_pci_ident_table[i];
177 if (entry->full_id == (full_id & entry->id_mask))
178 return (entry);
179 }
180 return (NULL);
181}
182
183static int
184adw_pci_probe(device_t dev)
185{
186 struct adw_pci_identity *entry;
187
188 entry = adw_find_pci_device(dev);
189 if (entry != NULL) {
190 device_set_desc(dev, entry->name);
191 return (BUS_PROBE_DEFAULT);
192 }
193 return (ENXIO);
194}
195
196static int
197adw_pci_attach(device_t dev)
198{
199 struct adw_softc *adw;
200 struct adw_pci_identity *entry;
201 u_int32_t command;
202 struct resource *regs;
203 int regs_type;
204 int regs_id;
205 int error;
206 int zero;
207
208 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
209 entry = adw_find_pci_device(dev);
210 if (entry == NULL)
211 return (ENXIO);
212 regs = NULL;
213 regs_type = 0;
214 regs_id = 0;
215#ifdef ADW_ALLOW_MEMIO
216 if ((command & PCIM_CMD_MEMEN) != 0) {
217 regs_type = SYS_RES_MEMORY;
218 regs_id = ADW_PCI_MEMBASE;
219 regs = bus_alloc_resource_any(dev, regs_type,
220 ®s_id, RF_ACTIVE);
221 }
222#endif
223 if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
224 regs_type = SYS_RES_IOPORT;
225 regs_id = ADW_PCI_IOBASE;
226 regs = bus_alloc_resource_any(dev, regs_type,
227 ®s_id, RF_ACTIVE);
228 }
229
230 if (regs == NULL) {
231 device_printf(dev, "can't allocate register resources\n");
232 return (ENOMEM);
233 }
234
235 adw = adw_alloc(dev, regs, regs_type, regs_id);
236 if (adw == NULL)
237 return(ENOMEM);
238
239 /*
240 * Now that we have access to our registers, just verify that
241 * this really is an AdvanSys device.
242 */
243 if (adw_find_signature(adw) == 0) {
244 adw_free(adw);
245 return (ENXIO);
246 }
247
248 adw_reset_chip(adw);
249
250 error = entry->setup(dev, entry, adw);
251
252 if (error != 0)
253 return (error);
254
255 /* Ensure busmastering is enabled */
256 command |= PCIM_CMD_BUSMASTEREN;
257 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
258
259 /* Allocate a dmatag for our transfer DMA maps */
260 /* XXX Should be a child of the PCI bus dma tag */
261 error = bus_dma_tag_create(
262 /* parent */ NULL,
263 /* alignment */ 1,
264 /* boundary */ 0,
265 /* lowaddr */ ADW_PCI_MAX_DMA_ADDR,
266 /* highaddr */ BUS_SPACE_MAXADDR,
267 /* filter */ NULL,
268 /* filterarg */ NULL,
269 /* maxsize */ BUS_SPACE_MAXSIZE_32BIT,
270 /* nsegments */ ~0,
271 /* maxsegsz */ ADW_PCI_MAX_DMA_COUNT,
272 /* flags */ 0,
273 /* lockfunc */ busdma_lock_mutex,
274 /* lockarg */ &Giant,
275 &adw->parent_dmat);
276
277 adw->init_level++;
278
279 if (error != 0) {
280 printf("%s: Could not allocate DMA tag - error %d\n",
281 adw_name(adw), error);
282 adw_free(adw);
283 return (error);
284 }
285
286 adw->init_level++;
287
288 error = adw_init(adw);
289 if (error != 0) {
290 adw_free(adw);
291 return (error);
292 }
293
294 /*
295 * If the PCI Configuration Command Register "Parity Error Response
296 * Control" Bit was clear (0), then set the microcode variable
297 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
298 * to ignore DMA parity errors.
299 */
300 if ((command & PCIM_CMD_PERRESPEN) == 0)
301 adw_lram_write_16(adw, ADW_MC_CONTROL_FLAG,
302 adw_lram_read_16(adw, ADW_MC_CONTROL_FLAG)
303 | ADW_MC_CONTROL_IGN_PERR);
304
305 zero = 0;
306 adw->irq_res_type = SYS_RES_IRQ;
307 adw->irq = bus_alloc_resource_any(dev, adw->irq_res_type, &zero,
308 RF_ACTIVE | RF_SHAREABLE);
309 if (adw->irq == NULL) {
310 adw_free(adw);
311 return (ENOMEM);
312 }
313
314 error = adw_attach(adw);
315 if (error != 0)
316 adw_free(adw);
317 return (error);
318}
319
320static int
321adw_generic_setup(device_t dev, struct adw_pci_identity *entry,
322 struct adw_softc *adw)
323{
324 adw->channel = pci_get_function(dev) == 1 ? 'B' : 'A';
325 adw->chip = ADW_CHIP_NONE;
326 adw->features = ADW_FENONE;
327 adw->flags = ADW_FNONE;
328 adw->mcode_data = entry->mcode_data;
329 adw->default_eeprom = entry->default_eeprom;
330 return (0);
331}
332
333static int
334adw_asc3550_setup(device_t dev, struct adw_pci_identity *entry,
335 struct adw_softc *adw)
336{
337 int error;
338
339 error = adw_generic_setup(dev, entry, adw);
340 if (error != 0)
341 return (error);
342 adw->chip = ADW_CHIP_ASC3550;
343 adw->features = ADW_ASC3550_FE;
344 adw->memsize = ADW_3550_MEMSIZE;
345 /*
346 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits
347 * sets a FIFO threshold of 128 bytes. This register is
348 * only accessible to the host.
349 */
350 adw_outb(adw, ADW_DMA_CFG0,
351 ADW_DMA_CFG0_START_CTL_EM_FU|ADW_DMA_CFG0_READ_CMD_MRM);
352 adw_outb(adw, ADW_MEM_CFG,
353 adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_8KB);
354 return (0);
355}
356
357static int
358adw_asc38C0800_setup(device_t dev, struct adw_pci_identity *entry,
359 struct adw_softc *adw)
360{
361 int error;
362
363 error = adw_generic_setup(dev, entry, adw);
364 if (error != 0)
365 return (error);
366 /*
367 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and
368 * START_CTL_TH [3:2] bits for the default FIFO threshold.
369 *
370 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
371 *
372 * For DMA Errata #4 set the BC_THRESH_ENB bit.
373 */
374 adw_outb(adw, ADW_DMA_CFG0,
375 ADW_DMA_CFG0_BC_THRESH_ENB|ADW_DMA_CFG0_FIFO_THRESH_80B
376 |ADW_DMA_CFG0_START_CTL_TH|ADW_DMA_CFG0_READ_CMD_MRM);
377 adw_outb(adw, ADW_MEM_CFG,
378 adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_16KB);
379 adw->chip = ADW_CHIP_ASC38C0800;
380 adw->features = ADW_ASC38C0800_FE;
381 adw->memsize = ADW_38C0800_MEMSIZE;
382 return (error);
383}
384
385#ifdef NOTYET
386static int
387adw_asc38C1600_setup(device_t dev, struct adw_pci_identity *entry,
388 struct adw_softc *adw)
389{
390 int error;
391
392 error = adw_generic_setup(dev, entry, adw);
393 if (error != 0)
394 return (error);
395 adw->chip = ADW_CHIP_ASC38C1600;
396 adw->features = ADW_ASC38C1600_FE;
397 adw->memsize = ADW_38C1600_MEMSIZE;
398 return (error);
399}
400#endif
| 111 /* XXX Disabled until I have hardware to test with */
112 /* asc38C1600 based controllers */
113 {
114 PCI_ID_ADVANSYS_38C1600_REV1,
115 PCI_ID_DEV_VENDOR_MASK,
116 "AdvanSys 38C1600 Ultra160 SCSI Adapter",
117 adw_asc38C1600_setup,
118 NULL, /* None provided by vendor thus far */
119 NULL /* None provided by vendor thus far */
120 }
121#endif
122};
123
124static const int adw_num_pci_devs =
125 sizeof(adw_pci_ident_table) / sizeof(*adw_pci_ident_table);
126
127#define ADW_PCI_MAX_DMA_ADDR (0xFFFFFFFFUL)
128#define ADW_PCI_MAX_DMA_COUNT (0xFFFFFFFFUL)
129
130static int adw_pci_probe(device_t dev);
131static int adw_pci_attach(device_t dev);
132
133static device_method_t adw_pci_methods[] = {
134 /* Device interface */
135 DEVMETHOD(device_probe, adw_pci_probe),
136 DEVMETHOD(device_attach, adw_pci_attach),
137 { 0, 0 }
138};
139
140static driver_t adw_pci_driver = {
141 "adw",
142 adw_pci_methods,
143 sizeof(struct adw_softc)
144};
145
146static devclass_t adw_devclass;
147
148DRIVER_MODULE(adw, pci, adw_pci_driver, adw_devclass, 0, 0);
149
150static __inline u_int64_t
151adw_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
152{
153 u_int64_t id;
154
155 id = subvendor
156 | (subdevice << 16)
157 | ((u_int64_t)vendor << 32)
158 | ((u_int64_t)device << 48);
159
160 return (id);
161}
162
163static struct adw_pci_identity *
164adw_find_pci_device(device_t dev)
165{
166 u_int64_t full_id;
167 struct adw_pci_identity *entry;
168 u_int i;
169
170 full_id = adw_compose_id(pci_get_device(dev),
171 pci_get_vendor(dev),
172 pci_get_subdevice(dev),
173 pci_get_subvendor(dev));
174
175 for (i = 0; i < adw_num_pci_devs; i++) {
176 entry = &adw_pci_ident_table[i];
177 if (entry->full_id == (full_id & entry->id_mask))
178 return (entry);
179 }
180 return (NULL);
181}
182
183static int
184adw_pci_probe(device_t dev)
185{
186 struct adw_pci_identity *entry;
187
188 entry = adw_find_pci_device(dev);
189 if (entry != NULL) {
190 device_set_desc(dev, entry->name);
191 return (BUS_PROBE_DEFAULT);
192 }
193 return (ENXIO);
194}
195
196static int
197adw_pci_attach(device_t dev)
198{
199 struct adw_softc *adw;
200 struct adw_pci_identity *entry;
201 u_int32_t command;
202 struct resource *regs;
203 int regs_type;
204 int regs_id;
205 int error;
206 int zero;
207
208 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
209 entry = adw_find_pci_device(dev);
210 if (entry == NULL)
211 return (ENXIO);
212 regs = NULL;
213 regs_type = 0;
214 regs_id = 0;
215#ifdef ADW_ALLOW_MEMIO
216 if ((command & PCIM_CMD_MEMEN) != 0) {
217 regs_type = SYS_RES_MEMORY;
218 regs_id = ADW_PCI_MEMBASE;
219 regs = bus_alloc_resource_any(dev, regs_type,
220 ®s_id, RF_ACTIVE);
221 }
222#endif
223 if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
224 regs_type = SYS_RES_IOPORT;
225 regs_id = ADW_PCI_IOBASE;
226 regs = bus_alloc_resource_any(dev, regs_type,
227 ®s_id, RF_ACTIVE);
228 }
229
230 if (regs == NULL) {
231 device_printf(dev, "can't allocate register resources\n");
232 return (ENOMEM);
233 }
234
235 adw = adw_alloc(dev, regs, regs_type, regs_id);
236 if (adw == NULL)
237 return(ENOMEM);
238
239 /*
240 * Now that we have access to our registers, just verify that
241 * this really is an AdvanSys device.
242 */
243 if (adw_find_signature(adw) == 0) {
244 adw_free(adw);
245 return (ENXIO);
246 }
247
248 adw_reset_chip(adw);
249
250 error = entry->setup(dev, entry, adw);
251
252 if (error != 0)
253 return (error);
254
255 /* Ensure busmastering is enabled */
256 command |= PCIM_CMD_BUSMASTEREN;
257 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
258
259 /* Allocate a dmatag for our transfer DMA maps */
260 /* XXX Should be a child of the PCI bus dma tag */
261 error = bus_dma_tag_create(
262 /* parent */ NULL,
263 /* alignment */ 1,
264 /* boundary */ 0,
265 /* lowaddr */ ADW_PCI_MAX_DMA_ADDR,
266 /* highaddr */ BUS_SPACE_MAXADDR,
267 /* filter */ NULL,
268 /* filterarg */ NULL,
269 /* maxsize */ BUS_SPACE_MAXSIZE_32BIT,
270 /* nsegments */ ~0,
271 /* maxsegsz */ ADW_PCI_MAX_DMA_COUNT,
272 /* flags */ 0,
273 /* lockfunc */ busdma_lock_mutex,
274 /* lockarg */ &Giant,
275 &adw->parent_dmat);
276
277 adw->init_level++;
278
279 if (error != 0) {
280 printf("%s: Could not allocate DMA tag - error %d\n",
281 adw_name(adw), error);
282 adw_free(adw);
283 return (error);
284 }
285
286 adw->init_level++;
287
288 error = adw_init(adw);
289 if (error != 0) {
290 adw_free(adw);
291 return (error);
292 }
293
294 /*
295 * If the PCI Configuration Command Register "Parity Error Response
296 * Control" Bit was clear (0), then set the microcode variable
297 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
298 * to ignore DMA parity errors.
299 */
300 if ((command & PCIM_CMD_PERRESPEN) == 0)
301 adw_lram_write_16(adw, ADW_MC_CONTROL_FLAG,
302 adw_lram_read_16(adw, ADW_MC_CONTROL_FLAG)
303 | ADW_MC_CONTROL_IGN_PERR);
304
305 zero = 0;
306 adw->irq_res_type = SYS_RES_IRQ;
307 adw->irq = bus_alloc_resource_any(dev, adw->irq_res_type, &zero,
308 RF_ACTIVE | RF_SHAREABLE);
309 if (adw->irq == NULL) {
310 adw_free(adw);
311 return (ENOMEM);
312 }
313
314 error = adw_attach(adw);
315 if (error != 0)
316 adw_free(adw);
317 return (error);
318}
319
320static int
321adw_generic_setup(device_t dev, struct adw_pci_identity *entry,
322 struct adw_softc *adw)
323{
324 adw->channel = pci_get_function(dev) == 1 ? 'B' : 'A';
325 adw->chip = ADW_CHIP_NONE;
326 adw->features = ADW_FENONE;
327 adw->flags = ADW_FNONE;
328 adw->mcode_data = entry->mcode_data;
329 adw->default_eeprom = entry->default_eeprom;
330 return (0);
331}
332
333static int
334adw_asc3550_setup(device_t dev, struct adw_pci_identity *entry,
335 struct adw_softc *adw)
336{
337 int error;
338
339 error = adw_generic_setup(dev, entry, adw);
340 if (error != 0)
341 return (error);
342 adw->chip = ADW_CHIP_ASC3550;
343 adw->features = ADW_ASC3550_FE;
344 adw->memsize = ADW_3550_MEMSIZE;
345 /*
346 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits
347 * sets a FIFO threshold of 128 bytes. This register is
348 * only accessible to the host.
349 */
350 adw_outb(adw, ADW_DMA_CFG0,
351 ADW_DMA_CFG0_START_CTL_EM_FU|ADW_DMA_CFG0_READ_CMD_MRM);
352 adw_outb(adw, ADW_MEM_CFG,
353 adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_8KB);
354 return (0);
355}
356
357static int
358adw_asc38C0800_setup(device_t dev, struct adw_pci_identity *entry,
359 struct adw_softc *adw)
360{
361 int error;
362
363 error = adw_generic_setup(dev, entry, adw);
364 if (error != 0)
365 return (error);
366 /*
367 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and
368 * START_CTL_TH [3:2] bits for the default FIFO threshold.
369 *
370 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
371 *
372 * For DMA Errata #4 set the BC_THRESH_ENB bit.
373 */
374 adw_outb(adw, ADW_DMA_CFG0,
375 ADW_DMA_CFG0_BC_THRESH_ENB|ADW_DMA_CFG0_FIFO_THRESH_80B
376 |ADW_DMA_CFG0_START_CTL_TH|ADW_DMA_CFG0_READ_CMD_MRM);
377 adw_outb(adw, ADW_MEM_CFG,
378 adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_16KB);
379 adw->chip = ADW_CHIP_ASC38C0800;
380 adw->features = ADW_ASC38C0800_FE;
381 adw->memsize = ADW_38C0800_MEMSIZE;
382 return (error);
383}
384
385#ifdef NOTYET
386static int
387adw_asc38C1600_setup(device_t dev, struct adw_pci_identity *entry,
388 struct adw_softc *adw)
389{
390 int error;
391
392 error = adw_generic_setup(dev, entry, adw);
393 if (error != 0)
394 return (error);
395 adw->chip = ADW_CHIP_ASC38C1600;
396 adw->features = ADW_ASC38C1600_FE;
397 adw->memsize = ADW_38C1600_MEMSIZE;
398 return (error);
399}
400#endif
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