1/*
2 * Device probe and attach routines for the following
3 * Advanced Systems Inc. SCSI controllers:
4 *
5 * Connectivity Products:
6 * ABP902/3902 - Bus-Master PCI (16 CDB)
7 * ABP3905 - Bus-Master PCI (16 CDB)
8 * ABP915 - Bus-Master PCI (16 CDB)
9 * ABP920 - Bus-Master PCI (16 CDB)
10 * ABP3922 - Bus-Master PCI (16 CDB)
11 * ABP3925 - Bus-Master PCI (16 CDB)
12 * ABP930 - Bus-Master PCI (16 CDB) *
13 * ABP930U - Bus-Master PCI Ultra (16 CDB)
14 * ABP930UA - Bus-Master PCI Ultra (16 CDB)
15 * ABP960 - Bus-Master PCI MAC/PC (16 CDB) **
16 * ABP960U - Bus-Master PCI MAC/PC (16 CDB) **
17 *
18 * Single Channel Products:
19 * ABP940 - Bus-Master PCI (240 CDB)
20 * ABP940U - Bus-Master PCI Ultra (240 CDB)
21 * ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB)
22 * ABP3960UA - Bus-Master PCI MAC/PC (240 CDB)
23 * ABP970 - Bus-Master PCI MAC/PC (240 CDB)
24 * ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
25 *
26 * Dual Channel Products:
27 * ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
28 * ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
29 * ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
30 * ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.)
31 *
32 * Footnotes:
33 * * This board has been sold by SIIG as the Fast SCSI Pro PCI.
34 * ** This board has been sold by Iomega as a Jaz Jet PCI adapter.
35 *
36 * Copyright (c) 1997 Justin Gibbs.
37 * All rights reserved.
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 * 1. Redistributions of source code must retain the above copyright
43 * notice, this list of conditions, and the following disclaimer,
44 * without modification.
45 * 2. The name of the author may not be used to endorse or promote products
46 * derived from this software without specific prior written permission.
47 *
48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
52 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
58 * SUCH DAMAGE.
59 */
60
61#include <sys/cdefs.h>
| 1/*
2 * Device probe and attach routines for the following
3 * Advanced Systems Inc. SCSI controllers:
4 *
5 * Connectivity Products:
6 * ABP902/3902 - Bus-Master PCI (16 CDB)
7 * ABP3905 - Bus-Master PCI (16 CDB)
8 * ABP915 - Bus-Master PCI (16 CDB)
9 * ABP920 - Bus-Master PCI (16 CDB)
10 * ABP3922 - Bus-Master PCI (16 CDB)
11 * ABP3925 - Bus-Master PCI (16 CDB)
12 * ABP930 - Bus-Master PCI (16 CDB) *
13 * ABP930U - Bus-Master PCI Ultra (16 CDB)
14 * ABP930UA - Bus-Master PCI Ultra (16 CDB)
15 * ABP960 - Bus-Master PCI MAC/PC (16 CDB) **
16 * ABP960U - Bus-Master PCI MAC/PC (16 CDB) **
17 *
18 * Single Channel Products:
19 * ABP940 - Bus-Master PCI (240 CDB)
20 * ABP940U - Bus-Master PCI Ultra (240 CDB)
21 * ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB)
22 * ABP3960UA - Bus-Master PCI MAC/PC (240 CDB)
23 * ABP970 - Bus-Master PCI MAC/PC (240 CDB)
24 * ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
25 *
26 * Dual Channel Products:
27 * ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
28 * ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
29 * ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
30 * ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.)
31 *
32 * Footnotes:
33 * * This board has been sold by SIIG as the Fast SCSI Pro PCI.
34 * ** This board has been sold by Iomega as a Jaz Jet PCI adapter.
35 *
36 * Copyright (c) 1997 Justin Gibbs.
37 * All rights reserved.
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 * 1. Redistributions of source code must retain the above copyright
43 * notice, this list of conditions, and the following disclaimer,
44 * without modification.
45 * 2. The name of the author may not be used to endorse or promote products
46 * derived from this software without specific prior written permission.
47 *
48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
52 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
58 * SUCH DAMAGE.
59 */
60
61#include <sys/cdefs.h>
|
83
84#define PCI_DEVICE_ID_ADVANSYS_1200A 0x110010CD
85#define PCI_DEVICE_ID_ADVANSYS_1200B 0x120010CD
86#define PCI_DEVICE_ID_ADVANSYS_3000 0x130010CD
87#define PCI_DEVICE_REV_ADVANSYS_3150 0x02
88#define PCI_DEVICE_REV_ADVANSYS_3050 0x03
89
90#define ADV_PCI_MAX_DMA_ADDR (0xFFFFFFFFL)
91#define ADV_PCI_MAX_DMA_COUNT (0xFFFFFFFFL)
92
93static int adv_pci_probe(device_t);
94static int adv_pci_attach(device_t);
95
96/*
97 * The overrun buffer shared amongst all PCI adapters.
98 */
99static u_int8_t* overrun_buf;
100static bus_dma_tag_t overrun_dmat;
101static bus_dmamap_t overrun_dmamap;
102static bus_addr_t overrun_physbase;
103
104static int
105adv_pci_probe(device_t dev)
106{
107 int rev = pci_get_revid(dev);
108
109 switch (pci_get_devid(dev)) {
110 case PCI_DEVICE_ID_ADVANSYS_1200A:
111 device_set_desc(dev, "AdvanSys ASC1200A SCSI controller");
112 return 0;
113 case PCI_DEVICE_ID_ADVANSYS_1200B:
114 device_set_desc(dev, "AdvanSys ASC1200B SCSI controller");
115 return 0;
116 case PCI_DEVICE_ID_ADVANSYS_3000:
117 if (rev == PCI_DEVICE_REV_ADVANSYS_3150) {
118 device_set_desc(dev,
119 "AdvanSys ASC3150 SCSI controller");
120 return 0;
121 } else if (rev == PCI_DEVICE_REV_ADVANSYS_3050) {
122 device_set_desc(dev,
123 "AdvanSys ASC3030/50 SCSI controller");
124 return 0;
125 } else if (rev >= PCI_DEVICE_REV_ADVANSYS_3150) {
126 device_set_desc(dev, "Unknown AdvanSys controller");
127 return 0;
128 }
129 break;
130 default:
131 break;
132 }
133 return ENXIO;
134}
135
136static int
137adv_pci_attach(device_t dev)
138{
139 struct adv_softc *adv;
140 u_int32_t id;
141 u_int32_t command;
142 int error, rid, irqrid;
143 void *ih;
144 struct resource *iores, *irqres;
145
146 /*
147 * Determine the chip version.
148 */
149 id = pci_read_config(dev, PCIR_DEVVENDOR, /*bytes*/4);
150 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
151
152 /*
153 * These cards do not allow memory mapped accesses, so we must
154 * ensure that I/O accesses are available or we won't be able
155 * to talk to them.
156 */
157 if ((command & (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN))
158 != (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN)) {
159 command |= PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN;
160 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
161 }
162
163 /*
164 * Early chips can't handle non-zero latency timer settings.
165 */
166 if (id == PCI_DEVICE_ID_ADVANSYS_1200A
167 || id == PCI_DEVICE_ID_ADVANSYS_1200B) {
168 pci_write_config(dev, PCIR_LATTIMER, /*value*/0, /*bytes*/1);
169 }
170
171 rid = PCI_BASEADR0;
172 iores = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1,
173 RF_ACTIVE);
174 if (iores == NULL)
175 return ENXIO;
176
177 if (adv_find_signature(rman_get_bustag(iores),
178 rman_get_bushandle(iores)) == 0) {
179 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
180 return ENXIO;
181 }
182
183 adv = adv_alloc(dev, rman_get_bustag(iores), rman_get_bushandle(iores));
184 if (adv == NULL) {
185 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
186 return ENXIO;
187 }
188
189 /* Allocate a dmatag for our transfer DMA maps */
190 /* XXX Should be a child of the PCI bus dma tag */
191 error = bus_dma_tag_create(
192 /* parent */ NULL,
193 /* alignment */ 1,
194 /* boundary */ 0,
195 /* lowaddr */ ADV_PCI_MAX_DMA_ADDR,
196 /* highaddr */ BUS_SPACE_MAXADDR,
197 /* filter */ NULL,
198 /* filterarg */ NULL,
199 /* maxsize */ BUS_SPACE_MAXSIZE_32BIT,
200 /* nsegments */ ~0,
201 /* maxsegsz */ ADV_PCI_MAX_DMA_COUNT,
202 /* flags */ 0,
203 /* lockfunc */ busdma_lock_mutex,
204 /* lockarg */ &Giant,
205 &adv->parent_dmat);
206
207 if (error != 0) {
208 printf("%s: Could not allocate DMA tag - error %d\n",
209 adv_name(adv), error);
210 adv_free(adv);
211 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
212 return ENXIO;
213 }
214
215 adv->init_level++;
216
217 if (overrun_buf == NULL) {
218 /* Need to allocate our overrun buffer */
219 if (bus_dma_tag_create(
220 /* parent */ adv->parent_dmat,
221 /* alignment */ 8,
222 /* boundary */ 0,
223 /* lowaddr */ ADV_PCI_MAX_DMA_ADDR,
224 /* highaddr */ BUS_SPACE_MAXADDR,
225 /* filter */ NULL,
226 /* filterarg */ NULL,
227 /* maxsize */ ADV_OVERRUN_BSIZE,
228 /* nsegments */ 1,
229 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT,
230 /* flags */ 0,
231 /* lockfunc */ busdma_lock_mutex,
232 /* lockarg */ &Giant,
233 &overrun_dmat) != 0) {
234 bus_dma_tag_destroy(adv->parent_dmat);
235 adv_free(adv);
236 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
237 return ENXIO;
238 }
239 if (bus_dmamem_alloc(overrun_dmat,
240 (void **)&overrun_buf,
241 BUS_DMA_NOWAIT,
242 &overrun_dmamap) != 0) {
243 bus_dma_tag_destroy(overrun_dmat);
244 bus_dma_tag_destroy(adv->parent_dmat);
245 adv_free(adv);
246 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
247 return ENXIO;
248 }
249 /* And permanently map it in */
250 bus_dmamap_load(overrun_dmat, overrun_dmamap,
251 overrun_buf, ADV_OVERRUN_BSIZE,
252 adv_map, &overrun_physbase,
253 /*flags*/0);
254 }
255
256 adv->overrun_physbase = overrun_physbase;
257
258 /*
259 * Stop the chip.
260 */
261 ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT);
262 ADV_OUTW(adv, ADV_CHIP_STATUS, 0);
263
264 adv->chip_version = ADV_INB(adv, ADV_NONEISA_CHIP_REVISION);
265 adv->type = ADV_PCI;
266
267 /*
268 * Setup active negation and signal filtering.
269 */
270 {
271 u_int8_t extra_cfg;
272
273 if (adv->chip_version >= ADV_CHIP_VER_PCI_ULTRA_3150)
274 adv->type |= ADV_ULTRA;
275 if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050)
276 extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_WR_EN_FILTER;
277 else
278 extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_SLEW_RATE;
279 ADV_OUTB(adv, ADV_REG_IFC, extra_cfg);
280 }
281
282 if (adv_init(adv) != 0) {
283 adv_free(adv);
284 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
285 return ENXIO;
286 }
287
288 adv->max_dma_count = ADV_PCI_MAX_DMA_COUNT;
289 adv->max_dma_addr = ADV_PCI_MAX_DMA_ADDR;
290
291#if CC_DISABLE_PCI_PARITY_INT
292 {
293 u_int16_t config_msw;
294
295 config_msw = ADV_INW(adv, ADV_CONFIG_MSW);
296 config_msw &= 0xFFC0;
297 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
298 }
299#endif
300
301 if (id == PCI_DEVICE_ID_ADVANSYS_1200A
302 || id == PCI_DEVICE_ID_ADVANSYS_1200B) {
303 adv->bug_fix_control |= ADV_BUG_FIX_IF_NOT_DWB;
304 adv->bug_fix_control |= ADV_BUG_FIX_ASYN_USE_SYN;
305 adv->fix_asyn_xfer = ~0;
306 }
307
308 irqrid = 0;
309 irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &irqrid, 0, ~0, 1,
310 RF_SHAREABLE | RF_ACTIVE);
311 if (irqres == NULL ||
312 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY, adv_intr, adv, &ih)) {
313 adv_free(adv);
314 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
315 return ENXIO;
316 }
317
318 adv_attach(adv);
319 return 0;
320}
321
322static device_method_t adv_pci_methods[] = {
323 /* Device interface */
324 DEVMETHOD(device_probe, adv_pci_probe),
325 DEVMETHOD(device_attach, adv_pci_attach),
326 { 0, 0 }
327};
328
329static driver_t adv_pci_driver = {
330 "adv", adv_pci_methods, sizeof(struct adv_softc)
331};
332
333static devclass_t adv_pci_devclass;
334DRIVER_MODULE(adv, pci, adv_pci_driver, adv_pci_devclass, 0, 0);
| 83
84#define PCI_DEVICE_ID_ADVANSYS_1200A 0x110010CD
85#define PCI_DEVICE_ID_ADVANSYS_1200B 0x120010CD
86#define PCI_DEVICE_ID_ADVANSYS_3000 0x130010CD
87#define PCI_DEVICE_REV_ADVANSYS_3150 0x02
88#define PCI_DEVICE_REV_ADVANSYS_3050 0x03
89
90#define ADV_PCI_MAX_DMA_ADDR (0xFFFFFFFFL)
91#define ADV_PCI_MAX_DMA_COUNT (0xFFFFFFFFL)
92
93static int adv_pci_probe(device_t);
94static int adv_pci_attach(device_t);
95
96/*
97 * The overrun buffer shared amongst all PCI adapters.
98 */
99static u_int8_t* overrun_buf;
100static bus_dma_tag_t overrun_dmat;
101static bus_dmamap_t overrun_dmamap;
102static bus_addr_t overrun_physbase;
103
104static int
105adv_pci_probe(device_t dev)
106{
107 int rev = pci_get_revid(dev);
108
109 switch (pci_get_devid(dev)) {
110 case PCI_DEVICE_ID_ADVANSYS_1200A:
111 device_set_desc(dev, "AdvanSys ASC1200A SCSI controller");
112 return 0;
113 case PCI_DEVICE_ID_ADVANSYS_1200B:
114 device_set_desc(dev, "AdvanSys ASC1200B SCSI controller");
115 return 0;
116 case PCI_DEVICE_ID_ADVANSYS_3000:
117 if (rev == PCI_DEVICE_REV_ADVANSYS_3150) {
118 device_set_desc(dev,
119 "AdvanSys ASC3150 SCSI controller");
120 return 0;
121 } else if (rev == PCI_DEVICE_REV_ADVANSYS_3050) {
122 device_set_desc(dev,
123 "AdvanSys ASC3030/50 SCSI controller");
124 return 0;
125 } else if (rev >= PCI_DEVICE_REV_ADVANSYS_3150) {
126 device_set_desc(dev, "Unknown AdvanSys controller");
127 return 0;
128 }
129 break;
130 default:
131 break;
132 }
133 return ENXIO;
134}
135
136static int
137adv_pci_attach(device_t dev)
138{
139 struct adv_softc *adv;
140 u_int32_t id;
141 u_int32_t command;
142 int error, rid, irqrid;
143 void *ih;
144 struct resource *iores, *irqres;
145
146 /*
147 * Determine the chip version.
148 */
149 id = pci_read_config(dev, PCIR_DEVVENDOR, /*bytes*/4);
150 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
151
152 /*
153 * These cards do not allow memory mapped accesses, so we must
154 * ensure that I/O accesses are available or we won't be able
155 * to talk to them.
156 */
157 if ((command & (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN))
158 != (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN)) {
159 command |= PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN;
160 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
161 }
162
163 /*
164 * Early chips can't handle non-zero latency timer settings.
165 */
166 if (id == PCI_DEVICE_ID_ADVANSYS_1200A
167 || id == PCI_DEVICE_ID_ADVANSYS_1200B) {
168 pci_write_config(dev, PCIR_LATTIMER, /*value*/0, /*bytes*/1);
169 }
170
171 rid = PCI_BASEADR0;
172 iores = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1,
173 RF_ACTIVE);
174 if (iores == NULL)
175 return ENXIO;
176
177 if (adv_find_signature(rman_get_bustag(iores),
178 rman_get_bushandle(iores)) == 0) {
179 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
180 return ENXIO;
181 }
182
183 adv = adv_alloc(dev, rman_get_bustag(iores), rman_get_bushandle(iores));
184 if (adv == NULL) {
185 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
186 return ENXIO;
187 }
188
189 /* Allocate a dmatag for our transfer DMA maps */
190 /* XXX Should be a child of the PCI bus dma tag */
191 error = bus_dma_tag_create(
192 /* parent */ NULL,
193 /* alignment */ 1,
194 /* boundary */ 0,
195 /* lowaddr */ ADV_PCI_MAX_DMA_ADDR,
196 /* highaddr */ BUS_SPACE_MAXADDR,
197 /* filter */ NULL,
198 /* filterarg */ NULL,
199 /* maxsize */ BUS_SPACE_MAXSIZE_32BIT,
200 /* nsegments */ ~0,
201 /* maxsegsz */ ADV_PCI_MAX_DMA_COUNT,
202 /* flags */ 0,
203 /* lockfunc */ busdma_lock_mutex,
204 /* lockarg */ &Giant,
205 &adv->parent_dmat);
206
207 if (error != 0) {
208 printf("%s: Could not allocate DMA tag - error %d\n",
209 adv_name(adv), error);
210 adv_free(adv);
211 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
212 return ENXIO;
213 }
214
215 adv->init_level++;
216
217 if (overrun_buf == NULL) {
218 /* Need to allocate our overrun buffer */
219 if (bus_dma_tag_create(
220 /* parent */ adv->parent_dmat,
221 /* alignment */ 8,
222 /* boundary */ 0,
223 /* lowaddr */ ADV_PCI_MAX_DMA_ADDR,
224 /* highaddr */ BUS_SPACE_MAXADDR,
225 /* filter */ NULL,
226 /* filterarg */ NULL,
227 /* maxsize */ ADV_OVERRUN_BSIZE,
228 /* nsegments */ 1,
229 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT,
230 /* flags */ 0,
231 /* lockfunc */ busdma_lock_mutex,
232 /* lockarg */ &Giant,
233 &overrun_dmat) != 0) {
234 bus_dma_tag_destroy(adv->parent_dmat);
235 adv_free(adv);
236 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
237 return ENXIO;
238 }
239 if (bus_dmamem_alloc(overrun_dmat,
240 (void **)&overrun_buf,
241 BUS_DMA_NOWAIT,
242 &overrun_dmamap) != 0) {
243 bus_dma_tag_destroy(overrun_dmat);
244 bus_dma_tag_destroy(adv->parent_dmat);
245 adv_free(adv);
246 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
247 return ENXIO;
248 }
249 /* And permanently map it in */
250 bus_dmamap_load(overrun_dmat, overrun_dmamap,
251 overrun_buf, ADV_OVERRUN_BSIZE,
252 adv_map, &overrun_physbase,
253 /*flags*/0);
254 }
255
256 adv->overrun_physbase = overrun_physbase;
257
258 /*
259 * Stop the chip.
260 */
261 ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT);
262 ADV_OUTW(adv, ADV_CHIP_STATUS, 0);
263
264 adv->chip_version = ADV_INB(adv, ADV_NONEISA_CHIP_REVISION);
265 adv->type = ADV_PCI;
266
267 /*
268 * Setup active negation and signal filtering.
269 */
270 {
271 u_int8_t extra_cfg;
272
273 if (adv->chip_version >= ADV_CHIP_VER_PCI_ULTRA_3150)
274 adv->type |= ADV_ULTRA;
275 if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050)
276 extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_WR_EN_FILTER;
277 else
278 extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_SLEW_RATE;
279 ADV_OUTB(adv, ADV_REG_IFC, extra_cfg);
280 }
281
282 if (adv_init(adv) != 0) {
283 adv_free(adv);
284 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
285 return ENXIO;
286 }
287
288 adv->max_dma_count = ADV_PCI_MAX_DMA_COUNT;
289 adv->max_dma_addr = ADV_PCI_MAX_DMA_ADDR;
290
291#if CC_DISABLE_PCI_PARITY_INT
292 {
293 u_int16_t config_msw;
294
295 config_msw = ADV_INW(adv, ADV_CONFIG_MSW);
296 config_msw &= 0xFFC0;
297 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
298 }
299#endif
300
301 if (id == PCI_DEVICE_ID_ADVANSYS_1200A
302 || id == PCI_DEVICE_ID_ADVANSYS_1200B) {
303 adv->bug_fix_control |= ADV_BUG_FIX_IF_NOT_DWB;
304 adv->bug_fix_control |= ADV_BUG_FIX_ASYN_USE_SYN;
305 adv->fix_asyn_xfer = ~0;
306 }
307
308 irqrid = 0;
309 irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &irqrid, 0, ~0, 1,
310 RF_SHAREABLE | RF_ACTIVE);
311 if (irqres == NULL ||
312 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY, adv_intr, adv, &ih)) {
313 adv_free(adv);
314 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
315 return ENXIO;
316 }
317
318 adv_attach(adv);
319 return 0;
320}
321
322static device_method_t adv_pci_methods[] = {
323 /* Device interface */
324 DEVMETHOD(device_probe, adv_pci_probe),
325 DEVMETHOD(device_attach, adv_pci_attach),
326 { 0, 0 }
327};
328
329static driver_t adv_pci_driver = {
330 "adv", adv_pci_methods, sizeof(struct adv_softc)
331};
332
333static devclass_t adv_pci_devclass;
334DRIVER_MODULE(adv, pci, adv_pci_driver, adv_pci_devclass, 0, 0);
|