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ar9300_reset.c (250007) ar9300_reset.c (250008)
1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH

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13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17
18
19#include "opt_ah.h"
20
1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH

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13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17
18
19#include "opt_ah.h"
20
21#ifdef AH_SUPPORT_AR9300
22
23#include "ah.h"
24#include "ah_internal.h"
25#include "ah_devid.h"
26#include "ah_desc.h"
27
28#include "ar9300.h"
29#include "ar9300reg.h"
30#include "ar9300phy.h"

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37/* Additional Time delay to wait after activiting the Base band */
38#define BASE_ACTIVATE_DELAY 100 /* usec */
39#define RTC_PLL_SETTLE_DELAY 100 /* usec */
40#define COEF_SCALE_S 24
41#define HT40_CHANNEL_CENTER_SHIFT 10 /* MHz */
42
43#define DELPT 32
44
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24#include "ah_desc.h"
25
26#include "ar9300.h"
27#include "ar9300reg.h"
28#include "ar9300phy.h"

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35/* Additional Time delay to wait after activiting the Base band */
36#define BASE_ACTIVATE_DELAY 100 /* usec */
37#define RTC_PLL_SETTLE_DELAY 100 /* usec */
38#define COEF_SCALE_S 24
39#define HT40_CHANNEL_CENTER_SHIFT 10 /* MHz */
40
41#define DELPT 32
42
43/* XXX Duplicates! (in ar9300desc.h) */
44#if 0
45extern HAL_BOOL ar9300_reset_tx_queue(struct ath_hal *ah, u_int q);
46extern u_int32_t ar9300_num_tx_pending(struct ath_hal *ah, u_int q);
45extern HAL_BOOL ar9300_reset_tx_queue(struct ath_hal *ah, u_int q);
46extern u_int32_t ar9300_num_tx_pending(struct ath_hal *ah, u_int q);
47#endif
47
48
49#define MAX_MEASUREMENT 8
50#define MAXIQCAL 3
51struct coeff_t {
52 int32_t mag_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MAXIQCAL];
53 int32_t phs_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MAXIQCAL];
54 int32_t iqc_coeff[2];

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62static void ar9300_tx_iq_cal_outlier_detection(struct ath_hal *ah,HAL_CHANNEL_INTERNAL *ichan,
63 u_int32_t num_chains, struct coeff_t *coeff, HAL_BOOL is_cal_reusable);
64#if ATH_SUPPORT_CAL_REUSE
65static void ar9300_tx_iq_cal_apply(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan);
66#endif
67
68
69static inline void ar9300_prog_ini(struct ath_hal *ah, struct ar9300_ini_array *ini_arr, int column);
48
49
50#define MAX_MEASUREMENT 8
51#define MAXIQCAL 3
52struct coeff_t {
53 int32_t mag_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MAXIQCAL];
54 int32_t phs_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MAXIQCAL];
55 int32_t iqc_coeff[2];

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63static void ar9300_tx_iq_cal_outlier_detection(struct ath_hal *ah,HAL_CHANNEL_INTERNAL *ichan,
64 u_int32_t num_chains, struct coeff_t *coeff, HAL_BOOL is_cal_reusable);
65#if ATH_SUPPORT_CAL_REUSE
66static void ar9300_tx_iq_cal_apply(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan);
67#endif
68
69
70static inline void ar9300_prog_ini(struct ath_hal *ah, struct ar9300_ini_array *ini_arr, int column);
70static inline void ar9300_set_rf_mode(struct ath_hal *ah, HAL_CHANNEL *chan);
71static inline HAL_BOOL ar9300_init_cal(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_BOOL skip_if_none, HAL_BOOL apply_last_corr);
71static inline void ar9300_set_rf_mode(struct ath_hal *ah, struct ieee80211_channel *chan);
72static inline HAL_BOOL ar9300_init_cal(struct ath_hal *ah, struct ieee80211_channel *chan, HAL_BOOL skip_if_none, HAL_BOOL apply_last_corr);
72static inline void ar9300_init_user_settings(struct ath_hal *ah);
73
74#ifdef HOST_OFFLOAD
75/*
76 * For usb offload solution, some USB registers must be tuned
77 * to gain better stability/performance but these registers
78 * might be changed while doing wlan reset so do this here
79 */

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100}
101
102/* Adjust various register settings based on half/quarter rate clock setting.
103 * This includes: +USEC, TX/RX latency,
104 * + IFS params: slot, eifs, misc etc.
105 * SIFS stays the same.
106 */
107static void
73static inline void ar9300_init_user_settings(struct ath_hal *ah);
74
75#ifdef HOST_OFFLOAD
76/*
77 * For usb offload solution, some USB registers must be tuned
78 * to gain better stability/performance but these registers
79 * might be changed while doing wlan reset so do this here
80 */

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101}
102
103/* Adjust various register settings based on half/quarter rate clock setting.
104 * This includes: +USEC, TX/RX latency,
105 * + IFS params: slot, eifs, misc etc.
106 * SIFS stays the same.
107 */
108static void
108ar9300_set_ifs_timing(struct ath_hal *ah, HAL_CHANNEL *chan)
109ar9300_set_ifs_timing(struct ath_hal *ah, struct ieee80211_channel *chan)
109{
110 u_int32_t tx_lat, rx_lat, usec, slot, regval, eifs;
111
112 regval = OS_REG_READ(ah, AR_USEC);
113 regval &= ~(AR_USEC_RX_LATENCY | AR_USEC_TX_LATENCY | AR_USEC_USEC);
110{
111 u_int32_t tx_lat, rx_lat, usec, slot, regval, eifs;
112
113 regval = OS_REG_READ(ah, AR_USEC);
114 regval &= ~(AR_USEC_RX_LATENCY | AR_USEC_TX_LATENCY | AR_USEC_USEC);
114 if (IS_CHAN_HALF_RATE(chan)) { /* half rates */
115 if (IEEE80211_IS_CHAN_HALF(chan)) { /* half rates */
115 slot = ar9300_mac_to_clks(ah, AR_SLOT_HALF);
116 eifs = ar9300_mac_to_clks(ah, AR_EIFS_HALF);
117 if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { /* fast clock */
118 rx_lat = SM(AR_RX_LATENCY_HALF_FAST_CLOCK, AR_USEC_RX_LATENCY);
119 tx_lat = SM(AR_TX_LATENCY_HALF_FAST_CLOCK, AR_USEC_TX_LATENCY);
120 usec = SM(AR_USEC_HALF_FAST_CLOCK, AR_USEC_USEC);
121 } else {
122 rx_lat = SM(AR_RX_LATENCY_HALF, AR_USEC_RX_LATENCY);

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187 OS_REG_RMW(ah,
188 AR_PCU_MISC_MODE2,
189 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT,
190 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
191 }
192}
193
194void
116 slot = ar9300_mac_to_clks(ah, AR_SLOT_HALF);
117 eifs = ar9300_mac_to_clks(ah, AR_EIFS_HALF);
118 if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { /* fast clock */
119 rx_lat = SM(AR_RX_LATENCY_HALF_FAST_CLOCK, AR_USEC_RX_LATENCY);
120 tx_lat = SM(AR_TX_LATENCY_HALF_FAST_CLOCK, AR_USEC_TX_LATENCY);
121 usec = SM(AR_USEC_HALF_FAST_CLOCK, AR_USEC_USEC);
122 } else {
123 rx_lat = SM(AR_RX_LATENCY_HALF, AR_USEC_RX_LATENCY);

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188 OS_REG_RMW(ah,
189 AR_PCU_MISC_MODE2,
190 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT,
191 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
192 }
193}
194
195void
195ar9300_get_channel_centers(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
196ar9300_get_channel_centers(struct ath_hal *ah, const struct ieee80211_channel *chan,
196 CHAN_CENTERS *centers)
197{
198 int8_t extoff;
199 struct ath_hal_9300 *ahp = AH9300(ah);
197 CHAN_CENTERS *centers)
198{
199 int8_t extoff;
200 struct ath_hal_9300 *ahp = AH9300(ah);
201 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
200
202
201 if (!IS_CHAN_HT40(chan)) {
203 if (!IEEE80211_IS_CHAN_HT40(chan)) {
202 centers->ctl_center = centers->ext_center =
204 centers->ctl_center = centers->ext_center =
203 centers->synth_center = chan->channel;
205 centers->synth_center = ichan->channel;
204 return;
205 }
206
206 return;
207 }
208
207 HALASSERT(IS_CHAN_HT40(chan));
209 HALASSERT(IEEE80211_IS_CHAN_HT40(chan));
208
209 /*
210 * In 20/40 phy mode, the center frequency is
211 * "between" the primary and extension channels.
212 */
210
211 /*
212 * In 20/40 phy mode, the center frequency is
213 * "between" the primary and extension channels.
214 */
213 if (chan->channel_flags & CHANNEL_HT40PLUS) {
214 centers->synth_center = chan->channel + HT40_CHANNEL_CENTER_SHIFT;
215 if (IEEE80211_IS_CHAN_HT40U(chan)) {
216 centers->synth_center = ichan->channel + HT40_CHANNEL_CENTER_SHIFT;
215 extoff = 1;
216 } else {
217 extoff = 1;
218 } else {
217 centers->synth_center = chan->channel - HT40_CHANNEL_CENTER_SHIFT;
219 centers->synth_center = ichan->channel - HT40_CHANNEL_CENTER_SHIFT;
218 extoff = -1;
219 }
220
221 centers->ctl_center =
222 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
223 centers->ext_center =
224 centers->synth_center +
225 (extoff * ((ahp->ah_ext_prot_spacing == HAL_HT_EXTPROTSPACING_20) ?

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247 * high (due to interference).
248 */
249#define AH_NF_SIGN_EXTEND(nf) \
250 ((nf) & 0x100) ? \
251 0 - (((nf) ^ 0x1ff) + 1) : \
252 (nf)
253void
254ar9300_upload_noise_floor(struct ath_hal *ah, int is_2g,
220 extoff = -1;
221 }
222
223 centers->ctl_center =
224 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
225 centers->ext_center =
226 centers->synth_center +
227 (extoff * ((ahp->ah_ext_prot_spacing == HAL_HT_EXTPROTSPACING_20) ?

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249 * high (due to interference).
250 */
251#define AH_NF_SIGN_EXTEND(nf) \
252 ((nf) & 0x100) ? \
253 0 - (((nf) ^ 0x1ff) + 1) : \
254 (nf)
255void
256ar9300_upload_noise_floor(struct ath_hal *ah, int is_2g,
255 int16_t nfarray[NUM_NF_READINGS])
257 int16_t nfarray[HAL_NUM_NF_READINGS])
256{
257 int16_t nf;
258 int chan, chain;
258{
259 int16_t nf;
260 int chan, chain;
259 u_int32_t regs[NUM_NF_READINGS] = {
261 u_int32_t regs[HAL_NUM_NF_READINGS] = {
260 /* control channel */
261 AR_PHY_CCA_0, /* chain 0 */
262 AR_PHY_CCA_1, /* chain 1 */
263 AR_PHY_CCA_2, /* chain 2 */
264 /* extension channel */
265 AR_PHY_EXT_CCA, /* chain 0 */
266 AR_PHY_EXT_CCA_1, /* chain 1 */
267 AR_PHY_EXT_CCA_2, /* chain 2 */

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316 * If the noise floor calibration has not been finished, it assumes this is
317 * due to presence of CW interference an returns a high value for noise floor,
318 * derived from the CW interference threshold + margin fudge factor.
319 */
320#define BAD_SCAN_NF_MARGIN (30)
321int16_t ar9300_get_min_cca_pwr(struct ath_hal *ah)
322{
323 int16_t nf;
262 /* control channel */
263 AR_PHY_CCA_0, /* chain 0 */
264 AR_PHY_CCA_1, /* chain 1 */
265 AR_PHY_CCA_2, /* chain 2 */
266 /* extension channel */
267 AR_PHY_EXT_CCA, /* chain 0 */
268 AR_PHY_EXT_CCA_1, /* chain 1 */
269 AR_PHY_EXT_CCA_2, /* chain 2 */

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318 * If the noise floor calibration has not been finished, it assumes this is
319 * due to presence of CW interference an returns a high value for noise floor,
320 * derived from the CW interference threshold + margin fudge factor.
321 */
322#define BAD_SCAN_NF_MARGIN (30)
323int16_t ar9300_get_min_cca_pwr(struct ath_hal *ah)
324{
325 int16_t nf;
324 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
326// struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
325
326 if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) {
327 nf = MS(OS_REG_READ(ah, AR_PHY_CCA_0), AR9280_PHY_MINCCA_PWR);
328 if (nf & 0x100) {
329 nf = 0 - ((nf ^ 0x1ff) + 1);
330 }
331 } else {
332 /* NF calibration is not done, assume CW interference */
327
328 if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) {
329 nf = MS(OS_REG_READ(ah, AR_PHY_CCA_0), AR9280_PHY_MINCCA_PWR);
330 if (nf & 0x100) {
331 nf = 0 - ((nf ^ 0x1ff) + 1);
332 }
333 } else {
334 /* NF calibration is not done, assume CW interference */
333 nf = ahpriv->nfp->nominal + ahpriv->nf_cw_int_delta +
334 BAD_SCAN_NF_MARGIN;
335 nf = AH9300(ah)->nfp->nominal + AH9300(ah)->nf_cw_int_delta +
336 BAD_SCAN_NF_MARGIN;
335 }
336 return nf;
337}
338
339
340/*
341 * Noise Floor values for all chains.
342 * Most recently updated values from the NF history buffer are used.
343 */
344void ar9300_chain_noise_floor(struct ath_hal *ah, int16_t *nf_buf,
337 }
338 return nf;
339}
340
341
342/*
343 * Noise Floor values for all chains.
344 * Most recently updated values from the NF history buffer are used.
345 */
346void ar9300_chain_noise_floor(struct ath_hal *ah, int16_t *nf_buf,
345 HAL_CHANNEL *chan, int is_scan)
347 struct ieee80211_channel *chan, int is_scan)
346{
347 struct ath_hal_9300 *ahp = AH9300(ah);
348 int i, nf_hist_len, recent_nf_index = 0;
349 HAL_NFCAL_HIST_FULL *h;
350 u_int8_t rx_chainmask = ahp->ah_rx_chainmask | (ahp->ah_rx_chainmask << 3);
351 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
352 HALASSERT(ichan);
353
354#ifdef ATH_NF_PER_CHAN
355 /* Fill 0 if valid internal channel is not found */
356 if (ichan == AH_NULL) {
348{
349 struct ath_hal_9300 *ahp = AH9300(ah);
350 int i, nf_hist_len, recent_nf_index = 0;
351 HAL_NFCAL_HIST_FULL *h;
352 u_int8_t rx_chainmask = ahp->ah_rx_chainmask | (ahp->ah_rx_chainmask << 3);
353 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
354 HALASSERT(ichan);
355
356#ifdef ATH_NF_PER_CHAN
357 /* Fill 0 if valid internal channel is not found */
358 if (ichan == AH_NULL) {
357 OS_MEMZERO(nf_buf, sizeof(nf_buf[0])*NUM_NF_READINGS);
359 OS_MEMZERO(nf_buf, sizeof(nf_buf[0])*HAL_NUM_NF_READINGS);
358 return;
359 }
360 h = &ichan->nf_cal_hist;
361 nf_hist_len = HAL_NF_CAL_HIST_LEN_FULL;
362#else
363 /*
364 * If a scan is not in progress, then the most recent value goes
365 * into ahpriv->nf_cal_hist. If a scan is in progress, then
366 * the most recent value goes into ichan->nf_cal_hist.
367 * Thus, return the value from ahpriv->nf_cal_hist if there's
368 * no scan, and if the specified channel is the current channel.
369 * Otherwise, return the noise floor from ichan->nf_cal_hist.
370 */
360 return;
361 }
362 h = &ichan->nf_cal_hist;
363 nf_hist_len = HAL_NF_CAL_HIST_LEN_FULL;
364#else
365 /*
366 * If a scan is not in progress, then the most recent value goes
367 * into ahpriv->nf_cal_hist. If a scan is in progress, then
368 * the most recent value goes into ichan->nf_cal_hist.
369 * Thus, return the value from ahpriv->nf_cal_hist if there's
370 * no scan, and if the specified channel is the current channel.
371 * Otherwise, return the noise floor from ichan->nf_cal_hist.
372 */
371 if ((!is_scan) && chan->channel == AH_PRIVATE(ah)->ah_curchan->channel) {
373 if ((!is_scan) && chan == AH_PRIVATE(ah)->ah_curchan) {
372 h = &AH_PRIVATE(ah)->nf_cal_hist;
373 nf_hist_len = HAL_NF_CAL_HIST_LEN_FULL;
374 } else {
375 /* Fill 0 if valid internal channel is not found */
376 if (ichan == AH_NULL) {
374 h = &AH_PRIVATE(ah)->nf_cal_hist;
375 nf_hist_len = HAL_NF_CAL_HIST_LEN_FULL;
376 } else {
377 /* Fill 0 if valid internal channel is not found */
378 if (ichan == AH_NULL) {
377 OS_MEMZERO(nf_buf, sizeof(nf_buf[0])*NUM_NF_READINGS);
379 OS_MEMZERO(nf_buf, sizeof(nf_buf[0])*HAL_NUM_NF_READINGS);
378 return;
379 }
380 /*
381 * It is okay to treat a HAL_NFCAL_HIST_SMALL struct as if it were a
382 * HAL_NFCAL_HIST_FULL struct, as long as only the index 0 of the
380 return;
381 }
382 /*
383 * It is okay to treat a HAL_NFCAL_HIST_SMALL struct as if it were a
384 * HAL_NFCAL_HIST_FULL struct, as long as only the index 0 of the
383 * nf_cal_buffer is used (nf_cal_buffer[0][0:NUM_NF_READINGS-1])
385 * nf_cal_buffer is used (nf_cal_buffer[0][0:HAL_NUM_NF_READINGS-1])
384 */
385 h = (HAL_NFCAL_HIST_FULL *) &ichan->nf_cal_hist;
386 nf_hist_len = HAL_NF_CAL_HIST_LEN_SMALL;
387 }
388#endif
389 /* Get most recently updated values from nf cal history buffer */
390 recent_nf_index =
391 (h->base.curr_index) ? h->base.curr_index - 1 : nf_hist_len - 1;
392
386 */
387 h = (HAL_NFCAL_HIST_FULL *) &ichan->nf_cal_hist;
388 nf_hist_len = HAL_NF_CAL_HIST_LEN_SMALL;
389 }
390#endif
391 /* Get most recently updated values from nf cal history buffer */
392 recent_nf_index =
393 (h->base.curr_index) ? h->base.curr_index - 1 : nf_hist_len - 1;
394
393 for (i = 0; i < NUM_NF_READINGS; i++) {
395 for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
394 /* Fill 0 for unsupported chains */
395 if (!(rx_chainmask & (1 << i))) {
396 nf_buf[i] = 0;
397 continue;
398 }
399 nf_buf[i] = h->nf_cal_buffer[recent_nf_index][i];
400 }
401}

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410 int hist_len)
411{
412 int16_t nfval;
413 int16_t sort[HAL_NF_CAL_HIST_LEN_FULL]; /* upper bound for hist_len */
414 int i, j;
415
416 for (i = 0; i < hist_len; i++) {
417 sort[i] = h->nf_cal_buffer[i][reading];
396 /* Fill 0 for unsupported chains */
397 if (!(rx_chainmask & (1 << i))) {
398 nf_buf[i] = 0;
399 continue;
400 }
401 nf_buf[i] = h->nf_cal_buffer[recent_nf_index][i];
402 }
403}

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412 int hist_len)
413{
414 int16_t nfval;
415 int16_t sort[HAL_NF_CAL_HIST_LEN_FULL]; /* upper bound for hist_len */
416 int i, j;
417
418 for (i = 0; i < hist_len; i++) {
419 sort[i] = h->nf_cal_buffer[i][reading];
418 HALDEBUG(ah, HAL_DEBUG_NF_CAL,
420 HALDEBUG(ah, HAL_DEBUG_NFCAL,
419 "nf_cal_buffer[%d][%d] = %d\n", i, reading, (int)sort[i]);
420 }
421 for (i = 0; i < hist_len - 1; i++) {
422 for (j = 1; j < hist_len - i; j++) {
423 if (sort[j] > sort[j - 1]) {
424 nfval = sort[j];
425 sort[j] = sort[j - 1];
426 sort[j - 1] = nfval;
427 }
428 }
429 }
430 nfval = sort[(hist_len - 1) >> 1];
431
432 return nfval;
433}
434
435static int16_t ar9300_limit_nf_range(struct ath_hal *ah, int16_t nf)
436{
421 "nf_cal_buffer[%d][%d] = %d\n", i, reading, (int)sort[i]);
422 }
423 for (i = 0; i < hist_len - 1; i++) {
424 for (j = 1; j < hist_len - i; j++) {
425 if (sort[j] > sort[j - 1]) {
426 nfval = sort[j];
427 sort[j] = sort[j - 1];
428 sort[j - 1] = nfval;
429 }
430 }
431 }
432 nfval = sort[(hist_len - 1) >> 1];
433
434 return nfval;
435}
436
437static int16_t ar9300_limit_nf_range(struct ath_hal *ah, int16_t nf)
438{
437 if (nf < AH_PRIVATE(ah)->nfp->min) {
438 return AH_PRIVATE(ah)->nfp->nominal;
439 } else if (nf > AH_PRIVATE(ah)->nfp->max) {
440 return AH_PRIVATE(ah)->nfp->max;
439 if (nf < AH9300(ah)->nfp->min) {
440 return AH9300(ah)->nfp->nominal;
441 } else if (nf > AH9300(ah)->nfp->max) {
442 return AH9300(ah)->nfp->max;
441 }
442 return nf;
443}
444
445#ifndef ATH_NF_PER_CHAN
446inline static void
447ar9300_reset_nf_hist_buff(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
448{

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466 * replicating a single NF reading into all nf_cal_buffer elements,
467 * if the single reading were above the CW_INT threshold, the CW_INT
468 * check in ar9300_get_nf would immediately conclude that CW interference
469 * is present, even though we're not supposed to set CW_INT unless
470 * NF values are _consistently_ above the CW_INT threshold.
471 * Applying the bounds limits to the nf_cal_buffer contents fixes this
472 * problem.
473 */
443 }
444 return nf;
445}
446
447#ifndef ATH_NF_PER_CHAN
448inline static void
449ar9300_reset_nf_hist_buff(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
450{

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468 * replicating a single NF reading into all nf_cal_buffer elements,
469 * if the single reading were above the CW_INT threshold, the CW_INT
470 * check in ar9300_get_nf would immediately conclude that CW interference
471 * is present, even though we're not supposed to set CW_INT unless
472 * NF values are _consistently_ above the CW_INT threshold.
473 * Applying the bounds limits to the nf_cal_buffer contents fixes this
474 * problem.
475 */
474 for (i = 0; i < NUM_NF_READINGS; i ++) {
476 for (i = 0; i < HAL_NUM_NF_READINGS; i ++) {
475 int j;
476 int16_t nf;
477 /*
478 * No need to set curr_index, since it already has a value in
479 * the range [0..HAL_NF_CAL_HIST_LEN_FULL), and all nf_cal_buffer
480 * values will be the same.
481 */
482 nf = ar9300_limit_nf_range(ah, h->nf_cal_buffer[0][i]);

--- 12 unchanged lines hidden (view full) ---

495ar9300_update_nf_hist_buff(struct ath_hal *ah, HAL_NFCAL_HIST_FULL *h,
496 int16_t *nfarray, int hist_len)
497{
498 int i, nr;
499 int16_t nf_no_lim_chain0;
500
501 nf_no_lim_chain0 = ar9300_get_nf_hist_mid(ah, h, 0, hist_len);
502
477 int j;
478 int16_t nf;
479 /*
480 * No need to set curr_index, since it already has a value in
481 * the range [0..HAL_NF_CAL_HIST_LEN_FULL), and all nf_cal_buffer
482 * values will be the same.
483 */
484 nf = ar9300_limit_nf_range(ah, h->nf_cal_buffer[0][i]);

--- 12 unchanged lines hidden (view full) ---

497ar9300_update_nf_hist_buff(struct ath_hal *ah, HAL_NFCAL_HIST_FULL *h,
498 int16_t *nfarray, int hist_len)
499{
500 int i, nr;
501 int16_t nf_no_lim_chain0;
502
503 nf_no_lim_chain0 = ar9300_get_nf_hist_mid(ah, h, 0, hist_len);
504
503 HALDEBUG(ah, HAL_DEBUG_NF_CAL, "%s[%d] BEFORE\n", __func__, __LINE__);
505 HALDEBUG(ah, HAL_DEBUG_NFCAL, "%s[%d] BEFORE\n", __func__, __LINE__);
504 for (nr = 0; nr < HAL_NF_CAL_HIST_LEN_FULL; nr++) {
506 for (nr = 0; nr < HAL_NF_CAL_HIST_LEN_FULL; nr++) {
505 for (i = 0; i < NUM_NF_READINGS; i++) {
506 HALDEBUG(ah, HAL_DEBUG_NF_CAL,
507 for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
508 HALDEBUG(ah, HAL_DEBUG_NFCAL,
507 "nf_cal_buffer[%d][%d] = %d\n",
508 nr, i, (int)h->nf_cal_buffer[nr][i]);
509 }
510 }
509 "nf_cal_buffer[%d][%d] = %d\n",
510 nr, i, (int)h->nf_cal_buffer[nr][i]);
511 }
512 }
511 for (i = 0; i < NUM_NF_READINGS; i++) {
513 for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
512 h->nf_cal_buffer[h->base.curr_index][i] = nfarray[i];
513 h->base.priv_nf[i] = ar9300_limit_nf_range(
514 ah, ar9300_get_nf_hist_mid(ah, h, i, hist_len));
515 }
514 h->nf_cal_buffer[h->base.curr_index][i] = nfarray[i];
515 h->base.priv_nf[i] = ar9300_limit_nf_range(
516 ah, ar9300_get_nf_hist_mid(ah, h, i, hist_len));
517 }
516 HALDEBUG(ah, HAL_DEBUG_NF_CAL, "%s[%d] AFTER\n", __func__, __LINE__);
518 HALDEBUG(ah, HAL_DEBUG_NFCAL, "%s[%d] AFTER\n", __func__, __LINE__);
517 for (nr = 0; nr < HAL_NF_CAL_HIST_LEN_FULL; nr++) {
519 for (nr = 0; nr < HAL_NF_CAL_HIST_LEN_FULL; nr++) {
518 for (i = 0; i < NUM_NF_READINGS; i++) {
519 HALDEBUG(ah, HAL_DEBUG_NF_CAL,
520 for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
521 HALDEBUG(ah, HAL_DEBUG_NFCAL,
520 "nf_cal_buffer[%d][%d] = %d\n",
521 nr, i, (int)h->nf_cal_buffer[nr][i]);
522 }
523 }
524
525 if (++h->base.curr_index >= hist_len) {
526 h->base.curr_index = 0;
527 }
528
529 return nf_no_lim_chain0;
530}
531
522 "nf_cal_buffer[%d][%d] = %d\n",
523 nr, i, (int)h->nf_cal_buffer[nr][i]);
524 }
525 }
526
527 if (++h->base.curr_index >= hist_len) {
528 h->base.curr_index = 0;
529 }
530
531 return nf_no_lim_chain0;
532}
533
532#if UNUSED
534#ifdef UNUSED
533static HAL_BOOL
534get_noise_floor_thresh(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *chan,
535 int16_t *nft)
536{
537 struct ath_hal_9300 *ahp = AH9300(ah);
538
539 switch (chan->channel_flags & CHANNEL_ALL_NOTURBO) {
540 case CHANNEL_A:

--- 18 unchanged lines hidden (view full) ---

559}
560#endif
561
562/*
563 * Read the NF and check it against the noise floor threshhold
564 */
565#define IS(_c, _f) (((_c)->channel_flags & _f) || 0)
566static int
535static HAL_BOOL
536get_noise_floor_thresh(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *chan,
537 int16_t *nft)
538{
539 struct ath_hal_9300 *ahp = AH9300(ah);
540
541 switch (chan->channel_flags & CHANNEL_ALL_NOTURBO) {
542 case CHANNEL_A:

--- 18 unchanged lines hidden (view full) ---

561}
562#endif
563
564/*
565 * Read the NF and check it against the noise floor threshhold
566 */
567#define IS(_c, _f) (((_c)->channel_flags & _f) || 0)
568static int
567ar9300_store_new_nf(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, int is_scan)
569ar9300_store_new_nf(struct ath_hal *ah, struct ieee80211_channel *chan,
570 int is_scan)
568{
571{
569 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
572// struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
570 int nf_hist_len;
571 int16_t nf_no_lim;
573 int nf_hist_len;
574 int16_t nf_no_lim;
572 int16_t nfarray[NUM_NF_READINGS] = {0};
575 int16_t nfarray[HAL_NUM_NF_READINGS] = {0};
573 HAL_NFCAL_HIST_FULL *h;
574 int is_2g = 0;
576 HAL_NFCAL_HIST_FULL *h;
577 int is_2g = 0;
578 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
579 struct ath_hal_9300 *ahp = AH9300(ah);
575
576 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
577 u_int32_t tsf32, nf_cal_dur_tsf;
578 /*
579 * The reason the NF calibration did not complete may just be that
580 * not enough time has passed since the NF calibration was started,
581 * because under certain conditions (when first moving to a new
582 * channel) the NF calibration may be checked very repeatedly.

--- 37 unchanged lines hidden (view full) ---

620 * this function is called, the timestamp comparison
621 * will be valid.
622 */
623 AH9300(ah)->nf_tsf32 = tsf32;
624 } else if (nf_cal_dur_tsf > AH_NF_CAL_DUR_TSF) {
625 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
626 "%s: NF did not complete in calibration window\n", __func__);
627 /* the NF incompletion is probably due to CW interference */
580
581 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
582 u_int32_t tsf32, nf_cal_dur_tsf;
583 /*
584 * The reason the NF calibration did not complete may just be that
585 * not enough time has passed since the NF calibration was started,
586 * because under certain conditions (when first moving to a new
587 * channel) the NF calibration may be checked very repeatedly.

--- 37 unchanged lines hidden (view full) ---

625 * this function is called, the timestamp comparison
626 * will be valid.
627 */
628 AH9300(ah)->nf_tsf32 = tsf32;
629 } else if (nf_cal_dur_tsf > AH_NF_CAL_DUR_TSF) {
630 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
631 "%s: NF did not complete in calibration window\n", __func__);
632 /* the NF incompletion is probably due to CW interference */
628 chan->channel_flags |= CHANNEL_CW_INT;
633 chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
629 }
630 return 0; /* HW's NF measurement not finished */
631 }
634 }
635 return 0; /* HW's NF measurement not finished */
636 }
632 HALDEBUG(ah, HAL_DEBUG_NF_CAL,
633 "%s[%d] chan %d\n", __func__, __LINE__, chan->channel);
634 is_2g = IS(chan, CHANNEL_2GHZ);
637 HALDEBUG(ah, HAL_DEBUG_NFCAL,
638 "%s[%d] chan %d\n", __func__, __LINE__, ichan->channel);
639 is_2g = !! IS_CHAN_2GHZ(ichan);
635 ar9300_upload_noise_floor(ah, is_2g, nfarray);
636
637 /* Update the NF buffer for each chain masked by chainmask */
638#ifdef ATH_NF_PER_CHAN
640 ar9300_upload_noise_floor(ah, is_2g, nfarray);
641
642 /* Update the NF buffer for each chain masked by chainmask */
643#ifdef ATH_NF_PER_CHAN
639 h = &chan->nf_cal_hist;
644 h = &ichan->nf_cal_hist;
640 nf_hist_len = HAL_NF_CAL_HIST_LEN_FULL;
641#else
642 if (is_scan) {
643 /*
644 * This channel's NF cal info is just a HAL_NFCAL_HIST_SMALL struct
645 * rather than a HAL_NFCAL_HIST_FULL struct.
646 * As long as we only use the first history element of nf_cal_buffer
645 nf_hist_len = HAL_NF_CAL_HIST_LEN_FULL;
646#else
647 if (is_scan) {
648 /*
649 * This channel's NF cal info is just a HAL_NFCAL_HIST_SMALL struct
650 * rather than a HAL_NFCAL_HIST_FULL struct.
651 * As long as we only use the first history element of nf_cal_buffer
647 * (nf_cal_buffer[0][0:NUM_NF_READINGS-1]), we can use
652 * (nf_cal_buffer[0][0:HAL_NUM_NF_READINGS-1]), we can use
648 * HAL_NFCAL_HIST_SMALL and HAL_NFCAL_HIST_FULL interchangeably.
649 */
653 * HAL_NFCAL_HIST_SMALL and HAL_NFCAL_HIST_FULL interchangeably.
654 */
650 h = (HAL_NFCAL_HIST_FULL *) &chan->nf_cal_hist;
655 h = (HAL_NFCAL_HIST_FULL *) &ichan->nf_cal_hist;
651 nf_hist_len = HAL_NF_CAL_HIST_LEN_SMALL;
652 } else {
653 h = &AH_PRIVATE(ah)->nf_cal_hist;
654 nf_hist_len = HAL_NF_CAL_HIST_LEN_FULL;
655 }
656#endif
657
658 /*
659 * nf_no_lim = median value from NF history buffer without bounds limits,
660 * priv_nf = median value from NF history buffer with bounds limits.
661 */
662 nf_no_lim = ar9300_update_nf_hist_buff(ah, h, nfarray, nf_hist_len);
656 nf_hist_len = HAL_NF_CAL_HIST_LEN_SMALL;
657 } else {
658 h = &AH_PRIVATE(ah)->nf_cal_hist;
659 nf_hist_len = HAL_NF_CAL_HIST_LEN_FULL;
660 }
661#endif
662
663 /*
664 * nf_no_lim = median value from NF history buffer without bounds limits,
665 * priv_nf = median value from NF history buffer with bounds limits.
666 */
667 nf_no_lim = ar9300_update_nf_hist_buff(ah, h, nfarray, nf_hist_len);
663 chan->raw_noise_floor = h->base.priv_nf[0];
668 ichan->rawNoiseFloor = h->base.priv_nf[0];
664
665 /* check if there is interference */
669
670 /* check if there is interference */
666 chan->channel_flags &= (~CHANNEL_CW_INT);
671// ichan->channel_flags &= (~CHANNEL_CW_INT);
667 /*
668 * Use AR9300_EMULATION to check for emulation purpose as PCIE Device ID
669 * 0xABCD is recognized as valid Osprey as WAR in some EVs.
670 */
672 /*
673 * Use AR9300_EMULATION to check for emulation purpose as PCIE Device ID
674 * 0xABCD is recognized as valid Osprey as WAR in some EVs.
675 */
671 if (nf_no_lim > ahpriv->nfp->nominal + ahpriv->nf_cw_int_delta) {
676 if (nf_no_lim > ahp->nfp->nominal + ahp->nf_cw_int_delta) {
672 /*
673 * Since this CW interference check is being applied to the
674 * median element of the NF history buffer, this indicates that
675 * the CW interference is persistent. A single high NF reading
676 * will not show up in the median, and thus will not cause the
677 * CW_INT flag to be set.
678 */
677 /*
678 * Since this CW interference check is being applied to the
679 * median element of the NF history buffer, this indicates that
680 * the CW interference is persistent. A single high NF reading
681 * will not show up in the median, and thus will not cause the
682 * CW_INT flag to be set.
683 */
679 HALDEBUG(ah, HAL_DEBUG_NF_CAL,
684 HALDEBUG(ah, HAL_DEBUG_NFCAL,
680 "%s: NF Cal: CW interferer detected through NF: %d\n",
681 __func__, nf_no_lim);
685 "%s: NF Cal: CW interferer detected through NF: %d\n",
686 __func__, nf_no_lim);
682 chan->channel_flags |= CHANNEL_CW_INT;
687 chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
683 }
684 return 1; /* HW's NF measurement finished */
685}
686#undef IS
687
688static inline void
689ar9300_get_delta_slope_values(struct ath_hal *ah, u_int32_t coef_scaled,
690 u_int32_t *coef_mantissa, u_int32_t *coef_exponent)

--- 26 unchanged lines hidden (view full) ---

717
718#define MAX_ANALOG_START 319 /* XXX */
719
720/*
721 * Delta slope coefficient computation.
722 * Required for OFDM operation.
723 */
724static void
688 }
689 return 1; /* HW's NF measurement finished */
690}
691#undef IS
692
693static inline void
694ar9300_get_delta_slope_values(struct ath_hal *ah, u_int32_t coef_scaled,
695 u_int32_t *coef_mantissa, u_int32_t *coef_exponent)

--- 26 unchanged lines hidden (view full) ---

722
723#define MAX_ANALOG_START 319 /* XXX */
724
725/*
726 * Delta slope coefficient computation.
727 * Required for OFDM operation.
728 */
729static void
725ar9300_set_delta_slope(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
730ar9300_set_delta_slope(struct ath_hal *ah, struct ieee80211_channel *chan)
726{
727 u_int32_t coef_scaled, ds_coef_exp, ds_coef_man;
728 u_int32_t fclk = COEFF; /* clock * 2.5 */
729
730 u_int32_t clock_mhz_scaled = 0x1000000 * fclk;
731 CHAN_CENTERS centers;
732
733 /*
734 * half and quarter rate can divide the scaled clock by 2 or 4
735 * scale for selected channel bandwidth
736 */
731{
732 u_int32_t coef_scaled, ds_coef_exp, ds_coef_man;
733 u_int32_t fclk = COEFF; /* clock * 2.5 */
734
735 u_int32_t clock_mhz_scaled = 0x1000000 * fclk;
736 CHAN_CENTERS centers;
737
738 /*
739 * half and quarter rate can divide the scaled clock by 2 or 4
740 * scale for selected channel bandwidth
741 */
737 if (IS_CHAN_HALF_RATE(chan)) {
742 if (IEEE80211_IS_CHAN_HALF(chan)) {
738 clock_mhz_scaled = clock_mhz_scaled >> 1;
743 clock_mhz_scaled = clock_mhz_scaled >> 1;
739 } else if (IS_CHAN_QUARTER_RATE(chan)) {
744 } else if (IEEE80211_IS_CHAN_QUARTER(chan)) {
740 clock_mhz_scaled = clock_mhz_scaled >> 2;
741 }
742
743 /*
744 * ALGO -> coef = 1e8/fcarrier*fclock/40;
745 * scaled coef to provide precision for this floating calculation
746 */
747 ar9300_get_channel_centers(ah, chan, &centers);

--- 12 unchanged lines hidden (view full) ---

760
761 ar9300_get_delta_slope_values(ah, coef_scaled, &ds_coef_man, &ds_coef_exp);
762
763 /* for short gi */
764 OS_REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, AR_PHY_SGI_DSC_MAN, ds_coef_man);
765 OS_REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, AR_PHY_SGI_DSC_EXP, ds_coef_exp);
766}
767
745 clock_mhz_scaled = clock_mhz_scaled >> 2;
746 }
747
748 /*
749 * ALGO -> coef = 1e8/fcarrier*fclock/40;
750 * scaled coef to provide precision for this floating calculation
751 */
752 ar9300_get_channel_centers(ah, chan, &centers);

--- 12 unchanged lines hidden (view full) ---

765
766 ar9300_get_delta_slope_values(ah, coef_scaled, &ds_coef_man, &ds_coef_exp);
767
768 /* for short gi */
769 OS_REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, AR_PHY_SGI_DSC_MAN, ds_coef_man);
770 OS_REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, AR_PHY_SGI_DSC_EXP, ds_coef_exp);
771}
772
768#define IS(_c, _f) (((_c)->channel_flags & _f) || 0)
773#define IS(_c, _f) (IEEE80211_IS_ ## _f(_c))
769
774
770static inline HAL_CHANNEL_INTERNAL*
771ar9300_check_chan(struct ath_hal *ah, HAL_CHANNEL *chan)
775/*
776 * XXX FreeBSD: This should be turned into something generic in ath_hal!
777 */
778HAL_CHANNEL_INTERNAL *
779ar9300_check_chan(struct ath_hal *ah, const struct ieee80211_channel *chan)
772{
780{
773 if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan, CHANNEL_5GHZ)) == 0) {
781 if ((IS(chan, CHAN_2GHZ) ^ IS(chan, CHAN_5GHZ)) == 0) {
774 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
775 "%s: invalid channel %u/0x%x; not marked as 2GHz or 5GHz\n",
782 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
783 "%s: invalid channel %u/0x%x; not marked as 2GHz or 5GHz\n",
776 __func__, chan->channel, chan->channel_flags);
784 __func__, chan->ic_freq , chan->ic_flags);
777 return AH_NULL;
778 }
779
785 return AH_NULL;
786 }
787
780 if ((IS(chan, CHANNEL_OFDM) ^ IS(chan, CHANNEL_CCK) ^
781 IS(chan, CHANNEL_HT20) ^ IS(chan, CHANNEL_HT40PLUS) ^
782 IS(chan, CHANNEL_HT40MINUS)) == 0)
788 /*
789 * FreeBSD sets multiple flags, so this will fail.
790 */
791#if 0
792 if ((IS(chan, CHAN_OFDM) ^ IS(chan, CHAN_CCK) ^ IS(chan, CHAN_DYN) ^
793 IS(chan, CHAN_HT20) ^ IS(chan, CHAN_HT40U) ^
794 IS(chan, CHAN_HT40D)) == 0)
783 {
784 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
785 "%s: invalid channel %u/0x%x; not marked as "
795 {
796 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
797 "%s: invalid channel %u/0x%x; not marked as "
786 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
787 __func__, chan->channel, chan->channel_flags);
798 "OFDM or CCK or DYN or HT20 or HT40PLUS or HT40MINUS\n",
799 __func__, chan->ic_freq , chan->ic_flags);
788 return AH_NULL;
789 }
800 return AH_NULL;
801 }
802#endif
790
791 return (ath_hal_checkchannel(ah, chan));
792}
793#undef IS
794
795static void
803
804 return (ath_hal_checkchannel(ah, chan));
805}
806#undef IS
807
808static void
796ar9300_set_11n_regs(struct ath_hal *ah, HAL_CHANNEL *chan,
809ar9300_set_11n_regs(struct ath_hal *ah, struct ieee80211_channel *chan,
797 HAL_HT_MACMODE macmode)
798{
799 u_int32_t phymode;
810 HAL_HT_MACMODE macmode)
811{
812 u_int32_t phymode;
800 struct ath_hal_9300 *ahp = AH9300(ah);
813// struct ath_hal_9300 *ahp = AH9300(ah);
801 u_int32_t enable_dac_fifo;
802
803 /* XXX */
804 enable_dac_fifo =
805 OS_REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO;
806
807 /* Enable 11n HT, 20 MHz */
808 phymode =
809 AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_SHORT_GI_40
810 | enable_dac_fifo;
811 /* Configure baseband for dynamic 20/40 operation */
814 u_int32_t enable_dac_fifo;
815
816 /* XXX */
817 enable_dac_fifo =
818 OS_REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO;
819
820 /* Enable 11n HT, 20 MHz */
821 phymode =
822 AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_SHORT_GI_40
823 | enable_dac_fifo;
824 /* Configure baseband for dynamic 20/40 operation */
812 if (IS_CHAN_HT40(chan)) {
825 if (IEEE80211_IS_CHAN_HT40(chan)) {
813 phymode |= AR_PHY_GC_DYN2040_EN;
814 /* Configure control (primary) channel at +-10MHz */
826 phymode |= AR_PHY_GC_DYN2040_EN;
827 /* Configure control (primary) channel at +-10MHz */
815 if (chan->channel_flags & CHANNEL_HT40PLUS) {
828 if (IEEE80211_IS_CHAN_HT40U(chan)) {
816 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
817 }
818
829 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
830 }
831
832#if 0
819 /* Configure 20/25 spacing */
820 if (ahp->ah_ext_prot_spacing == HAL_HT_EXTPROTSPACING_25) {
821 phymode |= AR_PHY_GC_DYN2040_EXT_CH;
822 }
833 /* Configure 20/25 spacing */
834 if (ahp->ah_ext_prot_spacing == HAL_HT_EXTPROTSPACING_25) {
835 phymode |= AR_PHY_GC_DYN2040_EXT_CH;
836 }
837#endif
823 }
824
825 /* make sure we preserve INI settings */
826 phymode |= OS_REG_READ(ah, AR_PHY_GEN_CTRL);
827
828 /* EV 62881/64991 - turn off Green Field detection for Maverick STA beta */
829 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
830
831 OS_REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
832
833 /* Set IFS timing for half/quarter rates */
838 }
839
840 /* make sure we preserve INI settings */
841 phymode |= OS_REG_READ(ah, AR_PHY_GEN_CTRL);
842
843 /* EV 62881/64991 - turn off Green Field detection for Maverick STA beta */
844 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
845
846 OS_REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
847
848 /* Set IFS timing for half/quarter rates */
834 if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) {
849 if (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan)) {
835 u_int32_t modeselect = OS_REG_READ(ah, AR_PHY_MODE);
836
850 u_int32_t modeselect = OS_REG_READ(ah, AR_PHY_MODE);
851
837 if (IS_CHAN_HALF_RATE(chan)) {
852 if (IEEE80211_IS_CHAN_HALF(chan)) {
838 modeselect |= AR_PHY_MS_HALF_RATE;
853 modeselect |= AR_PHY_MS_HALF_RATE;
839 } else if (IS_CHAN_QUARTER_RATE(chan)) {
854 } else if (IEEE80211_IS_CHAN_QUARTER(chan)) {
840 modeselect |= AR_PHY_MS_QUARTER_RATE;
841 }
842 OS_REG_WRITE(ah, AR_PHY_MODE, modeselect);
843
844 ar9300_set_ifs_timing(ah, chan);
845 OS_REG_RMW_FIELD(
846 ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 0x3);
847 }

--- 8 unchanged lines hidden (view full) ---

856 /* carrier sense timeout */
857 OS_REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
858}
859
860/*
861 * Spur mitigation for MRC CCK
862 */
863static void
855 modeselect |= AR_PHY_MS_QUARTER_RATE;
856 }
857 OS_REG_WRITE(ah, AR_PHY_MODE, modeselect);
858
859 ar9300_set_ifs_timing(ah, chan);
860 OS_REG_RMW_FIELD(
861 ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 0x3);
862 }

--- 8 unchanged lines hidden (view full) ---

871 /* carrier sense timeout */
872 OS_REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
873}
874
875/*
876 * Spur mitigation for MRC CCK
877 */
878static void
864ar9300_spur_mitigate_mrc_cck(struct ath_hal *ah, HAL_CHANNEL *chan)
879ar9300_spur_mitigate_mrc_cck(struct ath_hal *ah, struct ieee80211_channel *chan)
865{
866 int i;
867 /* spur_freq_for_osprey - hardcoded by Systems team for now. */
868 u_int32_t spur_freq_for_osprey[4] = { 2420, 2440, 2464, 2480 };
869 u_int32_t spur_freq_for_jupiter[2] = { 2440, 2464};
870 int cur_bb_spur, negative = 0, cck_spur_freq;
871 u_int8_t* spur_fbin_ptr = NULL;
872 int synth_freq;
873 int range = 10;
874 int max_spurcounts = OSPREY_EEPROM_MODAL_SPURS;
880{
881 int i;
882 /* spur_freq_for_osprey - hardcoded by Systems team for now. */
883 u_int32_t spur_freq_for_osprey[4] = { 2420, 2440, 2464, 2480 };
884 u_int32_t spur_freq_for_jupiter[2] = { 2440, 2464};
885 int cur_bb_spur, negative = 0, cck_spur_freq;
886 u_int8_t* spur_fbin_ptr = NULL;
887 int synth_freq;
888 int range = 10;
889 int max_spurcounts = OSPREY_EEPROM_MODAL_SPURS;
890 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
875
876 /*
877 * Need to verify range +/- 10 MHz in control channel, otherwise spur
878 * is out-of-band and can be ignored.
879 */
880 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) ||
881 AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
882 spur_fbin_ptr = ar9300_eeprom_get_spur_chans_ptr(ah, 1);
883 if (spur_fbin_ptr[0] == 0) {
884 return; /* No spur in the mode */
885 }
891
892 /*
893 * Need to verify range +/- 10 MHz in control channel, otherwise spur
894 * is out-of-band and can be ignored.
895 */
896 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) ||
897 AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
898 spur_fbin_ptr = ar9300_eeprom_get_spur_chans_ptr(ah, 1);
899 if (spur_fbin_ptr[0] == 0) {
900 return; /* No spur in the mode */
901 }
886 if (IS_CHAN_HT40(chan)) {
902 if (IEEE80211_IS_CHAN_HT40(chan)) {
887 range = 19;
888 if (OS_REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH)
889 == 0x0)
890 {
903 range = 19;
904 if (OS_REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH)
905 == 0x0)
906 {
891 synth_freq = chan->channel + 10;
907 synth_freq = ichan->channel + 10;
892 } else {
908 } else {
893 synth_freq = chan->channel - 10;
909 synth_freq = ichan->channel - 10;
894 }
895 } else {
896 range = 10;
910 }
911 } else {
912 range = 10;
897 synth_freq = chan->channel;
913 synth_freq = ichan->channel;
898 }
899 } else if(AR_SREV_JUPITER(ah)) {
900 range = 5;
901 max_spurcounts = 2; /* Hardcoded by Jupiter Systems team for now. */
914 }
915 } else if(AR_SREV_JUPITER(ah)) {
916 range = 5;
917 max_spurcounts = 2; /* Hardcoded by Jupiter Systems team for now. */
902 synth_freq = chan->channel;
918 synth_freq = ichan->channel;
903 } else {
904 range = 10;
905 max_spurcounts = 4; /* Hardcoded by Osprey Systems team for now. */
919 } else {
920 range = 10;
921 max_spurcounts = 4; /* Hardcoded by Osprey Systems team for now. */
906 synth_freq = chan->channel;
922 synth_freq = ichan->channel;
907 }
908
909 for (i = 0; i < max_spurcounts; i++) {
910 negative = 0;
911
912 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) ||
913 AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
914 cur_bb_spur =

--- 41 unchanged lines hidden (view full) ---

956 AR_PHY_CCK_SPUR_MIT, AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
957 /*OS_REG_WRITE(ah, BB_cck_spur_mit.cck_spur_freq, 0x0);*/
958 OS_REG_RMW_FIELD(ah,
959 AR_PHY_CCK_SPUR_MIT, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
960}
961
962/* Spur mitigation for OFDM */
963static void
923 }
924
925 for (i = 0; i < max_spurcounts; i++) {
926 negative = 0;
927
928 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) ||
929 AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
930 cur_bb_spur =

--- 41 unchanged lines hidden (view full) ---

972 AR_PHY_CCK_SPUR_MIT, AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
973 /*OS_REG_WRITE(ah, BB_cck_spur_mit.cck_spur_freq, 0x0);*/
974 OS_REG_RMW_FIELD(ah,
975 AR_PHY_CCK_SPUR_MIT, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
976}
977
978/* Spur mitigation for OFDM */
979static void
964ar9300_spur_mitigate_ofdm(struct ath_hal *ah, HAL_CHANNEL *chan)
980ar9300_spur_mitigate_ofdm(struct ath_hal *ah, struct ieee80211_channel *chan)
965{
966 int synth_freq;
967 int range = 10;
968 int freq_offset = 0;
969 int spur_freq_sd = 0;
970 int spur_subchannel_sd = 0;
971 int spur_delta_phase = 0;
972 int mask_index = 0;
973 int i;
974 int mode;
975 u_int8_t* spur_chans_ptr;
981{
982 int synth_freq;
983 int range = 10;
984 int freq_offset = 0;
985 int spur_freq_sd = 0;
986 int spur_subchannel_sd = 0;
987 int spur_delta_phase = 0;
988 int mask_index = 0;
989 int i;
990 int mode;
991 u_int8_t* spur_chans_ptr;
992 struct ath_hal_9300 *ahp;
993 ahp = AH9300(ah);
994 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
976
995
977 if (IS_CHAN_5GHZ(chan)) {
996 if (IS_CHAN_5GHZ(ichan)) {
978 spur_chans_ptr = ar9300_eeprom_get_spur_chans_ptr(ah, 0);
979 mode = 0;
980 } else {
981 spur_chans_ptr = ar9300_eeprom_get_spur_chans_ptr(ah, 1);
982 mode = 1;
983 }
984
997 spur_chans_ptr = ar9300_eeprom_get_spur_chans_ptr(ah, 0);
998 mode = 0;
999 } else {
1000 spur_chans_ptr = ar9300_eeprom_get_spur_chans_ptr(ah, 1);
1001 mode = 1;
1002 }
1003
985 if (IS_CHAN_HT40(chan)) {
1004 if (IEEE80211_IS_CHAN_HT40(chan)) {
986 range = 19;
987 if (OS_REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH)
988 == 0x0)
989 {
1005 range = 19;
1006 if (OS_REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH)
1007 == 0x0)
1008 {
990 synth_freq = chan->channel - 10;
1009 synth_freq = ichan->channel - 10;
991 } else {
1010 } else {
992 synth_freq = chan->channel + 10;
1011 synth_freq = ichan->channel + 10;
993 }
994 } else {
995 range = 10;
1012 }
1013 } else {
1014 range = 10;
996 synth_freq = chan->channel;
1015 synth_freq = ichan->channel;
997 }
998
999 /* Clean all spur register fields */
1000 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
1001 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING11, AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
1002 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING11, AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
1003 OS_REG_RMW_FIELD(ah,
1004 AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);

--- 27 unchanged lines hidden (view full) ---

1032 freq_offset = FBIN2FREQ(spur_chans_ptr[i], mode) - synth_freq;
1033 if (abs(freq_offset) < range) {
1034 /*
1035 printf(
1036 "Spur Mitigation for OFDM: Synth Frequency = %d, "
1037 "Spur Frequency = %d\n",
1038 synth_freq, FBIN2FREQ(spur_chans_ptr[i], mode));
1039 */
1016 }
1017
1018 /* Clean all spur register fields */
1019 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
1020 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING11, AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
1021 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING11, AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
1022 OS_REG_RMW_FIELD(ah,
1023 AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);

--- 27 unchanged lines hidden (view full) ---

1051 freq_offset = FBIN2FREQ(spur_chans_ptr[i], mode) - synth_freq;
1052 if (abs(freq_offset) < range) {
1053 /*
1054 printf(
1055 "Spur Mitigation for OFDM: Synth Frequency = %d, "
1056 "Spur Frequency = %d\n",
1057 synth_freq, FBIN2FREQ(spur_chans_ptr[i], mode));
1058 */
1040 if (IS_CHAN_HT40(chan)) {
1059 if (IEEE80211_IS_CHAN_HT40(chan)) {
1041 if (freq_offset < 0) {
1042 if (OS_REG_READ_FIELD(
1043 ah, AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
1044 {
1045 spur_subchannel_sd = 1;
1046 } else {
1047 spur_subchannel_sd = 0;
1048 }

--- 113 unchanged lines hidden (view full) ---

1162}
1163
1164
1165/*
1166 * Convert to baseband spur frequency given input channel frequency
1167 * and compute register settings below.
1168 */
1169static void
1060 if (freq_offset < 0) {
1061 if (OS_REG_READ_FIELD(
1062 ah, AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
1063 {
1064 spur_subchannel_sd = 1;
1065 } else {
1066 spur_subchannel_sd = 0;
1067 }

--- 113 unchanged lines hidden (view full) ---

1181}
1182
1183
1184/*
1185 * Convert to baseband spur frequency given input channel frequency
1186 * and compute register settings below.
1187 */
1188static void
1170ar9300_spur_mitigate(struct ath_hal *ah, HAL_CHANNEL *chan)
1189ar9300_spur_mitigate(struct ath_hal *ah, struct ieee80211_channel *chan)
1171{
1172 ar9300_spur_mitigate_ofdm(ah, chan);
1173 ar9300_spur_mitigate_mrc_cck(ah, chan);
1174}
1175
1190{
1191 ar9300_spur_mitigate_ofdm(ah, chan);
1192 ar9300_spur_mitigate_mrc_cck(ah, chan);
1193}
1194
1176
1177/**************************************************************
1178 * ar9300_channel_change
1179 * Assumes caller wants to change channel, and not reset.
1180 */
1181static inline HAL_BOOL
1195/**************************************************************
1196 * ar9300_channel_change
1197 * Assumes caller wants to change channel, and not reset.
1198 */
1199static inline HAL_BOOL
1182ar9300_channel_change(struct ath_hal *ah, HAL_CHANNEL *chan,
1200ar9300_channel_change(struct ath_hal *ah, struct ieee80211_channel *chan,
1183 HAL_CHANNEL_INTERNAL *ichan, HAL_HT_MACMODE macmode)
1184{
1185
1186 u_int32_t synth_delay, qnum;
1187 struct ath_hal_9300 *ahp = AH9300(ah);
1188
1189 /* TX must be stopped by now */
1190 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {

--- 6 unchanged lines hidden (view full) ---

1197 }
1198
1199
1200 /*
1201 * Kill last Baseband Rx Frame - Request analog bus grant
1202 */
1203 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1204 if (!ath_hal_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1201 HAL_CHANNEL_INTERNAL *ichan, HAL_HT_MACMODE macmode)
1202{
1203
1204 u_int32_t synth_delay, qnum;
1205 struct ath_hal_9300 *ahp = AH9300(ah);
1206
1207 /* TX must be stopped by now */
1208 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {

--- 6 unchanged lines hidden (view full) ---

1215 }
1216
1217
1218 /*
1219 * Kill last Baseband Rx Frame - Request analog bus grant
1220 */
1221 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1222 if (!ath_hal_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1205 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT))
1223 AR_PHY_RFBUS_GRANT_EN))
1206 {
1224 {
1207 HALDEBUG(ah, HAL_DEBUG_PHY_IO,
1225 HALDEBUG(ah, HAL_DEBUG_PHYIO,
1208 "%s: Could not kill baseband RX\n", __func__);
1209 return AH_FALSE;
1210 }
1211
1212
1213 /* Setup 11n MAC/Phy mode registers */
1214 ar9300_set_11n_regs(ah, chan, macmode);
1215
1216 /*
1217 * Change the synth
1218 */
1226 "%s: Could not kill baseband RX\n", __func__);
1227 return AH_FALSE;
1228 }
1229
1230
1231 /* Setup 11n MAC/Phy mode registers */
1232 ar9300_set_11n_regs(ah, chan, macmode);
1233
1234 /*
1235 * Change the synth
1236 */
1219 if (!ahp->ah_rf_hal.set_channel(ah, ichan)) {
1237 if (!ahp->ah_rf_hal.set_channel(ah, chan)) {
1220 HALDEBUG(ah, HAL_DEBUG_CHANNEL, "%s: failed to set channel\n", __func__);
1221 return AH_FALSE;
1222 }
1223
1224 /*
1225 * Some registers get reinitialized during ATH_INI_POST INI programming.
1226 */
1227 ar9300_init_user_settings(ah);
1228
1229 /*
1230 * Setup the transmit power values.
1231 *
1232 * After the public to private hal channel mapping, ichan contains the
1233 * valid regulatory power value.
1234 * ath_hal_getctl and ath_hal_getantennaallowed look up ichan from chan.
1235 */
1236 if (ar9300_eeprom_set_transmit_power(
1238 HALDEBUG(ah, HAL_DEBUG_CHANNEL, "%s: failed to set channel\n", __func__);
1239 return AH_FALSE;
1240 }
1241
1242 /*
1243 * Some registers get reinitialized during ATH_INI_POST INI programming.
1244 */
1245 ar9300_init_user_settings(ah);
1246
1247 /*
1248 * Setup the transmit power values.
1249 *
1250 * After the public to private hal channel mapping, ichan contains the
1251 * valid regulatory power value.
1252 * ath_hal_getctl and ath_hal_getantennaallowed look up ichan from chan.
1253 */
1254 if (ar9300_eeprom_set_transmit_power(
1237 ah, &ahp->ah_eeprom, ichan, ath_hal_getctl(ah, chan),
1255 ah, &ahp->ah_eeprom, chan, ath_hal_getctl(ah, chan),
1238 ath_hal_getantennaallowed(ah, chan),
1239 ath_hal_get_twice_max_regpower(AH_PRIVATE(ah), ichan, chan),
1256 ath_hal_getantennaallowed(ah, chan),
1257 ath_hal_get_twice_max_regpower(AH_PRIVATE(ah), ichan, chan),
1240 AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_power_limit)) != HAL_OK)
1258 AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit)) != HAL_OK)
1241 {
1242 HALDEBUG(ah, HAL_DEBUG_EEPROM,
1243 "%s: error init'ing transmit power\n", __func__);
1244 return AH_FALSE;
1245 }
1246
1247 /*
1248 * Release the RFBus Grant.
1249 */
1250 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1251
1252 /*
1253 * Write spur immunity and delta slope for OFDM enabled modes (A, G, Turbo)
1254 */
1259 {
1260 HALDEBUG(ah, HAL_DEBUG_EEPROM,
1261 "%s: error init'ing transmit power\n", __func__);
1262 return AH_FALSE;
1263 }
1264
1265 /*
1266 * Release the RFBus Grant.
1267 */
1268 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1269
1270 /*
1271 * Write spur immunity and delta slope for OFDM enabled modes (A, G, Turbo)
1272 */
1255 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) {
1256 ar9300_set_delta_slope(ah, ichan);
1273 if (IEEE80211_IS_CHAN_OFDM(chan) || IEEE80211_IS_CHAN_HT(chan)) {
1274 ar9300_set_delta_slope(ah, chan);
1257 } else {
1258 /* Set to Ini default */
1259 OS_REG_WRITE(ah, AR_PHY_TIMING3, 0x9c0a9f6b);
1260 OS_REG_WRITE(ah, AR_PHY_SGI_DELTA, 0x00046384);
1261 }
1262
1263 ar9300_spur_mitigate(ah, chan);
1264
1265
1266 /*
1267 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
1268 * Read the phy active delay register. Value is in 100ns increments.
1269 */
1270 synth_delay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1275 } else {
1276 /* Set to Ini default */
1277 OS_REG_WRITE(ah, AR_PHY_TIMING3, 0x9c0a9f6b);
1278 OS_REG_WRITE(ah, AR_PHY_SGI_DELTA, 0x00046384);
1279 }
1280
1281 ar9300_spur_mitigate(ah, chan);
1282
1283
1284 /*
1285 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
1286 * Read the phy active delay register. Value is in 100ns increments.
1287 */
1288 synth_delay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1271 if (IS_CHAN_CCK(chan)) {
1289 if (IEEE80211_IS_CHAN_CCK(chan)) {
1272 synth_delay = (4 * synth_delay) / 22;
1273 } else {
1274 synth_delay /= 10;
1275 }
1276
1277 OS_DELAY(synth_delay + BASE_ACTIVATE_DELAY);
1278
1279 /*

--- 25 unchanged lines hidden (view full) ---

1305 case HAL_M_MONITOR:
1306 OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1307 break;
1308 }
1309}
1310
1311/* XXX need the logic for Osprey */
1312inline void
1290 synth_delay = (4 * synth_delay) / 22;
1291 } else {
1292 synth_delay /= 10;
1293 }
1294
1295 OS_DELAY(synth_delay + BASE_ACTIVATE_DELAY);
1296
1297 /*

--- 25 unchanged lines hidden (view full) ---

1323 case HAL_M_MONITOR:
1324 OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1325 break;
1326 }
1327}
1328
1329/* XXX need the logic for Osprey */
1330inline void
1313ar9300_init_pll(struct ath_hal *ah, HAL_CHANNEL *chan)
1331ar9300_init_pll(struct ath_hal *ah, struct ieee80211_channel *chan)
1314{
1315 u_int32_t pll;
1316 u_int8_t clk_25mhz = AH9300(ah)->clk_25mhz;
1332{
1333 u_int32_t pll;
1334 u_int8_t clk_25mhz = AH9300(ah)->clk_25mhz;
1335 HAL_CHANNEL_INTERNAL *ichan = NULL;
1317
1336
1337 if (chan)
1338 ichan = ath_hal_checkchannel(ah, chan);
1339
1318 if (AR_SREV_HORNET(ah)) {
1319 if (clk_25mhz) {
1320 /* Hornet uses PLL_CONTROL_2. Xtal is 25MHz for Hornet.
1321 * REFDIV set to 0x1.
1322 * $xtal_freq = 25;
1323 * $PLL2_div = (704/$xtal_freq); # 176 * 4 = 704.
1324 * MAC and BB run at 176 MHz.
1325 * $PLL2_divint = int($PLL2_div);

--- 207 unchanged lines hidden (view full) ---

1533 /* Supposedly not needed on Osprey */
1534#if 0
1535 if (chan && IS_CHAN_HALF_RATE(chan)) {
1536 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1537 } else if (chan && IS_CHAN_QUARTER_RATE(chan)) {
1538 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1539 }
1540#endif
1340 if (AR_SREV_HORNET(ah)) {
1341 if (clk_25mhz) {
1342 /* Hornet uses PLL_CONTROL_2. Xtal is 25MHz for Hornet.
1343 * REFDIV set to 0x1.
1344 * $xtal_freq = 25;
1345 * $PLL2_div = (704/$xtal_freq); # 176 * 4 = 704.
1346 * MAC and BB run at 176 MHz.
1347 * $PLL2_divint = int($PLL2_div);

--- 207 unchanged lines hidden (view full) ---

1555 /* Supposedly not needed on Osprey */
1556#if 0
1557 if (chan && IS_CHAN_HALF_RATE(chan)) {
1558 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1559 } else if (chan && IS_CHAN_QUARTER_RATE(chan)) {
1560 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1561 }
1562#endif
1541 if (chan && IS_CHAN_5GHZ(chan)) {
1563 if (ichan && IS_CHAN_5GHZ(ichan)) {
1542 pll |= SM(0x28, AR_RTC_PLL_DIV);
1543 /*
1544 * When doing fast clock, set PLL to 0x142c
1545 */
1546 if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
1547 pll = 0x142c;
1548 }
1549 } else {

--- 70 unchanged lines hidden (view full) ---

1620
1621#ifdef AH_SUPPORT_HORNET
1622 /* Hornet WAR: trigger SoC to reset WMAC if ...
1623 * (1) doing cold reset. Ref: EV 69254
1624 * (2) beacon pending. Ref: EV 70983
1625 */
1626 if (AR_SREV_HORNET(ah) &&
1627 (ar9300_num_tx_pending(
1564 pll |= SM(0x28, AR_RTC_PLL_DIV);
1565 /*
1566 * When doing fast clock, set PLL to 0x142c
1567 */
1568 if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
1569 pll = 0x142c;
1570 }
1571 } else {

--- 70 unchanged lines hidden (view full) ---

1642
1643#ifdef AH_SUPPORT_HORNET
1644 /* Hornet WAR: trigger SoC to reset WMAC if ...
1645 * (1) doing cold reset. Ref: EV 69254
1646 * (2) beacon pending. Ref: EV 70983
1647 */
1648 if (AR_SREV_HORNET(ah) &&
1649 (ar9300_num_tx_pending(
1628 ah, AH_PRIVATE(ah)->ah_caps.hal_total_queues - 1) != 0 ||
1650 ah, AH_PRIVATE(ah)->ah_caps.halTotalQueues - 1) != 0 ||
1629 type == HAL_RESET_COLD))
1630 {
1631 u_int32_t time_out;
1632#define AR_SOC_RST_RESET 0xB806001C
1633#define AR_SOC_BOOT_STRAP 0xB80600AC
1634#define AR_SOC_WLAN_RST 0x00000800 /* WLAN reset */
1635#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val);
1636#define REG_READ(_reg) *((volatile u_int32_t *)(_reg))

--- 120 unchanged lines hidden (view full) ---

1757 OS_REG_WRITE(ah, AR_RTC_RC, rst_flags);
1758
1759 OS_DELAY(50); /* XXX 50 usec */
1760
1761 /*
1762 * Clear resets and force wakeup
1763 */
1764 OS_REG_WRITE(ah, AR_RTC_RC, 0);
1651 type == HAL_RESET_COLD))
1652 {
1653 u_int32_t time_out;
1654#define AR_SOC_RST_RESET 0xB806001C
1655#define AR_SOC_BOOT_STRAP 0xB80600AC
1656#define AR_SOC_WLAN_RST 0x00000800 /* WLAN reset */
1657#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val);
1658#define REG_READ(_reg) *((volatile u_int32_t *)(_reg))

--- 120 unchanged lines hidden (view full) ---

1779 OS_REG_WRITE(ah, AR_RTC_RC, rst_flags);
1780
1781 OS_DELAY(50); /* XXX 50 usec */
1782
1783 /*
1784 * Clear resets and force wakeup
1785 */
1786 OS_REG_WRITE(ah, AR_RTC_RC, 0);
1765 if (!ath_hal_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1787 if (!ath_hal_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) {
1766 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
1767 "%s: RTC stuck in MAC reset\n", __FUNCTION__);
1768 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
1769 "%s: AR_RTC_RC = 0x%x\n", __func__, OS_REG_READ(ah, AR_RTC_RC));
1770 return AH_FALSE;
1771 }
1772
1773 /* Clear AHB reset */

--- 18 unchanged lines hidden (view full) ---

1792 */
1793 OS_REG_WRITE(ah, AR_RTC_RESET, 0);
1794 OS_DELAY(2);
1795 OS_REG_WRITE(ah, AR_RTC_RESET, 1);
1796
1797 /*
1798 * Poll till RTC is ON
1799 */
1788 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
1789 "%s: RTC stuck in MAC reset\n", __FUNCTION__);
1790 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
1791 "%s: AR_RTC_RC = 0x%x\n", __func__, OS_REG_READ(ah, AR_RTC_RC));
1792 return AH_FALSE;
1793 }
1794
1795 /* Clear AHB reset */

--- 18 unchanged lines hidden (view full) ---

1814 */
1815 OS_REG_WRITE(ah, AR_RTC_RESET, 0);
1816 OS_DELAY(2);
1817 OS_REG_WRITE(ah, AR_RTC_RESET, 1);
1818
1819 /*
1820 * Poll till RTC is ON
1821 */
1800#define AH_RTC_POLL_TIMEOUT AH_WAIT_TIMEOUT
1801 if (!ath_hal_wait(ah,
1802 AR_RTC_STATUS, AR_RTC_STATUS_M,
1822 if (!ath_hal_wait(ah,
1823 AR_RTC_STATUS, AR_RTC_STATUS_M,
1803 AR_RTC_STATUS_ON, AH_RTC_POLL_TIMEOUT))
1824 AR_RTC_STATUS_ON))
1804 {
1805 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
1825 {
1826 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
1806 "%s: RTC not waking up for %d\n", __FUNCTION__, AH_WAIT_TIMEOUT);
1827 "%s: RTC not waking up for %d\n", __FUNCTION__, 1000);
1807 return AH_FALSE;
1808 }
1809
1810 /*
1811 * Read Revisions from Chip right after RTC is on for the first time.
1812 * This helps us detect the chip type early and initialize it accordingly.
1813 */
1814 ar9300_read_revisions(ah);

--- 29 unchanged lines hidden (view full) ---

1844 case HAL_RESET_COLD:
1845 ret = ar9300_set_reset(ah, type);
1846 break;
1847 default:
1848 break;
1849 }
1850
1851#if ATH_SUPPORT_MCI
1828 return AH_FALSE;
1829 }
1830
1831 /*
1832 * Read Revisions from Chip right after RTC is on for the first time.
1833 * This helps us detect the chip type early and initialize it accordingly.
1834 */
1835 ar9300_read_revisions(ah);

--- 29 unchanged lines hidden (view full) ---

1865 case HAL_RESET_COLD:
1866 ret = ar9300_set_reset(ah, type);
1867 break;
1868 default:
1869 break;
1870 }
1871
1872#if ATH_SUPPORT_MCI
1852 if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) {
1873 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
1853 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1854 }
1855#endif
1856
1857 return ret;
1858}
1859
1860/*

--- 65 unchanged lines hidden (view full) ---

1926}
1927
1928/*
1929 * TODO: Only write the PLL if we're changing to or from CCK mode
1930 *
1931 * WARNING: The order of the PLL and mode registers must be correct.
1932 */
1933static inline void
1874 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1875 }
1876#endif
1877
1878 return ret;
1879}
1880
1881/*

--- 65 unchanged lines hidden (view full) ---

1947}
1948
1949/*
1950 * TODO: Only write the PLL if we're changing to or from CCK mode
1951 *
1952 * WARNING: The order of the PLL and mode registers must be correct.
1953 */
1954static inline void
1934ar9300_set_rf_mode(struct ath_hal *ah, HAL_CHANNEL *chan)
1955ar9300_set_rf_mode(struct ath_hal *ah, struct ieee80211_channel *chan)
1935{
1936 u_int32_t rf_mode = 0;
1937
1938 if (chan == AH_NULL) {
1939 return;
1940 }
1941 switch (AH9300(ah)->ah_hwp) {
1942 case HAL_TRUE_CHIP:
1956{
1957 u_int32_t rf_mode = 0;
1958
1959 if (chan == AH_NULL) {
1960 return;
1961 }
1962 switch (AH9300(ah)->ah_hwp) {
1963 case HAL_TRUE_CHIP:
1943 rf_mode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) ?
1964 rf_mode |= (IEEE80211_IS_CHAN_B(chan) || IEEE80211_IS_CHAN_G(chan)) ?
1944 AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1945 break;
1946 default:
1947 HALASSERT(0);
1948 break;
1949 }
1950 /* Phy mode bits for 5GHz channels requiring Fast Clock */
1951 if ( IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
1952 rf_mode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1953 }
1954 OS_REG_WRITE(ah, AR_PHY_MODE, rf_mode);
1955}
1956
1957/*
1958 * Places the hardware into reset and then pulls it out of reset
1959 */
1960HAL_BOOL
1965 AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1966 break;
1967 default:
1968 HALASSERT(0);
1969 break;
1970 }
1971 /* Phy mode bits for 5GHz channels requiring Fast Clock */
1972 if ( IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
1973 rf_mode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1974 }
1975 OS_REG_WRITE(ah, AR_PHY_MODE, rf_mode);
1976}
1977
1978/*
1979 * Places the hardware into reset and then pulls it out of reset
1980 */
1981HAL_BOOL
1961ar9300_chip_reset(struct ath_hal *ah, HAL_CHANNEL *chan)
1982ar9300_chip_reset(struct ath_hal *ah, struct ieee80211_channel *chan)
1962{
1963 struct ath_hal_9300 *ahp = AH9300(ah);
1983{
1984 struct ath_hal_9300 *ahp = AH9300(ah);
1964 OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->channel : 0);
1965
1985
1986 OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0);
1987
1966 /*
1967 * Warm reset is optimistic.
1968 */
1969 if (!ar9300_set_reset_reg(ah, HAL_RESET_WARM)) {
1970 return AH_FALSE;
1971 }
1972
1973 /* Bring out of sleep mode (AGAIN) */

--- 168 unchanged lines hidden (view full) ---

2142 } else {
2143 chainmask = 0x3F;
2144 }
2145
2146 /*
2147 * Write filtered NF values into max_cca_pwr register parameter
2148 * so we can load below.
2149 */
1988 /*
1989 * Warm reset is optimistic.
1990 */
1991 if (!ar9300_set_reset_reg(ah, HAL_RESET_WARM)) {
1992 return AH_FALSE;
1993 }
1994
1995 /* Bring out of sleep mode (AGAIN) */

--- 168 unchanged lines hidden (view full) ---

2164 } else {
2165 chainmask = 0x3F;
2166 }
2167
2168 /*
2169 * Write filtered NF values into max_cca_pwr register parameter
2170 * so we can load below.
2171 */
2150 for (i = 0; i < NUM_NF_READINGS; i++) {
2172 for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
2151 if (chainmask & (1 << i)) {
2152 val = OS_REG_READ(ah, ar9300_cca_regs[i]);
2153 val &= 0xFFFFFE00;
2154 val |= (((u_int32_t)(nf[i]) << 1) & 0x1ff);
2155 OS_REG_WRITE(ah, ar9300_cca_regs[i], val);
2156 }
2157 }
2158
2173 if (chainmask & (1 << i)) {
2174 val = OS_REG_READ(ah, ar9300_cca_regs[i]);
2175 val &= 0xFFFFFE00;
2176 val |= (((u_int32_t)(nf[i]) << 1) & 0x1ff);
2177 OS_REG_WRITE(ah, ar9300_cca_regs[i], val);
2178 }
2179 }
2180
2181 HALDEBUG(ah, HAL_DEBUG_NFCAL, "%s: load %d %d %d %d %d %d\n",
2182 __func__,
2183 nf[0], nf[1], nf[2],
2184 nf[3], nf[4], nf[5]);
2185
2159 /*
2160 * Load software filtered NF value into baseband internal min_cca_pwr
2161 * variable.
2162 */
2163 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
2164 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
2165 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
2166

--- 27 unchanged lines hidden (view full) ---

2194 return AH_FALSE;
2195 }
2196
2197 /*
2198 * Restore max_cca_power register parameter again so that we're not capped
2199 * by the median we just loaded. This will be initial (and max) value
2200 * of next noise floor calibration the baseband does.
2201 */
2186 /*
2187 * Load software filtered NF value into baseband internal min_cca_pwr
2188 * variable.
2189 */
2190 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
2191 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
2192 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
2193

--- 27 unchanged lines hidden (view full) ---

2221 return AH_FALSE;
2222 }
2223
2224 /*
2225 * Restore max_cca_power register parameter again so that we're not capped
2226 * by the median we just loaded. This will be initial (and max) value
2227 * of next noise floor calibration the baseband does.
2228 */
2202 for (i = 0; i < NUM_NF_READINGS; i++) {
2229 for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
2203 if (chainmask & (1 << i)) {
2204 val = OS_REG_READ(ah, ar9300_cca_regs[i]);
2205 val &= 0xFFFFFE00;
2206 val |= (((u_int32_t)(-50) << 1) & 0x1ff);
2207 OS_REG_WRITE(ah, ar9300_cca_regs[i], val);
2208 }
2209 }
2210 return AH_TRUE;

--- 33 unchanged lines hidden (view full) ---

2244
2245 if (ahp->ah_cal_samples >= curr_cal->cal_data->cal_num_samples) {
2246 /*
2247 * Process accumulated data
2248 */
2249 curr_cal->cal_data->cal_post_proc(ah, num_chains);
2250
2251 /* Calibration has finished. */
2230 if (chainmask & (1 << i)) {
2231 val = OS_REG_READ(ah, ar9300_cca_regs[i]);
2232 val &= 0xFFFFFE00;
2233 val |= (((u_int32_t)(-50) << 1) & 0x1ff);
2234 OS_REG_WRITE(ah, ar9300_cca_regs[i], val);
2235 }
2236 }
2237 return AH_TRUE;

--- 33 unchanged lines hidden (view full) ---

2271
2272 if (ahp->ah_cal_samples >= curr_cal->cal_data->cal_num_samples) {
2273 /*
2274 * Process accumulated data
2275 */
2276 curr_cal->cal_data->cal_post_proc(ah, num_chains);
2277
2278 /* Calibration has finished. */
2252 ichan->cal_valid |= curr_cal->cal_data->cal_type;
2279 ichan->calValid |= curr_cal->cal_data->cal_type;
2253 curr_cal->cal_state = CAL_DONE;
2254 *is_cal_done = AH_TRUE;
2255 } else {
2256 /* Set-up collection of another sub-sample until we
2257 * get desired number
2258 */
2259 ar9300_setup_calibration(ah, curr_cal);
2260 }
2261 }
2280 curr_cal->cal_state = CAL_DONE;
2281 *is_cal_done = AH_TRUE;
2282 } else {
2283 /* Set-up collection of another sub-sample until we
2284 * get desired number
2285 */
2286 ar9300_setup_calibration(ah, curr_cal);
2287 }
2288 }
2262 } else if (!(ichan->cal_valid & curr_cal->cal_data->cal_type)) {
2289 } else if (!(ichan->calValid & curr_cal->cal_data->cal_type)) {
2263 /* If current cal is marked invalid in channel, kick it off */
2264 ar9300_reset_calibration(ah, curr_cal);
2265 }
2266}
2267
2268static void
2269ar9300_start_nf_cal(struct ath_hal *ah)
2270{
2271 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
2272 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
2273 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
2274 AH9300(ah)->nf_tsf32 = ar9300_get_tsf32(ah);
2275}
2276
2277/* ar9300_calibration
2278 * Wrapper for a more generic Calibration routine. Primarily to abstract to
2279 * upper layers whether there is 1 or more calibrations to be run.
2280 */
2281HAL_BOOL
2290 /* If current cal is marked invalid in channel, kick it off */
2291 ar9300_reset_calibration(ah, curr_cal);
2292 }
2293}
2294
2295static void
2296ar9300_start_nf_cal(struct ath_hal *ah)
2297{
2298 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
2299 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
2300 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
2301 AH9300(ah)->nf_tsf32 = ar9300_get_tsf32(ah);
2302}
2303
2304/* ar9300_calibration
2305 * Wrapper for a more generic Calibration routine. Primarily to abstract to
2306 * upper layers whether there is 1 or more calibrations to be run.
2307 */
2308HAL_BOOL
2282ar9300_calibration(struct ath_hal *ah, HAL_CHANNEL *chan, u_int8_t rxchainmask,
2309ar9300_calibration(struct ath_hal *ah, struct ieee80211_channel *chan, u_int8_t rxchainmask,
2283 HAL_BOOL do_nf_cal, HAL_BOOL *is_cal_done, int is_scan,
2284 u_int32_t *sched_cals)
2285{
2286 struct ath_hal_9300 *ahp = AH9300(ah);
2287 HAL_CAL_LIST *curr_cal = ahp->ah_cal_list_curr;
2288 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2310 HAL_BOOL do_nf_cal, HAL_BOOL *is_cal_done, int is_scan,
2311 u_int32_t *sched_cals)
2312{
2313 struct ath_hal_9300 *ahp = AH9300(ah);
2314 HAL_CAL_LIST *curr_cal = ahp->ah_cal_list_curr;
2315 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2289 int16_t nf_buf[NUM_NF_READINGS];
2316 int16_t nf_buf[HAL_NUM_NF_READINGS];
2290
2291 *is_cal_done = AH_TRUE;
2292
2293
2294 /* XXX: For initial wasp bringup - disable periodic calibration */
2295 /* Invalid channel check */
2296 if (ichan == AH_NULL) {
2297 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
2298 "%s: invalid channel %u/0x%x; no mapping\n",
2317
2318 *is_cal_done = AH_TRUE;
2319
2320
2321 /* XXX: For initial wasp bringup - disable periodic calibration */
2322 /* Invalid channel check */
2323 if (ichan == AH_NULL) {
2324 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
2325 "%s: invalid channel %u/0x%x; no mapping\n",
2299 __func__, chan->channel, chan->channel_flags);
2326 __func__, chan->ic_freq, chan->ic_flags);
2300 return AH_FALSE;
2301 }
2302
2303 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2304 "%s: Entering, Doing NF Cal = %d\n", __func__, do_nf_cal);
2305 HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s: Chain 0 Rx IQ Cal Correction 0x%08x\n",
2306 __func__, OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
2307 if (!AR_SREV_HORNET(ah) && !AR_SREV_POSEIDON(ah) && !AR_SREV_APHRODITE(ah)) {
2308 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2309 "%s: Chain 1 Rx IQ Cal Correction 0x%08x\n",
2310 __func__, OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B1));
2311 if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) {
2312 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2313 "%s: Chain 2 Rx IQ Cal Correction 0x%08x\n",
2314 __func__, OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B2));
2315 }
2316 }
2317
2327 return AH_FALSE;
2328 }
2329
2330 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2331 "%s: Entering, Doing NF Cal = %d\n", __func__, do_nf_cal);
2332 HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s: Chain 0 Rx IQ Cal Correction 0x%08x\n",
2333 __func__, OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
2334 if (!AR_SREV_HORNET(ah) && !AR_SREV_POSEIDON(ah) && !AR_SREV_APHRODITE(ah)) {
2335 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2336 "%s: Chain 1 Rx IQ Cal Correction 0x%08x\n",
2337 __func__, OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B1));
2338 if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) {
2339 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2340 "%s: Chain 2 Rx IQ Cal Correction 0x%08x\n",
2341 __func__, OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B2));
2342 }
2343 }
2344
2318 OS_MARK(ah, AH_MARK_PERCAL, chan->channel);
2345 OS_MARK(ah, AH_MARK_PERCAL, chan->ic_freq);
2319
2320 /* For given calibration:
2321 * 1. Call generic cal routine
2322 * 2. When this cal is done (is_cal_done) if we have more cals waiting
2323 * (eg after reset), mask this to upper layers by not propagating
2324 * is_cal_done if it is set to TRUE.
2325 * Instead, change is_cal_done to FALSE and setup the waiting cal(s)
2326 * to be run.

--- 16 unchanged lines hidden (view full) ---

2343 }
2344 }
2345
2346 /* Do NF cal only at longer intervals */
2347 if (do_nf_cal) {
2348 int nf_done;
2349
2350 /* Get the value from the previous NF cal and update history buffer */
2346
2347 /* For given calibration:
2348 * 1. Call generic cal routine
2349 * 2. When this cal is done (is_cal_done) if we have more cals waiting
2350 * (eg after reset), mask this to upper layers by not propagating
2351 * is_cal_done if it is set to TRUE.
2352 * Instead, change is_cal_done to FALSE and setup the waiting cal(s)
2353 * to be run.

--- 16 unchanged lines hidden (view full) ---

2370 }
2371 }
2372
2373 /* Do NF cal only at longer intervals */
2374 if (do_nf_cal) {
2375 int nf_done;
2376
2377 /* Get the value from the previous NF cal and update history buffer */
2351 nf_done = ar9300_store_new_nf(ah, ichan, is_scan);
2378 nf_done = ar9300_store_new_nf(ah, chan, is_scan);
2379#if 0
2352 if (ichan->channel_flags & CHANNEL_CW_INT) {
2353 chan->channel_flags |= CHANNEL_CW_INT;
2354 }
2380 if (ichan->channel_flags & CHANNEL_CW_INT) {
2381 chan->channel_flags |= CHANNEL_CW_INT;
2382 }
2355 ichan->channel_flags &= (~CHANNEL_CW_INT);
2383#endif
2384 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;
2356
2357 if (nf_done) {
2358 /*
2359 * Load the NF from history buffer of the current channel.
2360 * NF is slow time-variant, so it is OK to use a historical value.
2361 */
2385
2386 if (nf_done) {
2387 /*
2388 * Load the NF from history buffer of the current channel.
2389 * NF is slow time-variant, so it is OK to use a historical value.
2390 */
2362 ar9300_get_nf_hist_base(ah,
2363 AH_PRIVATE(ah)->ah_curchan, is_scan, nf_buf);
2391 ar9300_get_nf_hist_base(ah, ichan, is_scan, nf_buf);
2364 ar9300_load_nf(ah, nf_buf);
2365
2366 /* start NF calibration, without updating BB NF register*/
2367 ar9300_start_nf_cal(ah);
2368 }
2369 }
2370 return AH_TRUE;
2371}

--- 152 unchanged lines hidden (view full) ---

2524 * NB: limit is in units of 0.5 dbM.
2525 */
2526HAL_BOOL
2527ar9300_set_tx_power_limit(struct ath_hal *ah, u_int32_t limit,
2528 u_int16_t extra_txpow, u_int16_t tpc_in_db)
2529{
2530 struct ath_hal_9300 *ahp = AH9300(ah);
2531 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2392 ar9300_load_nf(ah, nf_buf);
2393
2394 /* start NF calibration, without updating BB NF register*/
2395 ar9300_start_nf_cal(ah);
2396 }
2397 }
2398 return AH_TRUE;
2399}

--- 152 unchanged lines hidden (view full) ---

2552 * NB: limit is in units of 0.5 dbM.
2553 */
2554HAL_BOOL
2555ar9300_set_tx_power_limit(struct ath_hal *ah, u_int32_t limit,
2556 u_int16_t extra_txpow, u_int16_t tpc_in_db)
2557{
2558 struct ath_hal_9300 *ahp = AH9300(ah);
2559 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2532 HAL_CHANNEL_INTERNAL *ichan = ahpriv->ah_curchan;
2533 HAL_CHANNEL *chan = (HAL_CHANNEL *)ichan;
2560 const struct ieee80211_channel *chan = ahpriv->ah_curchan;
2561 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2534
2535 if (NULL == chan) {
2562
2563 if (NULL == chan) {
2536 return AH_FALSE;
2537 }
2538 ahpriv->ah_power_limit = AH_MIN(limit, MAX_RATE_POWER);
2539 ahpriv->ah_extra_txpow = extra_txpow;
2564 return AH_FALSE;
2565 }
2540
2566
2567 ahpriv->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER);
2568 ahpriv->ah_extraTxPow = extra_txpow;
2569
2541 if(chan == NULL) {
2542 return AH_FALSE;
2543 }
2570 if(chan == NULL) {
2571 return AH_FALSE;
2572 }
2544 if (ar9300_eeprom_set_transmit_power(ah, &ahp->ah_eeprom, ichan,
2573 if (ar9300_eeprom_set_transmit_power(ah, &ahp->ah_eeprom, chan,
2545 ath_hal_getctl(ah, chan), ath_hal_getantennaallowed(ah, chan),
2546 ath_hal_get_twice_max_regpower(ahpriv, ichan, chan),
2574 ath_hal_getctl(ah, chan), ath_hal_getantennaallowed(ah, chan),
2575 ath_hal_get_twice_max_regpower(ahpriv, ichan, chan),
2547 AH_MIN(MAX_RATE_POWER, ahpriv->ah_power_limit)) != HAL_OK)
2576 AH_MIN(MAX_RATE_POWER, ahpriv->ah_powerLimit)) != HAL_OK)
2548 {
2549 return AH_FALSE;
2550 }
2551 return AH_TRUE;
2552}
2553
2554/*
2555 * Exported call to check for a recent gain reading and return

--- 5 unchanged lines hidden (view full) ---

2561 return HAL_RFGAIN_INACTIVE;
2562}
2563
2564#define HAL_GREEN_AP_RX_MASK 0x1
2565
2566static inline void
2567ar9300_init_chain_masks(struct ath_hal *ah, int rx_chainmask, int tx_chainmask)
2568{
2577 {
2578 return AH_FALSE;
2579 }
2580 return AH_TRUE;
2581}
2582
2583/*
2584 * Exported call to check for a recent gain reading and return

--- 5 unchanged lines hidden (view full) ---

2590 return HAL_RFGAIN_INACTIVE;
2591}
2592
2593#define HAL_GREEN_AP_RX_MASK 0x1
2594
2595static inline void
2596ar9300_init_chain_masks(struct ath_hal *ah, int rx_chainmask, int tx_chainmask)
2597{
2569 if (AH_PRIVATE(ah)->green_ap_ps_on ) {
2598 if (AH9300(ah)->green_ap_ps_on) {
2570 rx_chainmask = HAL_GREEN_AP_RX_MASK;
2571 }
2572 if (rx_chainmask == 0x5) {
2573 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
2574 }
2575 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2576 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2577
2578 /*
2579 * Adaptive Power Management:
2580 * Some 3 stream chips exceed the PCIe power requirements.
2581 * This workaround will reduce power consumption by using 2 tx chains
2582 * for 1 and 2 stream rates (5 GHz only).
2583 *
2584 * Set the self gen mask to 2 tx chains when APM is enabled.
2585 *
2586 */
2599 rx_chainmask = HAL_GREEN_AP_RX_MASK;
2600 }
2601 if (rx_chainmask == 0x5) {
2602 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
2603 }
2604 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2605 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2606
2607 /*
2608 * Adaptive Power Management:
2609 * Some 3 stream chips exceed the PCIe power requirements.
2610 * This workaround will reduce power consumption by using 2 tx chains
2611 * for 1 and 2 stream rates (5 GHz only).
2612 *
2613 * Set the self gen mask to 2 tx chains when APM is enabled.
2614 *
2615 */
2587 if (AH_PRIVATE(ah)->ah_caps.hal_enable_apm && (tx_chainmask == 0x7)) {
2616 if (AH_PRIVATE(ah)->ah_caps.halApmEnable && (tx_chainmask == 0x7)) {
2588 OS_REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
2589 }
2590 else {
2591 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
2592 }
2593
2594 if (tx_chainmask == 0x5) {
2595 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
2596 }
2597}
2598
2599/*
2600 * Override INI values with chip specific configuration.
2601 */
2602static inline void
2617 OS_REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
2618 }
2619 else {
2620 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
2621 }
2622
2623 if (tx_chainmask == 0x5) {
2624 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
2625 }
2626}
2627
2628/*
2629 * Override INI values with chip specific configuration.
2630 */
2631static inline void
2603ar9300_override_ini(struct ath_hal *ah, HAL_CHANNEL *chan)
2632ar9300_override_ini(struct ath_hal *ah, struct ieee80211_channel *chan)
2604{
2605 u_int32_t val;
2606 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
2607
2608 /*
2609 * Set the RX_ABORT and RX_DIS and clear it only after
2610 * RXE is set for MAC. This prevents frames with
2611 * corrupted descriptor status.

--- 11 unchanged lines hidden (view full) ---

2623 val | AR_BUG_58603_FIX_ENABLE | AR_AGG_WEP_ENABLE);
2624
2625
2626 /* Osprey revision specific configuration */
2627
2628 /* Osprey 2.0+ - if SW RAC support is disabled, must also disable
2629 * the Osprey 2.0 hardware RAC fix.
2630 */
2633{
2634 u_int32_t val;
2635 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
2636
2637 /*
2638 * Set the RX_ABORT and RX_DIS and clear it only after
2639 * RXE is set for MAC. This prevents frames with
2640 * corrupted descriptor status.

--- 11 unchanged lines hidden (view full) ---

2652 val | AR_BUG_58603_FIX_ENABLE | AR_AGG_WEP_ENABLE);
2653
2654
2655 /* Osprey revision specific configuration */
2656
2657 /* Osprey 2.0+ - if SW RAC support is disabled, must also disable
2658 * the Osprey 2.0 hardware RAC fix.
2659 */
2631 if (p_cap->hal_isr_rac_support == AH_FALSE) {
2660 if (p_cap->halIsrRacSupport == AH_FALSE) {
2632 OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_MISSING_TX_INTR_FIX_ENABLE);
2633 }
2634
2635 /* try to enable old pal if it is needed for h/w green tx */
2636 ar9300_hwgreentx_set_pal_spare(ah, 1);
2637}
2638
2639static inline void

--- 28 unchanged lines hidden (view full) ---

2668 */
2669 OS_REG_WRITE(ah, reg, val);
2670 WAR_6773(reg_writes);
2671
2672 }
2673}
2674
2675static inline HAL_STATUS
2661 OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_MISSING_TX_INTR_FIX_ENABLE);
2662 }
2663
2664 /* try to enable old pal if it is needed for h/w green tx */
2665 ar9300_hwgreentx_set_pal_spare(ah, 1);
2666}
2667
2668static inline void

--- 28 unchanged lines hidden (view full) ---

2697 */
2698 OS_REG_WRITE(ah, reg, val);
2699 WAR_6773(reg_writes);
2700
2701 }
2702}
2703
2704static inline HAL_STATUS
2676ar9300_process_ini(struct ath_hal *ah, HAL_CHANNEL *chan,
2705ar9300_process_ini(struct ath_hal *ah, struct ieee80211_channel *chan,
2677 HAL_CHANNEL_INTERNAL *ichan, HAL_HT_MACMODE macmode)
2678{
2679 int reg_writes = 0;
2680 struct ath_hal_9300 *ahp = AH9300(ah);
2681 u_int modes_index, modes_txgaintable_index = 0;
2682 int i;
2683 HAL_STATUS status;
2684 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2685 /* Setup the indices for the next set of register array writes */
2686 /* TODO:
2687 * If the channel marker is indicative of the current mode rather
2688 * than capability, we do not need to check the phy mode below.
2689 */
2706 HAL_CHANNEL_INTERNAL *ichan, HAL_HT_MACMODE macmode)
2707{
2708 int reg_writes = 0;
2709 struct ath_hal_9300 *ahp = AH9300(ah);
2710 u_int modes_index, modes_txgaintable_index = 0;
2711 int i;
2712 HAL_STATUS status;
2713 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2714 /* Setup the indices for the next set of register array writes */
2715 /* TODO:
2716 * If the channel marker is indicative of the current mode rather
2717 * than capability, we do not need to check the phy mode below.
2718 */
2719#if 0
2690 switch (chan->channel_flags & CHANNEL_ALL) {
2691 case CHANNEL_A:
2692 case CHANNEL_A_HT20:
2693 if (AR_SREV_SCORPION(ah)){
2694 if (chan->channel <= 5350){
2695 modes_txgaintable_index = 1;
2696 }else if ((chan->channel > 5350) && (chan->channel <= 5600)){
2697 modes_txgaintable_index = 3;

--- 38 unchanged lines hidden (view full) ---

2736 case CHANNEL_108G:
2737 modes_index = 5;
2738 break;
2739
2740 default:
2741 HALASSERT(0);
2742 return HAL_EINVAL;
2743 }
2720 switch (chan->channel_flags & CHANNEL_ALL) {
2721 case CHANNEL_A:
2722 case CHANNEL_A_HT20:
2723 if (AR_SREV_SCORPION(ah)){
2724 if (chan->channel <= 5350){
2725 modes_txgaintable_index = 1;
2726 }else if ((chan->channel > 5350) && (chan->channel <= 5600)){
2727 modes_txgaintable_index = 3;

--- 38 unchanged lines hidden (view full) ---

2766 case CHANNEL_108G:
2767 modes_index = 5;
2768 break;
2769
2770 default:
2771 HALASSERT(0);
2772 return HAL_EINVAL;
2773 }
2774#endif
2744
2775
2776 /* FreeBSD */
2777 if (IS_CHAN_5GHZ(ichan)) {
2778 if (IEEE80211_IS_CHAN_HT40U(chan) || IEEE80211_IS_CHAN_HT40D(chan)) {
2779 if (AR_SREV_SCORPION(ah)){
2780 if (ichan->channel <= 5350){
2781 modes_txgaintable_index = 2;
2782 }else if ((ichan->channel > 5350) && (ichan->channel <= 5600)){
2783 modes_txgaintable_index = 4;
2784 }else if (ichan->channel > 5600){
2785 modes_txgaintable_index = 6;
2786 }
2787 }
2788 modes_index = 2;
2789 } else if (IEEE80211_IS_CHAN_A(chan) || IEEE80211_IS_CHAN_HT20(chan)) {
2790 if (AR_SREV_SCORPION(ah)){
2791 if (ichan->channel <= 5350){
2792 modes_txgaintable_index = 1;
2793 }else if ((ichan->channel > 5350) && (ichan->channel <= 5600)){
2794 modes_txgaintable_index = 3;
2795 }else if (ichan->channel > 5600){
2796 modes_txgaintable_index = 5;
2797 }
2798 }
2799 modes_index = 1;
2800 } else
2801 return HAL_EINVAL;
2802 } else if (IS_CHAN_2GHZ(ichan)) {
2803 if (IEEE80211_IS_CHAN_108G(chan)) {
2804 modes_index = 5;
2805 } else if (IEEE80211_IS_CHAN_HT40U(chan) || IEEE80211_IS_CHAN_HT40D(chan)) {
2806 if (AR_SREV_SCORPION(ah)){
2807 modes_txgaintable_index = 7;
2808 }
2809 modes_index = 3;
2810 } else if (IEEE80211_IS_CHAN_HT20(chan) || IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_B(chan) || IEEE80211_IS_CHAN_PUREG(chan)) {
2811 if (AR_SREV_SCORPION(ah)){
2812 modes_txgaintable_index = 8;
2813 }
2814 modes_index = 4;
2815 } else
2816 return HAL_EINVAL;
2817 } else
2818 return HAL_EINVAL;
2819
2745#if 0
2746 /* Set correct Baseband to analog shift setting to access analog chips. */
2747 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
2748#endif
2749
2750 HALDEBUG(ah, HAL_DEBUG_RESET,
2751 "ar9300_process_ini: "
2752 "Skipping OS-REG-WRITE(ah, AR-PHY(0), 0x00000007)\n");

--- 117 unchanged lines hidden (view full) ---

2870 }
2871
2872 if (AR_SREV_WASP(ah) && (AH9300(ah)->clk_25mhz == 0)) {
2873 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Apply 40MHz ini settings\n", __func__);
2874 REG_WRITE_ARRAY(
2875 &ahp->ah_ini_modes_additional_40mhz, 1/*modesIndex*/, reg_writes);
2876 }
2877
2820#if 0
2821 /* Set correct Baseband to analog shift setting to access analog chips. */
2822 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
2823#endif
2824
2825 HALDEBUG(ah, HAL_DEBUG_RESET,
2826 "ar9300_process_ini: "
2827 "Skipping OS-REG-WRITE(ah, AR-PHY(0), 0x00000007)\n");

--- 117 unchanged lines hidden (view full) ---

2945 }
2946
2947 if (AR_SREV_WASP(ah) && (AH9300(ah)->clk_25mhz == 0)) {
2948 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Apply 40MHz ini settings\n", __func__);
2949 REG_WRITE_ARRAY(
2950 &ahp->ah_ini_modes_additional_40mhz, 1/*modesIndex*/, reg_writes);
2951 }
2952
2878 if (2484 == chan->channel) {
2953 /* Handle Japan Channel 14 channel spreading */
2954 if (2484 == ichan->channel) {
2879 ar9300_prog_ini(ah, &ahp->ah_ini_japan2484, 1);
2880 }
2881
2882#if 0
2883 if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) {
2884 ar9300_prog_ini(ah, &ahp->ah_ini_BTCOEX_MAX_TXPWR, 1);
2885 }
2886#endif

--- 14 unchanged lines hidden (view full) ---

2901
2902 /*
2903 * Setup the transmit power values.
2904 *
2905 * After the public to private hal channel mapping, ichan contains the
2906 * valid regulatory power value.
2907 * ath_hal_getctl and ath_hal_getantennaallowed look up ichan from chan.
2908 */
2955 ar9300_prog_ini(ah, &ahp->ah_ini_japan2484, 1);
2956 }
2957
2958#if 0
2959 if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) {
2960 ar9300_prog_ini(ah, &ahp->ah_ini_BTCOEX_MAX_TXPWR, 1);
2961 }
2962#endif

--- 14 unchanged lines hidden (view full) ---

2977
2978 /*
2979 * Setup the transmit power values.
2980 *
2981 * After the public to private hal channel mapping, ichan contains the
2982 * valid regulatory power value.
2983 * ath_hal_getctl and ath_hal_getantennaallowed look up ichan from chan.
2984 */
2909 status = ar9300_eeprom_set_transmit_power(ah, &ahp->ah_eeprom, ichan,
2985 status = ar9300_eeprom_set_transmit_power(ah, &ahp->ah_eeprom, chan,
2910 ath_hal_getctl(ah, chan), ath_hal_getantennaallowed(ah, chan),
2911 ath_hal_get_twice_max_regpower(ahpriv, ichan, chan),
2986 ath_hal_getctl(ah, chan), ath_hal_getantennaallowed(ah, chan),
2987 ath_hal_get_twice_max_regpower(ahpriv, ichan, chan),
2912 AH_MIN(MAX_RATE_POWER, ahpriv->ah_power_limit));
2988 AH_MIN(MAX_RATE_POWER, ahpriv->ah_powerLimit));
2913 if (status != HAL_OK) {
2914 HALDEBUG(ah, HAL_DEBUG_POWER_MGMT,
2915 "%s: error init'ing transmit power\n", __func__);
2916 return HAL_EIO;
2917 }
2918
2919
2920 return HAL_OK;
2921#undef N
2922}
2923
2924/* ar9300_is_cal_supp
2925 * Determine if calibration is supported by device and channel flags
2926 */
2927inline static HAL_BOOL
2989 if (status != HAL_OK) {
2990 HALDEBUG(ah, HAL_DEBUG_POWER_MGMT,
2991 "%s: error init'ing transmit power\n", __func__);
2992 return HAL_EIO;
2993 }
2994
2995
2996 return HAL_OK;
2997#undef N
2998}
2999
3000/* ar9300_is_cal_supp
3001 * Determine if calibration is supported by device and channel flags
3002 */
3003inline static HAL_BOOL
2928ar9300_is_cal_supp(struct ath_hal *ah, HAL_CHANNEL *chan,
3004ar9300_is_cal_supp(struct ath_hal *ah, const struct ieee80211_channel *chan,
2929 HAL_CAL_TYPES cal_type)
2930{
2931 struct ath_hal_9300 *ahp = AH9300(ah);
2932 HAL_BOOL retval = AH_FALSE;
2933
2934 switch (cal_type & ahp->ah_supp_cals) {
2935 case IQ_MISMATCH_CAL:
2936 /* Run IQ Mismatch for non-CCK only */
3005 HAL_CAL_TYPES cal_type)
3006{
3007 struct ath_hal_9300 *ahp = AH9300(ah);
3008 HAL_BOOL retval = AH_FALSE;
3009
3010 switch (cal_type & ahp->ah_supp_cals) {
3011 case IQ_MISMATCH_CAL:
3012 /* Run IQ Mismatch for non-CCK only */
2937 if (!IS_CHAN_B(chan)) {
3013 if (!IEEE80211_IS_CHAN_B(chan)) {
2938 retval = AH_TRUE;
2939 }
2940 break;
2941 case TEMP_COMP_CAL:
2942 retval = AH_TRUE;
2943 break;
2944 }
2945

--- 177 unchanged lines hidden (view full) ---

3123 */
3124inline static HAL_BOOL
3125ar9300_run_init_cals(struct ath_hal *ah, int init_cal_count)
3126{
3127 struct ath_hal_9300 *ahp = AH9300(ah);
3128 HAL_CHANNEL_INTERNAL ichan; /* bogus */
3129 HAL_BOOL is_cal_done;
3130 HAL_CAL_LIST *curr_cal;
3014 retval = AH_TRUE;
3015 }
3016 break;
3017 case TEMP_COMP_CAL:
3018 retval = AH_TRUE;
3019 break;
3020 }
3021

--- 177 unchanged lines hidden (view full) ---

3199 */
3200inline static HAL_BOOL
3201ar9300_run_init_cals(struct ath_hal *ah, int init_cal_count)
3202{
3203 struct ath_hal_9300 *ahp = AH9300(ah);
3204 HAL_CHANNEL_INTERNAL ichan; /* bogus */
3205 HAL_BOOL is_cal_done;
3206 HAL_CAL_LIST *curr_cal;
3207 const HAL_PERCAL_DATA *cal_data;
3131 int i;
3132
3133 curr_cal = ahp->ah_cal_list_curr;
3134 if (curr_cal == AH_NULL) {
3135 return AH_FALSE;
3136 }
3208 int i;
3209
3210 curr_cal = ahp->ah_cal_list_curr;
3211 if (curr_cal == AH_NULL) {
3212 return AH_FALSE;
3213 }
3137 ichan.cal_valid = 0;
3214 cal_data = curr_cal->cal_data;
3215 ichan.calValid = 0;
3138
3139 for (i = 0; i < init_cal_count; i++) {
3140 /* Reset this Cal */
3141 ar9300_reset_calibration(ah, curr_cal);
3142 /* Poll for offset calibration complete */
3143 if (!ath_hal_wait(
3216
3217 for (i = 0; i < init_cal_count; i++) {
3218 /* Reset this Cal */
3219 ar9300_reset_calibration(ah, curr_cal);
3220 /* Poll for offset calibration complete */
3221 if (!ath_hal_wait(
3144 ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL, 0, AH_WAIT_TIMEOUT))
3222 ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL, 0))
3145 {
3146 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3147 "%s: Cal %d failed to complete in 100ms.\n",
3148 __func__, curr_cal->cal_data->cal_type);
3149 /* Re-initialize list pointers for periodic cals */
3150 ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr
3151 = AH_NULL;
3152 return AH_FALSE;

--- 121 unchanged lines hidden (view full) ---

3274
3275 return restore_status;
3276}
3277
3278/* ar9300_init_cal
3279 * Initialize Calibration infrastructure
3280 */
3281static inline HAL_BOOL
3223 {
3224 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3225 "%s: Cal %d failed to complete in 100ms.\n",
3226 __func__, curr_cal->cal_data->cal_type);
3227 /* Re-initialize list pointers for periodic cals */
3228 ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr
3229 = AH_NULL;
3230 return AH_FALSE;

--- 121 unchanged lines hidden (view full) ---

3352
3353 return restore_status;
3354}
3355
3356/* ar9300_init_cal
3357 * Initialize Calibration infrastructure
3358 */
3359static inline HAL_BOOL
3282ar9300_init_cal_internal(struct ath_hal *ah, HAL_CHANNEL *chan,
3283 HAL_CHANNEL_INTERNAL *ichan, HAL_BOOL enable_rtt,
3284 HAL_BOOL do_rtt_cal, HAL_BOOL skip_if_none, HAL_BOOL apply_last_iqcorr)
3360ar9300_init_cal_internal(struct ath_hal *ah, struct ieee80211_channel *chan,
3361 HAL_CHANNEL_INTERNAL *ichan,
3362 HAL_BOOL enable_rtt, HAL_BOOL do_rtt_cal, HAL_BOOL skip_if_none, HAL_BOOL apply_last_iqcorr)
3285{
3286 struct ath_hal_9300 *ahp = AH9300(ah);
3287 HAL_BOOL txiqcal_success_flag = AH_FALSE;
3288 HAL_BOOL cal_done = AH_FALSE;
3289 int iqcal_idx = 0;
3290 HAL_BOOL do_sep_iq_cal = AH_FALSE;
3291 HAL_BOOL do_agc_cal = do_rtt_cal;
3292 HAL_BOOL is_cal_reusable = AH_TRUE;

--- 47 unchanged lines hidden (view full) ---

3340 OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
3341 do_agc_cal = AH_TRUE;
3342 }
3343 }
3344
3345 /* Do Tx IQ Calibration here for osprey hornet and wasp */
3346 /* XXX: For initial wasp bringup - check and enable this */
3347 /* EV 74233: Tx IQ fails to complete for half/quarter rates */
3363{
3364 struct ath_hal_9300 *ahp = AH9300(ah);
3365 HAL_BOOL txiqcal_success_flag = AH_FALSE;
3366 HAL_BOOL cal_done = AH_FALSE;
3367 int iqcal_idx = 0;
3368 HAL_BOOL do_sep_iq_cal = AH_FALSE;
3369 HAL_BOOL do_agc_cal = do_rtt_cal;
3370 HAL_BOOL is_cal_reusable = AH_TRUE;

--- 47 unchanged lines hidden (view full) ---

3418 OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
3419 do_agc_cal = AH_TRUE;
3420 }
3421 }
3422
3423 /* Do Tx IQ Calibration here for osprey hornet and wasp */
3424 /* XXX: For initial wasp bringup - check and enable this */
3425 /* EV 74233: Tx IQ fails to complete for half/quarter rates */
3348 if (!(IS_CHAN_HALF_RATE(ichan) || IS_CHAN_QUARTER_RATE(ichan))) {
3426 if (!(IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan))) {
3349 if (ahp->tx_iq_cal_enable) {
3350 /* this should be eventually moved to INI file */
3351 OS_REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1(ah),
3352 AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT);
3353
3354 /*
3355 * For poseidon and later chips,
3356 * Tx IQ cal HW run will be a part of AGC calibration

--- 41 unchanged lines hidden (view full) ---

3398 {
3399 do_sep_iq_cal = AH_TRUE;
3400 do_agc_cal = AH_TRUE;
3401 }
3402 }
3403 }
3404
3405#if ATH_SUPPORT_MCI
3427 if (ahp->tx_iq_cal_enable) {
3428 /* this should be eventually moved to INI file */
3429 OS_REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1(ah),
3430 AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT);
3431
3432 /*
3433 * For poseidon and later chips,
3434 * Tx IQ cal HW run will be a part of AGC calibration

--- 41 unchanged lines hidden (view full) ---

3476 {
3477 do_sep_iq_cal = AH_TRUE;
3478 do_agc_cal = AH_TRUE;
3479 }
3480 }
3481 }
3482
3483#if ATH_SUPPORT_MCI
3406 if (AH_PRIVATE(ah)->ah_caps.hal_mci_support &&
3484 if (AH_PRIVATE(ah)->ah_caps.halMciSupport &&
3407 IS_CHAN_2GHZ(ichan) &&
3408 (ahp->ah_mci_bt_state == MCI_BT_AWAKE) &&
3409 do_agc_cal &&
3485 IS_CHAN_2GHZ(ichan) &&
3486 (ahp->ah_mci_bt_state == MCI_BT_AWAKE) &&
3487 do_agc_cal &&
3410 !(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
3488 !(ah->ah_config.ath_hal_mci_config &
3411 ATH_MCI_CONFIG_DISABLE_MCI_CAL))
3412 {
3413 u_int32_t payload[4] = {0, 0, 0, 0};
3414
3415 /* Send CAL_REQ only when BT is AWAKE. */
3416 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Send WLAN_CAL_REQ 0x%X\n",
3417 __func__, ahp->ah_mci_wlan_cal_seq);
3418 MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_REQ);

--- 38 unchanged lines hidden (view full) ---

3457 */
3458 if(!AR_SREV_SCORPION(ah)) {
3459 if (do_agc_cal || !skip_if_none) {
3460 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
3461 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
3462
3463 /* Poll for offset calibration complete */
3464 cal_done = ath_hal_wait(ah,
3489 ATH_MCI_CONFIG_DISABLE_MCI_CAL))
3490 {
3491 u_int32_t payload[4] = {0, 0, 0, 0};
3492
3493 /* Send CAL_REQ only when BT is AWAKE. */
3494 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Send WLAN_CAL_REQ 0x%X\n",
3495 __func__, ahp->ah_mci_wlan_cal_seq);
3496 MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_REQ);

--- 38 unchanged lines hidden (view full) ---

3535 */
3536 if(!AR_SREV_SCORPION(ah)) {
3537 if (do_agc_cal || !skip_if_none) {
3538 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
3539 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
3540
3541 /* Poll for offset calibration complete */
3542 cal_done = ath_hal_wait(ah,
3465 AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT);
3543 AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0);
3466 if (!cal_done) {
3467 HALDEBUG(ah, HAL_DEBUG_FCS_RTT,
3468 "(FCS) CAL NOT DONE!!! - %d\n", ichan->channel);
3469 }
3470 } else {
3471 cal_done = AH_TRUE;
3472 }
3473 /*
3474 * Tx IQ cal post-processing in SW
3475 * This part of code should be common to all chips,
3476 * no chip specific code for Jupiter/Posdeion except for register names.
3477 */
3478 if (txiqcal_success_flag) {
3479 ar9300_tx_iq_cal_post_proc(ah,ichan, 1, 1,is_cal_reusable,false);
3480 }
3481 } else {
3482 if (!txiqcal_success_flag) {
3483 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
3484 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
3544 if (!cal_done) {
3545 HALDEBUG(ah, HAL_DEBUG_FCS_RTT,
3546 "(FCS) CAL NOT DONE!!! - %d\n", ichan->channel);
3547 }
3548 } else {
3549 cal_done = AH_TRUE;
3550 }
3551 /*
3552 * Tx IQ cal post-processing in SW
3553 * This part of code should be common to all chips,
3554 * no chip specific code for Jupiter/Posdeion except for register names.
3555 */
3556 if (txiqcal_success_flag) {
3557 ar9300_tx_iq_cal_post_proc(ah,ichan, 1, 1,is_cal_reusable,false);
3558 }
3559 } else {
3560 if (!txiqcal_success_flag) {
3561 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
3562 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
3485 if (!ath_hal_wait( ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
3486 0, AH_WAIT_TIMEOUT)) {
3563 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
3564 0)) {
3487 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3488 "%s: offset calibration failed to complete in 1ms; "
3489 "noisy environment?\n", __func__);
3490 return AH_FALSE;
3491 }
3492 if (apply_last_iqcorr == AH_TRUE) {
3493 ar9300_tx_iq_cal_post_proc(ah, ichan, 0, 0, is_cal_reusable, AH_TRUE);
3494 }
3495 } else {
3496 for (iqcal_idx=0;iqcal_idx<MAXIQCAL;iqcal_idx++) {
3497 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
3498 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
3499
3500 /* Poll for offset calibration complete */
3501 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL,
3565 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3566 "%s: offset calibration failed to complete in 1ms; "
3567 "noisy environment?\n", __func__);
3568 return AH_FALSE;
3569 }
3570 if (apply_last_iqcorr == AH_TRUE) {
3571 ar9300_tx_iq_cal_post_proc(ah, ichan, 0, 0, is_cal_reusable, AH_TRUE);
3572 }
3573 } else {
3574 for (iqcal_idx=0;iqcal_idx<MAXIQCAL;iqcal_idx++) {
3575 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
3576 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
3577
3578 /* Poll for offset calibration complete */
3579 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL,
3502 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
3580 AR_PHY_AGC_CONTROL_CAL, 0)) {
3503 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3504 "%s: offset calibration failed to complete in 1ms; "
3505 "noisy environment?\n", __func__);
3506 return AH_FALSE;
3507 }
3508 /*
3509 * Tx IQ cal post-processing in SW
3510 * This part of code should be common to all chips,
3511 * no chip specific code for Jupiter/Posdeion except for register names.
3512 */
3513 ar9300_tx_iq_cal_post_proc(ah, ichan, iqcal_idx+1, MAXIQCAL, is_cal_reusable, AH_FALSE);
3514 }
3515 }
3516 }
3517
3518
3519#if ATH_SUPPORT_MCI
3581 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3582 "%s: offset calibration failed to complete in 1ms; "
3583 "noisy environment?\n", __func__);
3584 return AH_FALSE;
3585 }
3586 /*
3587 * Tx IQ cal post-processing in SW
3588 * This part of code should be common to all chips,
3589 * no chip specific code for Jupiter/Posdeion except for register names.
3590 */
3591 ar9300_tx_iq_cal_post_proc(ah, ichan, iqcal_idx+1, MAXIQCAL, is_cal_reusable, AH_FALSE);
3592 }
3593 }
3594 }
3595
3596
3597#if ATH_SUPPORT_MCI
3520 if (AH_PRIVATE(ah)->ah_caps.hal_mci_support &&
3598 if (AH_PRIVATE(ah)->ah_caps.halMciSupport &&
3521 IS_CHAN_2GHZ(ichan) &&
3522 (ahp->ah_mci_bt_state == MCI_BT_AWAKE) &&
3523 do_agc_cal &&
3599 IS_CHAN_2GHZ(ichan) &&
3600 (ahp->ah_mci_bt_state == MCI_BT_AWAKE) &&
3601 do_agc_cal &&
3524 !(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
3602 !(ah->ah_config.ath_hal_mci_config &
3525 ATH_MCI_CONFIG_DISABLE_MCI_CAL))
3526 {
3527 u_int32_t payload[4] = {0, 0, 0, 0};
3528
3529 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Send WLAN_CAL_DONE 0x%X\n",
3530 __func__, ahp->ah_mci_wlan_cal_done);
3531 MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
3532 payload[MCI_GPM_WLAN_CAL_W_SEQUENCE] = ahp->ah_mci_wlan_cal_done++;

--- 67 unchanged lines hidden (view full) ---

3600 }
3601 ichan->one_time_txclcal_done = AH_TRUE;
3602 HALDEBUG(ah, HAL_DEBUG_FCS_RTT,
3603 "(FCS) TX CL CAL saved - %d\n", ichan->channel);
3604 }
3605 }
3606#endif /* ATH_SUPPORT_CAL_REUSE */
3607
3603 ATH_MCI_CONFIG_DISABLE_MCI_CAL))
3604 {
3605 u_int32_t payload[4] = {0, 0, 0, 0};
3606
3607 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Send WLAN_CAL_DONE 0x%X\n",
3608 __func__, ahp->ah_mci_wlan_cal_done);
3609 MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
3610 payload[MCI_GPM_WLAN_CAL_W_SEQUENCE] = ahp->ah_mci_wlan_cal_done++;

--- 67 unchanged lines hidden (view full) ---

3678 }
3679 ichan->one_time_txclcal_done = AH_TRUE;
3680 HALDEBUG(ah, HAL_DEBUG_FCS_RTT,
3681 "(FCS) TX CL CAL saved - %d\n", ichan->channel);
3682 }
3683 }
3684#endif /* ATH_SUPPORT_CAL_REUSE */
3685
3608
3609 /* Revert chainmasks to their original values before NF cal */
3610 ar9300_init_chain_masks(ah, ahp->ah_rx_chainmask, ahp->ah_tx_chainmask);
3611
3612#if !FIX_NOISE_FLOOR
3613 /*
3614 * Do NF calibration after DC offset and other CALs.
3615 * Per system engineers, noise floor value can sometimes be 20 dB
3616 * higher than normal value if DC offset and noise floor cal are

--- 46 unchanged lines hidden (view full) ---

3663 ahp->ah_cal_list_curr = ahp->ah_cal_list;
3664
3665 /* Reset state within current cal */
3666 if (ahp->ah_cal_list_curr) {
3667 ar9300_reset_calibration(ah, ahp->ah_cal_list_curr);
3668 }
3669
3670 /* Mark all calibrations on this channel as being invalid */
3686 /* Revert chainmasks to their original values before NF cal */
3687 ar9300_init_chain_masks(ah, ahp->ah_rx_chainmask, ahp->ah_tx_chainmask);
3688
3689#if !FIX_NOISE_FLOOR
3690 /*
3691 * Do NF calibration after DC offset and other CALs.
3692 * Per system engineers, noise floor value can sometimes be 20 dB
3693 * higher than normal value if DC offset and noise floor cal are

--- 46 unchanged lines hidden (view full) ---

3740 ahp->ah_cal_list_curr = ahp->ah_cal_list;
3741
3742 /* Reset state within current cal */
3743 if (ahp->ah_cal_list_curr) {
3744 ar9300_reset_calibration(ah, ahp->ah_cal_list_curr);
3745 }
3746
3747 /* Mark all calibrations on this channel as being invalid */
3671 ichan->cal_valid = 0;
3748 ichan->calValid = 0;
3672
3673 return AH_TRUE;
3674}
3675
3676static inline HAL_BOOL
3749
3750 return AH_TRUE;
3751}
3752
3753static inline HAL_BOOL
3677ar9300_init_cal(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_BOOL skip_if_none, HAL_BOOL apply_last_iqcorr)
3754ar9300_init_cal(struct ath_hal *ah, struct ieee80211_channel *chan, HAL_BOOL skip_if_none, HAL_BOOL apply_last_iqcorr)
3678{
3679 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
3680 HAL_BOOL do_rtt_cal = AH_TRUE;
3681 HAL_BOOL enable_rtt = AH_FALSE;
3682
3683 HALASSERT(ichan);
3684
3755{
3756 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
3757 HAL_BOOL do_rtt_cal = AH_TRUE;
3758 HAL_BOOL enable_rtt = AH_FALSE;
3759
3760 HALASSERT(ichan);
3761
3685
3686
3687 return ar9300_init_cal_internal(ah, chan, ichan, enable_rtt, do_rtt_cal, skip_if_none, apply_last_iqcorr);
3688}
3689
3690/* ar9300_reset_cal_valid
3691 * Entry point for upper layers to restart current cal.
3692 * Reset the calibration valid bit in channel.
3693 */
3694void
3762 return ar9300_init_cal_internal(ah, chan, ichan, enable_rtt, do_rtt_cal, skip_if_none, apply_last_iqcorr);
3763}
3764
3765/* ar9300_reset_cal_valid
3766 * Entry point for upper layers to restart current cal.
3767 * Reset the calibration valid bit in channel.
3768 */
3769void
3695ar9300_reset_cal_valid(struct ath_hal *ah, HAL_CHANNEL *chan,
3770ar9300_reset_cal_valid(struct ath_hal *ah, const struct ieee80211_channel *chan,
3696 HAL_BOOL *is_cal_done, u_int32_t cal_type)
3697{
3698 struct ath_hal_9300 *ahp = AH9300(ah);
3699 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
3700 HAL_CAL_LIST *curr_cal = ahp->ah_cal_list_curr;
3701
3702 *is_cal_done = AH_TRUE;
3703
3704 if (curr_cal == AH_NULL) {
3705 return;
3706 }
3707 if (ichan == AH_NULL) {
3708 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3709 "%s: invalid channel %u/0x%x; no mapping\n",
3771 HAL_BOOL *is_cal_done, u_int32_t cal_type)
3772{
3773 struct ath_hal_9300 *ahp = AH9300(ah);
3774 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
3775 HAL_CAL_LIST *curr_cal = ahp->ah_cal_list_curr;
3776
3777 *is_cal_done = AH_TRUE;
3778
3779 if (curr_cal == AH_NULL) {
3780 return;
3781 }
3782 if (ichan == AH_NULL) {
3783 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3784 "%s: invalid channel %u/0x%x; no mapping\n",
3710 __func__, chan->channel, chan->channel_flags);
3785 __func__, chan->ic_freq, chan->ic_flags);
3711 return;
3712 }
3713
3714 if (!(cal_type & IQ_MISMATCH_CAL)) {
3715 *is_cal_done = AH_FALSE;
3716 return;
3717 }
3718

--- 9 unchanged lines hidden (view full) ---

3728
3729 /* Verify Cal is supported on this channel */
3730 if (ar9300_is_cal_supp(ah, chan, curr_cal->cal_data->cal_type) == AH_FALSE) {
3731 return;
3732 }
3733
3734 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3735 "%s: Resetting Cal %d state for channel %u/0x%x\n", __func__,
3786 return;
3787 }
3788
3789 if (!(cal_type & IQ_MISMATCH_CAL)) {
3790 *is_cal_done = AH_FALSE;
3791 return;
3792 }
3793

--- 9 unchanged lines hidden (view full) ---

3803
3804 /* Verify Cal is supported on this channel */
3805 if (ar9300_is_cal_supp(ah, chan, curr_cal->cal_data->cal_type) == AH_FALSE) {
3806 return;
3807 }
3808
3809 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3810 "%s: Resetting Cal %d state for channel %u/0x%x\n", __func__,
3736 curr_cal->cal_data->cal_type, chan->channel, chan->channel_flags);
3811 curr_cal->cal_data->cal_type, chan->ic_freq, chan->ic_flags);
3737
3738 /* Disable cal validity in channel */
3812
3813 /* Disable cal validity in channel */
3739 ichan->cal_valid &= ~curr_cal->cal_data->cal_type;
3814 ichan->calValid &= ~curr_cal->cal_data->cal_type;
3740 curr_cal->cal_state = CAL_WAITING;
3741 /* Indicate to upper layers that we need polling */
3742 *is_cal_done = AH_FALSE;
3743}
3744
3745static inline void
3746ar9300_set_dma(struct ath_hal *ah)
3747{

--- 80 unchanged lines hidden (view full) ---

3828 * set receive buffer size.
3829 */
3830 if (ahp->rx_buf_size) {
3831 OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size);
3832 }
3833}
3834
3835static inline void
3815 curr_cal->cal_state = CAL_WAITING;
3816 /* Indicate to upper layers that we need polling */
3817 *is_cal_done = AH_FALSE;
3818}
3819
3820static inline void
3821ar9300_set_dma(struct ath_hal *ah)
3822{

--- 80 unchanged lines hidden (view full) ---

3903 * set receive buffer size.
3904 */
3905 if (ahp->rx_buf_size) {
3906 OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size);
3907 }
3908}
3909
3910static inline void
3836ar9300_init_bb(struct ath_hal *ah, HAL_CHANNEL *chan)
3911ar9300_init_bb(struct ath_hal *ah, struct ieee80211_channel *chan)
3837{
3838 u_int32_t synth_delay;
3839
3840 /*
3841 * Wait for the frequency synth to settle (synth goes on
3842 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
3843 * Value is in 100ns increments.
3844 */
3845 synth_delay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
3912{
3913 u_int32_t synth_delay;
3914
3915 /*
3916 * Wait for the frequency synth to settle (synth goes on
3917 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
3918 * Value is in 100ns increments.
3919 */
3920 synth_delay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
3846 if (IS_CHAN_CCK(chan)) {
3921 if (IEEE80211_IS_CHAN_CCK(chan)) {
3847 synth_delay = (4 * synth_delay) / 22;
3848 } else {
3849 synth_delay /= 10;
3850 }
3851
3852 /* Activate the PHY (includes baseband activate + synthesizer on) */
3853 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
3854

--- 44 unchanged lines hidden (view full) ---

3899 if (opmode == HAL_M_HOSTAP) {
3900 ahp->ah_mask_reg |= AR_IMR_MIB;
3901 }
3902
3903 OS_REG_WRITE(ah, AR_IMR, ahp->ah_mask_reg);
3904 OS_REG_WRITE(ah, AR_IMR_S2, OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
3905 ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2);
3906
3922 synth_delay = (4 * synth_delay) / 22;
3923 } else {
3924 synth_delay /= 10;
3925 }
3926
3927 /* Activate the PHY (includes baseband activate + synthesizer on) */
3928 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
3929

--- 44 unchanged lines hidden (view full) ---

3974 if (opmode == HAL_M_HOSTAP) {
3975 ahp->ah_mask_reg |= AR_IMR_MIB;
3976 }
3977
3978 OS_REG_WRITE(ah, AR_IMR, ahp->ah_mask_reg);
3979 OS_REG_WRITE(ah, AR_IMR_S2, OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
3980 ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2);
3981
3907 if (AH_PRIVATE(ah)->ah_config.ath_hal_enable_msi) {
3982 if (ah->ah_config.ath_hal_enable_msi) {
3908 /* Cache MSI register value */
3909 ahp->ah_msi_reg = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_MSI));
3910 ahp->ah_msi_reg |= AR_PCIE_MSI_HW_DBI_WR_EN;
3911 if (AR_SREV_POSEIDON(ah)) {
3912 ahp->ah_msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64;
3913 } else {
3914 ahp->ah_msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR;
3915 }

--- 80 unchanged lines hidden (view full) ---

3996 ar9300_cac_tx_quiet(ah, 1);
3997 }
3998#endif /* ATH_SUPPORT_DFS */
3999}
4000
4001int
4002ar9300_get_spur_info(struct ath_hal * ah, int *enable, int len, u_int16_t *freq)
4003{
3983 /* Cache MSI register value */
3984 ahp->ah_msi_reg = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_MSI));
3985 ahp->ah_msi_reg |= AR_PCIE_MSI_HW_DBI_WR_EN;
3986 if (AR_SREV_POSEIDON(ah)) {
3987 ahp->ah_msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64;
3988 } else {
3989 ahp->ah_msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR;
3990 }

--- 80 unchanged lines hidden (view full) ---

4071 ar9300_cac_tx_quiet(ah, 1);
4072 }
4073#endif /* ATH_SUPPORT_DFS */
4074}
4075
4076int
4077ar9300_get_spur_info(struct ath_hal * ah, int *enable, int len, u_int16_t *freq)
4078{
4004 struct ath_hal_private *ap = AH_PRIVATE(ah);
4079// struct ath_hal_private *ap = AH_PRIVATE(ah);
4005 int i, j;
4006
4007 for (i = 0; i < len; i++) {
4008 freq[i] = 0;
4009 }
4010
4080 int i, j;
4081
4082 for (i = 0; i < len; i++) {
4083 freq[i] = 0;
4084 }
4085
4011 *enable = ap->ah_config.ath_hal_spur_mode;
4086 *enable = ah->ah_config.ath_hal_spur_mode;
4012 for (i = 0, j = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4087 for (i = 0, j = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4013 if (ap->ah_config.ath_hal_spur_chans[i][0] != AR_NO_SPUR) {
4014 freq[j++] = ap->ah_config.ath_hal_spur_chans[i][0];
4088 if (AH9300(ah)->ath_hal_spur_chans[i][0] != AR_NO_SPUR) {
4089 freq[j++] = AH9300(ah)->ath_hal_spur_chans[i][0];
4015 HALDEBUG(ah, HAL_DEBUG_ANI,
4090 HALDEBUG(ah, HAL_DEBUG_ANI,
4016 "1. get spur %d\n", ap->ah_config.ath_hal_spur_chans[i][0]);
4091 "1. get spur %d\n", AH9300(ah)->ath_hal_spur_chans[i][0]);
4017 }
4092 }
4018 if (ap->ah_config.ath_hal_spur_chans[i][1] != AR_NO_SPUR) {
4019 freq[j++] = ap->ah_config.ath_hal_spur_chans[i][1];
4093 if (AH9300(ah)->ath_hal_spur_chans[i][1] != AR_NO_SPUR) {
4094 freq[j++] = AH9300(ah)->ath_hal_spur_chans[i][1];
4020 HALDEBUG(ah, HAL_DEBUG_ANI,
4095 HALDEBUG(ah, HAL_DEBUG_ANI,
4021 "2. get spur %d\n", ap->ah_config.ath_hal_spur_chans[i][1]);
4096 "2. get spur %d\n", AH9300(ah)->ath_hal_spur_chans[i][1]);
4022 }
4023 }
4024
4025 return 0;
4026}
4027
4028#define ATH_HAL_2GHZ_FREQ_MIN 20000
4029#define ATH_HAL_2GHZ_FREQ_MAX 29999
4030#define ATH_HAL_5GHZ_FREQ_MIN 50000
4031#define ATH_HAL_5GHZ_FREQ_MAX 59999
4032
4097 }
4098 }
4099
4100 return 0;
4101}
4102
4103#define ATH_HAL_2GHZ_FREQ_MIN 20000
4104#define ATH_HAL_2GHZ_FREQ_MAX 29999
4105#define ATH_HAL_5GHZ_FREQ_MIN 50000
4106#define ATH_HAL_5GHZ_FREQ_MAX 59999
4107
4108#if 0
4033int
4034ar9300_set_spur_info(struct ath_hal * ah, int enable, int len, u_int16_t *freq)
4035{
4036 struct ath_hal_private *ap = AH_PRIVATE(ah);
4037 int i, j, k;
4038
4039 ap->ah_config.ath_hal_spur_mode = enable;
4040
4041 if (ap->ah_config.ath_hal_spur_mode == SPUR_ENABLE_IOCTL) {
4042 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4109int
4110ar9300_set_spur_info(struct ath_hal * ah, int enable, int len, u_int16_t *freq)
4111{
4112 struct ath_hal_private *ap = AH_PRIVATE(ah);
4113 int i, j, k;
4114
4115 ap->ah_config.ath_hal_spur_mode = enable;
4116
4117 if (ap->ah_config.ath_hal_spur_mode == SPUR_ENABLE_IOCTL) {
4118 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4043 ap->ah_config.ath_hal_spur_chans[i][0] = AR_NO_SPUR;
4044 ap->ah_config.ath_hal_spur_chans[i][1] = AR_NO_SPUR;
4119 AH9300(ah)->ath_hal_spur_chans[i][0] = AR_NO_SPUR;
4120 AH9300(ah)->ath_hal_spur_chans[i][1] = AR_NO_SPUR;
4045 }
4046 for (i = 0, j = 0, k = 0; i < len; i++) {
4047 if (freq[i] > ATH_HAL_2GHZ_FREQ_MIN &&
4048 freq[i] < ATH_HAL_2GHZ_FREQ_MAX)
4049 {
4050 /* 2GHz Spur */
4051 if (j < AR_EEPROM_MODAL_SPURS) {
4121 }
4122 for (i = 0, j = 0, k = 0; i < len; i++) {
4123 if (freq[i] > ATH_HAL_2GHZ_FREQ_MIN &&
4124 freq[i] < ATH_HAL_2GHZ_FREQ_MAX)
4125 {
4126 /* 2GHz Spur */
4127 if (j < AR_EEPROM_MODAL_SPURS) {
4052 ap->ah_config.ath_hal_spur_chans[j++][1] = freq[i];
4128 AH9300(ah)->ath_hal_spur_chans[j++][1] = freq[i];
4053 HALDEBUG(ah, HAL_DEBUG_ANI, "1 set spur %d\n", freq[i]);
4054 }
4055 } else if (freq[i] > ATH_HAL_5GHZ_FREQ_MIN &&
4056 freq[i] < ATH_HAL_5GHZ_FREQ_MAX)
4057 {
4058 /* 5Ghz Spur */
4059 if (k < AR_EEPROM_MODAL_SPURS) {
4129 HALDEBUG(ah, HAL_DEBUG_ANI, "1 set spur %d\n", freq[i]);
4130 }
4131 } else if (freq[i] > ATH_HAL_5GHZ_FREQ_MIN &&
4132 freq[i] < ATH_HAL_5GHZ_FREQ_MAX)
4133 {
4134 /* 5Ghz Spur */
4135 if (k < AR_EEPROM_MODAL_SPURS) {
4060 ap->ah_config.ath_hal_spur_chans[k++][0] = freq[i];
4136 AH9300(ah)->ath_hal_spur_chans[k++][0] = freq[i];
4061 HALDEBUG(ah, HAL_DEBUG_ANI, "2 set spur %d\n", freq[i]);
4062 }
4063 }
4064 }
4065 }
4066
4067 return 0;
4068}
4137 HALDEBUG(ah, HAL_DEBUG_ANI, "2 set spur %d\n", freq[i]);
4138 }
4139 }
4140 }
4141 }
4142
4143 return 0;
4144}
4145#endif
4069
4070#define ar9300_check_op_mode(_opmode) \
4071 ((_opmode == HAL_M_STA) || (_opmode == HAL_M_IBSS) ||\
4072 (_opmode == HAL_M_HOSTAP) || (_opmode == HAL_M_MONITOR))
4073
4074
4075
4076
4077#ifndef ATH_NF_PER_CHAN
4078/*
4079* To fixed first reset noise floor value not correct issue
4080* For ART need it to fixed low rate sens too low issue
4081*/
4082static int
4083First_NFCal(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan,
4146
4147#define ar9300_check_op_mode(_opmode) \
4148 ((_opmode == HAL_M_STA) || (_opmode == HAL_M_IBSS) ||\
4149 (_opmode == HAL_M_HOSTAP) || (_opmode == HAL_M_MONITOR))
4150
4151
4152
4153
4154#ifndef ATH_NF_PER_CHAN
4155/*
4156* To fixed first reset noise floor value not correct issue
4157* For ART need it to fixed low rate sens too low issue
4158*/
4159static int
4160First_NFCal(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan,
4084 int is_scan, HAL_CHANNEL *chan)
4161 int is_scan, struct ieee80211_channel *chan)
4085{
4086 HAL_NFCAL_HIST_FULL *nfh;
4087 int i, j, k;
4162{
4163 HAL_NFCAL_HIST_FULL *nfh;
4164 int i, j, k;
4088 int16_t nfarray[NUM_NF_READINGS] = {0};
4165 int16_t nfarray[HAL_NUM_NF_READINGS] = {0};
4089 int is_2g = 0;
4090 int nf_hist_len;
4091 int stats = 0;
4092
4166 int is_2g = 0;
4167 int nf_hist_len;
4168 int stats = 0;
4169
4093 int16_t nf_buf[NUM_NF_READINGS];
4170 int16_t nf_buf[HAL_NUM_NF_READINGS];
4094#define IS(_c, _f) (((_c)->channel_flags & _f) || 0)
4095
4096
4097 if ((!is_scan) &&
4171#define IS(_c, _f) (((_c)->channel_flags & _f) || 0)
4172
4173
4174 if ((!is_scan) &&
4098 chan->channel == AH_PRIVATE(ah)->ah_curchan->channel)
4175 chan->ic_freq == AH_PRIVATE(ah)->ah_curchan->ic_freq)
4099 {
4100 nfh = &AH_PRIVATE(ah)->nf_cal_hist;
4101 } else {
4102 nfh = (HAL_NFCAL_HIST_FULL *) &ichan->nf_cal_hist;
4103 }
4176 {
4177 nfh = &AH_PRIVATE(ah)->nf_cal_hist;
4178 } else {
4179 nfh = (HAL_NFCAL_HIST_FULL *) &ichan->nf_cal_hist;
4180 }
4104
4181
4105 ar9300_start_nf_cal(ah);
4106 for (j = 0; j < 10000; j++) {
4107 if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0){
4108 break;
4109 }
4110 OS_DELAY(10);
4111 }
4112 if (j < 10000) {
4182 ar9300_start_nf_cal(ah);
4183 for (j = 0; j < 10000; j++) {
4184 if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0){
4185 break;
4186 }
4187 OS_DELAY(10);
4188 }
4189 if (j < 10000) {
4113 is_2g = IS(ichan, CHANNEL_2GHZ);
4190 is_2g = IEEE80211_IS_CHAN_2GHZ(chan);
4114 ar9300_upload_noise_floor(ah, is_2g, nfarray);
4115
4116 if (is_scan) {
4117 /*
4118 * This channel's NF cal info is just a HAL_NFCAL_HIST_SMALL struct
4119 * rather than a HAL_NFCAL_HIST_FULL struct.
4120 * As long as we only use the first history element of nf_cal_buffer
4191 ar9300_upload_noise_floor(ah, is_2g, nfarray);
4192
4193 if (is_scan) {
4194 /*
4195 * This channel's NF cal info is just a HAL_NFCAL_HIST_SMALL struct
4196 * rather than a HAL_NFCAL_HIST_FULL struct.
4197 * As long as we only use the first history element of nf_cal_buffer
4121 * (nf_cal_buffer[0][0:NUM_NF_READINGS-1]), we can use
4198 * (nf_cal_buffer[0][0:HAL_NUM_NF_READINGS-1]), we can use
4122 * HAL_NFCAL_HIST_SMALL and HAL_NFCAL_HIST_FULL interchangeably.
4123 */
4124 nfh = (HAL_NFCAL_HIST_FULL *) &ichan->nf_cal_hist;
4125 nf_hist_len = HAL_NF_CAL_HIST_LEN_SMALL;
4126 } else {
4127 nfh = &AH_PRIVATE(ah)->nf_cal_hist;
4128 nf_hist_len = HAL_NF_CAL_HIST_LEN_FULL;
4129 }
4130
4199 * HAL_NFCAL_HIST_SMALL and HAL_NFCAL_HIST_FULL interchangeably.
4200 */
4201 nfh = (HAL_NFCAL_HIST_FULL *) &ichan->nf_cal_hist;
4202 nf_hist_len = HAL_NF_CAL_HIST_LEN_SMALL;
4203 } else {
4204 nfh = &AH_PRIVATE(ah)->nf_cal_hist;
4205 nf_hist_len = HAL_NF_CAL_HIST_LEN_FULL;
4206 }
4207
4131 for (i = 0; i < NUM_NF_READINGS; i ++) {
4208 for (i = 0; i < HAL_NUM_NF_READINGS; i ++) {
4132 for (k = 0; k < HAL_NF_CAL_HIST_LEN_FULL; k++) {
4133 nfh->nf_cal_buffer[k][i] = nfarray[i];
4134 }
4135 nfh->base.priv_nf[i] = ar9300_limit_nf_range(ah,
4136 ar9300_get_nf_hist_mid(ah, nfh, i, nf_hist_len));
4137 }
4138
4139
4140 //ar9300StoreNewNf(ah, ichan, is_scan);
4141
4142 /*
4143 * See if the NF value from the old channel should be
4144 * retained when switching to a new channel.
4145 * TBD: this may need to be changed, as it wipes out the
4146 * purpose of saving NF values for each channel.
4147 */
4209 for (k = 0; k < HAL_NF_CAL_HIST_LEN_FULL; k++) {
4210 nfh->nf_cal_buffer[k][i] = nfarray[i];
4211 }
4212 nfh->base.priv_nf[i] = ar9300_limit_nf_range(ah,
4213 ar9300_get_nf_hist_mid(ah, nfh, i, nf_hist_len));
4214 }
4215
4216
4217 //ar9300StoreNewNf(ah, ichan, is_scan);
4218
4219 /*
4220 * See if the NF value from the old channel should be
4221 * retained when switching to a new channel.
4222 * TBD: this may need to be changed, as it wipes out the
4223 * purpose of saving NF values for each channel.
4224 */
4148 for (i = 0; i < NUM_NF_READINGS; i++)
4225 for (i = 0; i < HAL_NUM_NF_READINGS; i++)
4149 {
4226 {
4150 if (IS_CHAN_2GHZ(chan))
4227 if (IEEE80211_IS_CHAN_2GHZ(chan))
4151 {
4152 if (nfh->nf_cal_buffer[0][i] <
4153 AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ)
4154 {
4155 ichan->nf_cal_hist.nf_cal_buffer[0][i] =
4156 AH_PRIVATE(ah)->nf_cal_hist.nf_cal_buffer[0][i];
4157 }
4158 } else {

--- 14 unchanged lines hidden (view full) ---

4173 }
4174 }
4175 }
4176 /*
4177 * Copy the channel's NF buffer, which may have been modified
4178 * just above here, to the full NF history buffer.
4179 */
4180 ar9300_reset_nf_hist_buff(ah, ichan);
4228 {
4229 if (nfh->nf_cal_buffer[0][i] <
4230 AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ)
4231 {
4232 ichan->nf_cal_hist.nf_cal_buffer[0][i] =
4233 AH_PRIVATE(ah)->nf_cal_hist.nf_cal_buffer[0][i];
4234 }
4235 } else {

--- 14 unchanged lines hidden (view full) ---

4250 }
4251 }
4252 }
4253 /*
4254 * Copy the channel's NF buffer, which may have been modified
4255 * just above here, to the full NF history buffer.
4256 */
4257 ar9300_reset_nf_hist_buff(ah, ichan);
4181 ar9300_get_nf_hist_base(ah,
4182 AH_PRIVATE(ah)->ah_curchan, is_scan, nf_buf);
4258 ar9300_get_nf_hist_base(ah, ichan, is_scan, nf_buf);
4183 ar9300_load_nf(ah, nf_buf);
4184 stats = 0;
4185 } else {
4186 stats = 1;
4187 }
4188#undef IS
4189 return stats;
4190}

--- 4 unchanged lines hidden (view full) ---

4195 * Places the device in and out of reset and then places sane
4196 * values in the registers based on EEPROM config, initialization
4197 * vectors (as determined by the mode), and station configuration
4198 *
4199 * b_channel_change is used to preserve DMA/PCU registers across
4200 * a HW Reset during channel change.
4201 */
4202HAL_BOOL
4259 ar9300_load_nf(ah, nf_buf);
4260 stats = 0;
4261 } else {
4262 stats = 1;
4263 }
4264#undef IS
4265 return stats;
4266}

--- 4 unchanged lines hidden (view full) ---

4271 * Places the device in and out of reset and then places sane
4272 * values in the registers based on EEPROM config, initialization
4273 * vectors (as determined by the mode), and station configuration
4274 *
4275 * b_channel_change is used to preserve DMA/PCU registers across
4276 * a HW Reset during channel change.
4277 */
4278HAL_BOOL
4203ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, HAL_CHANNEL *chan,
4279ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *chan,
4204 HAL_HT_MACMODE macmode, u_int8_t txchainmask, u_int8_t rxchainmask,
4205 HAL_HT_EXTPROTSPACING extprotspacing, HAL_BOOL b_channel_change,
4206 HAL_STATUS *status, int is_scan)
4207{
4208#define FAIL(_code) do { ecode = _code; goto bad; } while (0)
4209 u_int32_t save_led_state;
4210 struct ath_hal_9300 *ahp = AH9300(ah);
4211 struct ath_hal_private *ap = AH_PRIVATE(ah);
4212 HAL_CHANNEL_INTERNAL *ichan;
4280 HAL_HT_MACMODE macmode, u_int8_t txchainmask, u_int8_t rxchainmask,
4281 HAL_HT_EXTPROTSPACING extprotspacing, HAL_BOOL b_channel_change,
4282 HAL_STATUS *status, int is_scan)
4283{
4284#define FAIL(_code) do { ecode = _code; goto bad; } while (0)
4285 u_int32_t save_led_state;
4286 struct ath_hal_9300 *ahp = AH9300(ah);
4287 struct ath_hal_private *ap = AH_PRIVATE(ah);
4288 HAL_CHANNEL_INTERNAL *ichan;
4213 HAL_CHANNEL_INTERNAL *curchan = ap->ah_curchan;
4289 //const struct ieee80211_channel *curchan = ap->ah_curchan;
4214#if ATH_SUPPORT_MCI
4215 HAL_BOOL save_full_sleep = ahp->ah_chip_full_sleep;
4216#endif
4217 u_int32_t save_def_antenna;
4218 u_int32_t mac_sta_id1;
4219 HAL_STATUS ecode;
4220 int i, rx_chainmask;
4221 int nf_hist_buff_reset = 0;
4290#if ATH_SUPPORT_MCI
4291 HAL_BOOL save_full_sleep = ahp->ah_chip_full_sleep;
4292#endif
4293 u_int32_t save_def_antenna;
4294 u_int32_t mac_sta_id1;
4295 HAL_STATUS ecode;
4296 int i, rx_chainmask;
4297 int nf_hist_buff_reset = 0;
4222 int16_t nf_buf[NUM_NF_READINGS];
4298 int16_t nf_buf[HAL_NUM_NF_READINGS];
4223#ifdef ATH_FORCE_PPM
4224 u_int32_t save_force_val, tmp_reg;
4225#endif
4226 HAL_BOOL stopped, cal_ret;
4227 HAL_BOOL apply_last_iqcorr = AH_FALSE;
4228
4229 if (OS_REG_READ(ah, AR_IER) == AR_IER_ENABLE) {
4230 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "** Reset called with WLAN "
4231 "interrupt enabled %08x **\n", ar9300_get_interrupts(ah));
4232 }
4233
4234 /*
4235 * Set the status to "ok" by default to cover the cases
4236 * where we return AH_FALSE without going to "bad"
4237 */
4238 HALASSERT(status);
4239 *status = HAL_OK;
4299#ifdef ATH_FORCE_PPM
4300 u_int32_t save_force_val, tmp_reg;
4301#endif
4302 HAL_BOOL stopped, cal_ret;
4303 HAL_BOOL apply_last_iqcorr = AH_FALSE;
4304
4305 if (OS_REG_READ(ah, AR_IER) == AR_IER_ENABLE) {
4306 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "** Reset called with WLAN "
4307 "interrupt enabled %08x **\n", ar9300_get_interrupts(ah));
4308 }
4309
4310 /*
4311 * Set the status to "ok" by default to cover the cases
4312 * where we return AH_FALSE without going to "bad"
4313 */
4314 HALASSERT(status);
4315 *status = HAL_OK;
4240 if ((AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable)) {
4241 AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_NONE;
4316 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable)) {
4317 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_NONE;
4242 }
4243
4244#if ATH_SUPPORT_MCI
4318 }
4319
4320#if ATH_SUPPORT_MCI
4245 if (AH_PRIVATE(ah)->ah_caps.hal_mci_support &&
4321 if (AH_PRIVATE(ah)->ah_caps.halMciSupport &&
4246 (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)))
4247 {
4322 (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)))
4323 {
4248 ar9300_mci_2g5g_changed(ah, IS_CHAN_2GHZ(chan));
4324 ar9300_mci_2g5g_changed(ah, IEEE80211_IS_CHAN_2GHZ(chan));
4249 }
4250#endif
4251
4252 ahp->ah_ext_prot_spacing = extprotspacing;
4325 }
4326#endif
4327
4328 ahp->ah_ext_prot_spacing = extprotspacing;
4253 ahp->ah_tx_chainmask = txchainmask & ap->ah_caps.hal_tx_chain_mask;
4254 ahp->ah_rx_chainmask = rxchainmask & ap->ah_caps.hal_rx_chain_mask;
4255 ahp->ah_tx_cal_chainmask = ap->ah_caps.hal_tx_chain_mask;
4256 ahp->ah_rx_cal_chainmask = ap->ah_caps.hal_rx_chain_mask;
4329 ahp->ah_tx_chainmask = txchainmask & ap->ah_caps.halTxChainMask;
4330 ahp->ah_rx_chainmask = rxchainmask & ap->ah_caps.halRxChainMask;
4331 ahp->ah_tx_cal_chainmask = ap->ah_caps.halTxChainMask;
4332 ahp->ah_rx_cal_chainmask = ap->ah_caps.halRxChainMask;
4257 HALASSERT(ar9300_check_op_mode(opmode));
4258
4259 OS_MARK(ah, AH_MARK_RESET, b_channel_change);
4260
4261 /*
4262 * Map public channel to private.
4263 */
4264 ichan = ar9300_check_chan(ah, chan);
4265 if (ichan == AH_NULL) {
4266 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
4267 "%s: invalid channel %u/0x%x; no mapping\n",
4333 HALASSERT(ar9300_check_op_mode(opmode));
4334
4335 OS_MARK(ah, AH_MARK_RESET, b_channel_change);
4336
4337 /*
4338 * Map public channel to private.
4339 */
4340 ichan = ar9300_check_chan(ah, chan);
4341 if (ichan == AH_NULL) {
4342 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
4343 "%s: invalid channel %u/0x%x; no mapping\n",
4268 __func__, chan->channel, chan->channel_flags);
4344 __func__, chan->ic_freq, chan->ic_flags);
4269 FAIL(HAL_EINVAL);
4270 }
4271
4272 ichan->paprd_table_write_done = 0; /* Clear PAPRD table write flag */
4345 FAIL(HAL_EINVAL);
4346 }
4347
4348 ichan->paprd_table_write_done = 0; /* Clear PAPRD table write flag */
4349#if 0
4273 chan->paprd_table_write_done = 0; /* Clear PAPRD table write flag */
4350 chan->paprd_table_write_done = 0; /* Clear PAPRD table write flag */
4351#endif
4274
4275 if (ar9300_get_power_mode(ah) != HAL_PM_FULL_SLEEP) {
4276 /* Need to stop RX DMA before reset otherwise chip might hang */
4277 stopped = ar9300_set_rx_abort(ah, AH_TRUE); /* abort and disable PCU */
4278 ar9300_set_rx_filter(ah, 0);
4279 stopped &= ar9300_stop_dma_receive(ah, 0); /* stop and disable RX DMA */
4280 if (!stopped) {
4281 /*

--- 5 unchanged lines hidden (view full) ---

4287 b_channel_change = AH_FALSE;
4288 }
4289 } else {
4290 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
4291 "%s[%d]: Chip is already in full sleep\n", __func__, __LINE__);
4292 }
4293
4294#if ATH_SUPPORT_MCI
4352
4353 if (ar9300_get_power_mode(ah) != HAL_PM_FULL_SLEEP) {
4354 /* Need to stop RX DMA before reset otherwise chip might hang */
4355 stopped = ar9300_set_rx_abort(ah, AH_TRUE); /* abort and disable PCU */
4356 ar9300_set_rx_filter(ah, 0);
4357 stopped &= ar9300_stop_dma_receive(ah, 0); /* stop and disable RX DMA */
4358 if (!stopped) {
4359 /*

--- 5 unchanged lines hidden (view full) ---

4365 b_channel_change = AH_FALSE;
4366 }
4367 } else {
4368 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
4369 "%s[%d]: Chip is already in full sleep\n", __func__, __LINE__);
4370 }
4371
4372#if ATH_SUPPORT_MCI
4295 if ((AH_PRIVATE(ah)->ah_caps.hal_mci_support) &&
4373 if ((AH_PRIVATE(ah)->ah_caps.halMciSupport) &&
4296 (ahp->ah_mci_bt_state == MCI_BT_CAL_START))
4297 {
4298 u_int32_t payload[4] = {0, 0, 0, 0};
4299
4300 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
4301 "(MCI) %s: Stop rx for BT cal.\n", __func__);
4302 ahp->ah_mci_bt_state = MCI_BT_CAL;
4303

--- 32 unchanged lines hidden (view full) ---

4336 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) {
4337 *status = HAL_INV_PMODE;
4338 return AH_FALSE;
4339 }
4340
4341 /* Check the Rx mitigation config again, it might have changed
4342 * during attach in ath_vap_attach.
4343 */
4374 (ahp->ah_mci_bt_state == MCI_BT_CAL_START))
4375 {
4376 u_int32_t payload[4] = {0, 0, 0, 0};
4377
4378 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
4379 "(MCI) %s: Stop rx for BT cal.\n", __func__);
4380 ahp->ah_mci_bt_state = MCI_BT_CAL;
4381

--- 32 unchanged lines hidden (view full) ---

4414 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) {
4415 *status = HAL_INV_PMODE;
4416 return AH_FALSE;
4417 }
4418
4419 /* Check the Rx mitigation config again, it might have changed
4420 * during attach in ath_vap_attach.
4421 */
4344 if (AH_PRIVATE(ah)->ah_config.ath_hal_intr_mitigation_rx != 0) {
4422 if (ah->ah_config.ath_hal_intr_mitigation_rx != 0) {
4345 ahp->ah_intr_mitigation_rx = AH_TRUE;
4346 } else {
4347 ahp->ah_intr_mitigation_rx = AH_FALSE;
4348 }
4349
4423 ahp->ah_intr_mitigation_rx = AH_TRUE;
4424 } else {
4425 ahp->ah_intr_mitigation_rx = AH_FALSE;
4426 }
4427
4428 /*
4429 * XXX TODO FreeBSD:
4430 *
4431 * This is painful because we don't have a non-const channel pointer
4432 * at this stage.
4433 *
4434 * Make sure this gets fixed!
4435 */
4436#if 0
4350 /* Get the value from the previous NF cal and update history buffer */
4351 if (curchan && (ahp->ah_chip_full_sleep != AH_TRUE)) {
4352 ar9300_store_new_nf(ah, curchan, is_scan);
4353 }
4437 /* Get the value from the previous NF cal and update history buffer */
4438 if (curchan && (ahp->ah_chip_full_sleep != AH_TRUE)) {
4439 ar9300_store_new_nf(ah, curchan, is_scan);
4440 }
4441#endif
4354
4355 /*
4356 * Account for the effect of being in either the 2 GHz or 5 GHz band
4357 * on the nominal, max allowable, and min allowable noise floor values.
4358 */
4442
4443 /*
4444 * Account for the effect of being in either the 2 GHz or 5 GHz band
4445 * on the nominal, max allowable, and min allowable noise floor values.
4446 */
4359 ap->nfp = IS_CHAN_2GHZ(chan) ? &ap->nf_2GHz : &ap->nf_5GHz;
4447 AH9300(ah)->nfp = IS_CHAN_2GHZ(ichan) ? &ahp->nf_2GHz : &ahp->nf_5GHz;
4360
4448
4449 /*
4450 * XXX For now, don't apply the last IQ correction.
4451 *
4452 * This should be done when scorpion is enabled on FreeBSD; just be
4453 * sure to fix this channel match code so it uses net80211 flags
4454 * instead.
4455 */
4456#if 0
4361 if (AR_SREV_SCORPION(ah) && curchan && (chan->channel == curchan->channel) &&
4362 ((chan->channel_flags & (CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER)) ==
4363 (curchan->channel_flags &
4364 (CHANNEL_ALL | CHANNEL_HALF | CHANNEL_QUARTER)))) {
4365 apply_last_iqcorr = AH_TRUE;
4366 }
4457 if (AR_SREV_SCORPION(ah) && curchan && (chan->channel == curchan->channel) &&
4458 ((chan->channel_flags & (CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER)) ==
4459 (curchan->channel_flags &
4460 (CHANNEL_ALL | CHANNEL_HALF | CHANNEL_QUARTER)))) {
4461 apply_last_iqcorr = AH_TRUE;
4462 }
4463#endif
4464 apply_last_iqcorr = AH_FALSE;
4465
4367
4368#ifndef ATH_NF_PER_CHAN
4369 /*
4370 * If there's only one full-size home-channel NF history buffer
4371 * rather than a full-size NF history buffer per channel, decide
4372 * whether to (re)initialize the home-channel NF buffer.
4373 * If this is just a channel change for a scan, or if the channel
4374 * is not being changed, don't mess up the home channel NF history
4375 * buffer with NF values from this scanned channel. If we're
4376 * changing the home channel to a new channel, reset the home-channel
4377 * NF history buffer with the most accurate NF known for the new channel.
4378 */
4379 if (!is_scan && (!ap->ah_curchan ||
4466
4467#ifndef ATH_NF_PER_CHAN
4468 /*
4469 * If there's only one full-size home-channel NF history buffer
4470 * rather than a full-size NF history buffer per channel, decide
4471 * whether to (re)initialize the home-channel NF buffer.
4472 * If this is just a channel change for a scan, or if the channel
4473 * is not being changed, don't mess up the home channel NF history
4474 * buffer with NF values from this scanned channel. If we're
4475 * changing the home channel to a new channel, reset the home-channel
4476 * NF history buffer with the most accurate NF known for the new channel.
4477 */
4478 if (!is_scan && (!ap->ah_curchan ||
4380 ap->ah_curchan->channel != chan->channel ||
4381 ap->ah_curchan->channel_flags != chan->channel_flags))
4479 ap->ah_curchan->ic_freq != chan->ic_freq)) // ||
4480// ap->ah_curchan->channel_flags != chan->channel_flags))
4382 {
4383 nf_hist_buff_reset = 1;
4384 ar9300_reset_nf_hist_buff(ah, ichan);
4385 }
4386#endif
4387 /*
4388 * Fast channel change (Change synthesizer based on channel freq
4389 * without resetting chip)

--- 4 unchanged lines hidden (view full) ---

4394 * - Channel flags are different, like when moving from 2GHz to 5GHz
4395 * channels
4396 * - Merlin: Switching in/out of fast clock enabled channels
4397 * (not currently coded, since fast clock is enabled
4398 * across the 5GHz band
4399 * and we already do a full reset when switching in/out
4400 * of 5GHz channels)
4401 */
4481 {
4482 nf_hist_buff_reset = 1;
4483 ar9300_reset_nf_hist_buff(ah, ichan);
4484 }
4485#endif
4486 /*
4487 * Fast channel change (Change synthesizer based on channel freq
4488 * without resetting chip)

--- 4 unchanged lines hidden (view full) ---

4493 * - Channel flags are different, like when moving from 2GHz to 5GHz
4494 * channels
4495 * - Merlin: Switching in/out of fast clock enabled channels
4496 * (not currently coded, since fast clock is enabled
4497 * across the 5GHz band
4498 * and we already do a full reset when switching in/out
4499 * of 5GHz channels)
4500 */
4501#if 0
4402 if (b_channel_change &&
4403 (ahp->ah_chip_full_sleep != AH_TRUE) &&
4404 (AH_PRIVATE(ah)->ah_curchan != AH_NULL) &&
4405 ((chan->channel != AH_PRIVATE(ah)->ah_curchan->channel) &&
4406 (((CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER) & chan->channel_flags) ==
4407 ((CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER) & AH_PRIVATE(ah)->ah_curchan->channel_flags))))
4408 {
4409 if (ar9300_channel_change(ah, chan, ichan, macmode)) {

--- 15 unchanged lines hidden (view full) ---

4425
4426 /*
4427 * If channel_change completed and DMA was stopped
4428 * successfully - skip the rest of reset
4429 */
4430 if (AH9300(ah)->ah_dma_stuck != AH_TRUE) {
4431 WAR_USB_DISABLE_PLL_LOCK_DETECT(ah);
4432#if ATH_SUPPORT_MCI
4502 if (b_channel_change &&
4503 (ahp->ah_chip_full_sleep != AH_TRUE) &&
4504 (AH_PRIVATE(ah)->ah_curchan != AH_NULL) &&
4505 ((chan->channel != AH_PRIVATE(ah)->ah_curchan->channel) &&
4506 (((CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER) & chan->channel_flags) ==
4507 ((CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER) & AH_PRIVATE(ah)->ah_curchan->channel_flags))))
4508 {
4509 if (ar9300_channel_change(ah, chan, ichan, macmode)) {

--- 15 unchanged lines hidden (view full) ---

4525
4526 /*
4527 * If channel_change completed and DMA was stopped
4528 * successfully - skip the rest of reset
4529 */
4530 if (AH9300(ah)->ah_dma_stuck != AH_TRUE) {
4531 WAR_USB_DISABLE_PLL_LOCK_DETECT(ah);
4532#if ATH_SUPPORT_MCI
4433 if (AH_PRIVATE(ah)->ah_caps.hal_mci_support && ahp->ah_mci_ready)
4533 if (AH_PRIVATE(ah)->ah_caps.halMciSupport && ahp->ah_mci_ready)
4434 {
4435 ar9300_mci_2g5g_switch(ah, AH_TRUE);
4436 }
4437#endif
4534 {
4535 ar9300_mci_2g5g_switch(ah, AH_TRUE);
4536 }
4537#endif
4438 return AH_TRUE;
4538 return HAL_OK;
4439 }
4440 }
4441 }
4539 }
4540 }
4541 }
4542#endif /* #if 0 */
4442
4443#if ATH_SUPPORT_MCI
4543
4544#if ATH_SUPPORT_MCI
4444 if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) {
4545 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
4445 ar9300_mci_disable_interrupt(ah);
4446 if (ahp->ah_mci_ready && !save_full_sleep) {
4447 ar9300_mci_mute_bt(ah);
4448 OS_DELAY(20);
4449 OS_REG_WRITE(ah, AR_BTCOEX_CTRL, 0);
4450 }
4451
4452 ahp->ah_mci_bt_state = MCI_BT_SLEEP;

--- 69 unchanged lines hidden (view full) ---

4522 if ((AH_PRIVATE(ah)->ah_curchan != AH_NULL) &&
4523 (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK))
4524 {
4525 /* Re-program RIFS Rx policy after reset */
4526 ar9300_set_rifs_delay(ah, ahp->ah_rifs_enabled);
4527 }
4528
4529#if ATH_SUPPORT_MCI
4546 ar9300_mci_disable_interrupt(ah);
4547 if (ahp->ah_mci_ready && !save_full_sleep) {
4548 ar9300_mci_mute_bt(ah);
4549 OS_DELAY(20);
4550 OS_REG_WRITE(ah, AR_BTCOEX_CTRL, 0);
4551 }
4552
4553 ahp->ah_mci_bt_state = MCI_BT_SLEEP;

--- 69 unchanged lines hidden (view full) ---

4623 if ((AH_PRIVATE(ah)->ah_curchan != AH_NULL) &&
4624 (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK))
4625 {
4626 /* Re-program RIFS Rx policy after reset */
4627 ar9300_set_rifs_delay(ah, ahp->ah_rifs_enabled);
4628 }
4629
4630#if ATH_SUPPORT_MCI
4530 if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) {
4531 ar9300_mci_reset(ah, AH_FALSE, IS_CHAN_2GHZ(chan), save_full_sleep);
4631 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
4632 ar9300_mci_reset(ah, AH_FALSE, IS_CHAN_2GHZ(ichan), save_full_sleep);
4532 }
4533#endif
4534
4535 /* Initialize Management Frame Protection */
4536 ar9300_init_mfp(ah);
4537
4538 ahp->ah_immunity_vals[0] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR_LOW,
4539 AR_PHY_SFCORR_LOW_M1_THRESH_LOW);

--- 4 unchanged lines hidden (view full) ---

4544 ahp->ah_immunity_vals[3] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR,
4545 AR_PHY_SFCORR_M2_THRESH);
4546 ahp->ah_immunity_vals[4] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR,
4547 AR_PHY_SFCORR_M2COUNT_THR);
4548 ahp->ah_immunity_vals[5] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR_LOW,
4549 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
4550
4551 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */
4633 }
4634#endif
4635
4636 /* Initialize Management Frame Protection */
4637 ar9300_init_mfp(ah);
4638
4639 ahp->ah_immunity_vals[0] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR_LOW,
4640 AR_PHY_SFCORR_LOW_M1_THRESH_LOW);

--- 4 unchanged lines hidden (view full) ---

4645 ahp->ah_immunity_vals[3] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR,
4646 AR_PHY_SFCORR_M2_THRESH);
4647 ahp->ah_immunity_vals[4] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR,
4648 AR_PHY_SFCORR_M2COUNT_THR);
4649 ahp->ah_immunity_vals[5] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR_LOW,
4650 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
4651
4652 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */
4552 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) {
4553 ar9300_set_delta_slope(ah, ichan);
4653 if (IEEE80211_IS_CHAN_OFDM(chan) || IEEE80211_IS_CHAN_HT(chan)) {
4654 ar9300_set_delta_slope(ah, chan);
4554 }
4555
4556 ar9300_spur_mitigate(ah, chan);
4655 }
4656
4657 ar9300_spur_mitigate(ah, chan);
4557 if (!ar9300_eeprom_set_board_values(ah, ichan)) {
4658 if (!ar9300_eeprom_set_board_values(ah, chan)) {
4558 HALDEBUG(ah, HAL_DEBUG_EEPROM,
4559 "%s: error setting board options\n", __func__);
4560 FAIL(HAL_EIO);
4561 }
4562
4563#ifdef ATH_HAL_WAR_REG16284_APH128
4564 /* temp work around, will be removed. */
4565 if (AR_SREV_WASP(ah)) {
4566 OS_REG_WRITE(ah, 0x16284, 0x1553e000);
4567 }
4568#endif
4569
4570 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
4571
4572 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
4573 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
4574 | mac_sta_id1
4575 | AR_STA_ID1_RTS_USE_DEF
4659 HALDEBUG(ah, HAL_DEBUG_EEPROM,
4660 "%s: error setting board options\n", __func__);
4661 FAIL(HAL_EIO);
4662 }
4663
4664#ifdef ATH_HAL_WAR_REG16284_APH128
4665 /* temp work around, will be removed. */
4666 if (AR_SREV_WASP(ah)) {
4667 OS_REG_WRITE(ah, 0x16284, 0x1553e000);
4668 }
4669#endif
4670
4671 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
4672
4673 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
4674 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
4675 | mac_sta_id1
4676 | AR_STA_ID1_RTS_USE_DEF
4576 | (ap->ah_config.ath_hal_6mb_ack ? AR_STA_ID1_ACKCTS_6MB : 0)
4677 | (ah->ah_config.ath_hal_6mb_ack ? AR_STA_ID1_ACKCTS_6MB : 0)
4577 | ahp->ah_sta_id1_defaults
4578 );
4579 ar9300_set_operating_mode(ah, opmode);
4580
4581 /* Set Venice BSSID mask according to current state */
4582 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask));
4583 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4));
4584

--- 12 unchanged lines hidden (view full) ---

4597 LE_READ_2(ahp->ah_bssid + 4) |
4598 ((ahp->ah_assoc_id & 0x3fff) << AR_BSS_ID1_AID_S));
4599
4600 OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */
4601
4602 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR, INIT_RSSI_THR);
4603
4604 /* HW beacon processing */
4678 | ahp->ah_sta_id1_defaults
4679 );
4680 ar9300_set_operating_mode(ah, opmode);
4681
4682 /* Set Venice BSSID mask according to current state */
4683 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask));
4684 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4));
4685

--- 12 unchanged lines hidden (view full) ---

4698 LE_READ_2(ahp->ah_bssid + 4) |
4699 ((ahp->ah_assoc_id & 0x3fff) << AR_BSS_ID1_AID_S));
4700
4701 OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */
4702
4703 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR, INIT_RSSI_THR);
4704
4705 /* HW beacon processing */
4706 /*
4707 * XXX what happens if I just leave filter_interval=0?
4708 * it stays disabled?
4709 */
4605 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_BCN_WEIGHT,
4606 INIT_RSSI_BEACON_WEIGHT);
4607 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE |
4608 AR_HWBCNPROC1_EXCLUDE_TIM_ELM);
4710 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_BCN_WEIGHT,
4711 INIT_RSSI_BEACON_WEIGHT);
4712 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE |
4713 AR_HWBCNPROC1_EXCLUDE_TIM_ELM);
4609 if (AH_PRIVATE(ah)->ah_config.ath_hal_beacon_filter_interval) {
4714 if (ah->ah_config.ath_hal_beacon_filter_interval) {
4610 OS_REG_RMW_FIELD(ah, AR_HWBCNPROC2, AR_HWBCNPROC2_FILTER_INTERVAL,
4715 OS_REG_RMW_FIELD(ah, AR_HWBCNPROC2, AR_HWBCNPROC2_FILTER_INTERVAL,
4611 AH_PRIVATE(ah)->ah_config.ath_hal_beacon_filter_interval);
4716 ah->ah_config.ath_hal_beacon_filter_interval);
4612 OS_REG_SET_BIT(ah, AR_HWBCNPROC2,
4613 AR_HWBCNPROC2_FILTER_INTERVAL_ENABLE);
4614 }
4615
4616
4617 /*
4618 * Set Channel now modifies bank 6 parameters for FOWL workaround
4619 * to force rf_pwd_icsyndiv bias current as function of synth
4620 * frequency.Thus must be called after ar9300_process_ini() to ensure
4621 * analog register cache is valid.
4622 */
4717 OS_REG_SET_BIT(ah, AR_HWBCNPROC2,
4718 AR_HWBCNPROC2_FILTER_INTERVAL_ENABLE);
4719 }
4720
4721
4722 /*
4723 * Set Channel now modifies bank 6 parameters for FOWL workaround
4724 * to force rf_pwd_icsyndiv bias current as function of synth
4725 * frequency.Thus must be called after ar9300_process_ini() to ensure
4726 * analog register cache is valid.
4727 */
4623 if (!ahp->ah_rf_hal.set_channel(ah, ichan)) {
4728 if (!ahp->ah_rf_hal.set_channel(ah, chan)) {
4624 FAIL(HAL_EIO);
4625 }
4626
4627
4628 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
4629
4630 /* Set 1:1 QCU to DCU mapping for all queues */
4631 for (i = 0; i < AR_NUM_DCU; i++) {
4632 OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
4633 }
4634
4635 ahp->ah_intr_txqs = 0;
4729 FAIL(HAL_EIO);
4730 }
4731
4732
4733 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
4734
4735 /* Set 1:1 QCU to DCU mapping for all queues */
4736 for (i = 0; i < AR_NUM_DCU; i++) {
4737 OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
4738 }
4739
4740 ahp->ah_intr_txqs = 0;
4636 for (i = 0; i < AH_PRIVATE(ah)->ah_caps.hal_total_queues; i++) {
4741 for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++) {
4637 ar9300_reset_tx_queue(ah, i);
4638 }
4639
4640 ar9300_init_interrupt_masks(ah, opmode);
4641
4642 /* Reset ier reference count to disabled */
4742 ar9300_reset_tx_queue(ah, i);
4743 }
4744
4745 ar9300_init_interrupt_masks(ah, opmode);
4746
4747 /* Reset ier reference count to disabled */
4643 OS_ATOMIC_SET(&ahp->ah_ier_ref_count, 1);
4748// OS_ATOMIC_SET(&ahp->ah_ier_ref_count, 1);
4644 if (ath_hal_isrfkillenabled(ah)) {
4645 ar9300_enable_rf_kill(ah);
4646 }
4647
4648 /* must be called AFTER ini is processed */
4649 ar9300_ani_init_defaults(ah, macmode);
4650
4651 ar9300_init_qos(ah);

--- 12 unchanged lines hidden (view full) ---

4664 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
4665
4666 ar9300_set_dma(ah);
4667
4668 /*
4669 * program OBS bus to see MAC interrupts
4670 */
4671#if ATH_SUPPORT_MCI
4749 if (ath_hal_isrfkillenabled(ah)) {
4750 ar9300_enable_rf_kill(ah);
4751 }
4752
4753 /* must be called AFTER ini is processed */
4754 ar9300_ani_init_defaults(ah, macmode);
4755
4756 ar9300_init_qos(ah);

--- 12 unchanged lines hidden (view full) ---

4769 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
4770
4771 ar9300_set_dma(ah);
4772
4773 /*
4774 * program OBS bus to see MAC interrupts
4775 */
4776#if ATH_SUPPORT_MCI
4672 if (!AH_PRIVATE(ah)->ah_caps.hal_mci_support) {
4777 if (!AH_PRIVATE(ah)->ah_caps.halMciSupport) {
4673 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_OBS), 8);
4674 }
4675#else
4676 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_OBS), 8);
4677#endif
4678
4679
4680 /* enabling AR_GTTM_IGNORE_IDLE in GTTM register so that

--- 62 unchanged lines hidden (view full) ---

4743
4744 ar9300_init_bb(ah, chan);
4745
4746 /* BB Step 7: Calibration */
4747 ar9300_invalidate_saved_cals(ah, ichan);
4748 cal_ret = ar9300_init_cal(ah, chan, AH_FALSE, apply_last_iqcorr);
4749
4750#if ATH_SUPPORT_MCI
4778 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_OBS), 8);
4779 }
4780#else
4781 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_OBS), 8);
4782#endif
4783
4784
4785 /* enabling AR_GTTM_IGNORE_IDLE in GTTM register so that

--- 62 unchanged lines hidden (view full) ---

4848
4849 ar9300_init_bb(ah, chan);
4850
4851 /* BB Step 7: Calibration */
4852 ar9300_invalidate_saved_cals(ah, ichan);
4853 cal_ret = ar9300_init_cal(ah, chan, AH_FALSE, apply_last_iqcorr);
4854
4855#if ATH_SUPPORT_MCI
4751 if (AH_PRIVATE(ah)->ah_caps.hal_mci_support && ahp->ah_mci_ready) {
4752 if (IS_CHAN_2GHZ(chan) &&
4856 if (AH_PRIVATE(ah)->ah_caps.halMciSupport && ahp->ah_mci_ready) {
4857 if (IS_CHAN_2GHZ(ichan) &&
4753 (ahp->ah_mci_bt_state == MCI_BT_SLEEP))
4754 {
4755 if (ar9300_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) ||
4756 ar9300_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE))
4757 {
4758 /*
4759 * BT is sleeping. Check if BT wakes up duing WLAN
4760 * calibration. If BT wakes up during WLAN calibration, need

--- 4 unchanged lines hidden (view full) ---

4765 __func__);
4766 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
4767 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET |
4768 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE);
4769 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) send REMOTE_RESET\n");
4770 ar9300_mci_remote_reset(ah, AH_TRUE);
4771 ar9300_mci_send_sys_waking(ah, AH_TRUE);
4772 OS_DELAY(1);
4858 (ahp->ah_mci_bt_state == MCI_BT_SLEEP))
4859 {
4860 if (ar9300_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) ||
4861 ar9300_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE))
4862 {
4863 /*
4864 * BT is sleeping. Check if BT wakes up duing WLAN
4865 * calibration. If BT wakes up during WLAN calibration, need

--- 4 unchanged lines hidden (view full) ---

4870 __func__);
4871 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
4872 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET |
4873 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE);
4874 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) send REMOTE_RESET\n");
4875 ar9300_mci_remote_reset(ah, AH_TRUE);
4876 ar9300_mci_send_sys_waking(ah, AH_TRUE);
4877 OS_DELAY(1);
4773 if (IS_CHAN_2GHZ(chan)) {
4878 if (IS_CHAN_2GHZ(ichan)) {
4774 ar9300_mci_send_lna_transfer(ah, AH_TRUE);
4775 }
4776 ahp->ah_mci_bt_state = MCI_BT_AWAKE;
4777
4778 /* Redo calibration */
4779 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Re-calibrate.\n",
4780 __func__);
4781 ar9300_invalidate_saved_cals(ah, ichan);
4879 ar9300_mci_send_lna_transfer(ah, AH_TRUE);
4880 }
4881 ahp->ah_mci_bt_state = MCI_BT_AWAKE;
4882
4883 /* Redo calibration */
4884 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Re-calibrate.\n",
4885 __func__);
4886 ar9300_invalidate_saved_cals(ah, ichan);
4782 cal_ret = ar9300_init_cal(ah, chan, AH_FALSE, ar9300_init_cal);
4887 cal_ret = ar9300_init_cal(ah, chan, AH_FALSE, apply_last_iqcorr);
4783 }
4784 }
4785 ar9300_mci_enable_interrupt(ah);
4786 }
4787#endif
4788
4789 if (!cal_ret) {
4790 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Init Cal Failed\n", __func__);

--- 10 unchanged lines hidden (view full) ---

4801 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
4802 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
4803 }
4804#endif
4805
4806 /* Restore previous led state */
4807 OS_REG_WRITE(ah, AR_CFG_LED, save_led_state | AR_CFG_SCLK_32KHZ);
4808
4888 }
4889 }
4890 ar9300_mci_enable_interrupt(ah);
4891 }
4892#endif
4893
4894 if (!cal_ret) {
4895 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Init Cal Failed\n", __func__);

--- 10 unchanged lines hidden (view full) ---

4906 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
4907 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
4908 }
4909#endif
4910
4911 /* Restore previous led state */
4912 OS_REG_WRITE(ah, AR_CFG_LED, save_led_state | AR_CFG_SCLK_32KHZ);
4913
4809#ifdef ATH_BT_COEX
4914#if ATH_BT_COEX
4810 if (ahp->ah_bt_coex_config_type != HAL_BT_COEX_CFG_NONE) {
4811 ar9300_init_bt_coex(ah);
4812
4813#if ATH_SUPPORT_MCI
4915 if (ahp->ah_bt_coex_config_type != HAL_BT_COEX_CFG_NONE) {
4916 ar9300_init_bt_coex(ah);
4917
4918#if ATH_SUPPORT_MCI
4814 if (AH_PRIVATE(ah)->ah_caps.hal_mci_support && ahp->ah_mci_ready) {
4919 if (AH_PRIVATE(ah)->ah_caps.halMciSupport && ahp->ah_mci_ready) {
4815 /* Check BT state again to make sure it's not changed. */
4816 ar9300_mci_sync_bt_state(ah);
4817 ar9300_mci_2g5g_switch(ah, AH_TRUE);
4818
4819 if ((ahp->ah_mci_bt_state == MCI_BT_AWAKE) &&
4820 (ahp->ah_mci_query_bt == AH_TRUE))
4821 {
4822 ahp->ah_mci_need_flush_btinfo = AH_TRUE;

--- 56 unchanged lines hidden (view full) ---

4879 REG_WRITE(ATH_GPIO_OUT_FUNCTION3, ( REG_READ(ATH_GPIO_OUT_FUNCTION3) & (~(0xff))) | (0x2F) );
4880 REG_WRITE(ATH_GPIO_OE, (( REG_READ(ATH_GPIO_OE) & (~(0x1 << 12) )) | (0x1 << 13)));
4881 }
4882 }
4883#undef REG_READ
4884#undef REG_WRITE
4885#endif
4886
4920 /* Check BT state again to make sure it's not changed. */
4921 ar9300_mci_sync_bt_state(ah);
4922 ar9300_mci_2g5g_switch(ah, AH_TRUE);
4923
4924 if ((ahp->ah_mci_bt_state == MCI_BT_AWAKE) &&
4925 (ahp->ah_mci_query_bt == AH_TRUE))
4926 {
4927 ahp->ah_mci_need_flush_btinfo = AH_TRUE;

--- 56 unchanged lines hidden (view full) ---

4984 REG_WRITE(ATH_GPIO_OUT_FUNCTION3, ( REG_READ(ATH_GPIO_OUT_FUNCTION3) & (~(0xff))) | (0x2F) );
4985 REG_WRITE(ATH_GPIO_OE, (( REG_READ(ATH_GPIO_OE) & (~(0x1 << 12) )) | (0x1 << 13)));
4986 }
4987 }
4988#undef REG_READ
4989#undef REG_WRITE
4990#endif
4991
4992 /* XXX FreeBSD What's this? -adrian */
4993#if 0
4887 chan->channel_flags = ichan->channel_flags;
4888 chan->priv_flags = ichan->priv_flags;
4994 chan->channel_flags = ichan->channel_flags;
4995 chan->priv_flags = ichan->priv_flags;
4996#endif
4889
4890#if FIX_NOISE_FLOOR
4997
4998#if FIX_NOISE_FLOOR
4891 ar9300_get_nf_hist_base(ah, AH_PRIVATE(ah)->ah_curchan, is_scan, nf_buf);
4999 /* XXX FreeBSD is ichan appropariate? It was curchan.. */
5000 ar9300_get_nf_hist_base(ah, ichan, is_scan, nf_buf);
4892 ar9300_load_nf(ah, nf_buf);
4893 if (nf_hist_buff_reset == 1)
4894 {
4895 nf_hist_buff_reset = 0;
4896 #ifndef ATH_NF_PER_CHAN
4897 if (First_NFCal(ah, ichan, is_scan, chan)){
4898 }
4899 #endif /* ATH_NF_PER_CHAN */

--- 18 unchanged lines hidden (view full) ---

4918 * see 0xb state after first bb panic, make sure that we
4919 * disable the phy_restart.
4920 *
4921 * There may be multiple panics, make sure that we always do
4922 * this if we see this panic at least once. This is required
4923 * because reset seems to be writing from INI file.
4924 */
4925 if ((ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL)
5001 ar9300_load_nf(ah, nf_buf);
5002 if (nf_hist_buff_reset == 1)
5003 {
5004 nf_hist_buff_reset = 0;
5005 #ifndef ATH_NF_PER_CHAN
5006 if (First_NFCal(ah, ichan, is_scan, chan)){
5007 }
5008 #endif /* ATH_NF_PER_CHAN */

--- 18 unchanged lines hidden (view full) ---

5027 * see 0xb state after first bb panic, make sure that we
5028 * disable the phy_restart.
5029 *
5030 * There may be multiple panics, make sure that we always do
5031 * this if we see this panic at least once. This is required
5032 * because reset seems to be writing from INI file.
5033 */
5034 if ((ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL)
4926 == HAL_OK) && (((MS((AH_PRIVATE(ah)->ah_bb_panic_last_status),
5035 == HAL_OK) && (((MS((AH9300(ah)->ah_bb_panic_last_status),
4927 AR_PHY_BB_WD_RX_OFDM_SM)) == 0xb) ||
5036 AR_PHY_BB_WD_RX_OFDM_SM)) == 0xb) ||
4928 AH_PRIVATE(ah)->ah_phyrestart_disabled) )
5037 AH9300(ah)->ah_phyrestart_disabled) )
4929 {
4930 ar9300_disable_phy_restart(ah, 1);
4931 }
4932
4933
4934
4935 ahp->ah_radar1 = MS(OS_REG_READ(ah, AR_PHY_RADAR_1),
4936 AR_PHY_RADAR_1_CF_BIN_THRESH);
4937 ahp->ah_dc_offset = MS(OS_REG_READ(ah, AR_PHY_TIMING2),
4938 AR_PHY_TIMING2_DC_OFFSET);
4939 ahp->ah_disable_cck = MS(OS_REG_READ(ah, AR_PHY_MODE),
4940 AR_PHY_MODE_DISABLE_CCK);
4941
5038 {
5039 ar9300_disable_phy_restart(ah, 1);
5040 }
5041
5042
5043
5044 ahp->ah_radar1 = MS(OS_REG_READ(ah, AR_PHY_RADAR_1),
5045 AR_PHY_RADAR_1_CF_BIN_THRESH);
5046 ahp->ah_dc_offset = MS(OS_REG_READ(ah, AR_PHY_TIMING2),
5047 AR_PHY_TIMING2_DC_OFFSET);
5048 ahp->ah_disable_cck = MS(OS_REG_READ(ah, AR_PHY_MODE),
5049 AR_PHY_MODE_DISABLE_CCK);
5050
4942 if (ap->ah_enable_keysearch_always) {
5051 if (AH9300(ah)->ah_enable_keysearch_always) {
4943 ar9300_enable_keysearch_always(ah, 1);
4944 }
4945
4946#if ATH_LOW_POWER_ENABLE
4947#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val)
4948#define REG_READ(_reg) *((volatile u_int32_t *)(_reg))
4949 if (AR_SREV_OSPREY(ah)) {
4950 REG_WRITE(0xb4000080, REG_READ(0xb4000080) | 3);

--- 6 unchanged lines hidden (view full) ---

4957#undef REG_WRITE
4958#endif /* ATH_LOW_POWER_ENABLE */
4959
4960 WAR_USB_DISABLE_PLL_LOCK_DETECT(ah);
4961
4962 /* H/W Green TX */
4963 ar9300_control_signals_for_green_tx_mode(ah);
4964 /* Smart Antenna, only for 5GHz on Scropion */
5052 ar9300_enable_keysearch_always(ah, 1);
5053 }
5054
5055#if ATH_LOW_POWER_ENABLE
5056#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val)
5057#define REG_READ(_reg) *((volatile u_int32_t *)(_reg))
5058 if (AR_SREV_OSPREY(ah)) {
5059 REG_WRITE(0xb4000080, REG_READ(0xb4000080) | 3);

--- 6 unchanged lines hidden (view full) ---

5066#undef REG_WRITE
5067#endif /* ATH_LOW_POWER_ENABLE */
5068
5069 WAR_USB_DISABLE_PLL_LOCK_DETECT(ah);
5070
5071 /* H/W Green TX */
5072 ar9300_control_signals_for_green_tx_mode(ah);
5073 /* Smart Antenna, only for 5GHz on Scropion */
4965 if (IS_CHAN_2GHZ((AH_PRIVATE(ah)->ah_curchan)) && AR_SREV_SCORPION(ah)) {
5074 if (IEEE80211_IS_CHAN_2GHZ((AH_PRIVATE(ah)->ah_curchan)) && AR_SREV_SCORPION(ah)) {
4966 ahp->ah_smartantenna_enable = 0;
4967 }
4968
4969 ar9300_set_smart_antenna(ah, ahp->ah_smartantenna_enable);
4970
4971
4972 return AH_TRUE;
4973bad:
4974 OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
4975 *status = ecode;
4976
4977 return AH_FALSE;
4978#undef FAIL
4979}
4980
4981void
4982ar9300_green_ap_ps_on_off( struct ath_hal *ah, u_int16_t on_off)
4983{
4984 /* Set/reset the ps flag */
5075 ahp->ah_smartantenna_enable = 0;
5076 }
5077
5078 ar9300_set_smart_antenna(ah, ahp->ah_smartantenna_enable);
5079
5080
5081 return AH_TRUE;
5082bad:
5083 OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
5084 *status = ecode;
5085
5086 return AH_FALSE;
5087#undef FAIL
5088}
5089
5090void
5091ar9300_green_ap_ps_on_off( struct ath_hal *ah, u_int16_t on_off)
5092{
5093 /* Set/reset the ps flag */
4985 AH_PRIVATE(ah)->green_ap_ps_on = !!on_off;
5094 AH9300(ah)->green_ap_ps_on = !!on_off;
4986}
4987
4988/*
4989 * This function returns 1, where it is possible to do
4990 * single-chain power save.
4991 */
4992u_int16_t
4993ar9300_is_single_ant_power_save_possible(struct ath_hal *ah)

--- 201 unchanged lines hidden (view full) ---

5195
5196 /* normalization sin and cos by mag */
5197 sin_2phi_1 = (sin_2phi_1 * res_scale / mag1);
5198 cos_2phi_1 = (cos_2phi_1 * res_scale / mag1);
5199 sin_2phi_2 = (sin_2phi_2 * res_scale / mag2);
5200 cos_2phi_2 = (cos_2phi_2 * res_scale / mag2);
5201
5202 /* calculate IQ mismatch */
5095}
5096
5097/*
5098 * This function returns 1, where it is possible to do
5099 * single-chain power save.
5100 */
5101u_int16_t
5102ar9300_is_single_ant_power_save_possible(struct ath_hal *ah)

--- 201 unchanged lines hidden (view full) ---

5304
5305 /* normalization sin and cos by mag */
5306 sin_2phi_1 = (sin_2phi_1 * res_scale / mag1);
5307 cos_2phi_1 = (cos_2phi_1 * res_scale / mag1);
5308 sin_2phi_2 = (sin_2phi_2 * res_scale / mag2);
5309 cos_2phi_2 = (cos_2phi_2 * res_scale / mag2);
5310
5311 /* calculate IQ mismatch */
5203 if (AH_FALSE== ar9300_solve_iq_cal(ah,
5312 if (AH_FALSE == ar9300_solve_iq_cal(ah,
5204 sin_2phi_1, cos_2phi_1, sin_2phi_2, cos_2phi_2, mag_a0_d0,
5205 phs_a0_d0, mag_a1_d0, phs_a1_d0, solved_eq))
5206 {
5207 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5208 "%s: Call to ar9300_solve_iq_cal failed.\n", __func__);
5209 return AH_FALSE;
5210 }
5211

--- 109 unchanged lines hidden (view full) ---

5321 AR_PHY_TX_IQCAL_CORR_COEFF_67_B2},
5322 { AR_PHY_TX_IQCAL_CORR_COEFF_67_B0,
5323 AR_PHY_TX_IQCAL_CORR_COEFF_67_B1,
5324 AR_PHY_TX_IQCAL_CORR_COEFF_67_B2},
5325 };
5326
5327static void
5328ar9300_tx_iq_cal_outlier_detection(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan, u_int32_t num_chains,
5313 sin_2phi_1, cos_2phi_1, sin_2phi_2, cos_2phi_2, mag_a0_d0,
5314 phs_a0_d0, mag_a1_d0, phs_a1_d0, solved_eq))
5315 {
5316 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5317 "%s: Call to ar9300_solve_iq_cal failed.\n", __func__);
5318 return AH_FALSE;
5319 }
5320

--- 109 unchanged lines hidden (view full) ---

5430 AR_PHY_TX_IQCAL_CORR_COEFF_67_B2},
5431 { AR_PHY_TX_IQCAL_CORR_COEFF_67_B0,
5432 AR_PHY_TX_IQCAL_CORR_COEFF_67_B1,
5433 AR_PHY_TX_IQCAL_CORR_COEFF_67_B2},
5434 };
5435
5436static void
5437ar9300_tx_iq_cal_outlier_detection(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan, u_int32_t num_chains,
5329 struct coeff_t *coeff,HAL_BOOL is_cal_reusable)
5438 struct coeff_t *coeff, HAL_BOOL is_cal_reusable)
5330{
5331 int nmeasurement, ch_idx, im;
5332 int32_t magnitude, phase;
5333 int32_t magnitude_max, phase_max;
5334 int32_t magnitude_min, phase_min;
5335
5336 int32_t magnitude_max_idx, phase_max_idx;
5337 int32_t magnitude_min_idx, phase_min_idx;

--- 260 unchanged lines hidden (view full) ---

5598 OS_REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN, AR_PHY_TXGAIN_FORCE, 0);
5599 }
5600
5601 /* enable tx IQ cal */
5602 OS_REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START(ah),
5603 AR_PHY_TX_IQCAL_START_DO_CAL, AR_PHY_TX_IQCAL_START_DO_CAL);
5604
5605 if (!ath_hal_wait(ah,
5439{
5440 int nmeasurement, ch_idx, im;
5441 int32_t magnitude, phase;
5442 int32_t magnitude_max, phase_max;
5443 int32_t magnitude_min, phase_min;
5444
5445 int32_t magnitude_max_idx, phase_max_idx;
5446 int32_t magnitude_min_idx, phase_min_idx;

--- 260 unchanged lines hidden (view full) ---

5707 OS_REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN, AR_PHY_TXGAIN_FORCE, 0);
5708 }
5709
5710 /* enable tx IQ cal */
5711 OS_REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START(ah),
5712 AR_PHY_TX_IQCAL_START_DO_CAL, AR_PHY_TX_IQCAL_START_DO_CAL);
5713
5714 if (!ath_hal_wait(ah,
5606 AR_PHY_TX_IQCAL_START(ah), AR_PHY_TX_IQCAL_START_DO_CAL, 0,
5607 AH_WAIT_TIMEOUT))
5715 AR_PHY_TX_IQCAL_START(ah), AR_PHY_TX_IQCAL_START_DO_CAL, 0))
5608 {
5609 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5610 "%s: Tx IQ Cal is never completed.\n", __func__);
5611 return AH_FALSE;
5612 }
5613 return AH_TRUE;
5614}
5615

--- 119 unchanged lines hidden (view full) ---

5735 iq_res[idx + 1] = 0xffff &
5736 OS_REG_READ(ah, chan_info_tab[ch_idx] + offset);
5737
5738 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5739 "%s: IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
5740 __func__, idx, iq_res[idx], idx + 1, iq_res[idx + 1]);
5741 }
5742
5716 {
5717 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5718 "%s: Tx IQ Cal is never completed.\n", __func__);
5719 return AH_FALSE;
5720 }
5721 return AH_TRUE;
5722}
5723

--- 119 unchanged lines hidden (view full) ---

5843 iq_res[idx + 1] = 0xffff &
5844 OS_REG_READ(ah, chan_info_tab[ch_idx] + offset);
5845
5846 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5847 "%s: IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
5848 __func__, idx, iq_res[idx], idx + 1, iq_res[idx + 1]);
5849 }
5850
5743 if (AH_FALSE== ar9300_calc_iq_corr(
5851 if (AH_FALSE == ar9300_calc_iq_corr(
5744 ah, ch_idx, iq_res, coeff.iqc_coeff))
5745 {
5746 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5747 "%s: Failed in calculation of IQ correction.\n",
5748 __func__);
5749 goto TX_IQ_CAL_FAILED_;
5750 }
5751

--- 75 unchanged lines hidden (view full) ---

5827 */
5828void ar9300_disable_phy_restart(struct ath_hal *ah, int disable_phy_restart)
5829{
5830 u_int32_t val;
5831
5832 val = OS_REG_READ(ah, AR_PHY_RESTART);
5833 if (disable_phy_restart) {
5834 val &= ~AR_PHY_RESTART_ENA;
5852 ah, ch_idx, iq_res, coeff.iqc_coeff))
5853 {
5854 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5855 "%s: Failed in calculation of IQ correction.\n",
5856 __func__);
5857 goto TX_IQ_CAL_FAILED_;
5858 }
5859

--- 75 unchanged lines hidden (view full) ---

5935 */
5936void ar9300_disable_phy_restart(struct ath_hal *ah, int disable_phy_restart)
5937{
5938 u_int32_t val;
5939
5940 val = OS_REG_READ(ah, AR_PHY_RESTART);
5941 if (disable_phy_restart) {
5942 val &= ~AR_PHY_RESTART_ENA;
5835 AH_PRIVATE(ah)->ah_phyrestart_disabled = 1;
5943 AH9300(ah)->ah_phyrestart_disabled = 1;
5836 } else {
5837 val |= AR_PHY_RESTART_ENA;
5944 } else {
5945 val |= AR_PHY_RESTART_ENA;
5838 AH_PRIVATE(ah)->ah_phyrestart_disabled = 0;
5946 AH9300(ah)->ah_phyrestart_disabled = 0;
5839 }
5840 OS_REG_WRITE(ah, AR_PHY_RESTART, val);
5841
5842 val = OS_REG_READ(ah, AR_PHY_RESTART);
5843}
5844
5845HAL_BOOL
5846ar9300_interference_is_present(struct ath_hal *ah)
5847{
5848 int i;
5849 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
5947 }
5948 OS_REG_WRITE(ah, AR_PHY_RESTART, val);
5949
5950 val = OS_REG_READ(ah, AR_PHY_RESTART);
5951}
5952
5953HAL_BOOL
5954ar9300_interference_is_present(struct ath_hal *ah)
5955{
5956 int i;
5957 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
5958 const struct ieee80211_channel *chan = ahpriv->ah_curchan;
5959 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
5850
5960
5961 if (ichan == NULL) {
5962 ath_hal_printf(ah, "%s: called with ichan=NULL\n", __func__);
5963 return AH_FALSE;
5964 }
5965
5851 /* This function is called after a stuck beacon, if EACS is enabled.
5852 * If CW interference is severe, then HW goes into a loop of continuous
5853 * stuck beacons and resets. On reset the NF cal history is cleared.
5854 * So the median value of the history cannot be used -
5855 * hence check if any value (Chain 0/Primary Channel)
5856 * is outside the bounds.
5857 */
5966 /* This function is called after a stuck beacon, if EACS is enabled.
5967 * If CW interference is severe, then HW goes into a loop of continuous
5968 * stuck beacons and resets. On reset the NF cal history is cleared.
5969 * So the median value of the history cannot be used -
5970 * hence check if any value (Chain 0/Primary Channel)
5971 * is outside the bounds.
5972 */
5858 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah);
5973 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan);
5859 for (i = 0; i < HAL_NF_CAL_HIST_LEN_FULL; i++) {
5860 if (h->nf_cal_buffer[i][0] >
5974 for (i = 0; i < HAL_NF_CAL_HIST_LEN_FULL; i++) {
5975 if (h->nf_cal_buffer[i][0] >
5861 ahpriv->nfp->nominal + ahpriv->nf_cw_int_delta)
5976 AH9300(ah)->nfp->nominal + AH9300(ah)->nf_cw_int_delta)
5862 {
5863 return AH_TRUE;
5864 }
5865
5866 }
5867 return AH_FALSE;
5868}
5869

--- 111 unchanged lines hidden (view full) ---

5981 ar9300_crdc_activate(ah, 0, 1);
5982 }
5983 }
5984}
5985#endif
5986
5987#if ATH_ANT_DIV_COMB
5988HAL_BOOL
5977 {
5978 return AH_TRUE;
5979 }
5980
5981 }
5982 return AH_FALSE;
5983}
5984

--- 111 unchanged lines hidden (view full) ---

6096 ar9300_crdc_activate(ah, 0, 1);
6097 }
6098 }
6099}
6100#endif
6101
6102#if ATH_ANT_DIV_COMB
6103HAL_BOOL
5989ar9300_ant_ctrl_set_lna_div_use_bt_ant(struct ath_hal *ah, HAL_BOOL enable, HAL_CHANNEL *chan)
6104ar9300_ant_ctrl_set_lna_div_use_bt_ant(struct ath_hal *ah, HAL_BOOL enable, const struct ieee80211_channel *chan)
5990{
5991 u_int32_t value;
5992 u_int32_t regval;
5993 struct ath_hal_9300 *ahp = AH9300(ah);
5994 HAL_CHANNEL_INTERNAL *ichan;
5995 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
5996 HAL_CAPABILITIES *pcap = &ahpriv->ah_caps;
5997
5998 if (AR_SREV_POSEIDON(ah)) {
5999 // Make sure this scheme is only used for WB225(Astra)
6000 ahp->ah_lna_div_use_bt_ant_enable = enable;
6001
6002 ichan = ar9300_check_chan(ah, chan);
6003 if ( ichan == AH_NULL ) {
6004 HALDEBUG(ah, HAL_DEBUG_CHANNEL, "%s: invalid channel %u/0x%x; no mapping\n",
6105{
6106 u_int32_t value;
6107 u_int32_t regval;
6108 struct ath_hal_9300 *ahp = AH9300(ah);
6109 HAL_CHANNEL_INTERNAL *ichan;
6110 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
6111 HAL_CAPABILITIES *pcap = &ahpriv->ah_caps;
6112
6113 if (AR_SREV_POSEIDON(ah)) {
6114 // Make sure this scheme is only used for WB225(Astra)
6115 ahp->ah_lna_div_use_bt_ant_enable = enable;
6116
6117 ichan = ar9300_check_chan(ah, chan);
6118 if ( ichan == AH_NULL ) {
6119 HALDEBUG(ah, HAL_DEBUG_CHANNEL, "%s: invalid channel %u/0x%x; no mapping\n",
6005 __func__, chan->channel, chan->channel_flags);
6120 __func__, chan->ic_freq, chan->ic_flags);
6006 return AH_FALSE;
6007 }
6008
6009 if ( enable == TRUE ) {
6121 return AH_FALSE;
6122 }
6123
6124 if ( enable == TRUE ) {
6010 pcap->hal_ant_div_comb_support = TRUE;
6125 pcap->halAntDivCombSupport = TRUE;
6011 } else {
6126 } else {
6012 pcap->hal_ant_div_comb_support = pcap->hal_ant_div_comb_support_org;
6127 pcap->halAntDivCombSupport = pcap->halAntDivCombSupportOrg;
6013 }
6014
6015#define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
6016#define AR_SWITCH_TABLE_COM2_ALL_S (0)
6017 value = ar9300_ant_ctrl_common2_get(ah, IS_CHAN_2GHZ(ichan));
6018 if ( enable == TRUE ) {
6019 value &= ~AR_SWITCH_TABLE_COM2_ALL;
6128 }
6129
6130#define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
6131#define AR_SWITCH_TABLE_COM2_ALL_S (0)
6132 value = ar9300_ant_ctrl_common2_get(ah, IS_CHAN_2GHZ(ichan));
6133 if ( enable == TRUE ) {
6134 value &= ~AR_SWITCH_TABLE_COM2_ALL;
6020 value |= ahpriv->ah_config.ath_hal_ant_ctrl_comm2g_switch_enable;
6135 value |= ah->ah_config.ath_hal_ant_ctrl_comm2g_switch_enable;
6021 }
6022 OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
6023
6024 value = ar9300_eeprom_get(ahp, EEP_ANTDIV_control);
6025 /* main_lnaconf, alt_lnaconf, main_tb, alt_tb */
6026 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
6027 regval &= (~ANT_DIV_CONTROL_ALL); /* clear bit 25~30 */
6028 regval |= (value & 0x3f) << ANT_DIV_CONTROL_ALL_S;

--- 12 unchanged lines hidden (view full) ---

6041 regval |= ((value >> 7) & 0x1) <<
6042 BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__SHIFT;
6043 if ( enable == TRUE ) {
6044 regval |= FAST_DIV_ENABLE;
6045 }
6046 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
6047
6048 if ( AR_SREV_POSEIDON_11_OR_LATER(ah) ) {
6136 }
6137 OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
6138
6139 value = ar9300_eeprom_get(ahp, EEP_ANTDIV_control);
6140 /* main_lnaconf, alt_lnaconf, main_tb, alt_tb */
6141 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
6142 regval &= (~ANT_DIV_CONTROL_ALL); /* clear bit 25~30 */
6143 regval |= (value & 0x3f) << ANT_DIV_CONTROL_ALL_S;

--- 12 unchanged lines hidden (view full) ---

6156 regval |= ((value >> 7) & 0x1) <<
6157 BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__SHIFT;
6158 if ( enable == TRUE ) {
6159 regval |= FAST_DIV_ENABLE;
6160 }
6161 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
6162
6163 if ( AR_SREV_POSEIDON_11_OR_LATER(ah) ) {
6049 if (pcap->hal_ant_div_comb_support) {
6164 if (pcap->halAntDivCombSupport) {
6050 /* If support DivComb, set MAIN to LNA1 and ALT to LNA2 at the first beginning */
6051 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
6052 /* clear bit 25~30 main_lnaconf, alt_lnaconf, main_tb, alt_tb */
6053 regval &= (~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK |
6054 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK |
6055 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK |
6056 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK));
6057 regval |= (HAL_ANT_DIV_COMB_LNA1 <<

--- 5 unchanged lines hidden (view full) ---

6063 }
6064
6065 return AH_TRUE;
6066 } else {
6067 return AH_TRUE;
6068 }
6069}
6070#endif /* ATH_ANT_DIV_COMB */
6165 /* If support DivComb, set MAIN to LNA1 and ALT to LNA2 at the first beginning */
6166 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
6167 /* clear bit 25~30 main_lnaconf, alt_lnaconf, main_tb, alt_tb */
6168 regval &= (~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK |
6169 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK |
6170 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK |
6171 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK));
6172 regval |= (HAL_ANT_DIV_COMB_LNA1 <<

--- 5 unchanged lines hidden (view full) ---

6178 }
6179
6180 return AH_TRUE;
6181 } else {
6182 return AH_TRUE;
6183 }
6184}
6185#endif /* ATH_ANT_DIV_COMB */
6071
6072#endif /* AH_SUPPORT_AR9300 */