1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "opt_ah.h"
18
| 1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "opt_ah.h"
18
|
19#ifdef AH_SUPPORT_AR9300
20
| |
21#include "ah.h"
22#include "ah_desc.h"
23#include "ah_internal.h"
24
25#include "ar9300/ar9300.h"
26#include "ar9300/ar9300reg.h"
27#include "ar9300/ar9300desc.h"
28
29
| 19#include "ah.h"
20#include "ah_desc.h"
21#include "ah_internal.h"
22
23#include "ar9300/ar9300.h"
24#include "ar9300/ar9300reg.h"
25#include "ar9300/ar9300desc.h"
26
27
|
30
| |
31/*
32 * Process an RX descriptor, and return the status to the caller.
33 * Copy some hardware specific items into the software portion
34 * of the descriptor.
35 *
36 * NB: the caller is responsible for validating the memory contents
37 * of the descriptor (e.g. flushing any cached copy).
38 */
39HAL_STATUS
40ar9300_proc_rx_desc_fast(struct ath_hal *ah, struct ath_desc *ds,
41 u_int32_t pa, struct ath_desc *nds, struct ath_rx_status *rxs,
42 void *buf_addr)
43{
44 struct ar9300_rxs *rxsp = AR9300RXS(buf_addr);
45
46 /*
47 ath_hal_printf(ah,"CHH=RX: ds_info 0x%x status1: 0x%x status11: 0x%x\n",
48 rxsp->ds_info,rxsp->status1,rxsp->status11);
49 */
50
51 if ((rxsp->status11 & AR_rx_done) == 0) {
52 return HAL_EINPROGRESS;
53 }
54
55 if (MS(rxsp->ds_info, AR_desc_id) != 0x168c) {
56#if __PKT_SERIOUS_ERRORS__
57 /*BUG: 63564-HT */
58 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "%s: Rx Descriptor error 0x%x\n",
59 __func__, rxsp->ds_info);
60#endif
61 return HAL_EINVAL;
62 }
63
64 if ((rxsp->ds_info & (AR_tx_rx_desc | AR_ctrl_stat)) != 0) {
65#if __PKT_SERIOUS_ERRORS__
66 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
67 "%s: Rx Descriptor wrong info 0x%x\n", __func__, rxsp->ds_info);
68#endif
69 return HAL_EINPROGRESS;
70 }
71
72 rxs->rs_status = 0;
73 rxs->rs_flags = 0;
74
75 rxs->rs_datalen = rxsp->status2 & AR_data_len;
76 rxs->rs_tstamp = rxsp->status3;
77
78 /* XXX what about key_cache_miss? */
79 rxs->rs_rssi = MS(rxsp->status5, AR_rx_rssi_combined);
| 28/*
29 * Process an RX descriptor, and return the status to the caller.
30 * Copy some hardware specific items into the software portion
31 * of the descriptor.
32 *
33 * NB: the caller is responsible for validating the memory contents
34 * of the descriptor (e.g. flushing any cached copy).
35 */
36HAL_STATUS
37ar9300_proc_rx_desc_fast(struct ath_hal *ah, struct ath_desc *ds,
38 u_int32_t pa, struct ath_desc *nds, struct ath_rx_status *rxs,
39 void *buf_addr)
40{
41 struct ar9300_rxs *rxsp = AR9300RXS(buf_addr);
42
43 /*
44 ath_hal_printf(ah,"CHH=RX: ds_info 0x%x status1: 0x%x status11: 0x%x\n",
45 rxsp->ds_info,rxsp->status1,rxsp->status11);
46 */
47
48 if ((rxsp->status11 & AR_rx_done) == 0) {
49 return HAL_EINPROGRESS;
50 }
51
52 if (MS(rxsp->ds_info, AR_desc_id) != 0x168c) {
53#if __PKT_SERIOUS_ERRORS__
54 /*BUG: 63564-HT */
55 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "%s: Rx Descriptor error 0x%x\n",
56 __func__, rxsp->ds_info);
57#endif
58 return HAL_EINVAL;
59 }
60
61 if ((rxsp->ds_info & (AR_tx_rx_desc | AR_ctrl_stat)) != 0) {
62#if __PKT_SERIOUS_ERRORS__
63 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
64 "%s: Rx Descriptor wrong info 0x%x\n", __func__, rxsp->ds_info);
65#endif
66 return HAL_EINPROGRESS;
67 }
68
69 rxs->rs_status = 0;
70 rxs->rs_flags = 0;
71
72 rxs->rs_datalen = rxsp->status2 & AR_data_len;
73 rxs->rs_tstamp = rxsp->status3;
74
75 /* XXX what about key_cache_miss? */
76 rxs->rs_rssi = MS(rxsp->status5, AR_rx_rssi_combined);
|
80 rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_rx_rssi_ant00);
81 rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_rx_rssi_ant01);
82 rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_rx_rssi_ant02);
83 rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_rx_rssi_ant10);
84 rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_rx_rssi_ant11);
85 rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_rx_rssi_ant12);
| 77 rxs->rs_rssi_ctl[0] = MS(rxsp->status1, AR_rx_rssi_ant00);
78 rxs->rs_rssi_ctl[1] = MS(rxsp->status1, AR_rx_rssi_ant01);
79 rxs->rs_rssi_ctl[2] = MS(rxsp->status1, AR_rx_rssi_ant02);
80 rxs->rs_rssi_ext[0] = MS(rxsp->status5, AR_rx_rssi_ant10);
81 rxs->rs_rssi_ext[1] = MS(rxsp->status5, AR_rx_rssi_ant11);
82 rxs->rs_rssi_ext[2] = MS(rxsp->status5, AR_rx_rssi_ant12);
|
86 if (rxsp->status11 & AR_rx_key_idx_valid) {
87 rxs->rs_keyix = MS(rxsp->status11, AR_key_idx);
88 } else {
89 rxs->rs_keyix = HAL_RXKEYIX_INVALID;
90 }
91 /* NB: caller expected to do rate table mapping */
92 rxs->rs_rate = MS(rxsp->status1, AR_rx_rate);
93 rxs->rs_more = (rxsp->status2 & AR_rx_more) ? 1 : 0;
94
95 rxs->rs_isaggr = (rxsp->status11 & AR_rx_aggr) ? 1 : 0;
96 rxs->rs_moreaggr = (rxsp->status11 & AR_rx_more_aggr) ? 1 : 0;
97 rxs->rs_antenna = (MS(rxsp->status4, AR_rx_antenna) & 0x7);
| 83 if (rxsp->status11 & AR_rx_key_idx_valid) {
84 rxs->rs_keyix = MS(rxsp->status11, AR_key_idx);
85 } else {
86 rxs->rs_keyix = HAL_RXKEYIX_INVALID;
87 }
88 /* NB: caller expected to do rate table mapping */
89 rxs->rs_rate = MS(rxsp->status1, AR_rx_rate);
90 rxs->rs_more = (rxsp->status2 & AR_rx_more) ? 1 : 0;
91
92 rxs->rs_isaggr = (rxsp->status11 & AR_rx_aggr) ? 1 : 0;
93 rxs->rs_moreaggr = (rxsp->status11 & AR_rx_more_aggr) ? 1 : 0;
94 rxs->rs_antenna = (MS(rxsp->status4, AR_rx_antenna) & 0x7);
|
98 rxs->rs_isapsd = (rxsp->status11 & AR_apsd_trig) ? 1 : 0;
99 rxs->rs_flags = (rxsp->status4 & AR_gi) ? HAL_RX_GI : 0;
| 95 rxs->rs_flags = (rxsp->status11 & AR_apsd_trig) ? HAL_RX_IS_APSD : 0;
96 rxs->rs_flags |= (rxsp->status4 & AR_gi) ? HAL_RX_GI : 0;
|
100 rxs->rs_flags |= (rxsp->status4 & AR_2040) ? HAL_RX_2040 : 0;
101
102 /* Copy EVM information */
| 97 rxs->rs_flags |= (rxsp->status4 & AR_2040) ? HAL_RX_2040 : 0;
98
99 /* Copy EVM information */
|
103 rxs->evm0 = rxsp->status6;
104 rxs->evm1 = rxsp->status7;
105 rxs->evm2 = rxsp->status8;
106 rxs->evm3 = rxsp->status9;
107 rxs->evm4 = (rxsp->status10 & 0xffff);
| 100 rxs->rs_evm0 = rxsp->status6;
101 rxs->rs_evm1 = rxsp->status7;
102 rxs->rs_evm2 = rxsp->status8;
103 rxs->rs_evm3 = rxsp->status9;
104 rxs->rs_evm4 = (rxsp->status10 & 0xffff);
|
108
109 if (rxsp->status11 & AR_pre_delim_crc_err) {
110 rxs->rs_flags |= HAL_RX_DELIM_CRC_PRE;
111 }
112 if (rxsp->status11 & AR_post_delim_crc_err) {
113 rxs->rs_flags |= HAL_RX_DELIM_CRC_POST;
114 }
115 if (rxsp->status11 & AR_decrypt_busy_err) {
116 rxs->rs_flags |= HAL_RX_DECRYPT_BUSY;
117 }
118 if (rxsp->status11 & AR_hi_rx_chain) {
119 rxs->rs_flags |= HAL_RX_HI_RX_CHAIN;
120 }
121 if (rxsp->status11 & AR_key_miss) {
122 rxs->rs_status |= HAL_RXERR_KEYMISS;
123 }
124
125 if ((rxsp->status11 & AR_rx_frame_ok) == 0) {
126 /*
127 * These four bits should not be set together. The
128 * 9300 spec states a Michael error can only occur if
129 * decrypt_crc_err not set (and TKIP is used). Experience
130 * indicates however that you can also get Michael errors
131 * when a CRC error is detected, but these are specious.
132 * Consequently we filter them out here so we don't
133 * confuse and/or complicate drivers.
134 */
135 if (rxsp->status11 & AR_crc_err) {
136 rxs->rs_status |= HAL_RXERR_CRC;
137 /*
138 * ignore CRC flag for spectral phy reports
139 */
140 if (rxsp->status11 & AR_phyerr) {
141 u_int phyerr = MS(rxsp->status11, AR_phy_err_code);
142 if (phyerr == HAL_PHYERR_SPECTRAL) {
143 rxs->rs_status |= HAL_RXERR_PHY;
144 rxs->rs_phyerr = phyerr;
145 }
146 }
147 } else if (rxsp->status11 & AR_phyerr) {
148 u_int phyerr;
149
150 /*
151 * Packets with OFDM_RESTART on post delimiter are CRC OK and
152 * usable and MAC ACKs them.
153 * To avoid packet from being lost, we remove the PHY Err flag
154 * so that lmac layer does not drop them.
155 * (EV 70071)
156 */
157 phyerr = MS(rxsp->status11, AR_phy_err_code);
158 if ((phyerr == HAL_PHYERR_OFDM_RESTART) &&
159 (rxsp->status11 & AR_post_delim_crc_err)) {
160 rxs->rs_phyerr = 0;
161 } else {
162 rxs->rs_status |= HAL_RXERR_PHY;
163 rxs->rs_phyerr = phyerr;
164 }
165 } else if (rxsp->status11 & AR_decrypt_crc_err) {
166 rxs->rs_status |= HAL_RXERR_DECRYPT;
167 } else if (rxsp->status11 & AR_michael_err) {
168 rxs->rs_status |= HAL_RXERR_MIC;
169 }
170 }
171
172 return HAL_OK;
173}
174
175HAL_STATUS
176ar9300_proc_rx_desc(struct ath_hal *ah, struct ath_desc *ds,
177 u_int32_t pa, struct ath_desc *nds, u_int64_t tsf,
178 struct ath_rx_status *rxs)
179{
180 return HAL_ENOTSUPP;
181}
182
183/*
184 * rx path in ISR is different for ar9300 from ar5416, and
185 * ath_rx_proc_descfast will not be called if edmasupport is true.
186 * So this function ath_hal_get_rxkeyidx will not be
187 * called for ar9300.
188 * This function in ar9300's HAL is just a stub one because we need
189 * to link something to the callback interface of the HAL module.
190 */
191HAL_STATUS
192ar9300_get_rx_key_idx(struct ath_hal *ah, struct ath_desc *ds, u_int8_t *keyix,
193 u_int8_t *status)
194{
195 *status = 0;
196 *keyix = HAL_RXKEYIX_INVALID;
197 return HAL_ENOTSUPP;
198}
| 105
106 if (rxsp->status11 & AR_pre_delim_crc_err) {
107 rxs->rs_flags |= HAL_RX_DELIM_CRC_PRE;
108 }
109 if (rxsp->status11 & AR_post_delim_crc_err) {
110 rxs->rs_flags |= HAL_RX_DELIM_CRC_POST;
111 }
112 if (rxsp->status11 & AR_decrypt_busy_err) {
113 rxs->rs_flags |= HAL_RX_DECRYPT_BUSY;
114 }
115 if (rxsp->status11 & AR_hi_rx_chain) {
116 rxs->rs_flags |= HAL_RX_HI_RX_CHAIN;
117 }
118 if (rxsp->status11 & AR_key_miss) {
119 rxs->rs_status |= HAL_RXERR_KEYMISS;
120 }
121
122 if ((rxsp->status11 & AR_rx_frame_ok) == 0) {
123 /*
124 * These four bits should not be set together. The
125 * 9300 spec states a Michael error can only occur if
126 * decrypt_crc_err not set (and TKIP is used). Experience
127 * indicates however that you can also get Michael errors
128 * when a CRC error is detected, but these are specious.
129 * Consequently we filter them out here so we don't
130 * confuse and/or complicate drivers.
131 */
132 if (rxsp->status11 & AR_crc_err) {
133 rxs->rs_status |= HAL_RXERR_CRC;
134 /*
135 * ignore CRC flag for spectral phy reports
136 */
137 if (rxsp->status11 & AR_phyerr) {
138 u_int phyerr = MS(rxsp->status11, AR_phy_err_code);
139 if (phyerr == HAL_PHYERR_SPECTRAL) {
140 rxs->rs_status |= HAL_RXERR_PHY;
141 rxs->rs_phyerr = phyerr;
142 }
143 }
144 } else if (rxsp->status11 & AR_phyerr) {
145 u_int phyerr;
146
147 /*
148 * Packets with OFDM_RESTART on post delimiter are CRC OK and
149 * usable and MAC ACKs them.
150 * To avoid packet from being lost, we remove the PHY Err flag
151 * so that lmac layer does not drop them.
152 * (EV 70071)
153 */
154 phyerr = MS(rxsp->status11, AR_phy_err_code);
155 if ((phyerr == HAL_PHYERR_OFDM_RESTART) &&
156 (rxsp->status11 & AR_post_delim_crc_err)) {
157 rxs->rs_phyerr = 0;
158 } else {
159 rxs->rs_status |= HAL_RXERR_PHY;
160 rxs->rs_phyerr = phyerr;
161 }
162 } else if (rxsp->status11 & AR_decrypt_crc_err) {
163 rxs->rs_status |= HAL_RXERR_DECRYPT;
164 } else if (rxsp->status11 & AR_michael_err) {
165 rxs->rs_status |= HAL_RXERR_MIC;
166 }
167 }
168
169 return HAL_OK;
170}
171
172HAL_STATUS
173ar9300_proc_rx_desc(struct ath_hal *ah, struct ath_desc *ds,
174 u_int32_t pa, struct ath_desc *nds, u_int64_t tsf,
175 struct ath_rx_status *rxs)
176{
177 return HAL_ENOTSUPP;
178}
179
180/*
181 * rx path in ISR is different for ar9300 from ar5416, and
182 * ath_rx_proc_descfast will not be called if edmasupport is true.
183 * So this function ath_hal_get_rxkeyidx will not be
184 * called for ar9300.
185 * This function in ar9300's HAL is just a stub one because we need
186 * to link something to the callback interface of the HAL module.
187 */
188HAL_STATUS
189ar9300_get_rx_key_idx(struct ath_hal *ah, struct ath_desc *ds, u_int8_t *keyix,
190 u_int8_t *status)
191{
192 *status = 0;
193 *keyix = HAL_RXKEYIX_INVALID;
194 return HAL_ENOTSUPP;
195}
|
199
200
201#endif
| |
| |