1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "opt_ah.h" 18 |
19#include "ah.h" 20#include "ah_internal.h" 21 22#include "ar9300/ar9300.h" 23#include "ar9300/ar9300reg.h" 24 25#if ATH_WOW_OFFLOAD 26void ar9300_wowoffload_prep(struct ath_hal *ah) --- 569 unchanged lines hidden (view full) --- 596ar9300_set_power_mode_network_sleep(struct ath_hal *ah, int set_chip) 597{ 598 struct ath_hal_9300 *ahp = AH9300(ah); 599 600 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 601 if (set_chip) { 602 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 603 |
604 if (! p_cap->halAutoSleepSupport) { |
605 /* Set wake_on_interrupt bit; clear force_wake bit */ 606 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT); 607 } 608 else { 609 /* 610 * When chip goes into network sleep, it could be waken up by 611 * MCI_INT interrupt caused by BT's HW messages (LNA_xxx, CONT_xxx) 612 * which chould be in a very fast rate (~100us). This will cause --- 35 unchanged lines hidden (view full) --- 648/* 649 * Set power mgt to the requested mode, and conditionally set 650 * the chip as well 651 */ 652HAL_BOOL 653ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode, int set_chip) 654{ 655 struct ath_hal_9300 *ahp = AH9300(ah); |
656#if defined(AH_DEBUG) || defined(AH_PRINT_FILTER) |
657 static const char* modes[] = { 658 "AWAKE", 659 "FULL-SLEEP", 660 "NETWORK SLEEP", 661 "UNDEFINED" 662 }; 663#endif 664 int status = AH_TRUE; 665 666 HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__, 667 modes[ar9300_get_power_mode(ah)], modes[mode], 668 set_chip ? "set chip " : ""); 669 670 switch (mode) { 671 case HAL_PM_AWAKE: 672 status = ar9300_set_power_mode_awake(ah, set_chip); 673#if ATH_SUPPORT_MCI |
674 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) { |
675 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 676 } 677#endif 678 break; 679 case HAL_PM_FULL_SLEEP: 680#if ATH_SUPPORT_MCI |
681 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) { |
682 if (ar9300_get_power_mode(ah) == HAL_PM_AWAKE) { 683 if ((ar9300_mci_state(ah, HAL_MCI_STATE_ENABLE, NULL) != 0) && 684 (ahp->ah_mci_bt_state != MCI_BT_SLEEP) && 685 !ahp->ah_mci_halted_bt_gpm) 686 { 687 HALDEBUG(ah, HAL_DEBUG_BT_COEX, 688 "(MCI) %s: HALT BT GPM (full_sleep)\n", __func__); 689 ar9300_mci_send_coex_halt_bt_gpm(ah, AH_TRUE, AH_TRUE); 690 } 691 } 692 ahp->ah_mci_ready = AH_FALSE; 693 } 694#endif 695#if ATH_SUPPORT_MCI |
696 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) { |
697 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 698 } 699#endif 700 ar9300_set_power_mode_sleep(ah, set_chip); 701 ahp->ah_chip_full_sleep = AH_TRUE; 702 break; 703 case HAL_PM_NETWORK_SLEEP: 704#if ATH_SUPPORT_MCI |
705 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) { |
706 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 707 } 708#endif 709 ar9300_set_power_mode_network_sleep(ah, set_chip); 710 break; 711 default: 712 HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, 713 "%s: unknown power mode %u\n", __func__, mode); --- 271 unchanged lines hidden (view full) --- 985#if 0 986 OS_REG_WRITE(ah, AR_RXDP, 0x0); 987#endif 988 989 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 990 "%s: TODO How to disable RXDP!!\n", __func__); 991 992#if ATH_SUPPORT_MCI |
993 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) { |
994 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 995 } 996#endif 997 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT); 998 999 return AH_TRUE; 1000 } 1001} --- 42 unchanged lines hidden (view full) --- 1044 if (AH_PRIVATE(ah)->ah_is_pci_express == AH_TRUE) { 1045 1046 u_int32_t wa_reg_val; 1047 /* 1048 * We need to untie the internal POR (power-on-reset) to the external 1049 * PCI-E reset. We also need to tie the PCI-E Phy reset to the PCI-E 1050 * reset. 1051 */ |
1052 HAL_DEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, |
1053 "%s: Untie POR and PCIE reset\n", __func__); 1054 wa_reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_WA)); 1055 wa_reg_val = wa_reg_val & ~(AR_WA_UNTIE_RESET_EN); 1056 wa_reg_val = wa_reg_val | AR_WA_RESET_EN | AR_WA_POR_SHORT; 1057 /* 1058 * This bit is to bypass the EEPROM/OTP state machine, (by clearing its 1059 * busy state while PCIE_rst is asserted), to allow BT embedded CPU 1060 * be able to access WLAN registers. Otherwise the eCPU access will be --- 293 unchanged lines hidden (view full) --- 1354 OS_REG_WRITE(ah, AR_BSS_ID1, 0); 1355 } 1356 } 1357 1358 /* Enable Seq# generation when asleep. */ 1359 OS_REG_WRITE(ah, AR_STA_ID1, 1360 OS_REG_READ(ah, AR_STA_ID1) & ~AR_STA_ID1_PRESERVE_SEQNUM); 1361 |
1362 AH_PRIVATE(ah)->ah_wow_event_mask = wow_event_mask; 1363 1364#if ATH_WOW_OFFLOAD 1365 if (offloadEnable) { 1366 /* Force MAC awake before entering SW WoW mode */ 1367 OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 1368#if ATH_SUPPORT_MCI |
1369 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) { |
1370 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 1371 } 1372#endif 1373 1374 OS_REG_WRITE(ah, AR_WOW_OFFLOAD_COMMAND_JUPITER, wow_feature_enable); 1375 OS_REG_WRITE(ah, AR_WOW_OFFLOAD_STATUS_JUPITER, 0x0); 1376 if (wow_feature_enable & AR_WOW_OFFLOAD_ENA_SW_NULL) { 1377 OS_REG_WRITE(ah, AR_WOW_SW_NULL_PARAMETER, --- 10 unchanged lines hidden (view full) --- 1388 AH9300(ah)->ah_chip_full_sleep = AH_FALSE; 1389 1390 //OS_REG_SET_BIT(ah, AR_SW_WOW_CONTROL, AR_HW_WOW_DISABLE); 1391 } 1392 else 1393#endif /* ATH_WOW_OFFLOAD */ 1394 { 1395#if ATH_SUPPORT_MCI |
1396 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) { |
1397 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 1398 } 1399#endif 1400 ar9300_set_power_mode_wow_sleep(ah); 1401 AH9300(ah)->ah_chip_full_sleep = AH_TRUE; 1402 } 1403 1404 return (AH_TRUE); --- 142 unchanged lines hidden (view full) --- 1547 1548 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT)); 1549 val |= (1 << (2 * 2)); 1550 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT), val); 1551 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT)); 1552 /* val = OS_REG_READ(ah,AR_GPIO_IN_OUT ); */ 1553} 1554#endif /* ATH_WOW */ |