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ar9300_misc.c (250007) ar9300_misc.c (250008)
1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "opt_ah.h"
18
1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "opt_ah.h"
18
19#ifdef AH_SUPPORT_AR9300
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24#ifdef AH_DEBUG
25#include "ah_desc.h" /* NB: for HAL_PHYERR* */
26#endif
27
28#include "ar9300/ar9300.h"

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54 == HAL_OK)
55 {
56 *hangs |= HAL_PHYRESTART_CLR_WAR;
57 }
58
59 ahp->ah_hang_wars = *hangs;
60}
61
19#include "ah.h"
20#include "ah_internal.h"
21#include "ah_devid.h"
22#ifdef AH_DEBUG
23#include "ah_desc.h" /* NB: for HAL_PHYERR* */
24#endif
25
26#include "ar9300/ar9300.h"

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52 == HAL_OK)
53 {
54 *hangs |= HAL_PHYRESTART_CLR_WAR;
55 }
56
57 ahp->ah_hang_wars = *hangs;
58}
59
60/*
61 * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about
62 * HT20, HT40, fast-clock, turbo mode, etc.
63 */
62static u_int
63ar9300_mac_to_usec(struct ath_hal *ah, u_int clks)
64{
64static u_int
65ar9300_mac_to_usec(struct ath_hal *ah, u_int clks)
66{
65 HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
67#if 0
68 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
66
69
67 if (chan && IS_CHAN_HT40(chan)) {
70 if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
68 return (ath_hal_mac_usec(ah, clks) / 2);
69 } else {
70 return (ath_hal_mac_usec(ah, clks));
71 }
71 return (ath_hal_mac_usec(ah, clks) / 2);
72 } else {
73 return (ath_hal_mac_usec(ah, clks));
74 }
75#endif
76 return (ath_hal_mac_usec(ah, clks));
72}
73
74u_int
75ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs)
76{
77}
78
79u_int
80ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs)
81{
77 HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
82#if 0
83 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
78
84
79 if (chan && IS_CHAN_HT40(chan)) {
85 if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
80 return (ath_hal_mac_clks(ah, usecs) * 2);
81 } else {
82 return (ath_hal_mac_clks(ah, usecs));
83 }
86 return (ath_hal_mac_clks(ah, usecs) * 2);
87 } else {
88 return (ath_hal_mac_clks(ah, usecs));
89 }
90#endif
91 return (ath_hal_mac_clks(ah, usecs));
84}
85
86void
87ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac)
88{
89 struct ath_hal_9300 *ahp = AH9300(ah);
90
91 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);

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127 * A_HARDWARE for an unwritable EEPROM or bad EEPROM version
128 */
129HAL_BOOL
130ar9300_set_regulatory_domain(struct ath_hal *ah,
131 u_int16_t reg_domain, HAL_STATUS *status)
132{
133 HAL_STATUS ecode;
134
92}
93
94void
95ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac)
96{
97 struct ath_hal_9300 *ahp = AH9300(ah);
98
99 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);

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135 * A_HARDWARE for an unwritable EEPROM or bad EEPROM version
136 */
137HAL_BOOL
138ar9300_set_regulatory_domain(struct ath_hal *ah,
139 u_int16_t reg_domain, HAL_STATUS *status)
140{
141 HAL_STATUS ecode;
142
135 if (AH_PRIVATE(ah)->ah_current_rd == 0) {
136 AH_PRIVATE(ah)->ah_current_rd = reg_domain;
143 if (AH_PRIVATE(ah)->ah_currentRD == 0) {
144 AH_PRIVATE(ah)->ah_currentRD = reg_domain;
137 return AH_TRUE;
138 }
139 ecode = HAL_EIO;
140
145 return AH_TRUE;
146 }
147 ecode = HAL_EIO;
148
141#if tbd
149#if 0
142bad:
143#endif
144 if (status) {
145 *status = ecode;
146 }
147 return AH_FALSE;
148}
149
150/*
151 * Return the wireless modes (a,b,g,t) supported by hardware.
152 *
153 * This value is what is actually supported by the hardware
154 * and is unaffected by regulatory/country code settings.
155 *
156 */
157u_int
158ar9300_get_wireless_modes(struct ath_hal *ah)
159{
150bad:
151#endif
152 if (status) {
153 *status = ecode;
154 }
155 return AH_FALSE;
156}
157
158/*
159 * Return the wireless modes (a,b,g,t) supported by hardware.
160 *
161 * This value is what is actually supported by the hardware
162 * and is unaffected by regulatory/country code settings.
163 *
164 */
165u_int
166ar9300_get_wireless_modes(struct ath_hal *ah)
167{
160 return AH_PRIVATE(ah)->ah_caps.hal_wireless_modes;
168 return AH_PRIVATE(ah)->ah_caps.halWirelessModes;
161}
162
163/*
164 * Set the interrupt and GPIO values so the ISR can disable RF
165 * on a switch signal. Assumes GPIO port and interrupt polarity
166 * are set prior to call.
167 */
168void

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196 AR_GPIO_INPUT_MUX2_RFSILENT);
197 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2),
198 (ahp->ah_gpio_select & 0x0f) << 4);
199
200 /*
201 * Configure the desired GPIO port for input and
202 * enable baseband rf silence
203 */
169}
170
171/*
172 * Set the interrupt and GPIO values so the ISR can disable RF
173 * on a switch signal. Assumes GPIO port and interrupt polarity
174 * are set prior to call.
175 */
176void

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204 AR_GPIO_INPUT_MUX2_RFSILENT);
205 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2),
206 (ahp->ah_gpio_select & 0x0f) << 4);
207
208 /*
209 * Configure the desired GPIO port for input and
210 * enable baseband rf silence
211 */
204 ath_hal_gpio_cfg_input(ah, ahp->ah_gpio_select);
212 ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select);
205 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
206 }
207
208 /*
209 * If radio disable switch connection to GPIO bit x is enabled
210 * program GPIO interrupt.
211 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
212 * verified that it is a later version of eeprom, it has a place for

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352/*
353 * Set or clear hardware basic rate bit
354 * Set hardware basic rate set if basic rate is found
355 * and basic rate is equal or less than 2Mbps
356 */
357void
358ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs)
359{
213 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
214 }
215
216 /*
217 * If radio disable switch connection to GPIO bit x is enabled
218 * program GPIO interrupt.
219 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
220 * verified that it is a later version of eeprom, it has a place for

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360/*
361 * Set or clear hardware basic rate bit
362 * Set hardware basic rate set if basic rate is found
363 * and basic rate is equal or less than 2Mbps
364 */
365void
366ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs)
367{
360 HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
368 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
361 u_int32_t reg;
362 u_int8_t xset;
363 int i;
364
369 u_int32_t reg;
370 u_int8_t xset;
371 int i;
372
365 if (chan == AH_NULL || !IS_CHAN_CCK(chan)) {
373 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) {
366 return;
367 }
368 xset = 0;
369 for (i = 0; i < rs->rs_count; i++) {
370 u_int8_t rset = rs->rs_rates[i];
371 /* Basic rate defined? */
372 if ((rset & 0x80) && (rset &= 0x7f) >= xset) {
373 xset = rset;

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510void
511ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna)
512{
513 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
514}
515
516HAL_BOOL
517ar9300_set_antenna_switch(struct ath_hal *ah,
374 return;
375 }
376 xset = 0;
377 for (i = 0; i < rs->rs_count; i++) {
378 u_int8_t rset = rs->rs_rates[i];
379 /* Basic rate defined? */
380 if ((rset & 0x80) && (rset &= 0x7f) >= xset) {
381 xset = rset;

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518void
519ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna)
520{
521 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
522}
523
524HAL_BOOL
525ar9300_set_antenna_switch(struct ath_hal *ah,
518 HAL_ANT_SETTING settings, HAL_CHANNEL *chan, u_int8_t *tx_chainmask,
519 u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd)
526 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan,
527 u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd)
520{
521 struct ath_hal_9300 *ahp = AH9300(ah);
522
523 /*
524 * Owl does not support diversity or changing antennas.
525 *
526 * Instead this API and function are defined differently for AR9300.
527 * To support Tablet PC's, this interface allows the system

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598 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
599 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */
600}
601
602HAL_STATUS
603ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration,
604 u_int32_t next_start, HAL_QUIET_FLAG flag)
605{
528{
529 struct ath_hal_9300 *ahp = AH9300(ah);
530
531 /*
532 * Owl does not support diversity or changing antennas.
533 *
534 * Instead this API and function are defined differently for AR9300.
535 * To support Tablet PC's, this interface allows the system

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606 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
607 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */
608}
609
610HAL_STATUS
611ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration,
612 u_int32_t next_start, HAL_QUIET_FLAG flag)
613{
614#define TU_TO_USEC(_tu) ((_tu) << 10)
606 HAL_STATUS status = HAL_EIO;
607 u_int32_t tsf = 0, j, next_start_us = 0;
608 if (flag & HAL_QUIET_ENABLE) {
609 for (j = 0; j < 2; j++) {
610 next_start_us = TU_TO_USEC(next_start);
611 tsf = OS_REG_READ(ah, AR_TSF_L32);
612 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) {
613 next_start_us += tsf;
614 }
615 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) {
616 next_start_us +=
615 HAL_STATUS status = HAL_EIO;
616 u_int32_t tsf = 0, j, next_start_us = 0;
617 if (flag & HAL_QUIET_ENABLE) {
618 for (j = 0; j < 2; j++) {
619 next_start_us = TU_TO_USEC(next_start);
620 tsf = OS_REG_READ(ah, AR_TSF_L32);
621 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) {
622 next_start_us += tsf;
623 }
624 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) {
625 next_start_us +=
617 AH_PRIVATE(ah)->ah_config.ath_hal_sw_beacon_response_time;
626 ah->ah_config.ah_sw_beacon_response_time;
618 }
619 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
620 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR));
621 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period));
622 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us);
623 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
624 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) {
625 status = HAL_OK;

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631 HALASSERT(j < 1);
632 }
633 } else {
634 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
635 status = HAL_OK;
636 }
637
638 return status;
627 }
628 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
629 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR));
630 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period));
631 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us);
632 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
633 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) {
634 status = HAL_OK;

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640 HALASSERT(j < 1);
641 }
642 } else {
643 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
644 status = HAL_OK;
645 }
646
647 return status;
648#undef TU_TO_USEC
639}
640#ifdef ATH_SUPPORT_DFS
641void
642ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable)
643{
644 u32 reg1, reg2;
645
646 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE));

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693 return HAL_OK;
694 case 1:
695 return (ahp->ah_sta_id1_defaults &
696 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO;
697 default:
698 return HAL_ENOTSUPP;
699 }
700 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
649}
650#ifdef ATH_SUPPORT_DFS
651void
652ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable)
653{
654 u32 reg1, reg2;
655
656 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE));

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703 return HAL_OK;
704 case 1:
705 return (ahp->ah_sta_id1_defaults &
706 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO;
707 default:
708 return HAL_ENOTSUPP;
709 }
710 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
701 /* XXX check rev when new parts are available */
702 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
703 HAL_ENXIO : HAL_OK;
711 switch (capability) {
712 case 0: /* hardware capability */
713 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK;
714 case 1: /* current setting */
715 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
716 HAL_ENXIO : HAL_OK;
717 default:
718 return HAL_ENOTSUPP;
719 }
704 case HAL_CAP_WME_TKIPMIC:
705 /* hardware can do TKIP MIC when WMM is turned on */
706 return HAL_OK;
707 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */
708 return HAL_OK;
709 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */
710 switch (capability) {
711 case 0: /* hardware capability */

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716 HAL_OK : HAL_ENXIO;
717 }
718 return HAL_EINVAL;
719 case HAL_CAP_TPC:
720 switch (capability) {
721 case 0: /* hardware capability */
722 return HAL_OK;
723 case 1:
720 case HAL_CAP_WME_TKIPMIC:
721 /* hardware can do TKIP MIC when WMM is turned on */
722 return HAL_OK;
723 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */
724 return HAL_OK;
725 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */
726 switch (capability) {
727 case 0: /* hardware capability */

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732 HAL_OK : HAL_ENXIO;
733 }
734 return HAL_EINVAL;
735 case HAL_CAP_TPC:
736 switch (capability) {
737 case 0: /* hardware capability */
738 return HAL_OK;
739 case 1:
724 return AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc ?
740 return ah->ah_config.ath_hal_desc_tpc ?
725 HAL_OK : HAL_ENXIO;
726 }
727 return HAL_OK;
728 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */
729 return HAL_OK;
730 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
731 switch (capability) {
732 case 0: /* hardware capability */

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743 return (ahp->ah_sta_id1_defaults &
744 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO;
745 }
746 }
747 return HAL_EINVAL;
748 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
749 switch (capability) {
750 case 0: /* hardware capability */
741 HAL_OK : HAL_ENXIO;
742 }
743 return HAL_OK;
744 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */
745 return HAL_OK;
746 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
747 switch (capability) {
748 case 0: /* hardware capability */

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759 return (ahp->ah_sta_id1_defaults &
760 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO;
761 }
762 }
763 return HAL_EINVAL;
764 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
765 switch (capability) {
766 case 0: /* hardware capability */
751 return p_cap->hal_tsf_add_support ? HAL_OK : HAL_ENOTSUPP;
767 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
752 case 1:
753 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ?
754 HAL_OK : HAL_ENXIO;
755 }
756 return HAL_EINVAL;
757 case HAL_CAP_RFSILENT: /* rfsilent support */
758 if (capability == 3) { /* rfkill interrupt */
759 /*

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777 return HAL_ENOTSUPP;
778 case HAL_CAP_MAC_HANG:
779 /* Track chips that are known to have MAC hangs.
780 */
781 return HAL_OK;
782 case HAL_CAP_RIFS_RX_ENABLED:
783 /* Is RIFS RX currently enabled */
784 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
768 case 1:
769 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ?
770 HAL_OK : HAL_ENXIO;
771 }
772 return HAL_EINVAL;
773 case HAL_CAP_RFSILENT: /* rfsilent support */
774 if (capability == 3) { /* rfkill interrupt */
775 /*

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793 return HAL_ENOTSUPP;
794 case HAL_CAP_MAC_HANG:
795 /* Track chips that are known to have MAC hangs.
796 */
797 return HAL_OK;
798 case HAL_CAP_RIFS_RX_ENABLED:
799 /* Is RIFS RX currently enabled */
800 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
801#if 0
785 case HAL_CAP_ANT_CFG_2GHZ:
802 case HAL_CAP_ANT_CFG_2GHZ:
786 *result = p_cap->hal_num_ant_cfg_2ghz;
803 *result = p_cap->halNumAntCfg2Ghz;
787 return HAL_OK;
788 case HAL_CAP_ANT_CFG_5GHZ:
804 return HAL_OK;
805 case HAL_CAP_ANT_CFG_5GHZ:
789 *result = p_cap->hal_num_ant_cfg_5ghz;
806 *result = p_cap->halNumAntCfg5Ghz;
790 return HAL_OK;
791 case HAL_CAP_RX_STBC:
792 *result = p_cap->hal_rx_stbc_support;
793 return HAL_OK;
794 case HAL_CAP_TX_STBC:
795 *result = p_cap->hal_tx_stbc_support;
796 return HAL_OK;
807 return HAL_OK;
808 case HAL_CAP_RX_STBC:
809 *result = p_cap->hal_rx_stbc_support;
810 return HAL_OK;
811 case HAL_CAP_TX_STBC:
812 *result = p_cap->hal_tx_stbc_support;
813 return HAL_OK;
814#endif
797 case HAL_CAP_LDPC:
815 case HAL_CAP_LDPC:
798 *result = p_cap->hal_ldpc_support;
816 *result = p_cap->halLDPCSupport;
799 return HAL_OK;
800 case HAL_CAP_DYNAMIC_SMPS:
801 return HAL_OK;
802 case HAL_CAP_DS:
803 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
817 return HAL_OK;
818 case HAL_CAP_DYNAMIC_SMPS:
819 return HAL_OK;
820 case HAL_CAP_DS:
821 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
804 (p_cap->hal_tx_chain_mask & 0x3) != 0x3 ||
805 (p_cap->hal_rx_chain_mask & 0x3) != 0x3) ?
822 (p_cap->halTxChainMask & 0x3) != 0x3 ||
823 (p_cap->halRxChainMask & 0x3) != 0x3) ?
806 HAL_ENOTSUPP : HAL_OK;
807 case HAL_CAP_TS:
808 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
824 HAL_ENOTSUPP : HAL_OK;
825 case HAL_CAP_TS:
826 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
809 (p_cap->hal_tx_chain_mask & 0x7) != 0x7 ||
810 (p_cap->hal_rx_chain_mask & 0x7) != 0x7) ?
827 (p_cap->halTxChainMask & 0x7) != 0x7 ||
828 (p_cap->halRxChainMask & 0x7) != 0x7) ?
811 HAL_ENOTSUPP : HAL_OK;
812 case HAL_CAP_OL_PWRCTRL:
813 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ?
814 HAL_OK : HAL_ENOTSUPP;
815 case HAL_CAP_CRDC:
816#if ATH_SUPPORT_CRDC
817 return (AR_SREV_WASP(ah) &&
829 HAL_ENOTSUPP : HAL_OK;
830 case HAL_CAP_OL_PWRCTRL:
831 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ?
832 HAL_OK : HAL_ENOTSUPP;
833 case HAL_CAP_CRDC:
834#if ATH_SUPPORT_CRDC
835 return (AR_SREV_WASP(ah) &&
818 AH_PRIVATE(ah)->ah_config.ath_hal_crdc_enable) ?
836 ah->ah_config.ath_hal_crdc_enable) ?
819 HAL_OK : HAL_ENOTSUPP;
820#else
821 return HAL_ENOTSUPP;
822#endif
837 HAL_OK : HAL_ENOTSUPP;
838#else
839 return HAL_ENOTSUPP;
840#endif
841#if 0
823 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS:
824 *result = (u_int32_t)(-1);
825 return HAL_OK;
826 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS:
827 *result = (u_int32_t)(-1);
828 return HAL_OK;
842 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS:
843 *result = (u_int32_t)(-1);
844 return HAL_OK;
845 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS:
846 *result = (u_int32_t)(-1);
847 return HAL_OK;
848#endif
829 case HAL_CAP_BB_PANIC_WATCHDOG:
830 return HAL_OK;
831 case HAL_CAP_PHYRESTART_CLR_WAR:
832 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) &&
833 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10))
834 {
835 return HAL_OK;
836 }

--- 4 unchanged lines hidden (view full) ---

841 case HAL_CAP_ENTERPRISE_MODE:
842 *result = ahp->ah_enterprise_mode >> 16;
843 /*
844 * WAR for EV 77658 - Add delimiters to first sub-frame when using
845 * RTS/CTS with aggregation and non-enterprise Osprey.
846 *
847 * Bug fixed in AR9580/Peacock, Wasp1.1 and later
848 */
849 case HAL_CAP_BB_PANIC_WATCHDOG:
850 return HAL_OK;
851 case HAL_CAP_PHYRESTART_CLR_WAR:
852 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) &&
853 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10))
854 {
855 return HAL_OK;
856 }

--- 4 unchanged lines hidden (view full) ---

861 case HAL_CAP_ENTERPRISE_MODE:
862 *result = ahp->ah_enterprise_mode >> 16;
863 /*
864 * WAR for EV 77658 - Add delimiters to first sub-frame when using
865 * RTS/CTS with aggregation and non-enterprise Osprey.
866 *
867 * Bug fixed in AR9580/Peacock, Wasp1.1 and later
868 */
849 if ((ahp->ah_enterprise_mode && AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) &&
869 if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) &&
850 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) ||
851 AR_SREV_WASP_10(ah))) {
852 *result |= AH_ENT_RTSCTS_DELIM_WAR;
853 }
854 return HAL_OK;
855 case HAL_CAP_LDPCWAR:
856 /* WAR for RIFS+LDPC issue is required for all chips currently
857 * supported by ar9300 HAL.
858 */
859 return HAL_OK;
860 case HAL_CAP_ENABLE_APM:
870 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) ||
871 AR_SREV_WASP_10(ah))) {
872 *result |= AH_ENT_RTSCTS_DELIM_WAR;
873 }
874 return HAL_OK;
875 case HAL_CAP_LDPCWAR:
876 /* WAR for RIFS+LDPC issue is required for all chips currently
877 * supported by ar9300 HAL.
878 */
879 return HAL_OK;
880 case HAL_CAP_ENABLE_APM:
861 *result = p_cap->hal_enable_apm;
881 *result = p_cap->halApmEnable;
862 return HAL_OK;
863 case HAL_CAP_PCIE_LCR_EXTSYNC_EN:
864 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
865 case HAL_CAP_PCIE_LCR_OFFSET:
866 *result = p_cap->hal_pcie_lcr_offset;
867 return HAL_OK;
868 case HAL_CAP_SMARTANTENNA:
869 /* FIXME A request is pending with h/w team to add feature bit in

--- 30 unchanged lines hidden (view full) ---

900ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
901 u_int32_t capability, u_int32_t setting, HAL_STATUS *status)
902{
903 struct ath_hal_9300 *ahp = AH9300(ah);
904 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
905 u_int32_t v;
906
907 switch (type) {
882 return HAL_OK;
883 case HAL_CAP_PCIE_LCR_EXTSYNC_EN:
884 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
885 case HAL_CAP_PCIE_LCR_OFFSET:
886 *result = p_cap->hal_pcie_lcr_offset;
887 return HAL_OK;
888 case HAL_CAP_SMARTANTENNA:
889 /* FIXME A request is pending with h/w team to add feature bit in

--- 30 unchanged lines hidden (view full) ---

920ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
921 u_int32_t capability, u_int32_t setting, HAL_STATUS *status)
922{
923 struct ath_hal_9300 *ahp = AH9300(ah);
924 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
925 u_int32_t v;
926
927 switch (type) {
928 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
929 if (! p_cap->halTkipMicTxRxKeySupport)
930 return AH_FALSE;
931
932 if (setting)
933 ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA;
934 else
935 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
936
937 OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode);
938 return AH_TRUE;
939
908 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
909 if (setting) {
910 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE;
911 } else {
912 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE;
913 }
914 return AH_TRUE;
915 case HAL_CAP_DIVERSITY:

--- 14 unchanged lines hidden (view full) ---

930#ifdef AH_DEBUG
931 AH_PRIVATE(ah)->ah_diagreg = setting;
932#else
933 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */
934#endif
935 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
936 return AH_TRUE;
937 case HAL_CAP_TPC:
940 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
941 if (setting) {
942 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE;
943 } else {
944 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE;
945 }
946 return AH_TRUE;
947 case HAL_CAP_DIVERSITY:

--- 14 unchanged lines hidden (view full) ---

962#ifdef AH_DEBUG
963 AH_PRIVATE(ah)->ah_diagreg = setting;
964#else
965 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */
966#endif
967 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
968 return AH_TRUE;
969 case HAL_CAP_TPC:
938 AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc = (setting != 0);
970 ah->ah_config.ath_hal_desc_tpc = (setting != 0);
939 return AH_TRUE;
940 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
941 if (setting) {
942 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
943 } else {
944 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
945 }
946 return AH_TRUE;
947 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
971 return AH_TRUE;
972 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
973 if (setting) {
974 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
975 } else {
976 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
977 }
978 return AH_TRUE;
979 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
948 if (p_cap->hal_tsf_add_support) {
980 if (p_cap->halTsfAddSupport) {
949 if (setting) {
950 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF;
951 } else {
952 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF;
953 }
954 return AH_TRUE;
955 }
956 return AH_FALSE;

--- 196 unchanged lines hidden (view full) ---

1153 ar9300_ani_control(
1154 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]);
1155 return AH_TRUE;
1156 case HAL_DIAG_TXCONT:
1157 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/
1158 return AH_TRUE;
1159#endif /* AH_PRIVATE_DIAG */
1160 case HAL_DIAG_CHANNELS:
981 if (setting) {
982 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF;
983 } else {
984 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF;
985 }
986 return AH_TRUE;
987 }
988 return AH_FALSE;

--- 196 unchanged lines hidden (view full) ---

1185 ar9300_ani_control(
1186 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]);
1187 return AH_TRUE;
1188 case HAL_DIAG_TXCONT:
1189 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/
1190 return AH_TRUE;
1191#endif /* AH_PRIVATE_DIAG */
1192 case HAL_DIAG_CHANNELS:
1193#if 0
1161 *result = &(ahp->ah_priv.ah_channels[0]);
1162 *resultsize =
1163 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan;
1194 *result = &(ahp->ah_priv.ah_channels[0]);
1195 *resultsize =
1196 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan;
1197#endif
1164 return AH_TRUE;
1165#ifdef AH_DEBUG
1166 case HAL_DIAG_PRINT_REG:
1167 ar9300_print_reg(ah, *((const u_int32_t *)args));
1168 return AH_TRUE;
1169#endif
1170 default:
1171 break;

--- 8 unchanged lines hidden (view full) ---

1180#ifdef AH_DEBUG
1181#define NUM_DMA_DEBUG_REGS 8
1182#define NUM_QUEUES 10
1183
1184 u_int32_t val[NUM_DMA_DEBUG_REGS];
1185 int qcu_offset = 0, dcu_offset = 0;
1186 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg;
1187 int i, j, k;
1198 return AH_TRUE;
1199#ifdef AH_DEBUG
1200 case HAL_DIAG_PRINT_REG:
1201 ar9300_print_reg(ah, *((const u_int32_t *)args));
1202 return AH_TRUE;
1203#endif
1204 default:
1205 break;

--- 8 unchanged lines hidden (view full) ---

1214#ifdef AH_DEBUG
1215#define NUM_DMA_DEBUG_REGS 8
1216#define NUM_QUEUES 10
1217
1218 u_int32_t val[NUM_DMA_DEBUG_REGS];
1219 int qcu_offset = 0, dcu_offset = 0;
1220 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg;
1221 int i, j, k;
1188 int16_t nfarray[NUM_NF_READINGS];
1189 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah);
1222 int16_t nfarray[HAL_NUM_NF_READINGS];
1223#ifdef ATH_NF_PER_CHAN
1224 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
1225#endif /* ATH_NF_PER_CHAN */
1226 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan);
1190
1191 /* selecting DMA OBS 8 */
1192 OS_REG_WRITE(ah, AR_MACMISC,
1193 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1194 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1195
1196 ath_hal_printf(ah, "Raw DMA Debug values:\n");
1197 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) {

--- 65 unchanged lines hidden (view full) ---

1263 ath_hal_printf(ah, "5G:\n");
1264 ath_hal_printf(ah, "Min CCA Out:\n");
1265 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n");
1266 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n",
1267 nfarray[0], nfarray[1], nfarray[2]);
1268 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
1269 nfarray[3], nfarray[4], nfarray[5]);
1270
1227
1228 /* selecting DMA OBS 8 */
1229 OS_REG_WRITE(ah, AR_MACMISC,
1230 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1231 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1232
1233 ath_hal_printf(ah, "Raw DMA Debug values:\n");
1234 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) {

--- 65 unchanged lines hidden (view full) ---

1300 ath_hal_printf(ah, "5G:\n");
1301 ath_hal_printf(ah, "Min CCA Out:\n");
1302 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n");
1303 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n",
1304 nfarray[0], nfarray[1], nfarray[2]);
1305 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
1306 nfarray[3], nfarray[4], nfarray[5]);
1307
1271 for (i = 0; i < NUM_NF_READINGS; i++) {
1308 for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
1272 ath_hal_printf(ah, "%s Chain %d NF History:\n",
1273 ((i < 3) ? "Control " : "Extension "), i%3);
1274 for (j = 0, k = h->base.curr_index;
1275 j < HAL_NF_CAL_HIST_LEN_FULL;
1276 j++, k++) {
1277 ath_hal_printf(ah, "Element %d: %d\n",
1278 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]);
1279 }

--- 205 unchanged lines hidden (view full) ---

1485 return good;
1486}
1487
1488/*
1489 * Return approximation of extension channel busy over an time interval
1490 * 0% (clear) -> 100% (busy)
1491 * -1 for invalid estimate
1492 */
1309 ath_hal_printf(ah, "%s Chain %d NF History:\n",
1310 ((i < 3) ? "Control " : "Extension "), i%3);
1311 for (j = 0, k = h->base.curr_index;
1312 j < HAL_NF_CAL_HIST_LEN_FULL;
1313 j++, k++) {
1314 ath_hal_printf(ah, "Element %d: %d\n",
1315 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]);
1316 }

--- 205 unchanged lines hidden (view full) ---

1522 return good;
1523}
1524
1525/*
1526 * Return approximation of extension channel busy over an time interval
1527 * 0% (clear) -> 100% (busy)
1528 * -1 for invalid estimate
1529 */
1493int8_t
1530uint32_t
1494ar9300_get_11n_ext_busy(struct ath_hal *ah)
1495{
1496 /*
1497 * Overflow condition to check before multiplying to get %
1498 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28)
1499 */
1500#define OVERFLOW_LIMIT 0x28F5C28
1501#define ERROR_CODE -1

--- 70 unchanged lines hidden (view full) ---

1572/* BB Panic Watchdog declarations */
1573#define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */
1574#define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */
1575
1576void
1577ar9300_config_bb_panic_watchdog(struct ath_hal *ah)
1578{
1579#define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000
1531ar9300_get_11n_ext_busy(struct ath_hal *ah)
1532{
1533 /*
1534 * Overflow condition to check before multiplying to get %
1535 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28)
1536 */
1537#define OVERFLOW_LIMIT 0x28F5C28
1538#define ERROR_CODE -1

--- 70 unchanged lines hidden (view full) ---

1609/* BB Panic Watchdog declarations */
1610#define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */
1611#define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */
1612
1613void
1614ar9300_config_bb_panic_watchdog(struct ath_hal *ah)
1615{
1616#define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000
1580 HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
1581 u_int32_t idle_tmo_ms = AH_PRIVATE(ah)->ah_bb_panic_timeout_ms;
1617 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
1618 u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms;
1582 u_int32_t val, idle_count;
1583
1584 if (idle_tmo_ms != 0) {
1585 /* enable IRQ, disable chip-reset for BB panic */
1586 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1587 AR_PHY_BB_PANIC_CNTL2_MASK;
1588 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2,
1589 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE);
1590 /* bound limit to 10 secs */
1591 if (idle_tmo_ms > 10000) {
1592 idle_tmo_ms = 10000;
1593 }
1619 u_int32_t val, idle_count;
1620
1621 if (idle_tmo_ms != 0) {
1622 /* enable IRQ, disable chip-reset for BB panic */
1623 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1624 AR_PHY_BB_PANIC_CNTL2_MASK;
1625 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2,
1626 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE);
1627 /* bound limit to 10 secs */
1628 if (idle_tmo_ms > 10000) {
1629 idle_tmo_ms = 10000;
1630 }
1594 if (chan != AH_NULL && IS_CHAN_HT40(chan)) {
1631 if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) {
1595 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR;
1596 } else {
1597 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR;
1598 }
1599 /*
1600 * enable panic in non-IDLE mode,
1601 * disable in IDLE mode,
1602 * set idle time-out

--- 12 unchanged lines hidden (view full) ---

1615 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1616 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE));
1617 /* disable panic in non-IDLE mode, disable in IDLE mode */
1618 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1,
1619 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) &
1620 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE));
1621 }
1622
1632 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR;
1633 } else {
1634 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR;
1635 }
1636 /*
1637 * enable panic in non-IDLE mode,
1638 * disable in IDLE mode,
1639 * set idle time-out

--- 12 unchanged lines hidden (view full) ---

1652 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1653 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE));
1654 /* disable panic in non-IDLE mode, disable in IDLE mode */
1655 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1,
1656 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) &
1657 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE));
1658 }
1659
1623 HALDEBUG(ah, HAL_DEBUG_RF_PARAM, "%s: %s BB Panic Watchdog tmo=%ums\n",
1660 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n",
1624 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms);
1625#undef HAL_BB_PANIC_IDLE_TIME_OUT
1626}
1627
1628
1629void
1630ar9300_handle_bb_panic(struct ath_hal *ah)
1631{
1632 u_int32_t status;
1633 /*
1634 * we want to avoid printing in ISR context so we save
1635 * panic watchdog status to be printed later in DPC context
1636 */
1661 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms);
1662#undef HAL_BB_PANIC_IDLE_TIME_OUT
1663}
1664
1665
1666void
1667ar9300_handle_bb_panic(struct ath_hal *ah)
1668{
1669 u_int32_t status;
1670 /*
1671 * we want to avoid printing in ISR context so we save
1672 * panic watchdog status to be printed later in DPC context
1673 */
1637 AH_PRIVATE(ah)->ah_bb_panic_last_status = status =
1674 AH9300(ah)->ah_bb_panic_last_status = status =
1638 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS);
1639 /*
1640 * panic watchdog timer should reset on status read
1641 * but to make sure we write 0 to the watchdog status bit
1642 */
1643 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR);
1644}
1645
1646int
1647ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic)
1648{
1675 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS);
1676 /*
1677 * panic watchdog timer should reset on status read
1678 * but to make sure we write 0 to the watchdog status bit
1679 */
1680 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR);
1681}
1682
1683int
1684ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic)
1685{
1649 bb_panic->status = AH_PRIVATE(ah)->ah_bb_panic_last_status;
1686 bb_panic->status = AH9300(ah)->ah_bb_panic_last_status;
1650
1651 /*
1652 * For signature 04000539 do not print anything.
1653 * This is a very common occurence as a compromise between
1654 * BB Panic and AH_FALSE detects (EV71009). It indicates
1655 * radar hang, which can be cleared by reprogramming
1656 * radar related register and does not requre a chip reset
1657 */

--- 21 unchanged lines hidden (view full) ---

1679 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2);
1680 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL);
1681 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0;
1682 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah,
1683 &bb_panic->rxc_pcnt,
1684 &bb_panic->rxf_pcnt,
1685 &bb_panic->txf_pcnt);
1686
1687
1688 /*
1689 * For signature 04000539 do not print anything.
1690 * This is a very common occurence as a compromise between
1691 * BB Panic and AH_FALSE detects (EV71009). It indicates
1692 * radar hang, which can be cleared by reprogramming
1693 * radar related register and does not requre a chip reset
1694 */

--- 21 unchanged lines hidden (view full) ---

1716 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2);
1717 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL);
1718 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0;
1719 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah,
1720 &bb_panic->rxc_pcnt,
1721 &bb_panic->rxf_pcnt,
1722 &bb_panic->txf_pcnt);
1723
1687 if (AH_PRIVATE(ah)->ah_config.ath_hal_show_bb_panic) {
1724 if (ah->ah_config.ath_hal_show_bb_panic) {
1688 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, "
1689 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf);
1690 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
1691 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1692 bb_panic->wd, bb_panic->det, bb_panic->rdar,
1693 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm,
1694 bb_panic->t_cck, bb_panic->agc, bb_panic->src);
1695 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",

--- 10 unchanged lines hidden (view full) ---

1706
1707 return 0; //The returned data will be stored for athstats to retrieve it
1708}
1709
1710/* set the reason for HAL reset */
1711void
1712ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason)
1713{
1725 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, "
1726 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf);
1727 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
1728 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1729 bb_panic->wd, bb_panic->det, bb_panic->rdar,
1730 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm,
1731 bb_panic->t_cck, bb_panic->agc, bb_panic->src);
1732 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",

--- 10 unchanged lines hidden (view full) ---

1743
1744 return 0; //The returned data will be stored for athstats to retrieve it
1745}
1746
1747/* set the reason for HAL reset */
1748void
1749ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason)
1750{
1714 AH_PRIVATE(ah)->ah_reset_reason = resetreason;
1751 AH9300(ah)->ah_reset_reason = resetreason;
1715}
1716
1717/*
1718 * Configure 20/40 operation
1719 *
1720 * 20/40 = joint rx clear (control and extension)
1721 * 20 = rx clear (control)
1722 *
1723 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz
1724 * when changing from 20/40 => 20 only
1725 */
1726void
1727ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode)
1728{
1729 u_int32_t macmode;
1730
1731 /* Configure MAC for 20/40 operation */
1732 if (mode == HAL_HT_MACMODE_2040 &&
1752}
1753
1754/*
1755 * Configure 20/40 operation
1756 *
1757 * 20/40 = joint rx clear (control and extension)
1758 * 20 = rx clear (control)
1759 *
1760 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz
1761 * when changing from 20/40 => 20 only
1762 */
1763void
1764ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode)
1765{
1766 u_int32_t macmode;
1767
1768 /* Configure MAC for 20/40 operation */
1769 if (mode == HAL_HT_MACMODE_2040 &&
1733 !AH_PRIVATE(ah)->ah_config.ath_hal_cwm_ignore_ext_cca) {
1770 !ah->ah_config.ath_hal_cwm_ignore_ext_cca) {
1734 macmode = AR_2040_JOINED_RX_CLEAR;
1735 } else {
1736 macmode = 0;
1737 }
1738 OS_REG_WRITE(ah, AR_2040_MODE, macmode);
1739}
1740
1741/*

--- 102 unchanged lines hidden (view full) ---

1844 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT)
1845 {
1846 /* get the positive value */
1847 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK;
1848 signed_val = AH_TRUE;
1849 }
1850 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT)
1851 {
1771 macmode = AR_2040_JOINED_RX_CLEAR;
1772 } else {
1773 macmode = 0;
1774 }
1775 OS_REG_WRITE(ah, AR_2040_MODE, macmode);
1776}
1777
1778/*

--- 102 unchanged lines hidden (view full) ---

1881 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT)
1882 {
1883 /* get the positive value */
1884 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK;
1885 signed_val = AH_TRUE;
1886 }
1887 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT)
1888 {
1852 HALDEBUG(ah, HAL_DEBUG_REG_IO,
1889 HALDEBUG(ah, HAL_DEBUG_REGIO,
1853 "%s Correcting ppm out of range %x\n",
1854 __func__, (data_fine & 0x7ff));
1855 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT;
1856 }
1857 /*
1858 * Restore signed value if changed above.
1859 * Use typecast to avoid compilation errors
1860 */

--- 62 unchanged lines hidden (view full) ---

1923 return
1924 OS_REG_READ(ah, AR_PHY_TIMING2) &
1925 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL);
1926}
1927
1928/*
1929 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame
1930 */
1890 "%s Correcting ppm out of range %x\n",
1891 __func__, (data_fine & 0x7ff));
1892 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT;
1893 }
1894 /*
1895 * Restore signed value if changed above.
1896 * Use typecast to avoid compilation errors
1897 */

--- 62 unchanged lines hidden (view full) ---

1960 return
1961 OS_REG_READ(ah, AR_PHY_TIMING2) &
1962 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL);
1963}
1964
1965/*
1966 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame
1967 */
1931void
1932ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_COUNTERS* p_cnts)
1968HAL_BOOL
1969ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs)
1933{
1970{
1971 /*
1972 * XXX FreeBSD todo: reimplement this
1973 */
1974#if 0
1934 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
1935 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
1936 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
1937 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT);
1938 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) ==
1939 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE;
1940 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) ==
1941 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE;
1975 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
1976 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
1977 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
1978 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT);
1979 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) ==
1980 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE;
1981 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) ==
1982 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE;
1983#endif
1984 return AH_FALSE;
1942}
1943
1944void
1945ar9300_clear_mib_counters(struct ath_hal *ah)
1946{
1947 u_int32_t reg_val;
1948
1949 reg_val = OS_REG_READ(ah, AR_MIBC);
1950 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC);
1951 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC);
1952}
1953
1954
1955/* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */
1956HAL_BOOL
1957ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable)
1958{
1959 struct ath_hal_9300 *ahp = AH9300(ah);
1985}
1986
1987void
1988ar9300_clear_mib_counters(struct ath_hal *ah)
1989{
1990 u_int32_t reg_val;
1991
1992 reg_val = OS_REG_READ(ah, AR_MIBC);
1993 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC);
1994 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC);
1995}
1996
1997
1998/* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */
1999HAL_BOOL
2000ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable)
2001{
2002 struct ath_hal_9300 *ahp = AH9300(ah);
1960 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(AH_PRIVATE(ah)->ah_curchan);
1961 u_int32_t tmp = 0;
2003 HAL_CHANNEL_INTERNAL *ichan =
2004 ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
2005 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan);
2006 u_int32_t tmp = 0;
1962
1963 if (enable) {
1964 if (ahp->ah_rifs_enabled == AH_TRUE) {
1965 return AH_TRUE;
1966 }
1967
1968 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]);
1969 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,

--- 7 unchanged lines hidden (view full) ---

1977 AR_PHY_SEARCH_START_DELAY);
1978 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH);
1979 }
1980 /* Change rifs init delay to 0 */
1981 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
1982 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY)));
1983 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY);
1984 if (is_chan_2g) {
2007
2008 if (enable) {
2009 if (ahp->ah_rifs_enabled == AH_TRUE) {
2010 return AH_TRUE;
2011 }
2012
2013 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]);
2014 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,

--- 7 unchanged lines hidden (view full) ---

2022 AR_PHY_SEARCH_START_DELAY);
2023 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH);
2024 }
2025 /* Change rifs init delay to 0 */
2026 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
2027 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY)));
2028 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY);
2029 if (is_chan_2g) {
1985 if (IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2030 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
1986 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500);
1987 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */
1988 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250);
1989 }
1990 } else {
2031 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500);
2032 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */
2033 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250);
2034 }
2035 } else {
1991 if (IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2036 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
1992 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370);
1993 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */
1994 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8);
1995 }
1996 }
1997
1998 ahp->ah_rifs_enabled = AH_FALSE;
1999 }

--- 170 unchanged lines hidden (view full) ---

2170} /* end - ar9300_detect_bb_hang () */
2171
2172#undef NUM_STATUS_READS
2173
2174HAL_STATUS
2175ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg)
2176{
2177 struct ath_hal_9300 *ahp = AH9300(ah);
2037 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370);
2038 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */
2039 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8);
2040 }
2041 }
2042
2043 ahp->ah_rifs_enabled = AH_FALSE;
2044 }

--- 170 unchanged lines hidden (view full) ---

2215} /* end - ar9300_detect_bb_hang () */
2216
2217#undef NUM_STATUS_READS
2218
2219HAL_STATUS
2220ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg)
2221{
2222 struct ath_hal_9300 *ahp = AH9300(ah);
2178 HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
2223 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2224 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2179 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
2180 u_int16_t ant_config;
2181 u_int32_t hal_num_ant_config;
2182
2225 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
2226 u_int16_t ant_config;
2227 u_int32_t hal_num_ant_config;
2228
2183 hal_num_ant_config = IS_CHAN_2GHZ(chan) ?
2184 p_cap->hal_num_ant_cfg_2ghz : p_cap->hal_num_ant_cfg_5ghz;
2229 hal_num_ant_config = IS_CHAN_2GHZ(ichan) ?
2230 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz;
2185
2186 if (cfg < hal_num_ant_config) {
2187 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) {
2188 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
2189 return HAL_OK;
2190 }
2191 }
2192
2193 return HAL_EINVAL;
2194}
2195
2196/*
2197 * Functions to get/set DCS mode
2198 */
2199void
2200ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode)
2201{
2231
2232 if (cfg < hal_num_ant_config) {
2233 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) {
2234 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
2235 return HAL_OK;
2236 }
2237 }
2238
2239 return HAL_EINVAL;
2240}
2241
2242/*
2243 * Functions to get/set DCS mode
2244 */
2245void
2246ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode)
2247{
2202 AH_PRIVATE(ah)->ah_dcs_enable = mode;
2248 AH9300(ah)->ah_dcs_enable = mode;
2203}
2204
2205u_int32_t
2206ar9300_get_dcs_mode(struct ath_hal *ah)
2207{
2249}
2250
2251u_int32_t
2252ar9300_get_dcs_mode(struct ath_hal *ah)
2253{
2208 return AH_PRIVATE(ah)->ah_dcs_enable;
2254 return AH9300(ah)->ah_dcs_enable;
2209}
2210
2255}
2256
2211#ifdef ATH_BT_COEX
2257#if ATH_BT_COEX
2212void
2213ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo)
2214{
2215 struct ath_hal_9300 *ahp = AH9300(ah);
2216
2217 ahp->ah_bt_module = btinfo->bt_module;
2218 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config;
2219 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active;

--- 94 unchanged lines hidden (view full) ---

2314 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH);
2315}
2316
2317static void
2318ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value)
2319{
2320 struct ath_hal_9300 *ahp = AH9300(ah);
2321#if ATH_ANT_DIV_COMB
2258void
2259ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo)
2260{
2261 struct ath_hal_9300 *ahp = AH9300(ah);
2262
2263 ahp->ah_bt_module = btinfo->bt_module;
2264 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config;
2265 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active;

--- 94 unchanged lines hidden (view full) ---

2360 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH);
2361}
2362
2363static void
2364ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value)
2365{
2366 struct ath_hal_9300 *ahp = AH9300(ah);
2367#if ATH_ANT_DIV_COMB
2322 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2323 HAL_CHANNEL *chan = (HAL_CHANNEL *) ahpriv->ah_curchan;
2368 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2369 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2324#endif
2325
2326 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW)
2327 {
2328 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE)
2329 {
2330 /* Config antenna diversity */
2331#if ATH_ANT_DIV_COMB

--- 13 unchanged lines hidden (view full) ---

2345
2346 switch (type) {
2347 case HAL_BT_COEX_SET_ACK_PWR:
2348 if (value) {
2349 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2350 } else {
2351 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2352 }
2370#endif
2371
2372 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW)
2373 {
2374 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE)
2375 {
2376 /* Config antenna diversity */
2377#if ATH_ANT_DIV_COMB

--- 13 unchanged lines hidden (view full) ---

2391
2392 switch (type) {
2393 case HAL_BT_COEX_SET_ACK_PWR:
2394 if (value) {
2395 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2396 } else {
2397 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2398 }
2353 ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit,
2354 ahpriv->ah_extra_txpow, 0);
2399 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2400 ahpriv->ah_extraTxPow, 0);
2355 break;
2356
2357 case HAL_BT_COEX_ANTENNA_DIVERSITY:
2358 if (AR_SREV_POSEIDON(ah)) {
2359 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW;
2360 if (value) {
2361 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE;
2362 }

--- 5 unchanged lines hidden (view full) ---

2368 break;
2369 case HAL_BT_COEX_LOWER_TX_PWR:
2370 if (value) {
2371 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2372 }
2373 else {
2374 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2375 }
2401 break;
2402
2403 case HAL_BT_COEX_ANTENNA_DIVERSITY:
2404 if (AR_SREV_POSEIDON(ah)) {
2405 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW;
2406 if (value) {
2407 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE;
2408 }

--- 5 unchanged lines hidden (view full) ---

2414 break;
2415 case HAL_BT_COEX_LOWER_TX_PWR:
2416 if (value) {
2417 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2418 }
2419 else {
2420 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2421 }
2376 ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit,
2377 ahpriv->ah_extra_txpow, 0);
2422 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2423 ahpriv->ah_extraTxPow, 0);
2378 break;
2379#if ATH_SUPPORT_MCI
2380 case HAL_BT_COEX_MCI_MAX_TX_PWR:
2424 break;
2425#if ATH_SUPPORT_MCI
2426 case HAL_BT_COEX_MCI_MAX_TX_PWR:
2381 if ((ahpriv->ah_config.ath_hal_mci_config &
2427 if ((ah->ah_config.ath_hal_mci_config &
2382 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN)
2383 {
2384 if (value) {
2385 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2386 ahp->ah_mci_concur_tx_en = AH_TRUE;
2387 }
2388 else {
2389 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2390 ahp->ah_mci_concur_tx_en = AH_FALSE;
2391 }
2428 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN)
2429 {
2430 if (value) {
2431 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2432 ahp->ah_mci_concur_tx_en = AH_TRUE;
2433 }
2434 else {
2435 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2436 ahp->ah_mci_concur_tx_en = AH_FALSE;
2437 }
2392 ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit,
2393 ahpriv->ah_extra_txpow, 0);
2438 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2439 ahpriv->ah_extraTxPow, 0);
2394 }
2395 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n",
2396 ahp->ah_mci_concur_tx_en);
2397 break;
2398 case HAL_BT_COEX_MCI_FTP_STOMP_RX:
2399 if (value) {
2400 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX;
2401 }

--- 8 unchanged lines hidden (view full) ---

2410}
2411
2412void
2413ar9300_bt_coex_disable(struct ath_hal *ah)
2414{
2415 struct ath_hal_9300 *ahp = AH9300(ah);
2416
2417 /* Always drive rx_clear_external output as 0 */
2440 }
2441 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n",
2442 ahp->ah_mci_concur_tx_en);
2443 break;
2444 case HAL_BT_COEX_MCI_FTP_STOMP_RX:
2445 if (value) {
2446 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX;
2447 }

--- 8 unchanged lines hidden (view full) ---

2456}
2457
2458void
2459ar9300_bt_coex_disable(struct ath_hal *ah)
2460{
2461 struct ath_hal_9300 *ahp = AH9300(ah);
2462
2463 /* Always drive rx_clear_external output as 0 */
2418 ath_hal_gpio_cfg_output(ah, ahp->ah_wlan_active_gpio_select,
2464 ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select,
2419 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
2420
2421 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2422 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
2423 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2424 }
2425
2426 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);

--- 33 unchanged lines hidden (view full) ---

2460 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2461 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1);
2462 } else {
2463 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2464 }
2465
2466 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
2467 /* For 3-wire, configure the desired GPIO port for rx_clear */
2465 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
2466
2467 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2468 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
2469 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2470 }
2471
2472 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);

--- 33 unchanged lines hidden (view full) ---

2506 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2507 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1);
2508 } else {
2509 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2510 }
2511
2512 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
2513 /* For 3-wire, configure the desired GPIO port for rx_clear */
2468 ath_hal_gpio_cfg_output(ah,
2514 ath_hal_gpioCfgOutput(ah,
2469 ahp->ah_wlan_active_gpio_select,
2470 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE);
2471 }
2472 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
2473 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
2474 {
2475 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */
2515 ahp->ah_wlan_active_gpio_select,
2516 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE);
2517 }
2518 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
2519 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
2520 {
2521 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */
2476 ath_hal_gpio_cfg_output(ah,
2522 ath_hal_gpioCfgOutput(ah,
2477 ahp->ah_wlan_active_gpio_select,
2478 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME);
2479 }
2480
2481 /*
2482 * Enable a weak pull down on BT_ACTIVE.
2483 * When BT device is disabled, BT_ACTIVE might be floating.
2484 */

--- 35 unchanged lines hidden (view full) ---

2520 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2521 ahp->ah_bt_active_gpio_select);
2522 OS_REG_RMW_FIELD(ah,
2523 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2524 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
2525 ahp->ah_bt_priority_gpio_select);
2526
2527 /* Configure the desired GPIO ports for input */
2523 ahp->ah_wlan_active_gpio_select,
2524 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME);
2525 }
2526
2527 /*
2528 * Enable a weak pull down on BT_ACTIVE.
2529 * When BT device is disabled, BT_ACTIVE might be floating.
2530 */

--- 35 unchanged lines hidden (view full) ---

2566 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2567 ahp->ah_bt_active_gpio_select);
2568 OS_REG_RMW_FIELD(ah,
2569 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2570 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
2571 ahp->ah_bt_priority_gpio_select);
2572
2573 /* Configure the desired GPIO ports for input */
2528 ath_hal_gpio_cfg_input(ah, ahp->ah_bt_active_gpio_select);
2529 ath_hal_gpio_cfg_input(ah, ahp->ah_bt_priority_gpio_select);
2574 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2575 ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select);
2530
2531 if (ahp->ah_bt_coex_enabled) {
2532 ar9300_bt_coex_enable(ah);
2533 } else {
2534 ar9300_bt_coex_disable(ah);
2535 }
2536 }
2537 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&

--- 15 unchanged lines hidden (view full) ---

2553 * bt_active_async to GPIO pins
2554 */
2555 OS_REG_RMW_FIELD(ah,
2556 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2557 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2558 ahp->ah_bt_active_gpio_select);
2559
2560 /* Configure the desired GPIO ports for input */
2576
2577 if (ahp->ah_bt_coex_enabled) {
2578 ar9300_bt_coex_enable(ah);
2579 } else {
2580 ar9300_bt_coex_disable(ah);
2581 }
2582 }
2583 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&

--- 15 unchanged lines hidden (view full) ---

2599 * bt_active_async to GPIO pins
2600 */
2601 OS_REG_RMW_FIELD(ah,
2602 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2603 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2604 ahp->ah_bt_active_gpio_select);
2605
2606 /* Configure the desired GPIO ports for input */
2561 ath_hal_gpio_cfg_input(ah, ahp->ah_bt_active_gpio_select);
2607 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2562
2563 /* Enable coexistence on initialization */
2564 ar9300_bt_coex_enable(ah);
2565 }
2566 }
2567#if ATH_SUPPORT_MCI
2568 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) {
2569 if (ahp->ah_bt_coex_enabled) {

--- 72 unchanged lines hidden (view full) ---

2642
2643 /* turn on filter pass hold (bit 9) */
2644 OS_REG_WRITE(ah, AR_AZIMUTH_MODE,
2645 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD);
2646
2647 return HAL_OK;
2648}
2649
2608
2609 /* Enable coexistence on initialization */
2610 ar9300_bt_coex_enable(ah);
2611 }
2612 }
2613#if ATH_SUPPORT_MCI
2614 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) {
2615 if (ahp->ah_bt_coex_enabled) {

--- 72 unchanged lines hidden (view full) ---

2688
2689 /* turn on filter pass hold (bit 9) */
2690 OS_REG_WRITE(ah, AR_AZIMUTH_MODE,
2691 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD);
2692
2693 return HAL_OK;
2694}
2695
2696#if 0
2650void ar9300_mat_enable(struct ath_hal *ah, int enable)
2651{
2652 /*
2653 * MAT (s/w ProxySTA) implementation requires to turn off interrupt
2654 * mitigation and turn on key search always for better performance.
2655 */
2656 struct ath_hal_9300 *ahp = AH9300(ah);
2657 struct ath_hal_private *ap = AH_PRIVATE(ah);

--- 12 unchanged lines hidden (view full) ---

2670 #define AH_RIMT_FIRST_MICROSEC 2000
2671 #endif
2672 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC);
2673 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC);
2674 } else {
2675 OS_REG_WRITE(ah, AR_RIMT, 0);
2676 }
2677
2697void ar9300_mat_enable(struct ath_hal *ah, int enable)
2698{
2699 /*
2700 * MAT (s/w ProxySTA) implementation requires to turn off interrupt
2701 * mitigation and turn on key search always for better performance.
2702 */
2703 struct ath_hal_9300 *ahp = AH9300(ah);
2704 struct ath_hal_private *ap = AH_PRIVATE(ah);

--- 12 unchanged lines hidden (view full) ---

2717 #define AH_RIMT_FIRST_MICROSEC 2000
2718 #endif
2719 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC);
2720 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC);
2721 } else {
2722 OS_REG_WRITE(ah, AR_RIMT, 0);
2723 }
2724
2678 ap->ah_enable_keysearch_always = !!enable;
2679 ar9300_enable_keysearch_always(ah, ap->ah_enable_keysearch_always);
2725 ahp->ah_enable_keysearch_always = !!enable;
2726 ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always);
2680}
2727}
2728#endif
2681
2729
2682
2683void ar9300_enable_tpc(struct ath_hal *ah)
2684{
2685 u_int32_t val = 0;
2686
2730void ar9300_enable_tpc(struct ath_hal *ah)
2731{
2732 u_int32_t val = 0;
2733
2687 AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc = 1;
2734 ah->ah_config.ath_hal_desc_tpc = 1;
2688
2689 /* Enable TPC */
2690 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1);
2691
2692 /*
2693 * Disable per chain power reduction since we are already
2694 * accounting for this in our calculations
2695 */

--- 29 unchanged lines hidden (view full) ---

2725 u_int32_t temp_powertx_rate9_reg_val;
2726 int8_t olpc_power_offset = 0;
2727 int8_t tmp_olpc_val = 0;
2728 HAL_RSSI_TX_POWER old_greentx_status;
2729 u_int8_t target_power_val_t[ar9300_rate_size];
2730 int8_t tmp_rss1_thr1, tmp_rss1_thr2;
2731
2732 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) ||
2735
2736 /* Enable TPC */
2737 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1);
2738
2739 /*
2740 * Disable per chain power reduction since we are already
2741 * accounting for this in our calculations
2742 */

--- 29 unchanged lines hidden (view full) ---

2772 u_int32_t temp_powertx_rate9_reg_val;
2773 int8_t olpc_power_offset = 0;
2774 int8_t tmp_olpc_val = 0;
2775 HAL_RSSI_TX_POWER old_greentx_status;
2776 u_int8_t target_power_val_t[ar9300_rate_size];
2777 int8_t tmp_rss1_thr1, tmp_rss1_thr2;
2778
2779 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) ||
2733 !AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable) {
2780 !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) {
2734 return;
2735 }
2736
2781 return;
2782 }
2783
2737 old_greentx_status = AH_PRIVATE(ah)->green_tx_status;
2784 old_greentx_status = AH9300(ah)->green_tx_status;
2738 if (ahp->ah_hw_green_tx_enable) {
2739 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB;
2740 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB;
2741 } else {
2742 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB;
2743 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB;
2744 }
2745
2785 if (ahp->ah_hw_green_tx_enable) {
2786 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB;
2787 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB;
2788 } else {
2789 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB;
2790 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB;
2791 }
2792
2746 if ((AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S1)
2793 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1)
2747 && (rssi > tmp_rss1_thr1))
2748 {
2749 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) {
2794 && (rssi > tmp_rss1_thr1))
2795 {
2796 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) {
2750 AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT;
2797 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT;
2751 }
2798 }
2752 } else if (AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S2
2799 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2
2753 && (rssi > tmp_rss1_thr2))
2754 {
2755 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) {
2800 && (rssi > tmp_rss1_thr2))
2801 {
2802 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) {
2756 AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE;
2803 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE;
2757 }
2804 }
2758 } else if (AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) {
2805 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) {
2759 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) {
2806 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) {
2760 AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG;
2807 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG;
2761 }
2762 }
2763
2764 /* If status is not change, don't do anything */
2808 }
2809 }
2810
2811 /* If status is not change, don't do anything */
2765 if (old_greentx_status == AH_PRIVATE(ah)->green_tx_status) {
2812 if (old_greentx_status == AH9300(ah)->green_tx_status) {
2766 return;
2767 }
2768
2769 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */
2813 return;
2814 }
2815
2816 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */
2770 if ((AH_PRIVATE(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE)
2817 if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE)
2771 && AR_SREV_POSEIDON(ah))
2772 {
2773 if (ahp->ah_hw_green_tx_enable) {
2818 && AR_SREV_POSEIDON(ah))
2819 {
2820 if (ahp->ah_hw_green_tx_enable) {
2774 switch (AH_PRIVATE(ah)->green_tx_status) {
2821 switch (AH9300(ah)->green_tx_status) {
2775 case HAL_RSSI_TX_POWER_SHORT:
2776 /* 1. TxPower Config */
2777 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short,
2778 sizeof(target_power_val_t));
2779 /* 1.1 Store OLPC Delta Calibration Offset*/
2780 olpc_power_offset = 0;
2781 /* 2. Store OB/DB */
2782 /* 3. Store TPC settting */

--- 26 unchanged lines hidden (view full) ---

2809 /* 1. TxPower Config */
2810 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
2811 sizeof(target_power_val_t));
2812 /* 1.1 Store OLPC Delta Calibration Offset*/
2813 olpc_power_offset = 0;
2814 /* 2. Store OB/DB1/DB2 */
2815 /* 3. Store TPC settting */
2816 temp_tcp_reg_val =
2822 case HAL_RSSI_TX_POWER_SHORT:
2823 /* 1. TxPower Config */
2824 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short,
2825 sizeof(target_power_val_t));
2826 /* 1.1 Store OLPC Delta Calibration Offset*/
2827 olpc_power_offset = 0;
2828 /* 2. Store OB/DB */
2829 /* 3. Store TPC settting */

--- 26 unchanged lines hidden (view full) ---

2856 /* 1. TxPower Config */
2857 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
2858 sizeof(target_power_val_t));
2859 /* 1.1 Store OLPC Delta Calibration Offset*/
2860 olpc_power_offset = 0;
2861 /* 2. Store OB/DB1/DB2 */
2862 /* 3. Store TPC settting */
2863 temp_tcp_reg_val =
2817 AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2864 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2818 /* 4. Store BB_powertx_rate9 value */
2819 temp_powertx_rate9_reg_val =
2865 /* 4. Store BB_powertx_rate9 value */
2866 temp_powertx_rate9_reg_val =
2820 AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2867 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2821 break;
2822 }
2823 } else {
2868 break;
2869 }
2870 } else {
2824 switch (AH_PRIVATE(ah)->green_tx_status) {
2871 switch (AH9300(ah)->green_tx_status) {
2825 case HAL_RSSI_TX_POWER_SHORT:
2826 /* 1. TxPower Config */
2827 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short,
2828 sizeof(target_power_val_t));
2829 /* 1.1 Store OLPC Delta Calibration Offset*/
2830 olpc_power_offset =
2831 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] -
2832 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2833 /* 2. Store OB/DB */
2834 temp_obdb_reg_val =
2872 case HAL_RSSI_TX_POWER_SHORT:
2873 /* 1. TxPower Config */
2874 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short,
2875 sizeof(target_power_val_t));
2876 /* 1.1 Store OLPC Delta Calibration Offset*/
2877 olpc_power_offset =
2878 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] -
2879 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2880 /* 2. Store OB/DB */
2881 temp_obdb_reg_val =
2835 AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2882 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2836 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
2837 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
2838 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
2839 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
2840 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
2841 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2842 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
2843 SM(WB225_OB_GREEN_TX_SHORT_VALUE,

--- 14 unchanged lines hidden (view full) ---

2858 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle,
2859 sizeof(target_power_val_t));
2860 /* 1.1 Store OLPC Delta Calibration Offset*/
2861 olpc_power_offset =
2862 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] -
2863 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2864 /* 2. Store OB/DB */
2865 temp_obdb_reg_val =
2883 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
2884 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
2885 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
2886 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
2887 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
2888 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2889 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
2890 SM(WB225_OB_GREEN_TX_SHORT_VALUE,

--- 14 unchanged lines hidden (view full) ---

2905 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle,
2906 sizeof(target_power_val_t));
2907 /* 1.1 Store OLPC Delta Calibration Offset*/
2908 olpc_power_offset =
2909 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] -
2910 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2911 /* 2. Store OB/DB */
2912 temp_obdb_reg_val =
2866 AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2913 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2867 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
2868 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
2869 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
2870 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
2871 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
2872 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
2873 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
2874 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,

--- 15 unchanged lines hidden (view full) ---

2890 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
2891 sizeof(target_power_val_t));
2892 /* 1.1 Store OLPC Delta Calibration Offset*/
2893 olpc_power_offset =
2894 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] -
2895 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2896 /* 2. Store OB/DB1/DB2 */
2897 temp_obdb_reg_val =
2914 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
2915 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
2916 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
2917 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
2918 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
2919 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
2920 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
2921 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,

--- 15 unchanged lines hidden (view full) ---

2937 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
2938 sizeof(target_power_val_t));
2939 /* 1.1 Store OLPC Delta Calibration Offset*/
2940 olpc_power_offset =
2941 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] -
2942 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2943 /* 2. Store OB/DB1/DB2 */
2944 temp_obdb_reg_val =
2898 AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2945 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2899 /* 3. Store TPC settting */
2900 temp_tcp_reg_val =
2946 /* 3. Store TPC settting */
2947 temp_tcp_reg_val =
2901 AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2948 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2902 /* 4. Store BB_powertx_rate9 value */
2903 temp_powertx_rate9_reg_val =
2949 /* 4. Store BB_powertx_rate9 value */
2950 temp_powertx_rate9_reg_val =
2904 AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2951 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2905 break;
2906 }
2907 }
2908 /* 1.1 Do OLPC Delta Calibration Offset */
2909 tmp_olpc_val =
2952 break;
2953 }
2954 }
2955 /* 1.1 Do OLPC Delta Calibration Offset */
2956 tmp_olpc_val =
2910 (int8_t) AH_PRIVATE(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET];
2957 (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET];
2911 tmp_olpc_val += olpc_power_offset;
2912 OS_REG_RMW(ah, AR_PHY_TPC_11_B0,
2913 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
2914 AR_PHY_TPC_OLPC_GAIN_DELTA);
2915
2916 /* 1.2 TxPower Config */
2917 ar9300_transmit_power_reg_write(ah, target_power_val_t);
2918 /* 2. Config OB/DB */
2919 if (!ahp->ah_hw_green_tx_enable) {
2920 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val);
2921 }
2922 /* 3. config TPC settting */
2923 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val);
2924 /* 4. config BB_powertx_rate9 value */
2925 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val);
2926 }
2927}
2928
2958 tmp_olpc_val += olpc_power_offset;
2959 OS_REG_RMW(ah, AR_PHY_TPC_11_B0,
2960 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
2961 AR_PHY_TPC_OLPC_GAIN_DELTA);
2962
2963 /* 1.2 TxPower Config */
2964 ar9300_transmit_power_reg_write(ah, target_power_val_t);
2965 /* 2. Config OB/DB */
2966 if (!ahp->ah_hw_green_tx_enable) {
2967 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val);
2968 }
2969 /* 3. config TPC settting */
2970 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val);
2971 /* 4. config BB_powertx_rate9 value */
2972 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val);
2973 }
2974}
2975
2976#if 0
2929void
2930ar9300_get_vow_stats(
2931 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags)
2932{
2933 if (vow_reg_flags & AR_REG_TX_FRM_CNT) {
2934 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
2935 }
2936 if (vow_reg_flags & AR_REG_RX_FRM_CNT) {

--- 4 unchanged lines hidden (view full) ---

2941 }
2942 if (vow_reg_flags & AR_REG_CYCLE_CNT) {
2943 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT);
2944 }
2945 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) {
2946 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT);
2947 }
2948}
2977void
2978ar9300_get_vow_stats(
2979 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags)
2980{
2981 if (vow_reg_flags & AR_REG_TX_FRM_CNT) {
2982 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
2983 }
2984 if (vow_reg_flags & AR_REG_RX_FRM_CNT) {

--- 4 unchanged lines hidden (view full) ---

2989 }
2990 if (vow_reg_flags & AR_REG_CYCLE_CNT) {
2991 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT);
2992 }
2993 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) {
2994 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT);
2995 }
2996}
2997#endif
2998
2949/*
2950 * ar9300_is_skip_paprd_by_greentx
2951 *
2952 * This function check if we need to skip PAPRD tuning
2953 * when GreenTx in specific state.
2954 */
2999/*
3000 * ar9300_is_skip_paprd_by_greentx
3001 *
3002 * This function check if we need to skip PAPRD tuning
3003 * when GreenTx in specific state.
3004 */
2955HAL_BOOL
3005HAL_BOOL
2956ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah)
2957{
2958 if (AR_SREV_POSEIDON(ah) &&
3006ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah)
3007{
3008 if (AR_SREV_POSEIDON(ah) &&
2959 AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable &&
2960 ((AH_PRIVATE(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) ||
2961 (AH_PRIVATE(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE)))
3009 ah->ah_config.ath_hal_sta_update_tx_pwr_enable &&
3010 ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) ||
3011 (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE)))
2962 {
2963 return AH_TRUE;
2964 }
2965 return AH_FALSE;
2966}
2967
2968void
2969ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah)

--- 83 unchanged lines hidden (view full) ---

3053 u_int32_t key0, key1, key2, key3, key4;
3054 u_int32_t mac_hi, mac_lo;
3055 u_int16_t entry = 0;
3056 u_int32_t valid = 0;
3057 u_int32_t key_type;
3058
3059 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n");
3060
3012 {
3013 return AH_TRUE;
3014 }
3015 return AH_FALSE;
3016}
3017
3018void
3019ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah)

--- 83 unchanged lines hidden (view full) ---

3103 u_int32_t key0, key1, key2, key3, key4;
3104 u_int32_t mac_hi, mac_lo;
3105 u_int16_t entry = 0;
3106 u_int32_t valid = 0;
3107 u_int32_t key_type;
3108
3109 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n");
3110
3061 for (entry = 0 ; entry < p_cap->hal_key_cache_size; entry++) {
3111 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) {
3062 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry));
3063 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry));
3064 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry));
3065 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry));
3066 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry));
3067
3068 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));
3069

--- 33 unchanged lines hidden (view full) ---

3103 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24,
3104 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 );
3105 }
3106
3107 return AH_TRUE;
3108}
3109
3110/* enable/disable smart antenna mode */
3112 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry));
3113 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry));
3114 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry));
3115 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry));
3116 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry));
3117
3118 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));
3119

--- 33 unchanged lines hidden (view full) ---

3153 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24,
3154 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 );
3155 }
3156
3157 return AH_TRUE;
3158}
3159
3160/* enable/disable smart antenna mode */
3111HAL_BOOL ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
3161HAL_BOOL
3162ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
3112{
3113 struct ath_hal_9300 *ahp = AH9300(ah);
3114
3115 if (enable) {
3116 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3117 } else {
3118 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3119 }

--- 12 unchanged lines hidden (view full) ---

3132 }
3133
3134 ahp->ah_smartantenna_enable = enable;
3135 return 1;
3136}
3137
3138#ifdef ATH_TX99_DIAG
3139#ifndef ATH_SUPPORT_HTC
3163{
3164 struct ath_hal_9300 *ahp = AH9300(ah);
3165
3166 if (enable) {
3167 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3168 } else {
3169 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3170 }

--- 12 unchanged lines hidden (view full) ---

3183 }
3184
3185 ahp->ah_smartantenna_enable = enable;
3186 return 1;
3187}
3188
3189#ifdef ATH_TX99_DIAG
3190#ifndef ATH_SUPPORT_HTC
3140void
3191void
3141ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c,
3142 u_int32_t txpower)
3143{
3144#define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s))
3145 static int16_t p_pwr_array[ar9300_rate_size] = { 0 };
3146 int32_t i;
3147
3148 /* The max power is limited to 63 */

--- 556 unchanged lines hidden (view full) ---

3705 return AH_FALSE;
3706}
3707
3708HAL_BOOL
3709ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val)
3710{
3711 return AH_FALSE;
3712}
3192ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c,
3193 u_int32_t txpower)
3194{
3195#define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s))
3196 static int16_t p_pwr_array[ar9300_rate_size] = { 0 };
3197 int32_t i;
3198
3199 /* The max power is limited to 63 */

--- 556 unchanged lines hidden (view full) ---

3756 return AH_FALSE;
3757}
3758
3759HAL_BOOL
3760ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val)
3761{
3762 return AH_FALSE;
3763}
3713
3714#endif /* AH_SUPPORT_AR9300 */