19,20d18
< #ifdef AH_SUPPORT_AR9300
<
61a60,63
> /*
> * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about
> * HT20, HT40, fast-clock, turbo mode, etc.
> */
65c67,68
< HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
---
> #if 0
> const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
67c70
< if (chan && IS_CHAN_HT40(chan)) {
---
> if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
71a75,76
> #endif
> return (ath_hal_mac_usec(ah, clks));
77c82,83
< HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
---
> #if 0
> const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
79c85
< if (chan && IS_CHAN_HT40(chan)) {
---
> if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
83a90,91
> #endif
> return (ath_hal_mac_clks(ah, usecs));
135,136c143,144
< if (AH_PRIVATE(ah)->ah_current_rd == 0) {
< AH_PRIVATE(ah)->ah_current_rd = reg_domain;
---
> if (AH_PRIVATE(ah)->ah_currentRD == 0) {
> AH_PRIVATE(ah)->ah_currentRD = reg_domain;
141c149
< #if tbd
---
> #if 0
160c168
< return AH_PRIVATE(ah)->ah_caps.hal_wireless_modes;
---
> return AH_PRIVATE(ah)->ah_caps.halWirelessModes;
204c212
< ath_hal_gpio_cfg_input(ah, ahp->ah_gpio_select);
---
> ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select);
360c368
< HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
---
> const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
365c373
< if (chan == AH_NULL || !IS_CHAN_CCK(chan)) {
---
> if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) {
518,519c526,527
< HAL_ANT_SETTING settings, HAL_CHANNEL *chan, u_int8_t *tx_chainmask,
< u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd)
---
> HAL_ANT_SETTING settings, const struct ieee80211_channel *chan,
> u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd)
605a614
> #define TU_TO_USEC(_tu) ((_tu) << 10)
617c626
< AH_PRIVATE(ah)->ah_config.ath_hal_sw_beacon_response_time;
---
> ah->ah_config.ah_sw_beacon_response_time;
638a648
> #undef TU_TO_USEC
701,703c711,719
< /* XXX check rev when new parts are available */
< return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
< HAL_ENXIO : HAL_OK;
---
> switch (capability) {
> case 0: /* hardware capability */
> return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK;
> case 1: /* current setting */
> return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
> HAL_ENXIO : HAL_OK;
> default:
> return HAL_ENOTSUPP;
> }
724c740
< return AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc ?
---
> return ah->ah_config.ath_hal_desc_tpc ?
751c767
< return p_cap->hal_tsf_add_support ? HAL_OK : HAL_ENOTSUPP;
---
> return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
784a801
> #if 0
786c803
< *result = p_cap->hal_num_ant_cfg_2ghz;
---
> *result = p_cap->halNumAntCfg2Ghz;
789c806
< *result = p_cap->hal_num_ant_cfg_5ghz;
---
> *result = p_cap->halNumAntCfg5Ghz;
796a814
> #endif
798c816
< *result = p_cap->hal_ldpc_support;
---
> *result = p_cap->halLDPCSupport;
804,805c822,823
< (p_cap->hal_tx_chain_mask & 0x3) != 0x3 ||
< (p_cap->hal_rx_chain_mask & 0x3) != 0x3) ?
---
> (p_cap->halTxChainMask & 0x3) != 0x3 ||
> (p_cap->halRxChainMask & 0x3) != 0x3) ?
809,810c827,828
< (p_cap->hal_tx_chain_mask & 0x7) != 0x7 ||
< (p_cap->hal_rx_chain_mask & 0x7) != 0x7) ?
---
> (p_cap->halTxChainMask & 0x7) != 0x7 ||
> (p_cap->halRxChainMask & 0x7) != 0x7) ?
818c836
< AH_PRIVATE(ah)->ah_config.ath_hal_crdc_enable) ?
---
> ah->ah_config.ath_hal_crdc_enable) ?
822a841
> #if 0
828a848
> #endif
849c869
< if ((ahp->ah_enterprise_mode && AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) &&
---
> if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) &&
861c881
< *result = p_cap->hal_enable_apm;
---
> *result = p_cap->halApmEnable;
907a928,939
> case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
> if (! p_cap->halTkipMicTxRxKeySupport)
> return AH_FALSE;
>
> if (setting)
> ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA;
> else
> ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
>
> OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode);
> return AH_TRUE;
>
938c970
< AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc = (setting != 0);
---
> ah->ah_config.ath_hal_desc_tpc = (setting != 0);
948c980
< if (p_cap->hal_tsf_add_support) {
---
> if (p_cap->halTsfAddSupport) {
1160a1193
> #if 0
1163a1197
> #endif
1188,1189c1222,1226
< int16_t nfarray[NUM_NF_READINGS];
< HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah);
---
> int16_t nfarray[HAL_NUM_NF_READINGS];
> #ifdef ATH_NF_PER_CHAN
> HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
> #endif /* ATH_NF_PER_CHAN */
> HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan);
1271c1308
< for (i = 0; i < NUM_NF_READINGS; i++) {
---
> for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
1493c1530
< int8_t
---
> uint32_t
1580,1581c1617,1618
< HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
< u_int32_t idle_tmo_ms = AH_PRIVATE(ah)->ah_bb_panic_timeout_ms;
---
> const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
> u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms;
1594c1631
< if (chan != AH_NULL && IS_CHAN_HT40(chan)) {
---
> if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) {
1623c1660
< HALDEBUG(ah, HAL_DEBUG_RF_PARAM, "%s: %s BB Panic Watchdog tmo=%ums\n",
---
> HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n",
1637c1674
< AH_PRIVATE(ah)->ah_bb_panic_last_status = status =
---
> AH9300(ah)->ah_bb_panic_last_status = status =
1649c1686
< bb_panic->status = AH_PRIVATE(ah)->ah_bb_panic_last_status;
---
> bb_panic->status = AH9300(ah)->ah_bb_panic_last_status;
1687c1724
< if (AH_PRIVATE(ah)->ah_config.ath_hal_show_bb_panic) {
---
> if (ah->ah_config.ath_hal_show_bb_panic) {
1714c1751
< AH_PRIVATE(ah)->ah_reset_reason = resetreason;
---
> AH9300(ah)->ah_reset_reason = resetreason;
1733c1770
< !AH_PRIVATE(ah)->ah_config.ath_hal_cwm_ignore_ext_cca) {
---
> !ah->ah_config.ath_hal_cwm_ignore_ext_cca) {
1852c1889
< HALDEBUG(ah, HAL_DEBUG_REG_IO,
---
> HALDEBUG(ah, HAL_DEBUG_REGIO,
1931,1932c1968,1969
< void
< ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_COUNTERS* p_cnts)
---
> HAL_BOOL
> ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs)
1933a1971,1974
> /*
> * XXX FreeBSD todo: reimplement this
> */
> #if 0
1941a1983,1984
> #endif
> return AH_FALSE;
1960,1961c2003,2006
< HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(AH_PRIVATE(ah)->ah_curchan);
< u_int32_t tmp = 0;
---
> HAL_CHANNEL_INTERNAL *ichan =
> ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
> HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan);
> u_int32_t tmp = 0;
1985c2030
< if (IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
---
> if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
1991c2036
< if (IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
---
> if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2178c2223,2224
< HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
---
> const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
> HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2183,2184c2229,2230
< hal_num_ant_config = IS_CHAN_2GHZ(chan) ?
< p_cap->hal_num_ant_cfg_2ghz : p_cap->hal_num_ant_cfg_5ghz;
---
> hal_num_ant_config = IS_CHAN_2GHZ(ichan) ?
> p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz;
2202c2248
< AH_PRIVATE(ah)->ah_dcs_enable = mode;
---
> AH9300(ah)->ah_dcs_enable = mode;
2208c2254
< return AH_PRIVATE(ah)->ah_dcs_enable;
---
> return AH9300(ah)->ah_dcs_enable;
2211c2257
< #ifdef ATH_BT_COEX
---
> #if ATH_BT_COEX
2322,2323c2368,2369
< struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
< HAL_CHANNEL *chan = (HAL_CHANNEL *) ahpriv->ah_curchan;
---
> //struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
> const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2353,2354c2399,2400
< ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit,
< ahpriv->ah_extra_txpow, 0);
---
> ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
> ahpriv->ah_extraTxPow, 0);
2376,2377c2422,2423
< ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit,
< ahpriv->ah_extra_txpow, 0);
---
> ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
> ahpriv->ah_extraTxPow, 0);
2381c2427
< if ((ahpriv->ah_config.ath_hal_mci_config &
---
> if ((ah->ah_config.ath_hal_mci_config &
2392,2393c2438,2439
< ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit,
< ahpriv->ah_extra_txpow, 0);
---
> ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
> ahpriv->ah_extraTxPow, 0);
2418c2464
< ath_hal_gpio_cfg_output(ah, ahp->ah_wlan_active_gpio_select,
---
> ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select,
2468c2514
< ath_hal_gpio_cfg_output(ah,
---
> ath_hal_gpioCfgOutput(ah,
2476c2522
< ath_hal_gpio_cfg_output(ah,
---
> ath_hal_gpioCfgOutput(ah,
2528,2529c2574,2575
< ath_hal_gpio_cfg_input(ah, ahp->ah_bt_active_gpio_select);
< ath_hal_gpio_cfg_input(ah, ahp->ah_bt_priority_gpio_select);
---
> ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
> ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select);
2561c2607
< ath_hal_gpio_cfg_input(ah, ahp->ah_bt_active_gpio_select);
---
> ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2649a2696
> #if 0
2678,2679c2725,2726
< ap->ah_enable_keysearch_always = !!enable;
< ar9300_enable_keysearch_always(ah, ap->ah_enable_keysearch_always);
---
> ahp->ah_enable_keysearch_always = !!enable;
> ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always);
2680a2728
> #endif
2682d2729
<
2687c2734
< AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc = 1;
---
> ah->ah_config.ath_hal_desc_tpc = 1;
2733c2780
< !AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable) {
---
> !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) {
2737c2784
< old_greentx_status = AH_PRIVATE(ah)->green_tx_status;
---
> old_greentx_status = AH9300(ah)->green_tx_status;
2746c2793
< if ((AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S1)
---
> if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1)
2750c2797
< AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT;
---
> AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT;
2752c2799
< } else if (AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S2
---
> } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2
2756c2803
< AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE;
---
> AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE;
2758c2805
< } else if (AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) {
---
> } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) {
2760c2807
< AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG;
---
> AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG;
2765c2812
< if (old_greentx_status == AH_PRIVATE(ah)->green_tx_status) {
---
> if (old_greentx_status == AH9300(ah)->green_tx_status) {
2770c2817
< if ((AH_PRIVATE(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE)
---
> if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE)
2774c2821
< switch (AH_PRIVATE(ah)->green_tx_status) {
---
> switch (AH9300(ah)->green_tx_status) {
2817c2864
< AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
---
> AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2820c2867
< AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
---
> AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2824c2871
< switch (AH_PRIVATE(ah)->green_tx_status) {
---
> switch (AH9300(ah)->green_tx_status) {
2835c2882
< AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
---
> AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2866c2913
< AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
---
> AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2898c2945
< AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
---
> AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2901c2948
< AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
---
> AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2904c2951
< AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
---
> AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2910c2957
< (int8_t) AH_PRIVATE(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET];
---
> (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET];
2928a2976
> #if 0
2948a2997,2998
> #endif
>
2955c3005
< HAL_BOOL
---
> HAL_BOOL
2959,2961c3009,3011
< AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable &&
< ((AH_PRIVATE(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) ||
< (AH_PRIVATE(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE)))
---
> ah->ah_config.ath_hal_sta_update_tx_pwr_enable &&
> ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) ||
> (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE)))
3061c3111
< for (entry = 0 ; entry < p_cap->hal_key_cache_size; entry++) {
---
> for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) {
3111c3161,3162
< HAL_BOOL ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
---
> HAL_BOOL
> ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
3140c3191
< void
---
> void
3713,3714d3763
<
< #endif /* AH_SUPPORT_AR9300 */
< #ifdef AH_SUPPORT_AR9300
<
61a60,63
> /*
> * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about
> * HT20, HT40, fast-clock, turbo mode, etc.
> */
65c67,68
< HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
---
> #if 0
> const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
67c70
< if (chan && IS_CHAN_HT40(chan)) {
---
> if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
71a75,76
> #endif
> return (ath_hal_mac_usec(ah, clks));
77c82,83
< HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
---
> #if 0
> const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
79c85
< if (chan && IS_CHAN_HT40(chan)) {
---
> if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
83a90,91
> #endif
> return (ath_hal_mac_clks(ah, usecs));
135,136c143,144
< if (AH_PRIVATE(ah)->ah_current_rd == 0) {
< AH_PRIVATE(ah)->ah_current_rd = reg_domain;
---
> if (AH_PRIVATE(ah)->ah_currentRD == 0) {
> AH_PRIVATE(ah)->ah_currentRD = reg_domain;
141c149
< #if tbd
---
> #if 0
160c168
< return AH_PRIVATE(ah)->ah_caps.hal_wireless_modes;
---
> return AH_PRIVATE(ah)->ah_caps.halWirelessModes;
204c212
< ath_hal_gpio_cfg_input(ah, ahp->ah_gpio_select);
---
> ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select);
360c368
< HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
---
> const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
365c373
< if (chan == AH_NULL || !IS_CHAN_CCK(chan)) {
---
> if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) {
518,519c526,527
< HAL_ANT_SETTING settings, HAL_CHANNEL *chan, u_int8_t *tx_chainmask,
< u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd)
---
> HAL_ANT_SETTING settings, const struct ieee80211_channel *chan,
> u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd)
605a614
> #define TU_TO_USEC(_tu) ((_tu) << 10)
617c626
< AH_PRIVATE(ah)->ah_config.ath_hal_sw_beacon_response_time;
---
> ah->ah_config.ah_sw_beacon_response_time;
638a648
> #undef TU_TO_USEC
701,703c711,719
< /* XXX check rev when new parts are available */
< return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
< HAL_ENXIO : HAL_OK;
---
> switch (capability) {
> case 0: /* hardware capability */
> return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK;
> case 1: /* current setting */
> return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
> HAL_ENXIO : HAL_OK;
> default:
> return HAL_ENOTSUPP;
> }
724c740
< return AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc ?
---
> return ah->ah_config.ath_hal_desc_tpc ?
751c767
< return p_cap->hal_tsf_add_support ? HAL_OK : HAL_ENOTSUPP;
---
> return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
784a801
> #if 0
786c803
< *result = p_cap->hal_num_ant_cfg_2ghz;
---
> *result = p_cap->halNumAntCfg2Ghz;
789c806
< *result = p_cap->hal_num_ant_cfg_5ghz;
---
> *result = p_cap->halNumAntCfg5Ghz;
796a814
> #endif
798c816
< *result = p_cap->hal_ldpc_support;
---
> *result = p_cap->halLDPCSupport;
804,805c822,823
< (p_cap->hal_tx_chain_mask & 0x3) != 0x3 ||
< (p_cap->hal_rx_chain_mask & 0x3) != 0x3) ?
---
> (p_cap->halTxChainMask & 0x3) != 0x3 ||
> (p_cap->halRxChainMask & 0x3) != 0x3) ?
809,810c827,828
< (p_cap->hal_tx_chain_mask & 0x7) != 0x7 ||
< (p_cap->hal_rx_chain_mask & 0x7) != 0x7) ?
---
> (p_cap->halTxChainMask & 0x7) != 0x7 ||
> (p_cap->halRxChainMask & 0x7) != 0x7) ?
818c836
< AH_PRIVATE(ah)->ah_config.ath_hal_crdc_enable) ?
---
> ah->ah_config.ath_hal_crdc_enable) ?
822a841
> #if 0
828a848
> #endif
849c869
< if ((ahp->ah_enterprise_mode && AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) &&
---
> if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) &&
861c881
< *result = p_cap->hal_enable_apm;
---
> *result = p_cap->halApmEnable;
907a928,939
> case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
> if (! p_cap->halTkipMicTxRxKeySupport)
> return AH_FALSE;
>
> if (setting)
> ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA;
> else
> ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
>
> OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode);
> return AH_TRUE;
>
938c970
< AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc = (setting != 0);
---
> ah->ah_config.ath_hal_desc_tpc = (setting != 0);
948c980
< if (p_cap->hal_tsf_add_support) {
---
> if (p_cap->halTsfAddSupport) {
1160a1193
> #if 0
1163a1197
> #endif
1188,1189c1222,1226
< int16_t nfarray[NUM_NF_READINGS];
< HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah);
---
> int16_t nfarray[HAL_NUM_NF_READINGS];
> #ifdef ATH_NF_PER_CHAN
> HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
> #endif /* ATH_NF_PER_CHAN */
> HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan);
1271c1308
< for (i = 0; i < NUM_NF_READINGS; i++) {
---
> for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
1493c1530
< int8_t
---
> uint32_t
1580,1581c1617,1618
< HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
< u_int32_t idle_tmo_ms = AH_PRIVATE(ah)->ah_bb_panic_timeout_ms;
---
> const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
> u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms;
1594c1631
< if (chan != AH_NULL && IS_CHAN_HT40(chan)) {
---
> if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) {
1623c1660
< HALDEBUG(ah, HAL_DEBUG_RF_PARAM, "%s: %s BB Panic Watchdog tmo=%ums\n",
---
> HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n",
1637c1674
< AH_PRIVATE(ah)->ah_bb_panic_last_status = status =
---
> AH9300(ah)->ah_bb_panic_last_status = status =
1649c1686
< bb_panic->status = AH_PRIVATE(ah)->ah_bb_panic_last_status;
---
> bb_panic->status = AH9300(ah)->ah_bb_panic_last_status;
1687c1724
< if (AH_PRIVATE(ah)->ah_config.ath_hal_show_bb_panic) {
---
> if (ah->ah_config.ath_hal_show_bb_panic) {
1714c1751
< AH_PRIVATE(ah)->ah_reset_reason = resetreason;
---
> AH9300(ah)->ah_reset_reason = resetreason;
1733c1770
< !AH_PRIVATE(ah)->ah_config.ath_hal_cwm_ignore_ext_cca) {
---
> !ah->ah_config.ath_hal_cwm_ignore_ext_cca) {
1852c1889
< HALDEBUG(ah, HAL_DEBUG_REG_IO,
---
> HALDEBUG(ah, HAL_DEBUG_REGIO,
1931,1932c1968,1969
< void
< ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_COUNTERS* p_cnts)
---
> HAL_BOOL
> ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs)
1933a1971,1974
> /*
> * XXX FreeBSD todo: reimplement this
> */
> #if 0
1941a1983,1984
> #endif
> return AH_FALSE;
1960,1961c2003,2006
< HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(AH_PRIVATE(ah)->ah_curchan);
< u_int32_t tmp = 0;
---
> HAL_CHANNEL_INTERNAL *ichan =
> ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
> HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan);
> u_int32_t tmp = 0;
1985c2030
< if (IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
---
> if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
1991c2036
< if (IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
---
> if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2178c2223,2224
< HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
---
> const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
> HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2183,2184c2229,2230
< hal_num_ant_config = IS_CHAN_2GHZ(chan) ?
< p_cap->hal_num_ant_cfg_2ghz : p_cap->hal_num_ant_cfg_5ghz;
---
> hal_num_ant_config = IS_CHAN_2GHZ(ichan) ?
> p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz;
2202c2248
< AH_PRIVATE(ah)->ah_dcs_enable = mode;
---
> AH9300(ah)->ah_dcs_enable = mode;
2208c2254
< return AH_PRIVATE(ah)->ah_dcs_enable;
---
> return AH9300(ah)->ah_dcs_enable;
2211c2257
< #ifdef ATH_BT_COEX
---
> #if ATH_BT_COEX
2322,2323c2368,2369
< struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
< HAL_CHANNEL *chan = (HAL_CHANNEL *) ahpriv->ah_curchan;
---
> //struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
> const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2353,2354c2399,2400
< ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit,
< ahpriv->ah_extra_txpow, 0);
---
> ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
> ahpriv->ah_extraTxPow, 0);
2376,2377c2422,2423
< ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit,
< ahpriv->ah_extra_txpow, 0);
---
> ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
> ahpriv->ah_extraTxPow, 0);
2381c2427
< if ((ahpriv->ah_config.ath_hal_mci_config &
---
> if ((ah->ah_config.ath_hal_mci_config &
2392,2393c2438,2439
< ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit,
< ahpriv->ah_extra_txpow, 0);
---
> ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
> ahpriv->ah_extraTxPow, 0);
2418c2464
< ath_hal_gpio_cfg_output(ah, ahp->ah_wlan_active_gpio_select,
---
> ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select,
2468c2514
< ath_hal_gpio_cfg_output(ah,
---
> ath_hal_gpioCfgOutput(ah,
2476c2522
< ath_hal_gpio_cfg_output(ah,
---
> ath_hal_gpioCfgOutput(ah,
2528,2529c2574,2575
< ath_hal_gpio_cfg_input(ah, ahp->ah_bt_active_gpio_select);
< ath_hal_gpio_cfg_input(ah, ahp->ah_bt_priority_gpio_select);
---
> ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
> ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select);
2561c2607
< ath_hal_gpio_cfg_input(ah, ahp->ah_bt_active_gpio_select);
---
> ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2649a2696
> #if 0
2678,2679c2725,2726
< ap->ah_enable_keysearch_always = !!enable;
< ar9300_enable_keysearch_always(ah, ap->ah_enable_keysearch_always);
---
> ahp->ah_enable_keysearch_always = !!enable;
> ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always);
2680a2728
> #endif
2682d2729
<
2687c2734
< AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc = 1;
---
> ah->ah_config.ath_hal_desc_tpc = 1;
2733c2780
< !AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable) {
---
> !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) {
2737c2784
< old_greentx_status = AH_PRIVATE(ah)->green_tx_status;
---
> old_greentx_status = AH9300(ah)->green_tx_status;
2746c2793
< if ((AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S1)
---
> if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1)
2750c2797
< AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT;
---
> AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT;
2752c2799
< } else if (AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S2
---
> } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2
2756c2803
< AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE;
---
> AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE;
2758c2805
< } else if (AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) {
---
> } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) {
2760c2807
< AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG;
---
> AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG;
2765c2812
< if (old_greentx_status == AH_PRIVATE(ah)->green_tx_status) {
---
> if (old_greentx_status == AH9300(ah)->green_tx_status) {
2770c2817
< if ((AH_PRIVATE(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE)
---
> if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE)
2774c2821
< switch (AH_PRIVATE(ah)->green_tx_status) {
---
> switch (AH9300(ah)->green_tx_status) {
2817c2864
< AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
---
> AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2820c2867
< AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
---
> AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2824c2871
< switch (AH_PRIVATE(ah)->green_tx_status) {
---
> switch (AH9300(ah)->green_tx_status) {
2835c2882
< AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
---
> AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2866c2913
< AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
---
> AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2898c2945
< AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
---
> AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2901c2948
< AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
---
> AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2904c2951
< AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
---
> AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2910c2957
< (int8_t) AH_PRIVATE(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET];
---
> (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET];
2928a2976
> #if 0
2948a2997,2998
> #endif
>
2955c3005
< HAL_BOOL
---
> HAL_BOOL
2959,2961c3009,3011
< AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable &&
< ((AH_PRIVATE(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) ||
< (AH_PRIVATE(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE)))
---
> ah->ah_config.ath_hal_sta_update_tx_pwr_enable &&
> ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) ||
> (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE)))
3061c3111
< for (entry = 0 ; entry < p_cap->hal_key_cache_size; entry++) {
---
> for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) {
3111c3161,3162
< HAL_BOOL ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
---
> HAL_BOOL
> ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
3140c3191
< void
---
> void
3713,3714d3763
<
< #endif /* AH_SUPPORT_AR9300 */