1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "opt_ah.h"
18
19#include "ah.h"
20#include "ah_internal.h"
21#include "ah_devid.h"
22#ifdef AH_DEBUG
23#include "ah_desc.h" /* NB: for HAL_PHYERR* */
24#endif
25
26#include "ar9300/ar9300.h"
--- 25 unchanged lines hidden (view full) ---
52 == HAL_OK)
53 {
54 *hangs |= HAL_PHYRESTART_CLR_WAR;
55 }
56
57 ahp->ah_hang_wars = *hangs;
58}
59
60/*
61 * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about
62 * HT20, HT40, fast-clock, turbo mode, etc.
63 */
64static u_int
65ar9300_mac_to_usec(struct ath_hal *ah, u_int clks)
66{
67#if 0
68 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
69
70 if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
71 return (ath_hal_mac_usec(ah, clks) / 2);
72 } else {
73 return (ath_hal_mac_usec(ah, clks));
74 }
75#endif
76 return (ath_hal_mac_usec(ah, clks));
77}
78
79u_int
80ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs)
81{
82#if 0
83 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
84
85 if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
86 return (ath_hal_mac_clks(ah, usecs) * 2);
87 } else {
88 return (ath_hal_mac_clks(ah, usecs));
89 }
90#endif
91 return (ath_hal_mac_clks(ah, usecs));
92}
93
94void
95ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac)
96{
97 struct ath_hal_9300 *ahp = AH9300(ah);
98
99 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
--- 35 unchanged lines hidden (view full) ---
135 * A_HARDWARE for an unwritable EEPROM or bad EEPROM version
136 */
137HAL_BOOL
138ar9300_set_regulatory_domain(struct ath_hal *ah,
139 u_int16_t reg_domain, HAL_STATUS *status)
140{
141 HAL_STATUS ecode;
142
143 if (AH_PRIVATE(ah)->ah_currentRD == 0) {
144 AH_PRIVATE(ah)->ah_currentRD = reg_domain;
145 return AH_TRUE;
146 }
147 ecode = HAL_EIO;
148
149#if 0
150bad:
151#endif
152 if (status) {
153 *status = ecode;
154 }
155 return AH_FALSE;
156}
157
158/*
159 * Return the wireless modes (a,b,g,t) supported by hardware.
160 *
161 * This value is what is actually supported by the hardware
162 * and is unaffected by regulatory/country code settings.
163 *
164 */
165u_int
166ar9300_get_wireless_modes(struct ath_hal *ah)
167{
168 return AH_PRIVATE(ah)->ah_caps.halWirelessModes;
169}
170
171/*
172 * Set the interrupt and GPIO values so the ISR can disable RF
173 * on a switch signal. Assumes GPIO port and interrupt polarity
174 * are set prior to call.
175 */
176void
--- 27 unchanged lines hidden (view full) ---
204 AR_GPIO_INPUT_MUX2_RFSILENT);
205 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2),
206 (ahp->ah_gpio_select & 0x0f) << 4);
207
208 /*
209 * Configure the desired GPIO port for input and
210 * enable baseband rf silence
211 */
212 ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select);
213 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
214 }
215
216 /*
217 * If radio disable switch connection to GPIO bit x is enabled
218 * program GPIO interrupt.
219 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
220 * verified that it is a later version of eeprom, it has a place for
--- 139 unchanged lines hidden (view full) ---
360/*
361 * Set or clear hardware basic rate bit
362 * Set hardware basic rate set if basic rate is found
363 * and basic rate is equal or less than 2Mbps
364 */
365void
366ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs)
367{
368 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
369 u_int32_t reg;
370 u_int8_t xset;
371 int i;
372
373 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) {
374 return;
375 }
376 xset = 0;
377 for (i = 0; i < rs->rs_count; i++) {
378 u_int8_t rset = rs->rs_rates[i];
379 /* Basic rate defined? */
380 if ((rset & 0x80) && (rset &= 0x7f) >= xset) {
381 xset = rset;
--- 136 unchanged lines hidden (view full) ---
518void
519ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna)
520{
521 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
522}
523
524HAL_BOOL
525ar9300_set_antenna_switch(struct ath_hal *ah,
526 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan,
527 u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd)
528{
529 struct ath_hal_9300 *ahp = AH9300(ah);
530
531 /*
532 * Owl does not support diversity or changing antennas.
533 *
534 * Instead this API and function are defined differently for AR9300.
535 * To support Tablet PC's, this interface allows the system
--- 70 unchanged lines hidden (view full) ---
606 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
607 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */
608}
609
610HAL_STATUS
611ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration,
612 u_int32_t next_start, HAL_QUIET_FLAG flag)
613{
614#define TU_TO_USEC(_tu) ((_tu) << 10)
615 HAL_STATUS status = HAL_EIO;
616 u_int32_t tsf = 0, j, next_start_us = 0;
617 if (flag & HAL_QUIET_ENABLE) {
618 for (j = 0; j < 2; j++) {
619 next_start_us = TU_TO_USEC(next_start);
620 tsf = OS_REG_READ(ah, AR_TSF_L32);
621 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) {
622 next_start_us += tsf;
623 }
624 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) {
625 next_start_us +=
626 ah->ah_config.ah_sw_beacon_response_time;
627 }
628 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
629 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR));
630 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period));
631 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us);
632 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
633 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) {
634 status = HAL_OK;
--- 5 unchanged lines hidden (view full) ---
640 HALASSERT(j < 1);
641 }
642 } else {
643 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
644 status = HAL_OK;
645 }
646
647 return status;
648#undef TU_TO_USEC
649}
650#ifdef ATH_SUPPORT_DFS
651void
652ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable)
653{
654 u32 reg1, reg2;
655
656 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE));
--- 46 unchanged lines hidden (view full) ---
703 return HAL_OK;
704 case 1:
705 return (ahp->ah_sta_id1_defaults &
706 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO;
707 default:
708 return HAL_ENOTSUPP;
709 }
710 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
711 switch (capability) {
712 case 0: /* hardware capability */
713 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK;
714 case 1: /* current setting */
715 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
716 HAL_ENXIO : HAL_OK;
717 default:
718 return HAL_ENOTSUPP;
719 }
720 case HAL_CAP_WME_TKIPMIC:
721 /* hardware can do TKIP MIC when WMM is turned on */
722 return HAL_OK;
723 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */
724 return HAL_OK;
725 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */
726 switch (capability) {
727 case 0: /* hardware capability */
--- 4 unchanged lines hidden (view full) ---
732 HAL_OK : HAL_ENXIO;
733 }
734 return HAL_EINVAL;
735 case HAL_CAP_TPC:
736 switch (capability) {
737 case 0: /* hardware capability */
738 return HAL_OK;
739 case 1:
740 return ah->ah_config.ath_hal_desc_tpc ?
741 HAL_OK : HAL_ENXIO;
742 }
743 return HAL_OK;
744 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */
745 return HAL_OK;
746 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
747 switch (capability) {
748 case 0: /* hardware capability */
--- 10 unchanged lines hidden (view full) ---
759 return (ahp->ah_sta_id1_defaults &
760 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO;
761 }
762 }
763 return HAL_EINVAL;
764 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
765 switch (capability) {
766 case 0: /* hardware capability */
767 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
768 case 1:
769 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ?
770 HAL_OK : HAL_ENXIO;
771 }
772 return HAL_EINVAL;
773 case HAL_CAP_RFSILENT: /* rfsilent support */
774 if (capability == 3) { /* rfkill interrupt */
775 /*
--- 17 unchanged lines hidden (view full) ---
793 return HAL_ENOTSUPP;
794 case HAL_CAP_MAC_HANG:
795 /* Track chips that are known to have MAC hangs.
796 */
797 return HAL_OK;
798 case HAL_CAP_RIFS_RX_ENABLED:
799 /* Is RIFS RX currently enabled */
800 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
801#if 0
802 case HAL_CAP_ANT_CFG_2GHZ:
803 *result = p_cap->halNumAntCfg2Ghz;
804 return HAL_OK;
805 case HAL_CAP_ANT_CFG_5GHZ:
806 *result = p_cap->halNumAntCfg5Ghz;
807 return HAL_OK;
808 case HAL_CAP_RX_STBC:
809 *result = p_cap->hal_rx_stbc_support;
810 return HAL_OK;
811 case HAL_CAP_TX_STBC:
812 *result = p_cap->hal_tx_stbc_support;
813 return HAL_OK;
814#endif
815 case HAL_CAP_LDPC:
816 *result = p_cap->halLDPCSupport;
817 return HAL_OK;
818 case HAL_CAP_DYNAMIC_SMPS:
819 return HAL_OK;
820 case HAL_CAP_DS:
821 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
822 (p_cap->halTxChainMask & 0x3) != 0x3 ||
823 (p_cap->halRxChainMask & 0x3) != 0x3) ?
824 HAL_ENOTSUPP : HAL_OK;
825 case HAL_CAP_TS:
826 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
827 (p_cap->halTxChainMask & 0x7) != 0x7 ||
828 (p_cap->halRxChainMask & 0x7) != 0x7) ?
829 HAL_ENOTSUPP : HAL_OK;
830 case HAL_CAP_OL_PWRCTRL:
831 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ?
832 HAL_OK : HAL_ENOTSUPP;
833 case HAL_CAP_CRDC:
834#if ATH_SUPPORT_CRDC
835 return (AR_SREV_WASP(ah) &&
836 ah->ah_config.ath_hal_crdc_enable) ?
837 HAL_OK : HAL_ENOTSUPP;
838#else
839 return HAL_ENOTSUPP;
840#endif
841#if 0
842 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS:
843 *result = (u_int32_t)(-1);
844 return HAL_OK;
845 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS:
846 *result = (u_int32_t)(-1);
847 return HAL_OK;
848#endif
849 case HAL_CAP_BB_PANIC_WATCHDOG:
850 return HAL_OK;
851 case HAL_CAP_PHYRESTART_CLR_WAR:
852 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) &&
853 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10))
854 {
855 return HAL_OK;
856 }
--- 4 unchanged lines hidden (view full) ---
861 case HAL_CAP_ENTERPRISE_MODE:
862 *result = ahp->ah_enterprise_mode >> 16;
863 /*
864 * WAR for EV 77658 - Add delimiters to first sub-frame when using
865 * RTS/CTS with aggregation and non-enterprise Osprey.
866 *
867 * Bug fixed in AR9580/Peacock, Wasp1.1 and later
868 */
869 if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) &&
870 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) ||
871 AR_SREV_WASP_10(ah))) {
872 *result |= AH_ENT_RTSCTS_DELIM_WAR;
873 }
874 return HAL_OK;
875 case HAL_CAP_LDPCWAR:
876 /* WAR for RIFS+LDPC issue is required for all chips currently
877 * supported by ar9300 HAL.
878 */
879 return HAL_OK;
880 case HAL_CAP_ENABLE_APM:
881 *result = p_cap->halApmEnable;
882 return HAL_OK;
883 case HAL_CAP_PCIE_LCR_EXTSYNC_EN:
884 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
885 case HAL_CAP_PCIE_LCR_OFFSET:
886 *result = p_cap->hal_pcie_lcr_offset;
887 return HAL_OK;
888 case HAL_CAP_SMARTANTENNA:
889 /* FIXME A request is pending with h/w team to add feature bit in
--- 30 unchanged lines hidden (view full) ---
920ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
921 u_int32_t capability, u_int32_t setting, HAL_STATUS *status)
922{
923 struct ath_hal_9300 *ahp = AH9300(ah);
924 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
925 u_int32_t v;
926
927 switch (type) {
928 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
929 if (! p_cap->halTkipMicTxRxKeySupport)
930 return AH_FALSE;
931
932 if (setting)
933 ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA;
934 else
935 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
936
937 OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode);
938 return AH_TRUE;
939
940 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
941 if (setting) {
942 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE;
943 } else {
944 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE;
945 }
946 return AH_TRUE;
947 case HAL_CAP_DIVERSITY:
--- 14 unchanged lines hidden (view full) ---
962#ifdef AH_DEBUG
963 AH_PRIVATE(ah)->ah_diagreg = setting;
964#else
965 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */
966#endif
967 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
968 return AH_TRUE;
969 case HAL_CAP_TPC:
970 ah->ah_config.ath_hal_desc_tpc = (setting != 0);
971 return AH_TRUE;
972 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
973 if (setting) {
974 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
975 } else {
976 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
977 }
978 return AH_TRUE;
979 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
980 if (p_cap->halTsfAddSupport) {
981 if (setting) {
982 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF;
983 } else {
984 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF;
985 }
986 return AH_TRUE;
987 }
988 return AH_FALSE;
--- 196 unchanged lines hidden (view full) ---
1185 ar9300_ani_control(
1186 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]);
1187 return AH_TRUE;
1188 case HAL_DIAG_TXCONT:
1189 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/
1190 return AH_TRUE;
1191#endif /* AH_PRIVATE_DIAG */
1192 case HAL_DIAG_CHANNELS:
1193#if 0
1194 *result = &(ahp->ah_priv.ah_channels[0]);
1195 *resultsize =
1196 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan;
1197#endif
1198 return AH_TRUE;
1199#ifdef AH_DEBUG
1200 case HAL_DIAG_PRINT_REG:
1201 ar9300_print_reg(ah, *((const u_int32_t *)args));
1202 return AH_TRUE;
1203#endif
1204 default:
1205 break;
--- 8 unchanged lines hidden (view full) ---
1214#ifdef AH_DEBUG
1215#define NUM_DMA_DEBUG_REGS 8
1216#define NUM_QUEUES 10
1217
1218 u_int32_t val[NUM_DMA_DEBUG_REGS];
1219 int qcu_offset = 0, dcu_offset = 0;
1220 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg;
1221 int i, j, k;
1222 int16_t nfarray[HAL_NUM_NF_READINGS];
1223#ifdef ATH_NF_PER_CHAN
1224 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
1225#endif /* ATH_NF_PER_CHAN */
1226 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan);
1227
1228 /* selecting DMA OBS 8 */
1229 OS_REG_WRITE(ah, AR_MACMISC,
1230 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1231 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1232
1233 ath_hal_printf(ah, "Raw DMA Debug values:\n");
1234 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) {
--- 65 unchanged lines hidden (view full) ---
1300 ath_hal_printf(ah, "5G:\n");
1301 ath_hal_printf(ah, "Min CCA Out:\n");
1302 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n");
1303 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n",
1304 nfarray[0], nfarray[1], nfarray[2]);
1305 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
1306 nfarray[3], nfarray[4], nfarray[5]);
1307
1308 for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
1309 ath_hal_printf(ah, "%s Chain %d NF History:\n",
1310 ((i < 3) ? "Control " : "Extension "), i%3);
1311 for (j = 0, k = h->base.curr_index;
1312 j < HAL_NF_CAL_HIST_LEN_FULL;
1313 j++, k++) {
1314 ath_hal_printf(ah, "Element %d: %d\n",
1315 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]);
1316 }
--- 205 unchanged lines hidden (view full) ---
1522 return good;
1523}
1524
1525/*
1526 * Return approximation of extension channel busy over an time interval
1527 * 0% (clear) -> 100% (busy)
1528 * -1 for invalid estimate
1529 */
1530uint32_t
1531ar9300_get_11n_ext_busy(struct ath_hal *ah)
1532{
1533 /*
1534 * Overflow condition to check before multiplying to get %
1535 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28)
1536 */
1537#define OVERFLOW_LIMIT 0x28F5C28
1538#define ERROR_CODE -1
--- 70 unchanged lines hidden (view full) ---
1609/* BB Panic Watchdog declarations */
1610#define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */
1611#define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */
1612
1613void
1614ar9300_config_bb_panic_watchdog(struct ath_hal *ah)
1615{
1616#define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000
1617 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
1618 u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms;
1619 u_int32_t val, idle_count;
1620
1621 if (idle_tmo_ms != 0) {
1622 /* enable IRQ, disable chip-reset for BB panic */
1623 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1624 AR_PHY_BB_PANIC_CNTL2_MASK;
1625 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2,
1626 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE);
1627 /* bound limit to 10 secs */
1628 if (idle_tmo_ms > 10000) {
1629 idle_tmo_ms = 10000;
1630 }
1631 if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) {
1632 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR;
1633 } else {
1634 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR;
1635 }
1636 /*
1637 * enable panic in non-IDLE mode,
1638 * disable in IDLE mode,
1639 * set idle time-out
--- 12 unchanged lines hidden (view full) ---
1652 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1653 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE));
1654 /* disable panic in non-IDLE mode, disable in IDLE mode */
1655 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1,
1656 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) &
1657 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE));
1658 }
1659
1660 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n",
1661 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms);
1662#undef HAL_BB_PANIC_IDLE_TIME_OUT
1663}
1664
1665
1666void
1667ar9300_handle_bb_panic(struct ath_hal *ah)
1668{
1669 u_int32_t status;
1670 /*
1671 * we want to avoid printing in ISR context so we save
1672 * panic watchdog status to be printed later in DPC context
1673 */
1674 AH9300(ah)->ah_bb_panic_last_status = status =
1675 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS);
1676 /*
1677 * panic watchdog timer should reset on status read
1678 * but to make sure we write 0 to the watchdog status bit
1679 */
1680 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR);
1681}
1682
1683int
1684ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic)
1685{
1686 bb_panic->status = AH9300(ah)->ah_bb_panic_last_status;
1687
1688 /*
1689 * For signature 04000539 do not print anything.
1690 * This is a very common occurence as a compromise between
1691 * BB Panic and AH_FALSE detects (EV71009). It indicates
1692 * radar hang, which can be cleared by reprogramming
1693 * radar related register and does not requre a chip reset
1694 */
--- 21 unchanged lines hidden (view full) ---
1716 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2);
1717 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL);
1718 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0;
1719 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah,
1720 &bb_panic->rxc_pcnt,
1721 &bb_panic->rxf_pcnt,
1722 &bb_panic->txf_pcnt);
1723
1724 if (ah->ah_config.ath_hal_show_bb_panic) {
1725 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, "
1726 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf);
1727 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
1728 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1729 bb_panic->wd, bb_panic->det, bb_panic->rdar,
1730 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm,
1731 bb_panic->t_cck, bb_panic->agc, bb_panic->src);
1732 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
--- 10 unchanged lines hidden (view full) ---
1743
1744 return 0; //The returned data will be stored for athstats to retrieve it
1745}
1746
1747/* set the reason for HAL reset */
1748void
1749ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason)
1750{
1751 AH9300(ah)->ah_reset_reason = resetreason;
1752}
1753
1754/*
1755 * Configure 20/40 operation
1756 *
1757 * 20/40 = joint rx clear (control and extension)
1758 * 20 = rx clear (control)
1759 *
1760 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz
1761 * when changing from 20/40 => 20 only
1762 */
1763void
1764ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode)
1765{
1766 u_int32_t macmode;
1767
1768 /* Configure MAC for 20/40 operation */
1769 if (mode == HAL_HT_MACMODE_2040 &&
1770 !ah->ah_config.ath_hal_cwm_ignore_ext_cca) {
1771 macmode = AR_2040_JOINED_RX_CLEAR;
1772 } else {
1773 macmode = 0;
1774 }
1775 OS_REG_WRITE(ah, AR_2040_MODE, macmode);
1776}
1777
1778/*
--- 102 unchanged lines hidden (view full) ---
1881 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT)
1882 {
1883 /* get the positive value */
1884 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK;
1885 signed_val = AH_TRUE;
1886 }
1887 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT)
1888 {
1889 HALDEBUG(ah, HAL_DEBUG_REGIO,
1890 "%s Correcting ppm out of range %x\n",
1891 __func__, (data_fine & 0x7ff));
1892 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT;
1893 }
1894 /*
1895 * Restore signed value if changed above.
1896 * Use typecast to avoid compilation errors
1897 */
--- 62 unchanged lines hidden (view full) ---
1960 return
1961 OS_REG_READ(ah, AR_PHY_TIMING2) &
1962 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL);
1963}
1964
1965/*
1966 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame
1967 */
1968HAL_BOOL
1969ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs)
1970{
1971 /*
1972 * XXX FreeBSD todo: reimplement this
1973 */
1974#if 0
1975 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
1976 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
1977 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
1978 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT);
1979 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) ==
1980 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE;
1981 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) ==
1982 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE;
1983#endif
1984 return AH_FALSE;
1985}
1986
1987void
1988ar9300_clear_mib_counters(struct ath_hal *ah)
1989{
1990 u_int32_t reg_val;
1991
1992 reg_val = OS_REG_READ(ah, AR_MIBC);
1993 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC);
1994 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC);
1995}
1996
1997
1998/* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */
1999HAL_BOOL
2000ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable)
2001{
2002 struct ath_hal_9300 *ahp = AH9300(ah);
2003 HAL_CHANNEL_INTERNAL *ichan =
2004 ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
2005 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan);
2006 u_int32_t tmp = 0;
2007
2008 if (enable) {
2009 if (ahp->ah_rifs_enabled == AH_TRUE) {
2010 return AH_TRUE;
2011 }
2012
2013 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]);
2014 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
--- 7 unchanged lines hidden (view full) ---
2022 AR_PHY_SEARCH_START_DELAY);
2023 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH);
2024 }
2025 /* Change rifs init delay to 0 */
2026 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
2027 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY)));
2028 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY);
2029 if (is_chan_2g) {
2030 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2031 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500);
2032 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */
2033 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250);
2034 }
2035 } else {
2036 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2037 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370);
2038 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */
2039 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8);
2040 }
2041 }
2042
2043 ahp->ah_rifs_enabled = AH_FALSE;
2044 }
--- 170 unchanged lines hidden (view full) ---
2215} /* end - ar9300_detect_bb_hang () */
2216
2217#undef NUM_STATUS_READS
2218
2219HAL_STATUS
2220ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg)
2221{
2222 struct ath_hal_9300 *ahp = AH9300(ah);
2223 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2224 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2225 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
2226 u_int16_t ant_config;
2227 u_int32_t hal_num_ant_config;
2228
2229 hal_num_ant_config = IS_CHAN_2GHZ(ichan) ?
2230 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz;
2231
2232 if (cfg < hal_num_ant_config) {
2233 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) {
2234 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
2235 return HAL_OK;
2236 }
2237 }
2238
2239 return HAL_EINVAL;
2240}
2241
2242/*
2243 * Functions to get/set DCS mode
2244 */
2245void
2246ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode)
2247{
2248 AH9300(ah)->ah_dcs_enable = mode;
2249}
2250
2251u_int32_t
2252ar9300_get_dcs_mode(struct ath_hal *ah)
2253{
2254 return AH9300(ah)->ah_dcs_enable;
2255}
2256
2257#if ATH_BT_COEX
2258void
2259ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo)
2260{
2261 struct ath_hal_9300 *ahp = AH9300(ah);
2262
2263 ahp->ah_bt_module = btinfo->bt_module;
2264 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config;
2265 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active;
--- 94 unchanged lines hidden (view full) ---
2360 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH);
2361}
2362
2363static void
2364ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value)
2365{
2366 struct ath_hal_9300 *ahp = AH9300(ah);
2367#if ATH_ANT_DIV_COMB
2368 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2369 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2370#endif
2371
2372 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW)
2373 {
2374 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE)
2375 {
2376 /* Config antenna diversity */
2377#if ATH_ANT_DIV_COMB
--- 13 unchanged lines hidden (view full) ---
2391
2392 switch (type) {
2393 case HAL_BT_COEX_SET_ACK_PWR:
2394 if (value) {
2395 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2396 } else {
2397 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2398 }
2399 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2400 ahpriv->ah_extraTxPow, 0);
2401 break;
2402
2403 case HAL_BT_COEX_ANTENNA_DIVERSITY:
2404 if (AR_SREV_POSEIDON(ah)) {
2405 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW;
2406 if (value) {
2407 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE;
2408 }
--- 5 unchanged lines hidden (view full) ---
2414 break;
2415 case HAL_BT_COEX_LOWER_TX_PWR:
2416 if (value) {
2417 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2418 }
2419 else {
2420 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2421 }
2422 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2423 ahpriv->ah_extraTxPow, 0);
2424 break;
2425#if ATH_SUPPORT_MCI
2426 case HAL_BT_COEX_MCI_MAX_TX_PWR:
2427 if ((ah->ah_config.ath_hal_mci_config &
2428 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN)
2429 {
2430 if (value) {
2431 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2432 ahp->ah_mci_concur_tx_en = AH_TRUE;
2433 }
2434 else {
2435 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2436 ahp->ah_mci_concur_tx_en = AH_FALSE;
2437 }
2438 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2439 ahpriv->ah_extraTxPow, 0);
2440 }
2441 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n",
2442 ahp->ah_mci_concur_tx_en);
2443 break;
2444 case HAL_BT_COEX_MCI_FTP_STOMP_RX:
2445 if (value) {
2446 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX;
2447 }
--- 8 unchanged lines hidden (view full) ---
2456}
2457
2458void
2459ar9300_bt_coex_disable(struct ath_hal *ah)
2460{
2461 struct ath_hal_9300 *ahp = AH9300(ah);
2462
2463 /* Always drive rx_clear_external output as 0 */
2464 ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select,
2465 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
2466
2467 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2468 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
2469 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2470 }
2471
2472 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
--- 33 unchanged lines hidden (view full) ---
2506 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2507 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1);
2508 } else {
2509 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2510 }
2511
2512 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
2513 /* For 3-wire, configure the desired GPIO port for rx_clear */
2514 ath_hal_gpioCfgOutput(ah,
2515 ahp->ah_wlan_active_gpio_select,
2516 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE);
2517 }
2518 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
2519 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
2520 {
2521 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */
2522 ath_hal_gpioCfgOutput(ah,
2523 ahp->ah_wlan_active_gpio_select,
2524 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME);
2525 }
2526
2527 /*
2528 * Enable a weak pull down on BT_ACTIVE.
2529 * When BT device is disabled, BT_ACTIVE might be floating.
2530 */
--- 35 unchanged lines hidden (view full) ---
2566 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2567 ahp->ah_bt_active_gpio_select);
2568 OS_REG_RMW_FIELD(ah,
2569 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2570 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
2571 ahp->ah_bt_priority_gpio_select);
2572
2573 /* Configure the desired GPIO ports for input */
2574 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2575 ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select);
2576
2577 if (ahp->ah_bt_coex_enabled) {
2578 ar9300_bt_coex_enable(ah);
2579 } else {
2580 ar9300_bt_coex_disable(ah);
2581 }
2582 }
2583 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
--- 15 unchanged lines hidden (view full) ---
2599 * bt_active_async to GPIO pins
2600 */
2601 OS_REG_RMW_FIELD(ah,
2602 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2603 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2604 ahp->ah_bt_active_gpio_select);
2605
2606 /* Configure the desired GPIO ports for input */
2607 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2608
2609 /* Enable coexistence on initialization */
2610 ar9300_bt_coex_enable(ah);
2611 }
2612 }
2613#if ATH_SUPPORT_MCI
2614 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) {
2615 if (ahp->ah_bt_coex_enabled) {
--- 72 unchanged lines hidden (view full) ---
2688
2689 /* turn on filter pass hold (bit 9) */
2690 OS_REG_WRITE(ah, AR_AZIMUTH_MODE,
2691 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD);
2692
2693 return HAL_OK;
2694}
2695
2696#if 0
2697void ar9300_mat_enable(struct ath_hal *ah, int enable)
2698{
2699 /*
2700 * MAT (s/w ProxySTA) implementation requires to turn off interrupt
2701 * mitigation and turn on key search always for better performance.
2702 */
2703 struct ath_hal_9300 *ahp = AH9300(ah);
2704 struct ath_hal_private *ap = AH_PRIVATE(ah);
--- 12 unchanged lines hidden (view full) ---
2717 #define AH_RIMT_FIRST_MICROSEC 2000
2718 #endif
2719 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC);
2720 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC);
2721 } else {
2722 OS_REG_WRITE(ah, AR_RIMT, 0);
2723 }
2724
2725 ahp->ah_enable_keysearch_always = !!enable;
2726 ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always);
2727}
2728#endif
2729
2730void ar9300_enable_tpc(struct ath_hal *ah)
2731{
2732 u_int32_t val = 0;
2733
2734 ah->ah_config.ath_hal_desc_tpc = 1;
2735
2736 /* Enable TPC */
2737 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1);
2738
2739 /*
2740 * Disable per chain power reduction since we are already
2741 * accounting for this in our calculations
2742 */
--- 29 unchanged lines hidden (view full) ---
2772 u_int32_t temp_powertx_rate9_reg_val;
2773 int8_t olpc_power_offset = 0;
2774 int8_t tmp_olpc_val = 0;
2775 HAL_RSSI_TX_POWER old_greentx_status;
2776 u_int8_t target_power_val_t[ar9300_rate_size];
2777 int8_t tmp_rss1_thr1, tmp_rss1_thr2;
2778
2779 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) ||
2780 !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) {
2781 return;
2782 }
2783
2784 old_greentx_status = AH9300(ah)->green_tx_status;
2785 if (ahp->ah_hw_green_tx_enable) {
2786 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB;
2787 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB;
2788 } else {
2789 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB;
2790 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB;
2791 }
2792
2793 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1)
2794 && (rssi > tmp_rss1_thr1))
2795 {
2796 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) {
2797 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT;
2798 }
2799 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2
2800 && (rssi > tmp_rss1_thr2))
2801 {
2802 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) {
2803 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE;
2804 }
2805 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) {
2806 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) {
2807 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG;
2808 }
2809 }
2810
2811 /* If status is not change, don't do anything */
2812 if (old_greentx_status == AH9300(ah)->green_tx_status) {
2813 return;
2814 }
2815
2816 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */
2817 if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE)
2818 && AR_SREV_POSEIDON(ah))
2819 {
2820 if (ahp->ah_hw_green_tx_enable) {
2821 switch (AH9300(ah)->green_tx_status) {
2822 case HAL_RSSI_TX_POWER_SHORT:
2823 /* 1. TxPower Config */
2824 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short,
2825 sizeof(target_power_val_t));
2826 /* 1.1 Store OLPC Delta Calibration Offset*/
2827 olpc_power_offset = 0;
2828 /* 2. Store OB/DB */
2829 /* 3. Store TPC settting */
--- 26 unchanged lines hidden (view full) ---
2856 /* 1. TxPower Config */
2857 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
2858 sizeof(target_power_val_t));
2859 /* 1.1 Store OLPC Delta Calibration Offset*/
2860 olpc_power_offset = 0;
2861 /* 2. Store OB/DB1/DB2 */
2862 /* 3. Store TPC settting */
2863 temp_tcp_reg_val =
2864 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2865 /* 4. Store BB_powertx_rate9 value */
2866 temp_powertx_rate9_reg_val =
2867 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2868 break;
2869 }
2870 } else {
2871 switch (AH9300(ah)->green_tx_status) {
2872 case HAL_RSSI_TX_POWER_SHORT:
2873 /* 1. TxPower Config */
2874 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short,
2875 sizeof(target_power_val_t));
2876 /* 1.1 Store OLPC Delta Calibration Offset*/
2877 olpc_power_offset =
2878 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] -
2879 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2880 /* 2. Store OB/DB */
2881 temp_obdb_reg_val =
2882 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2883 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
2884 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
2885 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
2886 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
2887 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
2888 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2889 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
2890 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
--- 14 unchanged lines hidden (view full) ---
2905 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle,
2906 sizeof(target_power_val_t));
2907 /* 1.1 Store OLPC Delta Calibration Offset*/
2908 olpc_power_offset =
2909 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] -
2910 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2911 /* 2. Store OB/DB */
2912 temp_obdb_reg_val =
2913 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2914 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
2915 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
2916 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
2917 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
2918 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
2919 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
2920 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
2921 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
--- 15 unchanged lines hidden (view full) ---
2937 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
2938 sizeof(target_power_val_t));
2939 /* 1.1 Store OLPC Delta Calibration Offset*/
2940 olpc_power_offset =
2941 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] -
2942 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2943 /* 2. Store OB/DB1/DB2 */
2944 temp_obdb_reg_val =
2945 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2946 /* 3. Store TPC settting */
2947 temp_tcp_reg_val =
2948 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2949 /* 4. Store BB_powertx_rate9 value */
2950 temp_powertx_rate9_reg_val =
2951 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2952 break;
2953 }
2954 }
2955 /* 1.1 Do OLPC Delta Calibration Offset */
2956 tmp_olpc_val =
2957 (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET];
2958 tmp_olpc_val += olpc_power_offset;
2959 OS_REG_RMW(ah, AR_PHY_TPC_11_B0,
2960 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
2961 AR_PHY_TPC_OLPC_GAIN_DELTA);
2962
2963 /* 1.2 TxPower Config */
2964 ar9300_transmit_power_reg_write(ah, target_power_val_t);
2965 /* 2. Config OB/DB */
2966 if (!ahp->ah_hw_green_tx_enable) {
2967 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val);
2968 }
2969 /* 3. config TPC settting */
2970 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val);
2971 /* 4. config BB_powertx_rate9 value */
2972 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val);
2973 }
2974}
2975
2976#if 0
2977void
2978ar9300_get_vow_stats(
2979 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags)
2980{
2981 if (vow_reg_flags & AR_REG_TX_FRM_CNT) {
2982 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
2983 }
2984 if (vow_reg_flags & AR_REG_RX_FRM_CNT) {
--- 4 unchanged lines hidden (view full) ---
2989 }
2990 if (vow_reg_flags & AR_REG_CYCLE_CNT) {
2991 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT);
2992 }
2993 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) {
2994 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT);
2995 }
2996}
2997#endif
2998
2999/*
3000 * ar9300_is_skip_paprd_by_greentx
3001 *
3002 * This function check if we need to skip PAPRD tuning
3003 * when GreenTx in specific state.
3004 */
3005HAL_BOOL
3006ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah)
3007{
3008 if (AR_SREV_POSEIDON(ah) &&
3009 ah->ah_config.ath_hal_sta_update_tx_pwr_enable &&
3010 ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) ||
3011 (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE)))
3012 {
3013 return AH_TRUE;
3014 }
3015 return AH_FALSE;
3016}
3017
3018void
3019ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah)
--- 83 unchanged lines hidden (view full) ---
3103 u_int32_t key0, key1, key2, key3, key4;
3104 u_int32_t mac_hi, mac_lo;
3105 u_int16_t entry = 0;
3106 u_int32_t valid = 0;
3107 u_int32_t key_type;
3108
3109 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n");
3110
3111 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) {
3112 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry));
3113 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry));
3114 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry));
3115 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry));
3116 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry));
3117
3118 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));
3119
--- 33 unchanged lines hidden (view full) ---
3153 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24,
3154 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 );
3155 }
3156
3157 return AH_TRUE;
3158}
3159
3160/* enable/disable smart antenna mode */
3161HAL_BOOL
3162ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
3163{
3164 struct ath_hal_9300 *ahp = AH9300(ah);
3165
3166 if (enable) {
3167 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3168 } else {
3169 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3170 }
--- 12 unchanged lines hidden (view full) ---
3183 }
3184
3185 ahp->ah_smartantenna_enable = enable;
3186 return 1;
3187}
3188
3189#ifdef ATH_TX99_DIAG
3190#ifndef ATH_SUPPORT_HTC
3191void
3192ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c,
3193 u_int32_t txpower)
3194{
3195#define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s))
3196 static int16_t p_pwr_array[ar9300_rate_size] = { 0 };
3197 int32_t i;
3198
3199 /* The max power is limited to 63 */
--- 556 unchanged lines hidden (view full) ---
3756 return AH_FALSE;
3757}
3758
3759HAL_BOOL
3760ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val)
3761{
3762 return AH_FALSE;
3763}
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "opt_ah.h"
18
19#include "ah.h"
20#include "ah_internal.h"
21#include "ah_devid.h"
22#ifdef AH_DEBUG
23#include "ah_desc.h" /* NB: for HAL_PHYERR* */
24#endif
25
26#include "ar9300/ar9300.h"
--- 25 unchanged lines hidden (view full) ---
52 == HAL_OK)
53 {
54 *hangs |= HAL_PHYRESTART_CLR_WAR;
55 }
56
57 ahp->ah_hang_wars = *hangs;
58}
59
60/*
61 * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about
62 * HT20, HT40, fast-clock, turbo mode, etc.
63 */
64static u_int
65ar9300_mac_to_usec(struct ath_hal *ah, u_int clks)
66{
67#if 0
68 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
69
70 if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
71 return (ath_hal_mac_usec(ah, clks) / 2);
72 } else {
73 return (ath_hal_mac_usec(ah, clks));
74 }
75#endif
76 return (ath_hal_mac_usec(ah, clks));
77}
78
79u_int
80ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs)
81{
82#if 0
83 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
84
85 if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
86 return (ath_hal_mac_clks(ah, usecs) * 2);
87 } else {
88 return (ath_hal_mac_clks(ah, usecs));
89 }
90#endif
91 return (ath_hal_mac_clks(ah, usecs));
92}
93
94void
95ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac)
96{
97 struct ath_hal_9300 *ahp = AH9300(ah);
98
99 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
--- 35 unchanged lines hidden (view full) ---
135 * A_HARDWARE for an unwritable EEPROM or bad EEPROM version
136 */
137HAL_BOOL
138ar9300_set_regulatory_domain(struct ath_hal *ah,
139 u_int16_t reg_domain, HAL_STATUS *status)
140{
141 HAL_STATUS ecode;
142
143 if (AH_PRIVATE(ah)->ah_currentRD == 0) {
144 AH_PRIVATE(ah)->ah_currentRD = reg_domain;
145 return AH_TRUE;
146 }
147 ecode = HAL_EIO;
148
149#if 0
150bad:
151#endif
152 if (status) {
153 *status = ecode;
154 }
155 return AH_FALSE;
156}
157
158/*
159 * Return the wireless modes (a,b,g,t) supported by hardware.
160 *
161 * This value is what is actually supported by the hardware
162 * and is unaffected by regulatory/country code settings.
163 *
164 */
165u_int
166ar9300_get_wireless_modes(struct ath_hal *ah)
167{
168 return AH_PRIVATE(ah)->ah_caps.halWirelessModes;
169}
170
171/*
172 * Set the interrupt and GPIO values so the ISR can disable RF
173 * on a switch signal. Assumes GPIO port and interrupt polarity
174 * are set prior to call.
175 */
176void
--- 27 unchanged lines hidden (view full) ---
204 AR_GPIO_INPUT_MUX2_RFSILENT);
205 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2),
206 (ahp->ah_gpio_select & 0x0f) << 4);
207
208 /*
209 * Configure the desired GPIO port for input and
210 * enable baseband rf silence
211 */
212 ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select);
213 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
214 }
215
216 /*
217 * If radio disable switch connection to GPIO bit x is enabled
218 * program GPIO interrupt.
219 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
220 * verified that it is a later version of eeprom, it has a place for
--- 139 unchanged lines hidden (view full) ---
360/*
361 * Set or clear hardware basic rate bit
362 * Set hardware basic rate set if basic rate is found
363 * and basic rate is equal or less than 2Mbps
364 */
365void
366ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs)
367{
368 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
369 u_int32_t reg;
370 u_int8_t xset;
371 int i;
372
373 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) {
374 return;
375 }
376 xset = 0;
377 for (i = 0; i < rs->rs_count; i++) {
378 u_int8_t rset = rs->rs_rates[i];
379 /* Basic rate defined? */
380 if ((rset & 0x80) && (rset &= 0x7f) >= xset) {
381 xset = rset;
--- 136 unchanged lines hidden (view full) ---
518void
519ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna)
520{
521 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
522}
523
524HAL_BOOL
525ar9300_set_antenna_switch(struct ath_hal *ah,
526 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan,
527 u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd)
528{
529 struct ath_hal_9300 *ahp = AH9300(ah);
530
531 /*
532 * Owl does not support diversity or changing antennas.
533 *
534 * Instead this API and function are defined differently for AR9300.
535 * To support Tablet PC's, this interface allows the system
--- 70 unchanged lines hidden (view full) ---
606 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
607 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */
608}
609
610HAL_STATUS
611ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration,
612 u_int32_t next_start, HAL_QUIET_FLAG flag)
613{
614#define TU_TO_USEC(_tu) ((_tu) << 10)
615 HAL_STATUS status = HAL_EIO;
616 u_int32_t tsf = 0, j, next_start_us = 0;
617 if (flag & HAL_QUIET_ENABLE) {
618 for (j = 0; j < 2; j++) {
619 next_start_us = TU_TO_USEC(next_start);
620 tsf = OS_REG_READ(ah, AR_TSF_L32);
621 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) {
622 next_start_us += tsf;
623 }
624 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) {
625 next_start_us +=
626 ah->ah_config.ah_sw_beacon_response_time;
627 }
628 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
629 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR));
630 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period));
631 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us);
632 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
633 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) {
634 status = HAL_OK;
--- 5 unchanged lines hidden (view full) ---
640 HALASSERT(j < 1);
641 }
642 } else {
643 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
644 status = HAL_OK;
645 }
646
647 return status;
648#undef TU_TO_USEC
649}
650#ifdef ATH_SUPPORT_DFS
651void
652ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable)
653{
654 u32 reg1, reg2;
655
656 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE));
--- 46 unchanged lines hidden (view full) ---
703 return HAL_OK;
704 case 1:
705 return (ahp->ah_sta_id1_defaults &
706 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO;
707 default:
708 return HAL_ENOTSUPP;
709 }
710 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
711 switch (capability) {
712 case 0: /* hardware capability */
713 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK;
714 case 1: /* current setting */
715 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
716 HAL_ENXIO : HAL_OK;
717 default:
718 return HAL_ENOTSUPP;
719 }
720 case HAL_CAP_WME_TKIPMIC:
721 /* hardware can do TKIP MIC when WMM is turned on */
722 return HAL_OK;
723 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */
724 return HAL_OK;
725 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */
726 switch (capability) {
727 case 0: /* hardware capability */
--- 4 unchanged lines hidden (view full) ---
732 HAL_OK : HAL_ENXIO;
733 }
734 return HAL_EINVAL;
735 case HAL_CAP_TPC:
736 switch (capability) {
737 case 0: /* hardware capability */
738 return HAL_OK;
739 case 1:
740 return ah->ah_config.ath_hal_desc_tpc ?
741 HAL_OK : HAL_ENXIO;
742 }
743 return HAL_OK;
744 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */
745 return HAL_OK;
746 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
747 switch (capability) {
748 case 0: /* hardware capability */
--- 10 unchanged lines hidden (view full) ---
759 return (ahp->ah_sta_id1_defaults &
760 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO;
761 }
762 }
763 return HAL_EINVAL;
764 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
765 switch (capability) {
766 case 0: /* hardware capability */
767 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
768 case 1:
769 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ?
770 HAL_OK : HAL_ENXIO;
771 }
772 return HAL_EINVAL;
773 case HAL_CAP_RFSILENT: /* rfsilent support */
774 if (capability == 3) { /* rfkill interrupt */
775 /*
--- 17 unchanged lines hidden (view full) ---
793 return HAL_ENOTSUPP;
794 case HAL_CAP_MAC_HANG:
795 /* Track chips that are known to have MAC hangs.
796 */
797 return HAL_OK;
798 case HAL_CAP_RIFS_RX_ENABLED:
799 /* Is RIFS RX currently enabled */
800 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
801#if 0
802 case HAL_CAP_ANT_CFG_2GHZ:
803 *result = p_cap->halNumAntCfg2Ghz;
804 return HAL_OK;
805 case HAL_CAP_ANT_CFG_5GHZ:
806 *result = p_cap->halNumAntCfg5Ghz;
807 return HAL_OK;
808 case HAL_CAP_RX_STBC:
809 *result = p_cap->hal_rx_stbc_support;
810 return HAL_OK;
811 case HAL_CAP_TX_STBC:
812 *result = p_cap->hal_tx_stbc_support;
813 return HAL_OK;
814#endif
815 case HAL_CAP_LDPC:
816 *result = p_cap->halLDPCSupport;
817 return HAL_OK;
818 case HAL_CAP_DYNAMIC_SMPS:
819 return HAL_OK;
820 case HAL_CAP_DS:
821 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
822 (p_cap->halTxChainMask & 0x3) != 0x3 ||
823 (p_cap->halRxChainMask & 0x3) != 0x3) ?
824 HAL_ENOTSUPP : HAL_OK;
825 case HAL_CAP_TS:
826 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
827 (p_cap->halTxChainMask & 0x7) != 0x7 ||
828 (p_cap->halRxChainMask & 0x7) != 0x7) ?
829 HAL_ENOTSUPP : HAL_OK;
830 case HAL_CAP_OL_PWRCTRL:
831 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ?
832 HAL_OK : HAL_ENOTSUPP;
833 case HAL_CAP_CRDC:
834#if ATH_SUPPORT_CRDC
835 return (AR_SREV_WASP(ah) &&
836 ah->ah_config.ath_hal_crdc_enable) ?
837 HAL_OK : HAL_ENOTSUPP;
838#else
839 return HAL_ENOTSUPP;
840#endif
841#if 0
842 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS:
843 *result = (u_int32_t)(-1);
844 return HAL_OK;
845 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS:
846 *result = (u_int32_t)(-1);
847 return HAL_OK;
848#endif
849 case HAL_CAP_BB_PANIC_WATCHDOG:
850 return HAL_OK;
851 case HAL_CAP_PHYRESTART_CLR_WAR:
852 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) &&
853 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10))
854 {
855 return HAL_OK;
856 }
--- 4 unchanged lines hidden (view full) ---
861 case HAL_CAP_ENTERPRISE_MODE:
862 *result = ahp->ah_enterprise_mode >> 16;
863 /*
864 * WAR for EV 77658 - Add delimiters to first sub-frame when using
865 * RTS/CTS with aggregation and non-enterprise Osprey.
866 *
867 * Bug fixed in AR9580/Peacock, Wasp1.1 and later
868 */
869 if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) &&
870 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) ||
871 AR_SREV_WASP_10(ah))) {
872 *result |= AH_ENT_RTSCTS_DELIM_WAR;
873 }
874 return HAL_OK;
875 case HAL_CAP_LDPCWAR:
876 /* WAR for RIFS+LDPC issue is required for all chips currently
877 * supported by ar9300 HAL.
878 */
879 return HAL_OK;
880 case HAL_CAP_ENABLE_APM:
881 *result = p_cap->halApmEnable;
882 return HAL_OK;
883 case HAL_CAP_PCIE_LCR_EXTSYNC_EN:
884 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
885 case HAL_CAP_PCIE_LCR_OFFSET:
886 *result = p_cap->hal_pcie_lcr_offset;
887 return HAL_OK;
888 case HAL_CAP_SMARTANTENNA:
889 /* FIXME A request is pending with h/w team to add feature bit in
--- 30 unchanged lines hidden (view full) ---
920ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
921 u_int32_t capability, u_int32_t setting, HAL_STATUS *status)
922{
923 struct ath_hal_9300 *ahp = AH9300(ah);
924 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
925 u_int32_t v;
926
927 switch (type) {
928 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
929 if (! p_cap->halTkipMicTxRxKeySupport)
930 return AH_FALSE;
931
932 if (setting)
933 ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA;
934 else
935 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
936
937 OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode);
938 return AH_TRUE;
939
940 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
941 if (setting) {
942 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE;
943 } else {
944 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE;
945 }
946 return AH_TRUE;
947 case HAL_CAP_DIVERSITY:
--- 14 unchanged lines hidden (view full) ---
962#ifdef AH_DEBUG
963 AH_PRIVATE(ah)->ah_diagreg = setting;
964#else
965 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */
966#endif
967 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
968 return AH_TRUE;
969 case HAL_CAP_TPC:
970 ah->ah_config.ath_hal_desc_tpc = (setting != 0);
971 return AH_TRUE;
972 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
973 if (setting) {
974 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
975 } else {
976 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
977 }
978 return AH_TRUE;
979 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
980 if (p_cap->halTsfAddSupport) {
981 if (setting) {
982 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF;
983 } else {
984 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF;
985 }
986 return AH_TRUE;
987 }
988 return AH_FALSE;
--- 196 unchanged lines hidden (view full) ---
1185 ar9300_ani_control(
1186 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]);
1187 return AH_TRUE;
1188 case HAL_DIAG_TXCONT:
1189 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/
1190 return AH_TRUE;
1191#endif /* AH_PRIVATE_DIAG */
1192 case HAL_DIAG_CHANNELS:
1193#if 0
1194 *result = &(ahp->ah_priv.ah_channels[0]);
1195 *resultsize =
1196 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan;
1197#endif
1198 return AH_TRUE;
1199#ifdef AH_DEBUG
1200 case HAL_DIAG_PRINT_REG:
1201 ar9300_print_reg(ah, *((const u_int32_t *)args));
1202 return AH_TRUE;
1203#endif
1204 default:
1205 break;
--- 8 unchanged lines hidden (view full) ---
1214#ifdef AH_DEBUG
1215#define NUM_DMA_DEBUG_REGS 8
1216#define NUM_QUEUES 10
1217
1218 u_int32_t val[NUM_DMA_DEBUG_REGS];
1219 int qcu_offset = 0, dcu_offset = 0;
1220 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg;
1221 int i, j, k;
1222 int16_t nfarray[HAL_NUM_NF_READINGS];
1223#ifdef ATH_NF_PER_CHAN
1224 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
1225#endif /* ATH_NF_PER_CHAN */
1226 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan);
1227
1228 /* selecting DMA OBS 8 */
1229 OS_REG_WRITE(ah, AR_MACMISC,
1230 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1231 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1232
1233 ath_hal_printf(ah, "Raw DMA Debug values:\n");
1234 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) {
--- 65 unchanged lines hidden (view full) ---
1300 ath_hal_printf(ah, "5G:\n");
1301 ath_hal_printf(ah, "Min CCA Out:\n");
1302 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n");
1303 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n",
1304 nfarray[0], nfarray[1], nfarray[2]);
1305 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
1306 nfarray[3], nfarray[4], nfarray[5]);
1307
1308 for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
1309 ath_hal_printf(ah, "%s Chain %d NF History:\n",
1310 ((i < 3) ? "Control " : "Extension "), i%3);
1311 for (j = 0, k = h->base.curr_index;
1312 j < HAL_NF_CAL_HIST_LEN_FULL;
1313 j++, k++) {
1314 ath_hal_printf(ah, "Element %d: %d\n",
1315 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]);
1316 }
--- 205 unchanged lines hidden (view full) ---
1522 return good;
1523}
1524
1525/*
1526 * Return approximation of extension channel busy over an time interval
1527 * 0% (clear) -> 100% (busy)
1528 * -1 for invalid estimate
1529 */
1530uint32_t
1531ar9300_get_11n_ext_busy(struct ath_hal *ah)
1532{
1533 /*
1534 * Overflow condition to check before multiplying to get %
1535 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28)
1536 */
1537#define OVERFLOW_LIMIT 0x28F5C28
1538#define ERROR_CODE -1
--- 70 unchanged lines hidden (view full) ---
1609/* BB Panic Watchdog declarations */
1610#define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */
1611#define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */
1612
1613void
1614ar9300_config_bb_panic_watchdog(struct ath_hal *ah)
1615{
1616#define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000
1617 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
1618 u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms;
1619 u_int32_t val, idle_count;
1620
1621 if (idle_tmo_ms != 0) {
1622 /* enable IRQ, disable chip-reset for BB panic */
1623 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1624 AR_PHY_BB_PANIC_CNTL2_MASK;
1625 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2,
1626 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE);
1627 /* bound limit to 10 secs */
1628 if (idle_tmo_ms > 10000) {
1629 idle_tmo_ms = 10000;
1630 }
1631 if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) {
1632 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR;
1633 } else {
1634 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR;
1635 }
1636 /*
1637 * enable panic in non-IDLE mode,
1638 * disable in IDLE mode,
1639 * set idle time-out
--- 12 unchanged lines hidden (view full) ---
1652 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1653 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE));
1654 /* disable panic in non-IDLE mode, disable in IDLE mode */
1655 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1,
1656 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) &
1657 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE));
1658 }
1659
1660 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n",
1661 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms);
1662#undef HAL_BB_PANIC_IDLE_TIME_OUT
1663}
1664
1665
1666void
1667ar9300_handle_bb_panic(struct ath_hal *ah)
1668{
1669 u_int32_t status;
1670 /*
1671 * we want to avoid printing in ISR context so we save
1672 * panic watchdog status to be printed later in DPC context
1673 */
1674 AH9300(ah)->ah_bb_panic_last_status = status =
1675 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS);
1676 /*
1677 * panic watchdog timer should reset on status read
1678 * but to make sure we write 0 to the watchdog status bit
1679 */
1680 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR);
1681}
1682
1683int
1684ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic)
1685{
1686 bb_panic->status = AH9300(ah)->ah_bb_panic_last_status;
1687
1688 /*
1689 * For signature 04000539 do not print anything.
1690 * This is a very common occurence as a compromise between
1691 * BB Panic and AH_FALSE detects (EV71009). It indicates
1692 * radar hang, which can be cleared by reprogramming
1693 * radar related register and does not requre a chip reset
1694 */
--- 21 unchanged lines hidden (view full) ---
1716 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2);
1717 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL);
1718 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0;
1719 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah,
1720 &bb_panic->rxc_pcnt,
1721 &bb_panic->rxf_pcnt,
1722 &bb_panic->txf_pcnt);
1723
1724 if (ah->ah_config.ath_hal_show_bb_panic) {
1725 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, "
1726 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf);
1727 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
1728 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1729 bb_panic->wd, bb_panic->det, bb_panic->rdar,
1730 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm,
1731 bb_panic->t_cck, bb_panic->agc, bb_panic->src);
1732 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
--- 10 unchanged lines hidden (view full) ---
1743
1744 return 0; //The returned data will be stored for athstats to retrieve it
1745}
1746
1747/* set the reason for HAL reset */
1748void
1749ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason)
1750{
1751 AH9300(ah)->ah_reset_reason = resetreason;
1752}
1753
1754/*
1755 * Configure 20/40 operation
1756 *
1757 * 20/40 = joint rx clear (control and extension)
1758 * 20 = rx clear (control)
1759 *
1760 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz
1761 * when changing from 20/40 => 20 only
1762 */
1763void
1764ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode)
1765{
1766 u_int32_t macmode;
1767
1768 /* Configure MAC for 20/40 operation */
1769 if (mode == HAL_HT_MACMODE_2040 &&
1770 !ah->ah_config.ath_hal_cwm_ignore_ext_cca) {
1771 macmode = AR_2040_JOINED_RX_CLEAR;
1772 } else {
1773 macmode = 0;
1774 }
1775 OS_REG_WRITE(ah, AR_2040_MODE, macmode);
1776}
1777
1778/*
--- 102 unchanged lines hidden (view full) ---
1881 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT)
1882 {
1883 /* get the positive value */
1884 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK;
1885 signed_val = AH_TRUE;
1886 }
1887 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT)
1888 {
1889 HALDEBUG(ah, HAL_DEBUG_REGIO,
1890 "%s Correcting ppm out of range %x\n",
1891 __func__, (data_fine & 0x7ff));
1892 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT;
1893 }
1894 /*
1895 * Restore signed value if changed above.
1896 * Use typecast to avoid compilation errors
1897 */
--- 62 unchanged lines hidden (view full) ---
1960 return
1961 OS_REG_READ(ah, AR_PHY_TIMING2) &
1962 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL);
1963}
1964
1965/*
1966 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame
1967 */
1968HAL_BOOL
1969ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs)
1970{
1971 /*
1972 * XXX FreeBSD todo: reimplement this
1973 */
1974#if 0
1975 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
1976 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
1977 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
1978 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT);
1979 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) ==
1980 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE;
1981 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) ==
1982 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE;
1983#endif
1984 return AH_FALSE;
1985}
1986
1987void
1988ar9300_clear_mib_counters(struct ath_hal *ah)
1989{
1990 u_int32_t reg_val;
1991
1992 reg_val = OS_REG_READ(ah, AR_MIBC);
1993 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC);
1994 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC);
1995}
1996
1997
1998/* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */
1999HAL_BOOL
2000ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable)
2001{
2002 struct ath_hal_9300 *ahp = AH9300(ah);
2003 HAL_CHANNEL_INTERNAL *ichan =
2004 ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
2005 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan);
2006 u_int32_t tmp = 0;
2007
2008 if (enable) {
2009 if (ahp->ah_rifs_enabled == AH_TRUE) {
2010 return AH_TRUE;
2011 }
2012
2013 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]);
2014 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
--- 7 unchanged lines hidden (view full) ---
2022 AR_PHY_SEARCH_START_DELAY);
2023 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH);
2024 }
2025 /* Change rifs init delay to 0 */
2026 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
2027 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY)));
2028 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY);
2029 if (is_chan_2g) {
2030 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2031 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500);
2032 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */
2033 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250);
2034 }
2035 } else {
2036 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2037 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370);
2038 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */
2039 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8);
2040 }
2041 }
2042
2043 ahp->ah_rifs_enabled = AH_FALSE;
2044 }
--- 170 unchanged lines hidden (view full) ---
2215} /* end - ar9300_detect_bb_hang () */
2216
2217#undef NUM_STATUS_READS
2218
2219HAL_STATUS
2220ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg)
2221{
2222 struct ath_hal_9300 *ahp = AH9300(ah);
2223 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2224 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2225 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
2226 u_int16_t ant_config;
2227 u_int32_t hal_num_ant_config;
2228
2229 hal_num_ant_config = IS_CHAN_2GHZ(ichan) ?
2230 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz;
2231
2232 if (cfg < hal_num_ant_config) {
2233 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) {
2234 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
2235 return HAL_OK;
2236 }
2237 }
2238
2239 return HAL_EINVAL;
2240}
2241
2242/*
2243 * Functions to get/set DCS mode
2244 */
2245void
2246ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode)
2247{
2248 AH9300(ah)->ah_dcs_enable = mode;
2249}
2250
2251u_int32_t
2252ar9300_get_dcs_mode(struct ath_hal *ah)
2253{
2254 return AH9300(ah)->ah_dcs_enable;
2255}
2256
2257#if ATH_BT_COEX
2258void
2259ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo)
2260{
2261 struct ath_hal_9300 *ahp = AH9300(ah);
2262
2263 ahp->ah_bt_module = btinfo->bt_module;
2264 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config;
2265 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active;
--- 94 unchanged lines hidden (view full) ---
2360 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH);
2361}
2362
2363static void
2364ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value)
2365{
2366 struct ath_hal_9300 *ahp = AH9300(ah);
2367#if ATH_ANT_DIV_COMB
2368 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2369 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2370#endif
2371
2372 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW)
2373 {
2374 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE)
2375 {
2376 /* Config antenna diversity */
2377#if ATH_ANT_DIV_COMB
--- 13 unchanged lines hidden (view full) ---
2391
2392 switch (type) {
2393 case HAL_BT_COEX_SET_ACK_PWR:
2394 if (value) {
2395 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2396 } else {
2397 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2398 }
2399 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2400 ahpriv->ah_extraTxPow, 0);
2401 break;
2402
2403 case HAL_BT_COEX_ANTENNA_DIVERSITY:
2404 if (AR_SREV_POSEIDON(ah)) {
2405 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW;
2406 if (value) {
2407 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE;
2408 }
--- 5 unchanged lines hidden (view full) ---
2414 break;
2415 case HAL_BT_COEX_LOWER_TX_PWR:
2416 if (value) {
2417 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2418 }
2419 else {
2420 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2421 }
2422 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2423 ahpriv->ah_extraTxPow, 0);
2424 break;
2425#if ATH_SUPPORT_MCI
2426 case HAL_BT_COEX_MCI_MAX_TX_PWR:
2427 if ((ah->ah_config.ath_hal_mci_config &
2428 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN)
2429 {
2430 if (value) {
2431 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2432 ahp->ah_mci_concur_tx_en = AH_TRUE;
2433 }
2434 else {
2435 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2436 ahp->ah_mci_concur_tx_en = AH_FALSE;
2437 }
2438 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2439 ahpriv->ah_extraTxPow, 0);
2440 }
2441 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n",
2442 ahp->ah_mci_concur_tx_en);
2443 break;
2444 case HAL_BT_COEX_MCI_FTP_STOMP_RX:
2445 if (value) {
2446 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX;
2447 }
--- 8 unchanged lines hidden (view full) ---
2456}
2457
2458void
2459ar9300_bt_coex_disable(struct ath_hal *ah)
2460{
2461 struct ath_hal_9300 *ahp = AH9300(ah);
2462
2463 /* Always drive rx_clear_external output as 0 */
2464 ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select,
2465 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
2466
2467 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2468 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
2469 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2470 }
2471
2472 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
--- 33 unchanged lines hidden (view full) ---
2506 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2507 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1);
2508 } else {
2509 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2510 }
2511
2512 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
2513 /* For 3-wire, configure the desired GPIO port for rx_clear */
2514 ath_hal_gpioCfgOutput(ah,
2515 ahp->ah_wlan_active_gpio_select,
2516 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE);
2517 }
2518 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
2519 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
2520 {
2521 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */
2522 ath_hal_gpioCfgOutput(ah,
2523 ahp->ah_wlan_active_gpio_select,
2524 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME);
2525 }
2526
2527 /*
2528 * Enable a weak pull down on BT_ACTIVE.
2529 * When BT device is disabled, BT_ACTIVE might be floating.
2530 */
--- 35 unchanged lines hidden (view full) ---
2566 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2567 ahp->ah_bt_active_gpio_select);
2568 OS_REG_RMW_FIELD(ah,
2569 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2570 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
2571 ahp->ah_bt_priority_gpio_select);
2572
2573 /* Configure the desired GPIO ports for input */
2574 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2575 ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select);
2576
2577 if (ahp->ah_bt_coex_enabled) {
2578 ar9300_bt_coex_enable(ah);
2579 } else {
2580 ar9300_bt_coex_disable(ah);
2581 }
2582 }
2583 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
--- 15 unchanged lines hidden (view full) ---
2599 * bt_active_async to GPIO pins
2600 */
2601 OS_REG_RMW_FIELD(ah,
2602 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2603 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2604 ahp->ah_bt_active_gpio_select);
2605
2606 /* Configure the desired GPIO ports for input */
2607 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2608
2609 /* Enable coexistence on initialization */
2610 ar9300_bt_coex_enable(ah);
2611 }
2612 }
2613#if ATH_SUPPORT_MCI
2614 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) {
2615 if (ahp->ah_bt_coex_enabled) {
--- 72 unchanged lines hidden (view full) ---
2688
2689 /* turn on filter pass hold (bit 9) */
2690 OS_REG_WRITE(ah, AR_AZIMUTH_MODE,
2691 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD);
2692
2693 return HAL_OK;
2694}
2695
2696#if 0
2697void ar9300_mat_enable(struct ath_hal *ah, int enable)
2698{
2699 /*
2700 * MAT (s/w ProxySTA) implementation requires to turn off interrupt
2701 * mitigation and turn on key search always for better performance.
2702 */
2703 struct ath_hal_9300 *ahp = AH9300(ah);
2704 struct ath_hal_private *ap = AH_PRIVATE(ah);
--- 12 unchanged lines hidden (view full) ---
2717 #define AH_RIMT_FIRST_MICROSEC 2000
2718 #endif
2719 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC);
2720 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC);
2721 } else {
2722 OS_REG_WRITE(ah, AR_RIMT, 0);
2723 }
2724
2725 ahp->ah_enable_keysearch_always = !!enable;
2726 ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always);
2727}
2728#endif
2729
2730void ar9300_enable_tpc(struct ath_hal *ah)
2731{
2732 u_int32_t val = 0;
2733
2734 ah->ah_config.ath_hal_desc_tpc = 1;
2735
2736 /* Enable TPC */
2737 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1);
2738
2739 /*
2740 * Disable per chain power reduction since we are already
2741 * accounting for this in our calculations
2742 */
--- 29 unchanged lines hidden (view full) ---
2772 u_int32_t temp_powertx_rate9_reg_val;
2773 int8_t olpc_power_offset = 0;
2774 int8_t tmp_olpc_val = 0;
2775 HAL_RSSI_TX_POWER old_greentx_status;
2776 u_int8_t target_power_val_t[ar9300_rate_size];
2777 int8_t tmp_rss1_thr1, tmp_rss1_thr2;
2778
2779 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) ||
2780 !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) {
2781 return;
2782 }
2783
2784 old_greentx_status = AH9300(ah)->green_tx_status;
2785 if (ahp->ah_hw_green_tx_enable) {
2786 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB;
2787 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB;
2788 } else {
2789 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB;
2790 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB;
2791 }
2792
2793 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1)
2794 && (rssi > tmp_rss1_thr1))
2795 {
2796 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) {
2797 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT;
2798 }
2799 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2
2800 && (rssi > tmp_rss1_thr2))
2801 {
2802 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) {
2803 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE;
2804 }
2805 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) {
2806 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) {
2807 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG;
2808 }
2809 }
2810
2811 /* If status is not change, don't do anything */
2812 if (old_greentx_status == AH9300(ah)->green_tx_status) {
2813 return;
2814 }
2815
2816 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */
2817 if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE)
2818 && AR_SREV_POSEIDON(ah))
2819 {
2820 if (ahp->ah_hw_green_tx_enable) {
2821 switch (AH9300(ah)->green_tx_status) {
2822 case HAL_RSSI_TX_POWER_SHORT:
2823 /* 1. TxPower Config */
2824 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short,
2825 sizeof(target_power_val_t));
2826 /* 1.1 Store OLPC Delta Calibration Offset*/
2827 olpc_power_offset = 0;
2828 /* 2. Store OB/DB */
2829 /* 3. Store TPC settting */
--- 26 unchanged lines hidden (view full) ---
2856 /* 1. TxPower Config */
2857 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
2858 sizeof(target_power_val_t));
2859 /* 1.1 Store OLPC Delta Calibration Offset*/
2860 olpc_power_offset = 0;
2861 /* 2. Store OB/DB1/DB2 */
2862 /* 3. Store TPC settting */
2863 temp_tcp_reg_val =
2864 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2865 /* 4. Store BB_powertx_rate9 value */
2866 temp_powertx_rate9_reg_val =
2867 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2868 break;
2869 }
2870 } else {
2871 switch (AH9300(ah)->green_tx_status) {
2872 case HAL_RSSI_TX_POWER_SHORT:
2873 /* 1. TxPower Config */
2874 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short,
2875 sizeof(target_power_val_t));
2876 /* 1.1 Store OLPC Delta Calibration Offset*/
2877 olpc_power_offset =
2878 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] -
2879 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2880 /* 2. Store OB/DB */
2881 temp_obdb_reg_val =
2882 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2883 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
2884 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
2885 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
2886 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
2887 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
2888 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2889 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
2890 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
--- 14 unchanged lines hidden (view full) ---
2905 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle,
2906 sizeof(target_power_val_t));
2907 /* 1.1 Store OLPC Delta Calibration Offset*/
2908 olpc_power_offset =
2909 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] -
2910 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2911 /* 2. Store OB/DB */
2912 temp_obdb_reg_val =
2913 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2914 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
2915 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
2916 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
2917 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
2918 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
2919 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
2920 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
2921 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
--- 15 unchanged lines hidden (view full) ---
2937 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
2938 sizeof(target_power_val_t));
2939 /* 1.1 Store OLPC Delta Calibration Offset*/
2940 olpc_power_offset =
2941 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] -
2942 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2943 /* 2. Store OB/DB1/DB2 */
2944 temp_obdb_reg_val =
2945 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2946 /* 3. Store TPC settting */
2947 temp_tcp_reg_val =
2948 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2949 /* 4. Store BB_powertx_rate9 value */
2950 temp_powertx_rate9_reg_val =
2951 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2952 break;
2953 }
2954 }
2955 /* 1.1 Do OLPC Delta Calibration Offset */
2956 tmp_olpc_val =
2957 (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET];
2958 tmp_olpc_val += olpc_power_offset;
2959 OS_REG_RMW(ah, AR_PHY_TPC_11_B0,
2960 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
2961 AR_PHY_TPC_OLPC_GAIN_DELTA);
2962
2963 /* 1.2 TxPower Config */
2964 ar9300_transmit_power_reg_write(ah, target_power_val_t);
2965 /* 2. Config OB/DB */
2966 if (!ahp->ah_hw_green_tx_enable) {
2967 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val);
2968 }
2969 /* 3. config TPC settting */
2970 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val);
2971 /* 4. config BB_powertx_rate9 value */
2972 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val);
2973 }
2974}
2975
2976#if 0
2977void
2978ar9300_get_vow_stats(
2979 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags)
2980{
2981 if (vow_reg_flags & AR_REG_TX_FRM_CNT) {
2982 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
2983 }
2984 if (vow_reg_flags & AR_REG_RX_FRM_CNT) {
--- 4 unchanged lines hidden (view full) ---
2989 }
2990 if (vow_reg_flags & AR_REG_CYCLE_CNT) {
2991 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT);
2992 }
2993 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) {
2994 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT);
2995 }
2996}
2997#endif
2998
2999/*
3000 * ar9300_is_skip_paprd_by_greentx
3001 *
3002 * This function check if we need to skip PAPRD tuning
3003 * when GreenTx in specific state.
3004 */
3005HAL_BOOL
3006ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah)
3007{
3008 if (AR_SREV_POSEIDON(ah) &&
3009 ah->ah_config.ath_hal_sta_update_tx_pwr_enable &&
3010 ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) ||
3011 (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE)))
3012 {
3013 return AH_TRUE;
3014 }
3015 return AH_FALSE;
3016}
3017
3018void
3019ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah)
--- 83 unchanged lines hidden (view full) ---
3103 u_int32_t key0, key1, key2, key3, key4;
3104 u_int32_t mac_hi, mac_lo;
3105 u_int16_t entry = 0;
3106 u_int32_t valid = 0;
3107 u_int32_t key_type;
3108
3109 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n");
3110
3111 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) {
3112 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry));
3113 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry));
3114 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry));
3115 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry));
3116 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry));
3117
3118 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));
3119
--- 33 unchanged lines hidden (view full) ---
3153 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24,
3154 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 );
3155 }
3156
3157 return AH_TRUE;
3158}
3159
3160/* enable/disable smart antenna mode */
3161HAL_BOOL
3162ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
3163{
3164 struct ath_hal_9300 *ahp = AH9300(ah);
3165
3166 if (enable) {
3167 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3168 } else {
3169 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3170 }
--- 12 unchanged lines hidden (view full) ---
3183 }
3184
3185 ahp->ah_smartantenna_enable = enable;
3186 return 1;
3187}
3188
3189#ifdef ATH_TX99_DIAG
3190#ifndef ATH_SUPPORT_HTC
3191void
3192ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c,
3193 u_int32_t txpower)
3194{
3195#define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s))
3196 static int16_t p_pwr_array[ar9300_rate_size] = { 0 };
3197 int32_t i;
3198
3199 /* The max power is limited to 63 */
--- 556 unchanged lines hidden (view full) ---
3756 return AH_FALSE;
3757}
3758
3759HAL_BOOL
3760ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val)
3761{
3762 return AH_FALSE;
3763}