1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17
18#include "opt_ah.h"
19
20#ifdef AH_SUPPORT_AR9300
21
22#include "ah.h"
23#include "ah_internal.h"
24
25#include "ar9300/ar9300.h"
26#include "ar9300/ar9300reg.h"
27#include "ar9300/ar9300phy.h"
28
29#if ATH_SUPPORT_MCI
30
31#define AH_MCI_REMOTE_RESET_INTERVAL_US 500
32#define AH_MCI_DEBUG_PRINT_SCHED 0
33
34static void ar9300_mci_print_msg(struct ath_hal *ah, HAL_BOOL send,u_int8_t hdr,
35 int len, u_int32_t *pl)
36{
37#if DBG
38 char s[128];
39 char *p = s;
40 int i;
41 u_int8_t *p_data = (u_int8_t *) pl;
42
43 if (send) {
44 p += snprintf(s, 60,
45 "(MCI) >>>>> Hdr: %02X, Len: %d, Payload:", hdr, len);
--- 14 unchanged lines hidden (view full) ---
60 }
61*/
62#endif
63}
64
65static
66void ar9300_mci_osla_setup(struct ath_hal *ah, HAL_BOOL enable)
67{
68 struct ath_hal_9300 *ahp = AH9300(ah);
69 u_int32_t thresh;
70
71 if (enable) {
72 OS_REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, AR_MCI_SCHD_TABLE_2_HW_BASED, 1);
73 OS_REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, AR_MCI_SCHD_TABLE_2_MEM_BASED, 1);
74
75 if (!(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
76 ATH_MCI_CONFIG_DISABLE_AGGR_THRESH))
77 {
78 thresh = MS(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config,
79 ATH_MCI_CONFIG_AGGR_THRESH);
80 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
81 AR_BTCOEX_CTRL_AGGR_THRESH, thresh);
82 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
83 AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN, 1);
84 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
85 "(MCI) SCHED aggr thresh: on, thresh=%d (%d.%d%%)\n",
86 thresh, (thresh + 1)*125/10, (thresh + 1)*125%10);
--- 27 unchanged lines hidden (view full) ---
114 }
115}
116
117static int32_t ar9300_mci_wait_for_interrupt(struct ath_hal *ah,
118 u_int32_t address,
119 u_int32_t bit_position,
120 int32_t time_out)
121{
122 int data, loop;
123
124 while (time_out) {
125 data = OS_REG_READ(ah, address);
126
127 if (data & bit_position) {
128 OS_REG_WRITE(ah, address, bit_position);
129 if (address == AR_MCI_INTERRUPT_RX_MSG_RAW) {
130 if (bit_position & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
--- 180 unchanged lines hidden (view full) ---
311 MCI_GPM_COEX_BT_GPM_UNHALT;
312 }
313 ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, AH_TRUE);
314}
315
316static HAL_BOOL ar9300_mci_send_coex_bt_flags(struct ath_hal *ah, HAL_BOOL wait_done,
317 u_int8_t opcode, u_int32_t bt_flags)
318{
319 struct ath_hal_9300 *ahp = AH9300(ah);
320 u_int32_t pld[4] = {0, 0, 0, 0};
321
322 MCI_GPM_SET_TYPE_OPCODE(pld,
323 MCI_GPM_COEX_AGENT, MCI_GPM_COEX_BT_UPDATE_FLAGS);
324
325 *(((u_int8_t *)pld) + MCI_GPM_COEX_B_BT_FLAGS_OP) = opcode;
326 *(((u_int8_t *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 0) = bt_flags & 0xFF;
327 *(((u_int8_t *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 1) =
--- 77 unchanged lines hidden (view full) ---
405 ar9300_mci_send_lna_transfer(ah, AH_TRUE);
406 OS_DELAY(5);
407
408 OS_REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
409 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
410 if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) {
411 OS_REG_CLR_BIT(ah, AR_GLB_CONTROL,
412 AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
413 if (!(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
414 ATH_MCI_CONFIG_DISABLE_OSLA))
415 {
416 ar9300_mci_osla_setup(ah, AH_TRUE);
417 }
418 }
419 } else {
420 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Send LNA take\n");
421 ar9300_mci_send_lna_take(ah, AH_TRUE);
--- 64 unchanged lines hidden (view full) ---
486 OS_REG_WRITE(ah, AR_GPIO_OUTPUT_MUX1, 0x000bdab4); // 4068
487 OS_REG_WRITE(ah, AR_OBS, 0x0000004b); // 4088
488 OS_REG_WRITE(ah, AR_DIAG_SW, 0x080c0000);
489 OS_REG_WRITE(ah, AR_MACMISC, 0x0001a000);
490 OS_REG_WRITE(ah, AR_PHY_TEST, 0x00080000); // a360
491 OS_REG_WRITE(ah, AR_PHY_TEST_CTL_STATUS, 0xe0000000); // a364
492 */
493
494 if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
495 ATH_MCI_CONFIG_MCI_OBS_MCI)
496 {
497 ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA);
498 ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK);
499 ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
500 ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
501 }
502 else if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
503 ATH_MCI_CONFIG_MCI_OBS_TXRX)
504 {
505 ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX);
506 ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX);
507 ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
508 ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
509 ar9300_gpio_cfg_output(ah, 5, HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
510 }
511 else if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
512 ATH_MCI_CONFIG_MCI_OBS_BT)
513 {
514 ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
515 ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
516 ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
517 ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
518 }
519 else {
--- 394 unchanged lines hidden (view full) ---
914 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
915 AR_MCI_INTERRUPT_RX_MSG_DEFAULT);
916}
917
918void ar9300_mci_reset(struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g,
919 HAL_BOOL is_full_sleep)
920{
921 struct ath_hal_9300 *ahp = AH9300(ah);
922 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
923 u_int32_t regval;
924
925 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: full_sleep = %d, is_2g = %d\n",
926 __func__, is_full_sleep, is_2g);
927
928 if (!ahp->ah_mci_gpm_addr && !ahp->ah_mci_sched_addr) {
929 /* GPM buffer and scheduling message buffer are not allocated */
930 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
--- 28 unchanged lines hidden (view full) ---
959
960 if (AR_SREV_JUPITER_10(ah)) {
961 regval |= SM(1, AR_BTCOEX_CTRL_SPDT_ENABLE_10);
962 }
963
964 OS_REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
965
966 if (is_2g && (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) &&
967 !(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
968 ATH_MCI_CONFIG_DISABLE_OSLA))
969 {
970 ar9300_mci_osla_setup(ah, AH_TRUE);
971 }
972 else {
973 ar9300_mci_osla_setup(ah, AH_FALSE);
974 }
975
976 if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) {
977 OS_REG_SET_BIT(ah, AR_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
978
979 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL3,
980 AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT, 20);
981 }
982
983 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_RX_DEWEIGHT, 0);
984
985 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
986
987 if (ahpriv->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_CONCUR_TX) {
988 u_int8_t i;
989 u_int32_t const *pmax_tx_pwr;
990
991 if ((ahpriv->ah_config.ath_hal_mci_config &
992 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN)
993 {
994 ahp->ah_mci_concur_tx_en = (ahp->ah_bt_coex_flag &
995 HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR) ? AH_TRUE : AH_FALSE;
996
997 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n",
998 ahp->ah_mci_concur_tx_en);
999 /*
--- 25 unchanged lines hidden (view full) ---
1025 chan_flags,
1026 (MS(pmax_tx_pwr[2],
1027 ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK) >> 1));
1028 }
1029#else
1030 pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0];
1031#endif
1032 }
1033 else if ((ahpriv->ah_config.ath_hal_mci_config &
1034 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_UNSHARED_CHN)
1035 {
1036 pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0];
1037 ahp->ah_mci_concur_tx_en = AH_TRUE;
1038 }
1039 else {
1040 pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0];
1041 ahp->ah_mci_concur_tx_en = AH_TRUE;
--- 6 unchanged lines hidden (view full) ---
1048 AR_BTCOEX_CTRL2_TXPWR_THRESH, 0x7f);
1049 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
1050 AR_BTCOEX_CTRL_REDUCE_TXPWR, 0);
1051 for (i = 0; i < 8; i++) {
1052 OS_REG_WRITE(ah, AR_BTCOEX_MAX_TXPWR(i), pmax_tx_pwr[i]);
1053 }
1054 }
1055
1056 regval = MS(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config,
1057 ATH_MCI_CONFIG_CLK_DIV);
1058 OS_REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, regval);
1059
1060 OS_REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN);
1061
1062 /* Resetting the Rx and Tx paths of MCI */
1063 regval = OS_REG_READ(ah, AR_MCI_COMMAND2);
1064 regval |= SM(1, AR_MCI_COMMAND2_RESET_TX);
--- 271 unchanged lines hidden (view full) ---
1336u_int32_t
1337ar9300_mci_state(struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data)
1338{
1339 u_int32_t value = 0, more_gpm = 0, gpm_ptr;
1340 struct ath_hal_9300 *ahp = AH9300(ah);
1341
1342 switch (state_type) {
1343 case HAL_MCI_STATE_ENABLE:
1344 if (AH_PRIVATE(ah)->ah_caps.hal_mci_support && ahp->ah_mci_ready) {
1345 value = OS_REG_READ(ah, AR_BTCOEX_CTRL);
1346 if ((value == 0xdeadbeef) || (value == 0xffffffff)) {
1347 // HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1348 // "(MCI) BTCOEX_CTRL = 0xdeadbeef\n");
1349 value = 0;
1350 }
1351 }
1352 value &= AR_BTCOEX_CTRL_MCI_MODE_EN;
--- 190 unchanged lines hidden (view full) ---
1543 ahp->ah_mci_bt_state = MCI_BT_CAL;
1544 break;
1545
1546 case HAL_MCI_STATE_RESET_REQ_WAKE:
1547 ar9300_mci_reset_req_wakeup(ah);
1548 ahp->ah_mci_coex_2g5g_update = AH_TRUE;
1549
1550 if ((AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) &&
1551 (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
1552 ATH_MCI_CONFIG_MCI_OBS_MASK))
1553 {
1554 /* Check if we still have control of the GPIOs */
1555 if ((OS_REG_READ(ah, AR_GLB_GPIO_CONTROL) &
1556 ATH_MCI_CONFIG_MCI_OBS_GPIO) !=
1557 ATH_MCI_CONFIG_MCI_OBS_GPIO)
1558 {
1559 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
--- 71 unchanged lines hidden (view full) ---
1631 (ahp->ah_mci_need_flush_btinfo == AH_TRUE))
1632 {
1633 value = 1;
1634 }
1635 else {
1636 value = 0;
1637 }
1638 if (p_data != NULL) {
1639 ahp->ah_mci_need_flush_btinfo = (*p_data != 0)?true:false;
1640 }
1641 break;
1642
1643 case HAL_MCI_STATE_SET_CONCUR_TX_PRI:
1644 if (p_data) {
1645 ahp->ah_mci_stomp_none_tx_pri = *p_data & 0xff;
1646 ahp->ah_mci_stomp_low_tx_pri = (*p_data >> 8) & 0xff;
1647 ahp->ah_mci_stomp_all_tx_pri = (*p_data >> 16) & 0xff;
--- 20 unchanged lines hidden (view full) ---
1668 ar9300_mci_send_coex_bt_flags(ah, AH_TRUE,
1669 MCI_GPM_COEX_BT_FLAGS_READ, 0);
1670 }
1671 }
1672 }
1673 break;
1674
1675 case HAL_MCI_STATE_NEED_FTP_STOMP:
1676 value = (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
1677 ATH_MCI_CONFIG_DISABLE_FTP_STOMP) ? 0 : 1;
1678 break;
1679
1680 case HAL_MCI_STATE_NEED_TUNING:
1681 value = (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
1682 ATH_MCI_CONFIG_DISABLE_TUNING) ? 0 : 1;
1683 break;
1684
1685 case HAL_MCI_STATE_SHARED_CHAIN_CONCUR_TX:
1686 value = ((AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
1687 ATH_MCI_CONFIG_CONCUR_TX) ==
1688 ATH_MCI_CONCUR_TX_SHARED_CHN)? 1 : 0;
1689 break;
1690
1691 default:
1692 break;
1693 }
1694 return value;
--- 44 unchanged lines hidden (view full) ---
1739 ah_bt_coex_wlan_weight[1] = 0x7d000000
1740 ah_bt_coex_wlan_weight[2] = 0x00000000
1741 ah_bt_coex_wlan_weight[3] = 0x00000000
1742*/
1743
1744void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type)
1745{
1746 struct ath_hal_9300 *ahp = AH9300(ah);
1747 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
1748 u_int32_t tx_priority = 0;
1749
1750 switch (stomp_type) {
1751 case HAL_BT_COEX_STOMP_ALL:
1752 ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_ALL_WLAN_WGHT0;
1753 ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_ALL_WLAN_WGHT1;
1754 ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_ALL_WLAN_WGHT2;
1755 ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_ALL_WLAN_WGHT3;
--- 12 unchanged lines hidden (view full) ---
1768 ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_LOW_WLAN_WGHT0;
1769 ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_LOW_WLAN_WGHT1;
1770 ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_LOW_WLAN_WGHT2;
1771 ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_LOW_WLAN_WGHT3;
1772 }
1773 if (ahp->ah_mci_concur_tx_en && ahp->ah_mci_stomp_low_tx_pri) {
1774 tx_priority = ahp->ah_mci_stomp_low_tx_pri;
1775 }
1776 if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
1777 ATH_MCI_CONFIG_MCI_OBS_TXRX)
1778 {
1779 ar9300_gpio_set(ah, 5, 1);
1780 }
1781 break;
1782 case HAL_BT_COEX_STOMP_ALL_FORCE:
1783 ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_ALL_FORCE_WLAN_WGHT0;
1784 ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_ALL_FORCE_WLAN_WGHT1;
--- 13 unchanged lines hidden (view full) ---
1798 case HAL_BT_COEX_NO_STOMP:
1799 ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_NONE_WLAN_WGHT0;
1800 ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_NONE_WLAN_WGHT1;
1801 ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_NONE_WLAN_WGHT2;
1802 ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_NONE_WLAN_WGHT3;
1803 if (ahp->ah_mci_concur_tx_en && ahp->ah_mci_stomp_none_tx_pri) {
1804 tx_priority = ahp->ah_mci_stomp_none_tx_pri;
1805 }
1806 if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
1807 ATH_MCI_CONFIG_MCI_OBS_TXRX)
1808 {
1809 ar9300_gpio_set(ah, 5, 0);
1810 }
1811 break;
1812 default:
1813 /* There is a forceWeight from registry */
1814 ahp->ah_bt_coex_wlan_weight[0] = stomp_type;
--- 10 unchanged lines hidden (view full) ---
1825 SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT2_MASK);
1826 ahp->ah_bt_coex_wlan_weight[3] &= ~MCI_CONCUR_TX_WLAN_WGHT3_MASK;
1827 ahp->ah_bt_coex_wlan_weight[3] |=
1828 SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT3_MASK);
1829 ahp->ah_bt_coex_wlan_weight[3] &= ~MCI_CONCUR_TX_WLAN_WGHT3_MASK2;
1830 ahp->ah_bt_coex_wlan_weight[3] |=
1831 SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT3_MASK2);
1832 }
1833 if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
1834 ATH_MCI_CONFIG_MCI_WEIGHT_DBG)
1835 {
1836 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1837 "(MCI) Set weights: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1838 ahp->ah_bt_coex_wlan_weight[0],
1839 ahp->ah_bt_coex_wlan_weight[1],
1840 ahp->ah_bt_coex_wlan_weight[2],
1841 ahp->ah_bt_coex_wlan_weight[3]);
--- 42 unchanged lines hidden (view full) ---
1884 }
1885
1886 ahp->ah_bt_coex_enabled = AH_TRUE;
1887
1888 return 0;
1889}
1890
1891#endif /* ATH_SUPPORT_MCI */
1892#endif /* AH_SUPPORT_AR9300 */
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17
18#include "opt_ah.h"
19
20#ifdef AH_SUPPORT_AR9300
21
22#include "ah.h"
23#include "ah_internal.h"
24
25#include "ar9300/ar9300.h"
26#include "ar9300/ar9300reg.h"
27#include "ar9300/ar9300phy.h"
28
29#if ATH_SUPPORT_MCI
30
31#define AH_MCI_REMOTE_RESET_INTERVAL_US 500
32#define AH_MCI_DEBUG_PRINT_SCHED 0
33
34static void ar9300_mci_print_msg(struct ath_hal *ah, HAL_BOOL send,u_int8_t hdr,
35 int len, u_int32_t *pl)
36{
37#if DBG
38 char s[128];
39 char *p = s;
40 int i;
41 u_int8_t *p_data = (u_int8_t *) pl;
42
43 if (send) {
44 p += snprintf(s, 60,
45 "(MCI) >>>>> Hdr: %02X, Len: %d, Payload:", hdr, len);
--- 14 unchanged lines hidden (view full) ---
60 }
61*/
62#endif
63}
64
65static
66void ar9300_mci_osla_setup(struct ath_hal *ah, HAL_BOOL enable)
67{
68 struct ath_hal_9300 *ahp = AH9300(ah);
69 u_int32_t thresh;
70
71 if (enable) {
72 OS_REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, AR_MCI_SCHD_TABLE_2_HW_BASED, 1);
73 OS_REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, AR_MCI_SCHD_TABLE_2_MEM_BASED, 1);
74
75 if (!(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
76 ATH_MCI_CONFIG_DISABLE_AGGR_THRESH))
77 {
78 thresh = MS(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config,
79 ATH_MCI_CONFIG_AGGR_THRESH);
80 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
81 AR_BTCOEX_CTRL_AGGR_THRESH, thresh);
82 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
83 AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN, 1);
84 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
85 "(MCI) SCHED aggr thresh: on, thresh=%d (%d.%d%%)\n",
86 thresh, (thresh + 1)*125/10, (thresh + 1)*125%10);
--- 27 unchanged lines hidden (view full) ---
114 }
115}
116
117static int32_t ar9300_mci_wait_for_interrupt(struct ath_hal *ah,
118 u_int32_t address,
119 u_int32_t bit_position,
120 int32_t time_out)
121{
122 int data, loop;
123
124 while (time_out) {
125 data = OS_REG_READ(ah, address);
126
127 if (data & bit_position) {
128 OS_REG_WRITE(ah, address, bit_position);
129 if (address == AR_MCI_INTERRUPT_RX_MSG_RAW) {
130 if (bit_position & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
--- 180 unchanged lines hidden (view full) ---
311 MCI_GPM_COEX_BT_GPM_UNHALT;
312 }
313 ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, AH_TRUE);
314}
315
316static HAL_BOOL ar9300_mci_send_coex_bt_flags(struct ath_hal *ah, HAL_BOOL wait_done,
317 u_int8_t opcode, u_int32_t bt_flags)
318{
319 struct ath_hal_9300 *ahp = AH9300(ah);
320 u_int32_t pld[4] = {0, 0, 0, 0};
321
322 MCI_GPM_SET_TYPE_OPCODE(pld,
323 MCI_GPM_COEX_AGENT, MCI_GPM_COEX_BT_UPDATE_FLAGS);
324
325 *(((u_int8_t *)pld) + MCI_GPM_COEX_B_BT_FLAGS_OP) = opcode;
326 *(((u_int8_t *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 0) = bt_flags & 0xFF;
327 *(((u_int8_t *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 1) =
--- 77 unchanged lines hidden (view full) ---
405 ar9300_mci_send_lna_transfer(ah, AH_TRUE);
406 OS_DELAY(5);
407
408 OS_REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
409 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
410 if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) {
411 OS_REG_CLR_BIT(ah, AR_GLB_CONTROL,
412 AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
413 if (!(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
414 ATH_MCI_CONFIG_DISABLE_OSLA))
415 {
416 ar9300_mci_osla_setup(ah, AH_TRUE);
417 }
418 }
419 } else {
420 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Send LNA take\n");
421 ar9300_mci_send_lna_take(ah, AH_TRUE);
--- 64 unchanged lines hidden (view full) ---
486 OS_REG_WRITE(ah, AR_GPIO_OUTPUT_MUX1, 0x000bdab4); // 4068
487 OS_REG_WRITE(ah, AR_OBS, 0x0000004b); // 4088
488 OS_REG_WRITE(ah, AR_DIAG_SW, 0x080c0000);
489 OS_REG_WRITE(ah, AR_MACMISC, 0x0001a000);
490 OS_REG_WRITE(ah, AR_PHY_TEST, 0x00080000); // a360
491 OS_REG_WRITE(ah, AR_PHY_TEST_CTL_STATUS, 0xe0000000); // a364
492 */
493
494 if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
495 ATH_MCI_CONFIG_MCI_OBS_MCI)
496 {
497 ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA);
498 ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK);
499 ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
500 ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
501 }
502 else if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
503 ATH_MCI_CONFIG_MCI_OBS_TXRX)
504 {
505 ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX);
506 ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX);
507 ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
508 ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
509 ar9300_gpio_cfg_output(ah, 5, HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
510 }
511 else if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
512 ATH_MCI_CONFIG_MCI_OBS_BT)
513 {
514 ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
515 ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
516 ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
517 ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
518 }
519 else {
--- 394 unchanged lines hidden (view full) ---
914 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
915 AR_MCI_INTERRUPT_RX_MSG_DEFAULT);
916}
917
918void ar9300_mci_reset(struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g,
919 HAL_BOOL is_full_sleep)
920{
921 struct ath_hal_9300 *ahp = AH9300(ah);
922 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
923 u_int32_t regval;
924
925 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: full_sleep = %d, is_2g = %d\n",
926 __func__, is_full_sleep, is_2g);
927
928 if (!ahp->ah_mci_gpm_addr && !ahp->ah_mci_sched_addr) {
929 /* GPM buffer and scheduling message buffer are not allocated */
930 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
--- 28 unchanged lines hidden (view full) ---
959
960 if (AR_SREV_JUPITER_10(ah)) {
961 regval |= SM(1, AR_BTCOEX_CTRL_SPDT_ENABLE_10);
962 }
963
964 OS_REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
965
966 if (is_2g && (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) &&
967 !(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
968 ATH_MCI_CONFIG_DISABLE_OSLA))
969 {
970 ar9300_mci_osla_setup(ah, AH_TRUE);
971 }
972 else {
973 ar9300_mci_osla_setup(ah, AH_FALSE);
974 }
975
976 if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) {
977 OS_REG_SET_BIT(ah, AR_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
978
979 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL3,
980 AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT, 20);
981 }
982
983 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_RX_DEWEIGHT, 0);
984
985 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
986
987 if (ahpriv->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_CONCUR_TX) {
988 u_int8_t i;
989 u_int32_t const *pmax_tx_pwr;
990
991 if ((ahpriv->ah_config.ath_hal_mci_config &
992 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN)
993 {
994 ahp->ah_mci_concur_tx_en = (ahp->ah_bt_coex_flag &
995 HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR) ? AH_TRUE : AH_FALSE;
996
997 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n",
998 ahp->ah_mci_concur_tx_en);
999 /*
--- 25 unchanged lines hidden (view full) ---
1025 chan_flags,
1026 (MS(pmax_tx_pwr[2],
1027 ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK) >> 1));
1028 }
1029#else
1030 pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0];
1031#endif
1032 }
1033 else if ((ahpriv->ah_config.ath_hal_mci_config &
1034 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_UNSHARED_CHN)
1035 {
1036 pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0];
1037 ahp->ah_mci_concur_tx_en = AH_TRUE;
1038 }
1039 else {
1040 pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0];
1041 ahp->ah_mci_concur_tx_en = AH_TRUE;
--- 6 unchanged lines hidden (view full) ---
1048 AR_BTCOEX_CTRL2_TXPWR_THRESH, 0x7f);
1049 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
1050 AR_BTCOEX_CTRL_REDUCE_TXPWR, 0);
1051 for (i = 0; i < 8; i++) {
1052 OS_REG_WRITE(ah, AR_BTCOEX_MAX_TXPWR(i), pmax_tx_pwr[i]);
1053 }
1054 }
1055
1056 regval = MS(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config,
1057 ATH_MCI_CONFIG_CLK_DIV);
1058 OS_REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, regval);
1059
1060 OS_REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN);
1061
1062 /* Resetting the Rx and Tx paths of MCI */
1063 regval = OS_REG_READ(ah, AR_MCI_COMMAND2);
1064 regval |= SM(1, AR_MCI_COMMAND2_RESET_TX);
--- 271 unchanged lines hidden (view full) ---
1336u_int32_t
1337ar9300_mci_state(struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data)
1338{
1339 u_int32_t value = 0, more_gpm = 0, gpm_ptr;
1340 struct ath_hal_9300 *ahp = AH9300(ah);
1341
1342 switch (state_type) {
1343 case HAL_MCI_STATE_ENABLE:
1344 if (AH_PRIVATE(ah)->ah_caps.hal_mci_support && ahp->ah_mci_ready) {
1345 value = OS_REG_READ(ah, AR_BTCOEX_CTRL);
1346 if ((value == 0xdeadbeef) || (value == 0xffffffff)) {
1347 // HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1348 // "(MCI) BTCOEX_CTRL = 0xdeadbeef\n");
1349 value = 0;
1350 }
1351 }
1352 value &= AR_BTCOEX_CTRL_MCI_MODE_EN;
--- 190 unchanged lines hidden (view full) ---
1543 ahp->ah_mci_bt_state = MCI_BT_CAL;
1544 break;
1545
1546 case HAL_MCI_STATE_RESET_REQ_WAKE:
1547 ar9300_mci_reset_req_wakeup(ah);
1548 ahp->ah_mci_coex_2g5g_update = AH_TRUE;
1549
1550 if ((AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) &&
1551 (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
1552 ATH_MCI_CONFIG_MCI_OBS_MASK))
1553 {
1554 /* Check if we still have control of the GPIOs */
1555 if ((OS_REG_READ(ah, AR_GLB_GPIO_CONTROL) &
1556 ATH_MCI_CONFIG_MCI_OBS_GPIO) !=
1557 ATH_MCI_CONFIG_MCI_OBS_GPIO)
1558 {
1559 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
--- 71 unchanged lines hidden (view full) ---
1631 (ahp->ah_mci_need_flush_btinfo == AH_TRUE))
1632 {
1633 value = 1;
1634 }
1635 else {
1636 value = 0;
1637 }
1638 if (p_data != NULL) {
1639 ahp->ah_mci_need_flush_btinfo = (*p_data != 0)?true:false;
1640 }
1641 break;
1642
1643 case HAL_MCI_STATE_SET_CONCUR_TX_PRI:
1644 if (p_data) {
1645 ahp->ah_mci_stomp_none_tx_pri = *p_data & 0xff;
1646 ahp->ah_mci_stomp_low_tx_pri = (*p_data >> 8) & 0xff;
1647 ahp->ah_mci_stomp_all_tx_pri = (*p_data >> 16) & 0xff;
--- 20 unchanged lines hidden (view full) ---
1668 ar9300_mci_send_coex_bt_flags(ah, AH_TRUE,
1669 MCI_GPM_COEX_BT_FLAGS_READ, 0);
1670 }
1671 }
1672 }
1673 break;
1674
1675 case HAL_MCI_STATE_NEED_FTP_STOMP:
1676 value = (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
1677 ATH_MCI_CONFIG_DISABLE_FTP_STOMP) ? 0 : 1;
1678 break;
1679
1680 case HAL_MCI_STATE_NEED_TUNING:
1681 value = (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
1682 ATH_MCI_CONFIG_DISABLE_TUNING) ? 0 : 1;
1683 break;
1684
1685 case HAL_MCI_STATE_SHARED_CHAIN_CONCUR_TX:
1686 value = ((AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
1687 ATH_MCI_CONFIG_CONCUR_TX) ==
1688 ATH_MCI_CONCUR_TX_SHARED_CHN)? 1 : 0;
1689 break;
1690
1691 default:
1692 break;
1693 }
1694 return value;
--- 44 unchanged lines hidden (view full) ---
1739 ah_bt_coex_wlan_weight[1] = 0x7d000000
1740 ah_bt_coex_wlan_weight[2] = 0x00000000
1741 ah_bt_coex_wlan_weight[3] = 0x00000000
1742*/
1743
1744void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type)
1745{
1746 struct ath_hal_9300 *ahp = AH9300(ah);
1747 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
1748 u_int32_t tx_priority = 0;
1749
1750 switch (stomp_type) {
1751 case HAL_BT_COEX_STOMP_ALL:
1752 ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_ALL_WLAN_WGHT0;
1753 ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_ALL_WLAN_WGHT1;
1754 ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_ALL_WLAN_WGHT2;
1755 ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_ALL_WLAN_WGHT3;
--- 12 unchanged lines hidden (view full) ---
1768 ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_LOW_WLAN_WGHT0;
1769 ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_LOW_WLAN_WGHT1;
1770 ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_LOW_WLAN_WGHT2;
1771 ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_LOW_WLAN_WGHT3;
1772 }
1773 if (ahp->ah_mci_concur_tx_en && ahp->ah_mci_stomp_low_tx_pri) {
1774 tx_priority = ahp->ah_mci_stomp_low_tx_pri;
1775 }
1776 if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
1777 ATH_MCI_CONFIG_MCI_OBS_TXRX)
1778 {
1779 ar9300_gpio_set(ah, 5, 1);
1780 }
1781 break;
1782 case HAL_BT_COEX_STOMP_ALL_FORCE:
1783 ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_ALL_FORCE_WLAN_WGHT0;
1784 ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_ALL_FORCE_WLAN_WGHT1;
--- 13 unchanged lines hidden (view full) ---
1798 case HAL_BT_COEX_NO_STOMP:
1799 ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_NONE_WLAN_WGHT0;
1800 ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_NONE_WLAN_WGHT1;
1801 ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_NONE_WLAN_WGHT2;
1802 ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_NONE_WLAN_WGHT3;
1803 if (ahp->ah_mci_concur_tx_en && ahp->ah_mci_stomp_none_tx_pri) {
1804 tx_priority = ahp->ah_mci_stomp_none_tx_pri;
1805 }
1806 if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
1807 ATH_MCI_CONFIG_MCI_OBS_TXRX)
1808 {
1809 ar9300_gpio_set(ah, 5, 0);
1810 }
1811 break;
1812 default:
1813 /* There is a forceWeight from registry */
1814 ahp->ah_bt_coex_wlan_weight[0] = stomp_type;
--- 10 unchanged lines hidden (view full) ---
1825 SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT2_MASK);
1826 ahp->ah_bt_coex_wlan_weight[3] &= ~MCI_CONCUR_TX_WLAN_WGHT3_MASK;
1827 ahp->ah_bt_coex_wlan_weight[3] |=
1828 SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT3_MASK);
1829 ahp->ah_bt_coex_wlan_weight[3] &= ~MCI_CONCUR_TX_WLAN_WGHT3_MASK2;
1830 ahp->ah_bt_coex_wlan_weight[3] |=
1831 SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT3_MASK2);
1832 }
1833 if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
1834 ATH_MCI_CONFIG_MCI_WEIGHT_DBG)
1835 {
1836 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1837 "(MCI) Set weights: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1838 ahp->ah_bt_coex_wlan_weight[0],
1839 ahp->ah_bt_coex_wlan_weight[1],
1840 ahp->ah_bt_coex_wlan_weight[2],
1841 ahp->ah_bt_coex_wlan_weight[3]);
--- 42 unchanged lines hidden (view full) ---
1884 }
1885
1886 ahp->ah_bt_coex_enabled = AH_TRUE;
1887
1888 return 0;
1889}
1890
1891#endif /* ATH_SUPPORT_MCI */
1892#endif /* AH_SUPPORT_AR9300 */