1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17
18#include "opt_ah.h"
19
20#include "ah.h"
21#include "ah_internal.h"
22
23#include "ar9300/ar9300.h"
24#include "ar9300/ar9300reg.h"
25#include "ar9300/ar9300phy.h"
26
27#if ATH_SUPPORT_MCI
28
29#define AH_MCI_REMOTE_RESET_INTERVAL_US 500
30#define AH_MCI_DEBUG_PRINT_SCHED 0
31
32static void ar9300_mci_print_msg(struct ath_hal *ah, HAL_BOOL send,u_int8_t hdr,
33 int len, u_int32_t *pl)
34{
35#if 0
36 char s[128];
37 char *p = s;
38 int i;
39 u_int8_t *p_data = (u_int8_t *) pl;
40
41 if (send) {
42 p += snprintf(s, 60,
43 "(MCI) >>>>> Hdr: %02X, Len: %d, Payload:", hdr, len);
--- 14 unchanged lines hidden (view full) ---
58 }
59*/
60#endif
61}
62
63static
64void ar9300_mci_osla_setup(struct ath_hal *ah, HAL_BOOL enable)
65{
66// struct ath_hal_9300 *ahp = AH9300(ah);
67 u_int32_t thresh;
68
69 if (enable) {
70 OS_REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, AR_MCI_SCHD_TABLE_2_HW_BASED, 1);
71 OS_REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, AR_MCI_SCHD_TABLE_2_MEM_BASED, 1);
72
73 if (!(ah->ah_config.ath_hal_mci_config &
74 ATH_MCI_CONFIG_DISABLE_AGGR_THRESH))
75 {
76 thresh = MS(ah->ah_config.ath_hal_mci_config,
77 ATH_MCI_CONFIG_AGGR_THRESH);
78 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
79 AR_BTCOEX_CTRL_AGGR_THRESH, thresh);
80 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
81 AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN, 1);
82 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
83 "(MCI) SCHED aggr thresh: on, thresh=%d (%d.%d%%)\n",
84 thresh, (thresh + 1)*125/10, (thresh + 1)*125%10);
--- 27 unchanged lines hidden (view full) ---
112 }
113}
114
115static int32_t ar9300_mci_wait_for_interrupt(struct ath_hal *ah,
116 u_int32_t address,
117 u_int32_t bit_position,
118 int32_t time_out)
119{
120 int data; //, loop;
121
122 while (time_out) {
123 data = OS_REG_READ(ah, address);
124
125 if (data & bit_position) {
126 OS_REG_WRITE(ah, address, bit_position);
127 if (address == AR_MCI_INTERRUPT_RX_MSG_RAW) {
128 if (bit_position & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
--- 180 unchanged lines hidden (view full) ---
309 MCI_GPM_COEX_BT_GPM_UNHALT;
310 }
311 ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, AH_TRUE);
312}
313
314static HAL_BOOL ar9300_mci_send_coex_bt_flags(struct ath_hal *ah, HAL_BOOL wait_done,
315 u_int8_t opcode, u_int32_t bt_flags)
316{
317// struct ath_hal_9300 *ahp = AH9300(ah);
318 u_int32_t pld[4] = {0, 0, 0, 0};
319
320 MCI_GPM_SET_TYPE_OPCODE(pld,
321 MCI_GPM_COEX_AGENT, MCI_GPM_COEX_BT_UPDATE_FLAGS);
322
323 *(((u_int8_t *)pld) + MCI_GPM_COEX_B_BT_FLAGS_OP) = opcode;
324 *(((u_int8_t *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 0) = bt_flags & 0xFF;
325 *(((u_int8_t *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 1) =
--- 77 unchanged lines hidden (view full) ---
403 ar9300_mci_send_lna_transfer(ah, AH_TRUE);
404 OS_DELAY(5);
405
406 OS_REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
407 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
408 if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) {
409 OS_REG_CLR_BIT(ah, AR_GLB_CONTROL,
410 AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
411 if (!(ah->ah_config.ath_hal_mci_config &
412 ATH_MCI_CONFIG_DISABLE_OSLA))
413 {
414 ar9300_mci_osla_setup(ah, AH_TRUE);
415 }
416 }
417 } else {
418 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Send LNA take\n");
419 ar9300_mci_send_lna_take(ah, AH_TRUE);
--- 64 unchanged lines hidden (view full) ---
484 OS_REG_WRITE(ah, AR_GPIO_OUTPUT_MUX1, 0x000bdab4); // 4068
485 OS_REG_WRITE(ah, AR_OBS, 0x0000004b); // 4088
486 OS_REG_WRITE(ah, AR_DIAG_SW, 0x080c0000);
487 OS_REG_WRITE(ah, AR_MACMISC, 0x0001a000);
488 OS_REG_WRITE(ah, AR_PHY_TEST, 0x00080000); // a360
489 OS_REG_WRITE(ah, AR_PHY_TEST_CTL_STATUS, 0xe0000000); // a364
490 */
491
492 if (ah->ah_config.ath_hal_mci_config &
493 ATH_MCI_CONFIG_MCI_OBS_MCI)
494 {
495 ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA);
496 ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK);
497 ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
498 ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
499 }
500 else if (ah->ah_config.ath_hal_mci_config &
501 ATH_MCI_CONFIG_MCI_OBS_TXRX)
502 {
503 ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX);
504 ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX);
505 ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
506 ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
507 ar9300_gpio_cfg_output(ah, 5, HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
508 }
509 else if (ah->ah_config.ath_hal_mci_config &
510 ATH_MCI_CONFIG_MCI_OBS_BT)
511 {
512 ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
513 ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
514 ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
515 ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
516 }
517 else {
--- 394 unchanged lines hidden (view full) ---
912 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
913 AR_MCI_INTERRUPT_RX_MSG_DEFAULT);
914}
915
916void ar9300_mci_reset(struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g,
917 HAL_BOOL is_full_sleep)
918{
919 struct ath_hal_9300 *ahp = AH9300(ah);
920// struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
921 u_int32_t regval;
922
923 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: full_sleep = %d, is_2g = %d\n",
924 __func__, is_full_sleep, is_2g);
925
926 if (!ahp->ah_mci_gpm_addr && !ahp->ah_mci_sched_addr) {
927 /* GPM buffer and scheduling message buffer are not allocated */
928 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
--- 28 unchanged lines hidden (view full) ---
957
958 if (AR_SREV_JUPITER_10(ah)) {
959 regval |= SM(1, AR_BTCOEX_CTRL_SPDT_ENABLE_10);
960 }
961
962 OS_REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
963
964 if (is_2g && (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) &&
965 !(ah->ah_config.ath_hal_mci_config &
966 ATH_MCI_CONFIG_DISABLE_OSLA))
967 {
968 ar9300_mci_osla_setup(ah, AH_TRUE);
969 }
970 else {
971 ar9300_mci_osla_setup(ah, AH_FALSE);
972 }
973
974 if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) {
975 OS_REG_SET_BIT(ah, AR_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
976
977 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL3,
978 AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT, 20);
979 }
980
981 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_RX_DEWEIGHT, 0);
982
983 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
984
985 if (ah->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_CONCUR_TX) {
986 u_int8_t i;
987 u_int32_t const *pmax_tx_pwr;
988
989 if ((ah->ah_config.ath_hal_mci_config &
990 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN)
991 {
992 ahp->ah_mci_concur_tx_en = (ahp->ah_bt_coex_flag &
993 HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR) ? AH_TRUE : AH_FALSE;
994
995 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n",
996 ahp->ah_mci_concur_tx_en);
997 /*
--- 25 unchanged lines hidden (view full) ---
1023 chan_flags,
1024 (MS(pmax_tx_pwr[2],
1025 ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK) >> 1));
1026 }
1027#else
1028 pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0];
1029#endif
1030 }
1031 else if ((ah->ah_config.ath_hal_mci_config &
1032 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_UNSHARED_CHN)
1033 {
1034 pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0];
1035 ahp->ah_mci_concur_tx_en = AH_TRUE;
1036 }
1037 else {
1038 pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0];
1039 ahp->ah_mci_concur_tx_en = AH_TRUE;
--- 6 unchanged lines hidden (view full) ---
1046 AR_BTCOEX_CTRL2_TXPWR_THRESH, 0x7f);
1047 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
1048 AR_BTCOEX_CTRL_REDUCE_TXPWR, 0);
1049 for (i = 0; i < 8; i++) {
1050 OS_REG_WRITE(ah, AR_BTCOEX_MAX_TXPWR(i), pmax_tx_pwr[i]);
1051 }
1052 }
1053
1054 regval = MS(ah->ah_config.ath_hal_mci_config,
1055 ATH_MCI_CONFIG_CLK_DIV);
1056 OS_REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, regval);
1057
1058 OS_REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN);
1059
1060 /* Resetting the Rx and Tx paths of MCI */
1061 regval = OS_REG_READ(ah, AR_MCI_COMMAND2);
1062 regval |= SM(1, AR_MCI_COMMAND2_RESET_TX);
--- 271 unchanged lines hidden (view full) ---
1334u_int32_t
1335ar9300_mci_state(struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data)
1336{
1337 u_int32_t value = 0, more_gpm = 0, gpm_ptr;
1338 struct ath_hal_9300 *ahp = AH9300(ah);
1339
1340 switch (state_type) {
1341 case HAL_MCI_STATE_ENABLE:
1342 if (AH_PRIVATE(ah)->ah_caps.halMciSupport && ahp->ah_mci_ready) {
1343 value = OS_REG_READ(ah, AR_BTCOEX_CTRL);
1344 if ((value == 0xdeadbeef) || (value == 0xffffffff)) {
1345 // HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1346 // "(MCI) BTCOEX_CTRL = 0xdeadbeef\n");
1347 value = 0;
1348 }
1349 }
1350 value &= AR_BTCOEX_CTRL_MCI_MODE_EN;
--- 190 unchanged lines hidden (view full) ---
1541 ahp->ah_mci_bt_state = MCI_BT_CAL;
1542 break;
1543
1544 case HAL_MCI_STATE_RESET_REQ_WAKE:
1545 ar9300_mci_reset_req_wakeup(ah);
1546 ahp->ah_mci_coex_2g5g_update = AH_TRUE;
1547
1548 if ((AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) &&
1549 (ah->ah_config.ath_hal_mci_config &
1550 ATH_MCI_CONFIG_MCI_OBS_MASK))
1551 {
1552 /* Check if we still have control of the GPIOs */
1553 if ((OS_REG_READ(ah, AR_GLB_GPIO_CONTROL) &
1554 ATH_MCI_CONFIG_MCI_OBS_GPIO) !=
1555 ATH_MCI_CONFIG_MCI_OBS_GPIO)
1556 {
1557 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
--- 71 unchanged lines hidden (view full) ---
1629 (ahp->ah_mci_need_flush_btinfo == AH_TRUE))
1630 {
1631 value = 1;
1632 }
1633 else {
1634 value = 0;
1635 }
1636 if (p_data != NULL) {
1637 ahp->ah_mci_need_flush_btinfo = (*p_data != 0)? AH_TRUE : AH_FALSE;
1638 }
1639 break;
1640
1641 case HAL_MCI_STATE_SET_CONCUR_TX_PRI:
1642 if (p_data) {
1643 ahp->ah_mci_stomp_none_tx_pri = *p_data & 0xff;
1644 ahp->ah_mci_stomp_low_tx_pri = (*p_data >> 8) & 0xff;
1645 ahp->ah_mci_stomp_all_tx_pri = (*p_data >> 16) & 0xff;
--- 20 unchanged lines hidden (view full) ---
1666 ar9300_mci_send_coex_bt_flags(ah, AH_TRUE,
1667 MCI_GPM_COEX_BT_FLAGS_READ, 0);
1668 }
1669 }
1670 }
1671 break;
1672
1673 case HAL_MCI_STATE_NEED_FTP_STOMP:
1674 value = (ah->ah_config.ath_hal_mci_config &
1675 ATH_MCI_CONFIG_DISABLE_FTP_STOMP) ? 0 : 1;
1676 break;
1677
1678 case HAL_MCI_STATE_NEED_TUNING:
1679 value = (ah->ah_config.ath_hal_mci_config &
1680 ATH_MCI_CONFIG_DISABLE_TUNING) ? 0 : 1;
1681 break;
1682
1683 case HAL_MCI_STATE_SHARED_CHAIN_CONCUR_TX:
1684 value = ((ah->ah_config.ath_hal_mci_config &
1685 ATH_MCI_CONFIG_CONCUR_TX) ==
1686 ATH_MCI_CONCUR_TX_SHARED_CHN)? 1 : 0;
1687 break;
1688
1689 default:
1690 break;
1691 }
1692 return value;
--- 44 unchanged lines hidden (view full) ---
1737 ah_bt_coex_wlan_weight[1] = 0x7d000000
1738 ah_bt_coex_wlan_weight[2] = 0x00000000
1739 ah_bt_coex_wlan_weight[3] = 0x00000000
1740*/
1741
1742void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type)
1743{
1744 struct ath_hal_9300 *ahp = AH9300(ah);
1745// struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
1746 u_int32_t tx_priority = 0;
1747
1748 switch (stomp_type) {
1749 case HAL_BT_COEX_STOMP_ALL:
1750 ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_ALL_WLAN_WGHT0;
1751 ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_ALL_WLAN_WGHT1;
1752 ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_ALL_WLAN_WGHT2;
1753 ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_ALL_WLAN_WGHT3;
--- 12 unchanged lines hidden (view full) ---
1766 ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_LOW_WLAN_WGHT0;
1767 ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_LOW_WLAN_WGHT1;
1768 ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_LOW_WLAN_WGHT2;
1769 ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_LOW_WLAN_WGHT3;
1770 }
1771 if (ahp->ah_mci_concur_tx_en && ahp->ah_mci_stomp_low_tx_pri) {
1772 tx_priority = ahp->ah_mci_stomp_low_tx_pri;
1773 }
1774 if (ah->ah_config.ath_hal_mci_config &
1775 ATH_MCI_CONFIG_MCI_OBS_TXRX)
1776 {
1777 ar9300_gpio_set(ah, 5, 1);
1778 }
1779 break;
1780 case HAL_BT_COEX_STOMP_ALL_FORCE:
1781 ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_ALL_FORCE_WLAN_WGHT0;
1782 ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_ALL_FORCE_WLAN_WGHT1;
--- 13 unchanged lines hidden (view full) ---
1796 case HAL_BT_COEX_NO_STOMP:
1797 ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_NONE_WLAN_WGHT0;
1798 ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_NONE_WLAN_WGHT1;
1799 ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_NONE_WLAN_WGHT2;
1800 ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_NONE_WLAN_WGHT3;
1801 if (ahp->ah_mci_concur_tx_en && ahp->ah_mci_stomp_none_tx_pri) {
1802 tx_priority = ahp->ah_mci_stomp_none_tx_pri;
1803 }
1804 if (ah->ah_config.ath_hal_mci_config &
1805 ATH_MCI_CONFIG_MCI_OBS_TXRX)
1806 {
1807 ar9300_gpio_set(ah, 5, 0);
1808 }
1809 break;
1810 default:
1811 /* There is a forceWeight from registry */
1812 ahp->ah_bt_coex_wlan_weight[0] = stomp_type;
--- 10 unchanged lines hidden (view full) ---
1823 SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT2_MASK);
1824 ahp->ah_bt_coex_wlan_weight[3] &= ~MCI_CONCUR_TX_WLAN_WGHT3_MASK;
1825 ahp->ah_bt_coex_wlan_weight[3] |=
1826 SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT3_MASK);
1827 ahp->ah_bt_coex_wlan_weight[3] &= ~MCI_CONCUR_TX_WLAN_WGHT3_MASK2;
1828 ahp->ah_bt_coex_wlan_weight[3] |=
1829 SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT3_MASK2);
1830 }
1831 if (ah->ah_config.ath_hal_mci_config &
1832 ATH_MCI_CONFIG_MCI_WEIGHT_DBG)
1833 {
1834 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1835 "(MCI) Set weights: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1836 ahp->ah_bt_coex_wlan_weight[0],
1837 ahp->ah_bt_coex_wlan_weight[1],
1838 ahp->ah_bt_coex_wlan_weight[2],
1839 ahp->ah_bt_coex_wlan_weight[3]);
--- 42 unchanged lines hidden (view full) ---
1882 }
1883
1884 ahp->ah_bt_coex_enabled = AH_TRUE;
1885
1886 return 0;
1887}
1888
1889#endif /* ATH_SUPPORT_MCI */
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17
18#include "opt_ah.h"
19
20#include "ah.h"
21#include "ah_internal.h"
22
23#include "ar9300/ar9300.h"
24#include "ar9300/ar9300reg.h"
25#include "ar9300/ar9300phy.h"
26
27#if ATH_SUPPORT_MCI
28
29#define AH_MCI_REMOTE_RESET_INTERVAL_US 500
30#define AH_MCI_DEBUG_PRINT_SCHED 0
31
32static void ar9300_mci_print_msg(struct ath_hal *ah, HAL_BOOL send,u_int8_t hdr,
33 int len, u_int32_t *pl)
34{
35#if 0
36 char s[128];
37 char *p = s;
38 int i;
39 u_int8_t *p_data = (u_int8_t *) pl;
40
41 if (send) {
42 p += snprintf(s, 60,
43 "(MCI) >>>>> Hdr: %02X, Len: %d, Payload:", hdr, len);
--- 14 unchanged lines hidden (view full) ---
58 }
59*/
60#endif
61}
62
63static
64void ar9300_mci_osla_setup(struct ath_hal *ah, HAL_BOOL enable)
65{
66// struct ath_hal_9300 *ahp = AH9300(ah);
67 u_int32_t thresh;
68
69 if (enable) {
70 OS_REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, AR_MCI_SCHD_TABLE_2_HW_BASED, 1);
71 OS_REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, AR_MCI_SCHD_TABLE_2_MEM_BASED, 1);
72
73 if (!(ah->ah_config.ath_hal_mci_config &
74 ATH_MCI_CONFIG_DISABLE_AGGR_THRESH))
75 {
76 thresh = MS(ah->ah_config.ath_hal_mci_config,
77 ATH_MCI_CONFIG_AGGR_THRESH);
78 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
79 AR_BTCOEX_CTRL_AGGR_THRESH, thresh);
80 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
81 AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN, 1);
82 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
83 "(MCI) SCHED aggr thresh: on, thresh=%d (%d.%d%%)\n",
84 thresh, (thresh + 1)*125/10, (thresh + 1)*125%10);
--- 27 unchanged lines hidden (view full) ---
112 }
113}
114
115static int32_t ar9300_mci_wait_for_interrupt(struct ath_hal *ah,
116 u_int32_t address,
117 u_int32_t bit_position,
118 int32_t time_out)
119{
120 int data; //, loop;
121
122 while (time_out) {
123 data = OS_REG_READ(ah, address);
124
125 if (data & bit_position) {
126 OS_REG_WRITE(ah, address, bit_position);
127 if (address == AR_MCI_INTERRUPT_RX_MSG_RAW) {
128 if (bit_position & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
--- 180 unchanged lines hidden (view full) ---
309 MCI_GPM_COEX_BT_GPM_UNHALT;
310 }
311 ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, AH_TRUE);
312}
313
314static HAL_BOOL ar9300_mci_send_coex_bt_flags(struct ath_hal *ah, HAL_BOOL wait_done,
315 u_int8_t opcode, u_int32_t bt_flags)
316{
317// struct ath_hal_9300 *ahp = AH9300(ah);
318 u_int32_t pld[4] = {0, 0, 0, 0};
319
320 MCI_GPM_SET_TYPE_OPCODE(pld,
321 MCI_GPM_COEX_AGENT, MCI_GPM_COEX_BT_UPDATE_FLAGS);
322
323 *(((u_int8_t *)pld) + MCI_GPM_COEX_B_BT_FLAGS_OP) = opcode;
324 *(((u_int8_t *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 0) = bt_flags & 0xFF;
325 *(((u_int8_t *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 1) =
--- 77 unchanged lines hidden (view full) ---
403 ar9300_mci_send_lna_transfer(ah, AH_TRUE);
404 OS_DELAY(5);
405
406 OS_REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
407 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
408 if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) {
409 OS_REG_CLR_BIT(ah, AR_GLB_CONTROL,
410 AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
411 if (!(ah->ah_config.ath_hal_mci_config &
412 ATH_MCI_CONFIG_DISABLE_OSLA))
413 {
414 ar9300_mci_osla_setup(ah, AH_TRUE);
415 }
416 }
417 } else {
418 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Send LNA take\n");
419 ar9300_mci_send_lna_take(ah, AH_TRUE);
--- 64 unchanged lines hidden (view full) ---
484 OS_REG_WRITE(ah, AR_GPIO_OUTPUT_MUX1, 0x000bdab4); // 4068
485 OS_REG_WRITE(ah, AR_OBS, 0x0000004b); // 4088
486 OS_REG_WRITE(ah, AR_DIAG_SW, 0x080c0000);
487 OS_REG_WRITE(ah, AR_MACMISC, 0x0001a000);
488 OS_REG_WRITE(ah, AR_PHY_TEST, 0x00080000); // a360
489 OS_REG_WRITE(ah, AR_PHY_TEST_CTL_STATUS, 0xe0000000); // a364
490 */
491
492 if (ah->ah_config.ath_hal_mci_config &
493 ATH_MCI_CONFIG_MCI_OBS_MCI)
494 {
495 ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA);
496 ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK);
497 ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
498 ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
499 }
500 else if (ah->ah_config.ath_hal_mci_config &
501 ATH_MCI_CONFIG_MCI_OBS_TXRX)
502 {
503 ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX);
504 ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX);
505 ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
506 ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
507 ar9300_gpio_cfg_output(ah, 5, HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
508 }
509 else if (ah->ah_config.ath_hal_mci_config &
510 ATH_MCI_CONFIG_MCI_OBS_BT)
511 {
512 ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
513 ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
514 ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
515 ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
516 }
517 else {
--- 394 unchanged lines hidden (view full) ---
912 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
913 AR_MCI_INTERRUPT_RX_MSG_DEFAULT);
914}
915
916void ar9300_mci_reset(struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g,
917 HAL_BOOL is_full_sleep)
918{
919 struct ath_hal_9300 *ahp = AH9300(ah);
920// struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
921 u_int32_t regval;
922
923 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: full_sleep = %d, is_2g = %d\n",
924 __func__, is_full_sleep, is_2g);
925
926 if (!ahp->ah_mci_gpm_addr && !ahp->ah_mci_sched_addr) {
927 /* GPM buffer and scheduling message buffer are not allocated */
928 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
--- 28 unchanged lines hidden (view full) ---
957
958 if (AR_SREV_JUPITER_10(ah)) {
959 regval |= SM(1, AR_BTCOEX_CTRL_SPDT_ENABLE_10);
960 }
961
962 OS_REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
963
964 if (is_2g && (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) &&
965 !(ah->ah_config.ath_hal_mci_config &
966 ATH_MCI_CONFIG_DISABLE_OSLA))
967 {
968 ar9300_mci_osla_setup(ah, AH_TRUE);
969 }
970 else {
971 ar9300_mci_osla_setup(ah, AH_FALSE);
972 }
973
974 if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) {
975 OS_REG_SET_BIT(ah, AR_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
976
977 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL3,
978 AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT, 20);
979 }
980
981 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_RX_DEWEIGHT, 0);
982
983 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
984
985 if (ah->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_CONCUR_TX) {
986 u_int8_t i;
987 u_int32_t const *pmax_tx_pwr;
988
989 if ((ah->ah_config.ath_hal_mci_config &
990 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN)
991 {
992 ahp->ah_mci_concur_tx_en = (ahp->ah_bt_coex_flag &
993 HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR) ? AH_TRUE : AH_FALSE;
994
995 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n",
996 ahp->ah_mci_concur_tx_en);
997 /*
--- 25 unchanged lines hidden (view full) ---
1023 chan_flags,
1024 (MS(pmax_tx_pwr[2],
1025 ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK) >> 1));
1026 }
1027#else
1028 pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0];
1029#endif
1030 }
1031 else if ((ah->ah_config.ath_hal_mci_config &
1032 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_UNSHARED_CHN)
1033 {
1034 pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0];
1035 ahp->ah_mci_concur_tx_en = AH_TRUE;
1036 }
1037 else {
1038 pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0];
1039 ahp->ah_mci_concur_tx_en = AH_TRUE;
--- 6 unchanged lines hidden (view full) ---
1046 AR_BTCOEX_CTRL2_TXPWR_THRESH, 0x7f);
1047 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
1048 AR_BTCOEX_CTRL_REDUCE_TXPWR, 0);
1049 for (i = 0; i < 8; i++) {
1050 OS_REG_WRITE(ah, AR_BTCOEX_MAX_TXPWR(i), pmax_tx_pwr[i]);
1051 }
1052 }
1053
1054 regval = MS(ah->ah_config.ath_hal_mci_config,
1055 ATH_MCI_CONFIG_CLK_DIV);
1056 OS_REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, regval);
1057
1058 OS_REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN);
1059
1060 /* Resetting the Rx and Tx paths of MCI */
1061 regval = OS_REG_READ(ah, AR_MCI_COMMAND2);
1062 regval |= SM(1, AR_MCI_COMMAND2_RESET_TX);
--- 271 unchanged lines hidden (view full) ---
1334u_int32_t
1335ar9300_mci_state(struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data)
1336{
1337 u_int32_t value = 0, more_gpm = 0, gpm_ptr;
1338 struct ath_hal_9300 *ahp = AH9300(ah);
1339
1340 switch (state_type) {
1341 case HAL_MCI_STATE_ENABLE:
1342 if (AH_PRIVATE(ah)->ah_caps.halMciSupport && ahp->ah_mci_ready) {
1343 value = OS_REG_READ(ah, AR_BTCOEX_CTRL);
1344 if ((value == 0xdeadbeef) || (value == 0xffffffff)) {
1345 // HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1346 // "(MCI) BTCOEX_CTRL = 0xdeadbeef\n");
1347 value = 0;
1348 }
1349 }
1350 value &= AR_BTCOEX_CTRL_MCI_MODE_EN;
--- 190 unchanged lines hidden (view full) ---
1541 ahp->ah_mci_bt_state = MCI_BT_CAL;
1542 break;
1543
1544 case HAL_MCI_STATE_RESET_REQ_WAKE:
1545 ar9300_mci_reset_req_wakeup(ah);
1546 ahp->ah_mci_coex_2g5g_update = AH_TRUE;
1547
1548 if ((AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) &&
1549 (ah->ah_config.ath_hal_mci_config &
1550 ATH_MCI_CONFIG_MCI_OBS_MASK))
1551 {
1552 /* Check if we still have control of the GPIOs */
1553 if ((OS_REG_READ(ah, AR_GLB_GPIO_CONTROL) &
1554 ATH_MCI_CONFIG_MCI_OBS_GPIO) !=
1555 ATH_MCI_CONFIG_MCI_OBS_GPIO)
1556 {
1557 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
--- 71 unchanged lines hidden (view full) ---
1629 (ahp->ah_mci_need_flush_btinfo == AH_TRUE))
1630 {
1631 value = 1;
1632 }
1633 else {
1634 value = 0;
1635 }
1636 if (p_data != NULL) {
1637 ahp->ah_mci_need_flush_btinfo = (*p_data != 0)? AH_TRUE : AH_FALSE;
1638 }
1639 break;
1640
1641 case HAL_MCI_STATE_SET_CONCUR_TX_PRI:
1642 if (p_data) {
1643 ahp->ah_mci_stomp_none_tx_pri = *p_data & 0xff;
1644 ahp->ah_mci_stomp_low_tx_pri = (*p_data >> 8) & 0xff;
1645 ahp->ah_mci_stomp_all_tx_pri = (*p_data >> 16) & 0xff;
--- 20 unchanged lines hidden (view full) ---
1666 ar9300_mci_send_coex_bt_flags(ah, AH_TRUE,
1667 MCI_GPM_COEX_BT_FLAGS_READ, 0);
1668 }
1669 }
1670 }
1671 break;
1672
1673 case HAL_MCI_STATE_NEED_FTP_STOMP:
1674 value = (ah->ah_config.ath_hal_mci_config &
1675 ATH_MCI_CONFIG_DISABLE_FTP_STOMP) ? 0 : 1;
1676 break;
1677
1678 case HAL_MCI_STATE_NEED_TUNING:
1679 value = (ah->ah_config.ath_hal_mci_config &
1680 ATH_MCI_CONFIG_DISABLE_TUNING) ? 0 : 1;
1681 break;
1682
1683 case HAL_MCI_STATE_SHARED_CHAIN_CONCUR_TX:
1684 value = ((ah->ah_config.ath_hal_mci_config &
1685 ATH_MCI_CONFIG_CONCUR_TX) ==
1686 ATH_MCI_CONCUR_TX_SHARED_CHN)? 1 : 0;
1687 break;
1688
1689 default:
1690 break;
1691 }
1692 return value;
--- 44 unchanged lines hidden (view full) ---
1737 ah_bt_coex_wlan_weight[1] = 0x7d000000
1738 ah_bt_coex_wlan_weight[2] = 0x00000000
1739 ah_bt_coex_wlan_weight[3] = 0x00000000
1740*/
1741
1742void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type)
1743{
1744 struct ath_hal_9300 *ahp = AH9300(ah);
1745// struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
1746 u_int32_t tx_priority = 0;
1747
1748 switch (stomp_type) {
1749 case HAL_BT_COEX_STOMP_ALL:
1750 ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_ALL_WLAN_WGHT0;
1751 ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_ALL_WLAN_WGHT1;
1752 ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_ALL_WLAN_WGHT2;
1753 ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_ALL_WLAN_WGHT3;
--- 12 unchanged lines hidden (view full) ---
1766 ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_LOW_WLAN_WGHT0;
1767 ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_LOW_WLAN_WGHT1;
1768 ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_LOW_WLAN_WGHT2;
1769 ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_LOW_WLAN_WGHT3;
1770 }
1771 if (ahp->ah_mci_concur_tx_en && ahp->ah_mci_stomp_low_tx_pri) {
1772 tx_priority = ahp->ah_mci_stomp_low_tx_pri;
1773 }
1774 if (ah->ah_config.ath_hal_mci_config &
1775 ATH_MCI_CONFIG_MCI_OBS_TXRX)
1776 {
1777 ar9300_gpio_set(ah, 5, 1);
1778 }
1779 break;
1780 case HAL_BT_COEX_STOMP_ALL_FORCE:
1781 ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_ALL_FORCE_WLAN_WGHT0;
1782 ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_ALL_FORCE_WLAN_WGHT1;
--- 13 unchanged lines hidden (view full) ---
1796 case HAL_BT_COEX_NO_STOMP:
1797 ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_NONE_WLAN_WGHT0;
1798 ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_NONE_WLAN_WGHT1;
1799 ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_NONE_WLAN_WGHT2;
1800 ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_NONE_WLAN_WGHT3;
1801 if (ahp->ah_mci_concur_tx_en && ahp->ah_mci_stomp_none_tx_pri) {
1802 tx_priority = ahp->ah_mci_stomp_none_tx_pri;
1803 }
1804 if (ah->ah_config.ath_hal_mci_config &
1805 ATH_MCI_CONFIG_MCI_OBS_TXRX)
1806 {
1807 ar9300_gpio_set(ah, 5, 0);
1808 }
1809 break;
1810 default:
1811 /* There is a forceWeight from registry */
1812 ahp->ah_bt_coex_wlan_weight[0] = stomp_type;
--- 10 unchanged lines hidden (view full) ---
1823 SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT2_MASK);
1824 ahp->ah_bt_coex_wlan_weight[3] &= ~MCI_CONCUR_TX_WLAN_WGHT3_MASK;
1825 ahp->ah_bt_coex_wlan_weight[3] |=
1826 SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT3_MASK);
1827 ahp->ah_bt_coex_wlan_weight[3] &= ~MCI_CONCUR_TX_WLAN_WGHT3_MASK2;
1828 ahp->ah_bt_coex_wlan_weight[3] |=
1829 SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT3_MASK2);
1830 }
1831 if (ah->ah_config.ath_hal_mci_config &
1832 ATH_MCI_CONFIG_MCI_WEIGHT_DBG)
1833 {
1834 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1835 "(MCI) Set weights: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1836 ahp->ah_bt_coex_wlan_weight[0],
1837 ahp->ah_bt_coex_wlan_weight[1],
1838 ahp->ah_bt_coex_wlan_weight[2],
1839 ahp->ah_bt_coex_wlan_weight[3]);
--- 42 unchanged lines hidden (view full) ---
1882 }
1883
1884 ahp->ah_bt_coex_enabled = AH_TRUE;
1885
1886 return 0;
1887}
1888
1889#endif /* ATH_SUPPORT_MCI */