Deleted Added
sdiff udiff text old ( 250007 ) new ( 250008 )
full compact
ar9300_gpio.c (250007) ar9300_gpio.c (250008)
1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "opt_ah.h"
18
1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "opt_ah.h"
18
19#ifdef AH_SUPPORT_AR9300
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24#ifdef AH_DEBUG
25#include "ah_desc.h" /* NB: for HAL_PHYERR* */
26#endif
27
28#include "ar9300/ar9300.h"
29#include "ar9300/ar9300reg.h"
30#include "ar9300/ar9300phy.h"
31
32#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
33
34/*
35 * Configure GPIO Output Mux control
36 */
19#include "ah.h"
20#include "ah_internal.h"
21#include "ah_devid.h"
22#ifdef AH_DEBUG
23#include "ah_desc.h" /* NB: for HAL_PHYERR* */
24#endif
25
26#include "ar9300/ar9300.h"
27#include "ar9300/ar9300reg.h"
28#include "ar9300/ar9300phy.h"
29
30#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
31
32/*
33 * Configure GPIO Output Mux control
34 */
37#ifdef UMAC_SUPPORT_SMARTANTENNA
35#if UMAC_SUPPORT_SMARTANTENNA
38static void ar9340_soc_gpio_cfg_output_mux(
39 struct ath_hal *ah,
40 u_int32_t gpio,
41 u_int32_t ah_signal_type)
42{
43#define ADDR_READ(addr) (*((volatile u_int32_t *)(addr)))
44#define ADDR_WRITE(addr, b) (void)((*(volatile u_int32_t *) (addr)) = (b))
45#define AR9340_SOC_GPIO_FUN0 0xB804002c

--- 61 unchanged lines hidden (view full) ---

107
108/*
109 * Configure GPIO Output lines
110 */
111HAL_BOOL
112ar9300_gpio_cfg_output(
113 struct ath_hal *ah,
114 u_int32_t gpio,
36static void ar9340_soc_gpio_cfg_output_mux(
37 struct ath_hal *ah,
38 u_int32_t gpio,
39 u_int32_t ah_signal_type)
40{
41#define ADDR_READ(addr) (*((volatile u_int32_t *)(addr)))
42#define ADDR_WRITE(addr, b) (void)((*(volatile u_int32_t *) (addr)) = (b))
43#define AR9340_SOC_GPIO_FUN0 0xB804002c

--- 61 unchanged lines hidden (view full) ---

105
106/*
107 * Configure GPIO Output lines
108 */
109HAL_BOOL
110ar9300_gpio_cfg_output(
111 struct ath_hal *ah,
112 u_int32_t gpio,
115 HAL_GPIO_OUTPUT_MUX_TYPE hal_signal_type)
113 HAL_GPIO_MUX_TYPE hal_signal_type)
116{
117 u_int32_t ah_signal_type;
118 u_int32_t gpio_shift;
119 u_int8_t smart_ant = 0;
120 static const u_int32_t mux_signal_conversion_table[] = {
121 /* HAL_GPIO_OUTPUT_MUX_AS_OUTPUT */
122 AR_GPIO_OUTPUT_MUX_AS_OUTPUT,
123 /* HAL_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED */

--- 33 unchanged lines hidden (view full) ---

157 /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1 */
158 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1,
159 /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2 */
160 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2,
161 /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_SWCOM3 */
162 AR_GPIO_OUTPUT_MUX_AS_SWCOM3,
163 };
164
114{
115 u_int32_t ah_signal_type;
116 u_int32_t gpio_shift;
117 u_int8_t smart_ant = 0;
118 static const u_int32_t mux_signal_conversion_table[] = {
119 /* HAL_GPIO_OUTPUT_MUX_AS_OUTPUT */
120 AR_GPIO_OUTPUT_MUX_AS_OUTPUT,
121 /* HAL_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED */

--- 33 unchanged lines hidden (view full) ---

155 /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1 */
156 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1,
157 /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2 */
158 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2,
159 /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_SWCOM3 */
160 AR_GPIO_OUTPUT_MUX_AS_SWCOM3,
161 };
162
165 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
163 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
166 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
167 (gpio == AR9382_GPIO_PIN_11_RESERVED) ||
168 (gpio == AR9382_GPIO_9_INPUT_ONLY))
169 {
170 return AH_FALSE;
171 }
172
173 /* Convert HAL signal type definitions to hardware-specific values. */
164 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
165 (gpio == AR9382_GPIO_PIN_11_RESERVED) ||
166 (gpio == AR9382_GPIO_9_INPUT_ONLY))
167 {
168 return AH_FALSE;
169 }
170
171 /* Convert HAL signal type definitions to hardware-specific values. */
174 if (hal_signal_type < ARRAY_LENGTH(mux_signal_conversion_table))
172 if ((int) hal_signal_type < ARRAY_LENGTH(mux_signal_conversion_table))
175 {
176 ah_signal_type = mux_signal_conversion_table[hal_signal_type];
177 } else {
178 return AH_FALSE;
179 }
180
181 if (gpio <= AR9382_MAX_JTAG_GPIO_PIN_NUM) {
182 OS_REG_SET_BIT(ah,

--- 28 unchanged lines hidden (view full) ---

211#endif
212 default:
213 break;
214 }
215#endif
216
217 if (smart_ant && (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)))
218 {
173 {
174 ah_signal_type = mux_signal_conversion_table[hal_signal_type];
175 } else {
176 return AH_FALSE;
177 }
178
179 if (gpio <= AR9382_MAX_JTAG_GPIO_PIN_NUM) {
180 OS_REG_SET_BIT(ah,

--- 28 unchanged lines hidden (view full) ---

209#endif
210 default:
211 break;
212 }
213#endif
214
215 if (smart_ant && (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)))
216 {
219#ifdef UMAC_SUPPORT_SMARTANTENNA
217#if UMAC_SUPPORT_SMARTANTENNA
220 ar9340_soc_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
221#endif
222 return AH_TRUE;
223 } else
224 {
225 /* Configure the MUX */
226 ar9300_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
227 }

--- 10 unchanged lines hidden (view full) ---

238
239/*
240 * Configure GPIO Output lines -LED off
241 */
242HAL_BOOL
243ar9300_gpio_cfg_output_led_off(
244 struct ath_hal *ah,
245 u_int32_t gpio,
218 ar9340_soc_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
219#endif
220 return AH_TRUE;
221 } else
222 {
223 /* Configure the MUX */
224 ar9300_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
225 }

--- 10 unchanged lines hidden (view full) ---

236
237/*
238 * Configure GPIO Output lines -LED off
239 */
240HAL_BOOL
241ar9300_gpio_cfg_output_led_off(
242 struct ath_hal *ah,
243 u_int32_t gpio,
246 HAL_GPIO_OUTPUT_MUX_TYPE halSignalType)
244 HAL_GPIO_MUX_TYPE halSignalType)
247{
248#define N(a) (sizeof(a) / sizeof(a[0]))
249 u_int32_t ah_signal_type;
250 u_int32_t gpio_shift;
251 u_int8_t smart_ant = 0;
252
253 static const u_int32_t mux_signal_conversion_table[] = {
254 /* HAL_GPIO_OUTPUT_MUX_AS_OUTPUT */

--- 30 unchanged lines hidden (view full) ---

285 AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA,
286 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0,
287 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1,
288 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2
289 };
290 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
291
292 /* Convert HAL signal type definitions to hardware-specific values. */
245{
246#define N(a) (sizeof(a) / sizeof(a[0]))
247 u_int32_t ah_signal_type;
248 u_int32_t gpio_shift;
249 u_int8_t smart_ant = 0;
250
251 static const u_int32_t mux_signal_conversion_table[] = {
252 /* HAL_GPIO_OUTPUT_MUX_AS_OUTPUT */

--- 30 unchanged lines hidden (view full) ---

283 AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA,
284 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0,
285 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1,
286 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2
287 };
288 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
289
290 /* Convert HAL signal type definitions to hardware-specific values. */
293 if (halSignalType < ARRAY_LENGTH(mux_signal_conversion_table))
291 if ((int) halSignalType < ARRAY_LENGTH(mux_signal_conversion_table))
294 {
295 ah_signal_type = mux_signal_conversion_table[halSignalType];
296 } else {
297 return AH_FALSE;
298 }
299#if UMAC_SUPPORT_SMARTANTENNA
300 /* Get the pin and func values for smart antenna */
301 switch (halSignalType)

--- 41 unchanged lines hidden (view full) ---

343/*
344 * Configure GPIO Input lines
345 */
346HAL_BOOL
347ar9300_gpio_cfg_input(struct ath_hal *ah, u_int32_t gpio)
348{
349 u_int32_t gpio_shift;
350
292 {
293 ah_signal_type = mux_signal_conversion_table[halSignalType];
294 } else {
295 return AH_FALSE;
296 }
297#if UMAC_SUPPORT_SMARTANTENNA
298 /* Get the pin and func values for smart antenna */
299 switch (halSignalType)

--- 41 unchanged lines hidden (view full) ---

341/*
342 * Configure GPIO Input lines
343 */
344HAL_BOOL
345ar9300_gpio_cfg_input(struct ath_hal *ah, u_int32_t gpio)
346{
347 u_int32_t gpio_shift;
348
351 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
349 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
352 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
353 (gpio == AR9382_GPIO_PIN_11_RESERVED) ||
354 (gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM))
355 {
356 return AH_FALSE;
357 }
358
359 if (gpio <= AR9382_MAX_JTAG_GPIO_PIN_NUM) {

--- 13 unchanged lines hidden (view full) ---

373
374/*
375 * Once configured for I/O - set output lines
376 * output the level of GPio PIN without care work mode
377 */
378HAL_BOOL
379ar9300_gpio_set(struct ath_hal *ah, u_int32_t gpio, u_int32_t val)
380{
350 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
351 (gpio == AR9382_GPIO_PIN_11_RESERVED) ||
352 (gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM))
353 {
354 return AH_FALSE;
355 }
356
357 if (gpio <= AR9382_MAX_JTAG_GPIO_PIN_NUM) {

--- 13 unchanged lines hidden (view full) ---

371
372/*
373 * Once configured for I/O - set output lines
374 * output the level of GPio PIN without care work mode
375 */
376HAL_BOOL
377ar9300_gpio_set(struct ath_hal *ah, u_int32_t gpio, u_int32_t val)
378{
381 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
379 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
382 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
383 (gpio == AR9382_GPIO_PIN_11_RESERVED) ||
384 (gpio == AR9382_GPIO_9_INPUT_ONLY))
385 {
386 return AH_FALSE;
387 }
388 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT),
389 ((val & 1) << gpio), AR_GPIO_BIT(gpio));
390
391 return AH_TRUE;
392}
393
394/*
395 * Once configured for I/O - get input lines
396 */
397u_int32_t
398ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio)
399{
400 u_int32_t gpio_in;
380 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
381 (gpio == AR9382_GPIO_PIN_11_RESERVED) ||
382 (gpio == AR9382_GPIO_9_INPUT_ONLY))
383 {
384 return AH_FALSE;
385 }
386 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT),
387 ((val & 1) << gpio), AR_GPIO_BIT(gpio));
388
389 return AH_TRUE;
390}
391
392/*
393 * Once configured for I/O - get input lines
394 */
395u_int32_t
396ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio)
397{
398 u_int32_t gpio_in;
401 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
399 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
402 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
403 (gpio == AR9382_GPIO_PIN_11_RESERVED))
404 {
405 return 0xffffffff;
406 }
407
408 gpio_in = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN));
409 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN),

--- 37 unchanged lines hidden (view full) ---

447 shifts[1] = AR_INTR_ASYNC_MASK_GPIO_S;
448#else
449 regs[0] = AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE);
450 regs[1] = AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK);
451 shifts[0] = AR_INTR_SYNC_ENABLE_GPIO_S;
452 shifts[1] = AR_INTR_SYNC_MASK_GPIO_S;
453#endif
454
400 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
401 (gpio == AR9382_GPIO_PIN_11_RESERVED))
402 {
403 return 0xffffffff;
404 }
405
406 gpio_in = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN));
407 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN),

--- 37 unchanged lines hidden (view full) ---

445 shifts[1] = AR_INTR_ASYNC_MASK_GPIO_S;
446#else
447 regs[0] = AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE);
448 regs[1] = AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK);
449 shifts[0] = AR_INTR_SYNC_ENABLE_GPIO_S;
450 shifts[1] = AR_INTR_SYNC_MASK_GPIO_S;
451#endif
452
455 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
453 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
456
457 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
458 (gpio == AR9382_GPIO_PIN_11_RESERVED) ||
459 (gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM))
460 {
461 return;
462 }
463
464#ifdef AH_ASSERT
454
455 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
456 (gpio == AR9382_GPIO_PIN_11_RESERVED) ||
457 (gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM))
458 {
459 return;
460 }
461
462#ifdef AH_ASSERT
465 gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins) - 1;
463 gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.halNumGpioPins) - 1;
466#endif
464#endif
467
468 if (ilevel == HAL_GPIO_INTR_DISABLE) {
469 /* clear this GPIO's bit in the interrupt registers */
470 for (i = 0; i < ARRAY_LENGTH(regs); i++) {
471 reg_val = OS_REG_READ(ah, regs[i]);
472 reg_bit = shifts[i] + gpio;
473 reg_val &= ~(1 << reg_bit);
474 OS_REG_WRITE(ah, regs[i], reg_val);
475

--- 42 unchanged lines hidden (view full) ---

518}
519
520void
521ar9300_gpio_set_polarity(struct ath_hal *ah, u_int32_t pol_map,
522 u_int32_t changed_mask)
523{
524 u_int32_t gpio_mask;
525
465 if (ilevel == HAL_GPIO_INTR_DISABLE) {
466 /* clear this GPIO's bit in the interrupt registers */
467 for (i = 0; i < ARRAY_LENGTH(regs); i++) {
468 reg_val = OS_REG_READ(ah, regs[i]);
469 reg_bit = shifts[i] + gpio;
470 reg_val &= ~(1 << reg_bit);
471 OS_REG_WRITE(ah, regs[i], reg_val);
472

--- 42 unchanged lines hidden (view full) ---

515}
516
517void
518ar9300_gpio_set_polarity(struct ath_hal *ah, u_int32_t pol_map,
519 u_int32_t changed_mask)
520{
521 u_int32_t gpio_mask;
522
526 gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins) - 1;
523 gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.halNumGpioPins) - 1;
527 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), gpio_mask & pol_map);
528
529#ifndef ATH_GPIO_USE_ASYNC_CAUSE
530 /*
531 * For SYNC_CAUSE type interrupts, we need to clear the cause register
532 * explicitly. Otherwise an interrupt with the original polarity setting
533 * will come up immediately (if there is already an interrupt source),
534 * which is not what we want usually.

--- 108 unchanged lines hidden (view full) ---

643 "AR_INTR_ASYNC_CAUSE: 0x%08X\n",
644 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE)));
645 ath_hal_printf(ah,
646 "AR_INTR_SYNC_CAUSE: 0x%08X\n",
647 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE)));
648
649}
650#endif /*AH_DEBUG*/
524 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), gpio_mask & pol_map);
525
526#ifndef ATH_GPIO_USE_ASYNC_CAUSE
527 /*
528 * For SYNC_CAUSE type interrupts, we need to clear the cause register
529 * explicitly. Otherwise an interrupt with the original polarity setting
530 * will come up immediately (if there is already an interrupt source),
531 * which is not what we want usually.

--- 108 unchanged lines hidden (view full) ---

640 "AR_INTR_ASYNC_CAUSE: 0x%08X\n",
641 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE)));
642 ath_hal_printf(ah,
643 "AR_INTR_SYNC_CAUSE: 0x%08X\n",
644 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE)));
645
646}
647#endif /*AH_DEBUG*/
651
652#endif /* AH_SUPPORT_AR9300 */