1/*-
2 * Copyright (c) 2013 Thomas Skibo
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
| 1/*-
2 * Copyright (c) 2013 Thomas Skibo
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
|
26 * $FreeBSD: stable/10/sys/arm/xilinx/zy7_gpio.c 266152 2014-05-15 16:11:06Z ian $
| 26 * $FreeBSD: stable/10/sys/arm/xilinx/zy7_gpio.c 278782 2015-02-14 20:37:33Z loos $
|
27 */
28
29/*
30 * A GPIO driver for Xilinx Zynq-7000.
31 *
32 * The GPIO peripheral on Zynq allows controlling 114 general purpose I/Os.
33 *
34 * Pins 53-0 are sent to the MIO. Any MIO pins not used by a PS peripheral are
35 * available as a GPIO pin. Pins 64-127 are sent to the PL (FPGA) section of
36 * Zynq as EMIO signals.
37 *
38 * The hardware provides a way to use IOs as interrupt sources but the
39 * gpio framework doesn't seem to have hooks for this.
40 *
41 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
42 * (v1.4) November 16, 2012. Xilinx doc UG585. GPIO is covered in
43 * chater 14. Register definitions are in appendix B.19.
44 */
45
46#include <sys/cdefs.h>
| 27 */
28
29/*
30 * A GPIO driver for Xilinx Zynq-7000.
31 *
32 * The GPIO peripheral on Zynq allows controlling 114 general purpose I/Os.
33 *
34 * Pins 53-0 are sent to the MIO. Any MIO pins not used by a PS peripheral are
35 * available as a GPIO pin. Pins 64-127 are sent to the PL (FPGA) section of
36 * Zynq as EMIO signals.
37 *
38 * The hardware provides a way to use IOs as interrupt sources but the
39 * gpio framework doesn't seem to have hooks for this.
40 *
41 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
42 * (v1.4) November 16, 2012. Xilinx doc UG585. GPIO is covered in
43 * chater 14. Register definitions are in appendix B.19.
44 */
45
46#include <sys/cdefs.h>
|
47__FBSDID("$FreeBSD: stable/10/sys/arm/xilinx/zy7_gpio.c 266152 2014-05-15 16:11:06Z ian $");
| 47__FBSDID("$FreeBSD: stable/10/sys/arm/xilinx/zy7_gpio.c 278782 2015-02-14 20:37:33Z loos $");
|
48
49#include <sys/param.h>
50#include <sys/systm.h>
51#include <sys/conf.h>
52#include <sys/bus.h>
53#include <sys/kernel.h>
54#include <sys/module.h>
55#include <sys/lock.h>
56#include <sys/mutex.h>
57#include <sys/resource.h>
58#include <sys/rman.h>
59#include <sys/gpio.h>
60
61#include <machine/bus.h>
62#include <machine/resource.h>
63#include <machine/stdarg.h>
64
65#include <dev/fdt/fdt_common.h>
66#include <dev/ofw/ofw_bus.h>
67#include <dev/ofw/ofw_bus_subr.h>
68
69#include "gpio_if.h"
70
71#define NUMBANKS 4
72#define MAXPIN (32*NUMBANKS)
73
74#define MIO_PIN 0 /* pins 0-53 go to MIO */
75#define NUM_MIO_PINS 54
76#define EMIO_PIN 64 /* pins 64-127 go to PL */
77#define NUM_EMIO_PINS 64
78
79#define VALID_PIN(u) (((u) >= MIO_PIN && (u) < MIO_PIN + NUM_MIO_PINS) || \
80 ((u) >= EMIO_PIN && (u) < EMIO_PIN + NUM_EMIO_PINS))
81
82#define ZGPIO_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
83#define ZGPIO_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
84#define ZGPIO_LOCK_INIT(sc) \
85 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
86 "gpio", MTX_DEF)
87#define ZGPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
88
89struct zy7_gpio_softc {
90 device_t dev;
91 struct mtx sc_mtx;
92 struct resource *mem_res; /* Memory resource */
93};
94
95#define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val))
96#define RD4(sc, off) bus_read_4((sc)->mem_res, (off))
97
98
99/* Xilinx Zynq-7000 GPIO register definitions:
100 */
101#define ZY7_GPIO_MASK_DATA_LSW(b) (0x0000+8*(b)) /* maskable wr lo */
102#define ZY7_GPIO_MASK_DATA_MSW(b) (0x0004+8*(b)) /* maskable wr hi */
103#define ZY7_GPIO_DATA(b) (0x0040+4*(b)) /* in/out data */
104#define ZY7_GPIO_DATA_RO(b) (0x0060+4*(b)) /* input data */
105
106#define ZY7_GPIO_DIRM(b) (0x0204+0x40*(b)) /* direction mode */
107#define ZY7_GPIO_OEN(b) (0x0208+0x40*(b)) /* output enable */
108#define ZY7_GPIO_INT_MASK(b) (0x020c+0x40*(b)) /* int mask */
109#define ZY7_GPIO_INT_EN(b) (0x0210+0x40*(b)) /* int enable */
110#define ZY7_GPIO_INT_DIS(b) (0x0214+0x40*(b)) /* int disable */
111#define ZY7_GPIO_INT_STAT(b) (0x0218+0x40*(b)) /* int status */
112#define ZY7_GPIO_INT_TYPE(b) (0x021c+0x40*(b)) /* int type */
113#define ZY7_GPIO_INT_POLARITY(b) (0x0220+0x40*(b)) /* int polarity */
114#define ZY7_GPIO_INT_ANY(b) (0x0224+0x40*(b)) /* any edge */
115
116
117static int
118zy7_gpio_pin_max(device_t dev, int *maxpin)
119{
120
121 *maxpin = MAXPIN;
122 return (0);
123}
124
125/* Get a specific pin's capabilities. */
126static int
127zy7_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
128{
129
130 if (!VALID_PIN(pin))
131 return (EINVAL);
132
133 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
134
135 return (0);
136}
137
138/* Get a specific pin's name. */
139static int
140zy7_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
141{
142
143 if (!VALID_PIN(pin))
144 return (EINVAL);
145
146 if (pin < NUM_MIO_PINS) {
147 snprintf(name, GPIOMAXNAME, "MIO_%d", pin);
148 name[GPIOMAXNAME - 1] = '\0';
149 } else {
150 snprintf(name, GPIOMAXNAME, "EMIO_%d", pin - EMIO_PIN);
151 name[GPIOMAXNAME - 1] = '\0';
152 }
153
154 return (0);
155}
156
157/* Get a specific pin's current in/out/tri state. */
158static int
159zy7_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
160{
161 struct zy7_gpio_softc *sc = device_get_softc(dev);
162
163 if (!VALID_PIN(pin))
164 return (EINVAL);
165
166 ZGPIO_LOCK(sc);
167
168 if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) {
169 /* output */
170 if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0)
171 *flags = (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
172 else
173 *flags = GPIO_PIN_OUTPUT;
174 } else
175 /* input */
176 *flags = GPIO_PIN_INPUT;
177
178 ZGPIO_UNLOCK(sc);
179
180 return (0);
181}
182
183/* Set a specific pin's in/out/tri state. */
184static int
185zy7_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
186{
187 struct zy7_gpio_softc *sc = device_get_softc(dev);
188
189 if (!VALID_PIN(pin))
190 return (EINVAL);
191
192 ZGPIO_LOCK(sc);
193
194 if ((flags & GPIO_PIN_OUTPUT) != 0) {
195 /* Output. Set or reset OEN too. */
196 WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
197 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31)));
198
199 if ((flags & GPIO_PIN_TRISTATE) != 0)
200 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
201 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) &
202 ~(1 << (pin & 31)));
203 else
204 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
205 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) |
206 (1 << (pin & 31)));
207 } else {
208 /* Input. Turn off OEN. */
209 WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
210 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31)));
211 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
212 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31)));
213 }
214
215 ZGPIO_UNLOCK(sc);
216
217 return (0);
218}
219
220/* Set a specific output pin's value. */
221static int
222zy7_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
223{
224 struct zy7_gpio_softc *sc = device_get_softc(dev);
225
226 if (!VALID_PIN(pin) || value > 1)
227 return (EINVAL);
228
229 /* Fancy register tricks allow atomic set or reset. */
230 if ((pin & 16) != 0)
231 WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5),
232 (0xffff0000 ^ (0x10000 << (pin & 15))) |
233 (value << (pin & 15)));
234 else
235 WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5),
236 (0xffff0000 ^ (0x10000 << (pin & 15))) |
237 (value << (pin & 15)));
238
239 return (0);
240}
241
242/* Get a specific pin's input value. */
243static int
244zy7_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
245{
246 struct zy7_gpio_softc *sc = device_get_softc(dev);
247
248 if (!VALID_PIN(pin))
249 return (EINVAL);
250
251 *value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1;
252
253 return (0);
254}
255
256/* Toggle a pin's output value. */
257static int
258zy7_gpio_pin_toggle(device_t dev, uint32_t pin)
259{
260 struct zy7_gpio_softc *sc = device_get_softc(dev);
261
262 if (!VALID_PIN(pin))
263 return (EINVAL);
264
265 ZGPIO_LOCK(sc);
266
267 WR4(sc, ZY7_GPIO_DATA(pin >> 5),
268 RD4(sc, ZY7_GPIO_DATA(pin >> 5)) ^ (1 << (pin & 31)));
269
270 ZGPIO_UNLOCK(sc);
271
272 return (0);
273}
274
275static int
276zy7_gpio_probe(device_t dev)
277{
278
279 if (!ofw_bus_status_okay(dev))
280 return (ENXIO);
281
282 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_gpio"))
283 return (ENXIO);
284
285 device_set_desc(dev, "Zynq-7000 GPIO driver");
286 return (0);
287}
288
289static void
290zy7_gpio_hw_reset(struct zy7_gpio_softc *sc)
291{
292 int i;
293
294 for (i = 0; i < NUMBANKS; i++) {
295 WR4(sc, ZY7_GPIO_DATA(i), 0);
296 WR4(sc, ZY7_GPIO_DIRM(i), 0);
297 WR4(sc, ZY7_GPIO_OEN(i), 0);
298 WR4(sc, ZY7_GPIO_INT_DIS(i), 0xffffffff);
299 WR4(sc, ZY7_GPIO_INT_POLARITY(i), 0);
300 WR4(sc, ZY7_GPIO_INT_TYPE(i),
301 i == 1 ? 0x003fffff : 0xffffffff);
302 WR4(sc, ZY7_GPIO_INT_ANY(i), 0);
303 WR4(sc, ZY7_GPIO_INT_STAT(i), 0xffffffff);
304 }
305}
306
307static int zy7_gpio_detach(device_t dev);
308
309static int
310zy7_gpio_attach(device_t dev)
311{
312 struct zy7_gpio_softc *sc = device_get_softc(dev);
313 int rid;
314
315 sc->dev = dev;
316
317 ZGPIO_LOCK_INIT(sc);
318
319 /* Allocate memory. */
320 rid = 0;
321 sc->mem_res = bus_alloc_resource_any(dev,
322 SYS_RES_MEMORY, &rid, RF_ACTIVE);
323 if (sc->mem_res == NULL) {
324 device_printf(dev, "Can't allocate memory for device");
325 zy7_gpio_detach(dev);
326 return (ENOMEM);
327 }
328
329 /* Completely reset. */
330 zy7_gpio_hw_reset(sc);
331
| 48
49#include <sys/param.h>
50#include <sys/systm.h>
51#include <sys/conf.h>
52#include <sys/bus.h>
53#include <sys/kernel.h>
54#include <sys/module.h>
55#include <sys/lock.h>
56#include <sys/mutex.h>
57#include <sys/resource.h>
58#include <sys/rman.h>
59#include <sys/gpio.h>
60
61#include <machine/bus.h>
62#include <machine/resource.h>
63#include <machine/stdarg.h>
64
65#include <dev/fdt/fdt_common.h>
66#include <dev/ofw/ofw_bus.h>
67#include <dev/ofw/ofw_bus_subr.h>
68
69#include "gpio_if.h"
70
71#define NUMBANKS 4
72#define MAXPIN (32*NUMBANKS)
73
74#define MIO_PIN 0 /* pins 0-53 go to MIO */
75#define NUM_MIO_PINS 54
76#define EMIO_PIN 64 /* pins 64-127 go to PL */
77#define NUM_EMIO_PINS 64
78
79#define VALID_PIN(u) (((u) >= MIO_PIN && (u) < MIO_PIN + NUM_MIO_PINS) || \
80 ((u) >= EMIO_PIN && (u) < EMIO_PIN + NUM_EMIO_PINS))
81
82#define ZGPIO_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
83#define ZGPIO_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
84#define ZGPIO_LOCK_INIT(sc) \
85 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
86 "gpio", MTX_DEF)
87#define ZGPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
88
89struct zy7_gpio_softc {
90 device_t dev;
91 struct mtx sc_mtx;
92 struct resource *mem_res; /* Memory resource */
93};
94
95#define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val))
96#define RD4(sc, off) bus_read_4((sc)->mem_res, (off))
97
98
99/* Xilinx Zynq-7000 GPIO register definitions:
100 */
101#define ZY7_GPIO_MASK_DATA_LSW(b) (0x0000+8*(b)) /* maskable wr lo */
102#define ZY7_GPIO_MASK_DATA_MSW(b) (0x0004+8*(b)) /* maskable wr hi */
103#define ZY7_GPIO_DATA(b) (0x0040+4*(b)) /* in/out data */
104#define ZY7_GPIO_DATA_RO(b) (0x0060+4*(b)) /* input data */
105
106#define ZY7_GPIO_DIRM(b) (0x0204+0x40*(b)) /* direction mode */
107#define ZY7_GPIO_OEN(b) (0x0208+0x40*(b)) /* output enable */
108#define ZY7_GPIO_INT_MASK(b) (0x020c+0x40*(b)) /* int mask */
109#define ZY7_GPIO_INT_EN(b) (0x0210+0x40*(b)) /* int enable */
110#define ZY7_GPIO_INT_DIS(b) (0x0214+0x40*(b)) /* int disable */
111#define ZY7_GPIO_INT_STAT(b) (0x0218+0x40*(b)) /* int status */
112#define ZY7_GPIO_INT_TYPE(b) (0x021c+0x40*(b)) /* int type */
113#define ZY7_GPIO_INT_POLARITY(b) (0x0220+0x40*(b)) /* int polarity */
114#define ZY7_GPIO_INT_ANY(b) (0x0224+0x40*(b)) /* any edge */
115
116
117static int
118zy7_gpio_pin_max(device_t dev, int *maxpin)
119{
120
121 *maxpin = MAXPIN;
122 return (0);
123}
124
125/* Get a specific pin's capabilities. */
126static int
127zy7_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
128{
129
130 if (!VALID_PIN(pin))
131 return (EINVAL);
132
133 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
134
135 return (0);
136}
137
138/* Get a specific pin's name. */
139static int
140zy7_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
141{
142
143 if (!VALID_PIN(pin))
144 return (EINVAL);
145
146 if (pin < NUM_MIO_PINS) {
147 snprintf(name, GPIOMAXNAME, "MIO_%d", pin);
148 name[GPIOMAXNAME - 1] = '\0';
149 } else {
150 snprintf(name, GPIOMAXNAME, "EMIO_%d", pin - EMIO_PIN);
151 name[GPIOMAXNAME - 1] = '\0';
152 }
153
154 return (0);
155}
156
157/* Get a specific pin's current in/out/tri state. */
158static int
159zy7_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
160{
161 struct zy7_gpio_softc *sc = device_get_softc(dev);
162
163 if (!VALID_PIN(pin))
164 return (EINVAL);
165
166 ZGPIO_LOCK(sc);
167
168 if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) {
169 /* output */
170 if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0)
171 *flags = (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
172 else
173 *flags = GPIO_PIN_OUTPUT;
174 } else
175 /* input */
176 *flags = GPIO_PIN_INPUT;
177
178 ZGPIO_UNLOCK(sc);
179
180 return (0);
181}
182
183/* Set a specific pin's in/out/tri state. */
184static int
185zy7_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
186{
187 struct zy7_gpio_softc *sc = device_get_softc(dev);
188
189 if (!VALID_PIN(pin))
190 return (EINVAL);
191
192 ZGPIO_LOCK(sc);
193
194 if ((flags & GPIO_PIN_OUTPUT) != 0) {
195 /* Output. Set or reset OEN too. */
196 WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
197 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31)));
198
199 if ((flags & GPIO_PIN_TRISTATE) != 0)
200 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
201 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) &
202 ~(1 << (pin & 31)));
203 else
204 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
205 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) |
206 (1 << (pin & 31)));
207 } else {
208 /* Input. Turn off OEN. */
209 WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
210 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31)));
211 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
212 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31)));
213 }
214
215 ZGPIO_UNLOCK(sc);
216
217 return (0);
218}
219
220/* Set a specific output pin's value. */
221static int
222zy7_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
223{
224 struct zy7_gpio_softc *sc = device_get_softc(dev);
225
226 if (!VALID_PIN(pin) || value > 1)
227 return (EINVAL);
228
229 /* Fancy register tricks allow atomic set or reset. */
230 if ((pin & 16) != 0)
231 WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5),
232 (0xffff0000 ^ (0x10000 << (pin & 15))) |
233 (value << (pin & 15)));
234 else
235 WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5),
236 (0xffff0000 ^ (0x10000 << (pin & 15))) |
237 (value << (pin & 15)));
238
239 return (0);
240}
241
242/* Get a specific pin's input value. */
243static int
244zy7_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
245{
246 struct zy7_gpio_softc *sc = device_get_softc(dev);
247
248 if (!VALID_PIN(pin))
249 return (EINVAL);
250
251 *value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1;
252
253 return (0);
254}
255
256/* Toggle a pin's output value. */
257static int
258zy7_gpio_pin_toggle(device_t dev, uint32_t pin)
259{
260 struct zy7_gpio_softc *sc = device_get_softc(dev);
261
262 if (!VALID_PIN(pin))
263 return (EINVAL);
264
265 ZGPIO_LOCK(sc);
266
267 WR4(sc, ZY7_GPIO_DATA(pin >> 5),
268 RD4(sc, ZY7_GPIO_DATA(pin >> 5)) ^ (1 << (pin & 31)));
269
270 ZGPIO_UNLOCK(sc);
271
272 return (0);
273}
274
275static int
276zy7_gpio_probe(device_t dev)
277{
278
279 if (!ofw_bus_status_okay(dev))
280 return (ENXIO);
281
282 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_gpio"))
283 return (ENXIO);
284
285 device_set_desc(dev, "Zynq-7000 GPIO driver");
286 return (0);
287}
288
289static void
290zy7_gpio_hw_reset(struct zy7_gpio_softc *sc)
291{
292 int i;
293
294 for (i = 0; i < NUMBANKS; i++) {
295 WR4(sc, ZY7_GPIO_DATA(i), 0);
296 WR4(sc, ZY7_GPIO_DIRM(i), 0);
297 WR4(sc, ZY7_GPIO_OEN(i), 0);
298 WR4(sc, ZY7_GPIO_INT_DIS(i), 0xffffffff);
299 WR4(sc, ZY7_GPIO_INT_POLARITY(i), 0);
300 WR4(sc, ZY7_GPIO_INT_TYPE(i),
301 i == 1 ? 0x003fffff : 0xffffffff);
302 WR4(sc, ZY7_GPIO_INT_ANY(i), 0);
303 WR4(sc, ZY7_GPIO_INT_STAT(i), 0xffffffff);
304 }
305}
306
307static int zy7_gpio_detach(device_t dev);
308
309static int
310zy7_gpio_attach(device_t dev)
311{
312 struct zy7_gpio_softc *sc = device_get_softc(dev);
313 int rid;
314
315 sc->dev = dev;
316
317 ZGPIO_LOCK_INIT(sc);
318
319 /* Allocate memory. */
320 rid = 0;
321 sc->mem_res = bus_alloc_resource_any(dev,
322 SYS_RES_MEMORY, &rid, RF_ACTIVE);
323 if (sc->mem_res == NULL) {
324 device_printf(dev, "Can't allocate memory for device");
325 zy7_gpio_detach(dev);
326 return (ENOMEM);
327 }
328
329 /* Completely reset. */
330 zy7_gpio_hw_reset(sc);
331
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332 device_add_child(dev, "gpioc", device_get_unit(dev));
333 device_add_child(dev, "gpiobus", device_get_unit(dev));
| 332 device_add_child(dev, "gpioc", -1);
333 device_add_child(dev, "gpiobus", -1);
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334
335 return (bus_generic_attach(dev));
336}
337
338static int
339zy7_gpio_detach(device_t dev)
340{
341 struct zy7_gpio_softc *sc = device_get_softc(dev);
342
343 bus_generic_detach(dev);
344
345 if (sc->mem_res != NULL) {
346 /* Release memory resource. */
347 bus_release_resource(dev, SYS_RES_MEMORY,
348 rman_get_rid(sc->mem_res), sc->mem_res);
349 }
350
351 ZGPIO_LOCK_DESTROY(sc);
352
353 return (0);
354}
355
356static device_method_t zy7_gpio_methods[] = {
357 /* device_if */
358 DEVMETHOD(device_probe, zy7_gpio_probe),
359 DEVMETHOD(device_attach, zy7_gpio_attach),
360 DEVMETHOD(device_detach, zy7_gpio_detach),
361
362 /* GPIO protocol */
363 DEVMETHOD(gpio_pin_max, zy7_gpio_pin_max),
364 DEVMETHOD(gpio_pin_getname, zy7_gpio_pin_getname),
365 DEVMETHOD(gpio_pin_getflags, zy7_gpio_pin_getflags),
366 DEVMETHOD(gpio_pin_getcaps, zy7_gpio_pin_getcaps),
367 DEVMETHOD(gpio_pin_setflags, zy7_gpio_pin_setflags),
368 DEVMETHOD(gpio_pin_get, zy7_gpio_pin_get),
369 DEVMETHOD(gpio_pin_set, zy7_gpio_pin_set),
370 DEVMETHOD(gpio_pin_toggle, zy7_gpio_pin_toggle),
371
372 DEVMETHOD_END
373};
374
375static driver_t zy7_gpio_driver = {
376 "zy7_gpio",
377 zy7_gpio_methods,
378 sizeof(struct zy7_gpio_softc),
379};
380static devclass_t zy7_gpio_devclass;
381
382extern devclass_t gpiobus_devclass, gpioc_devclass;
383extern driver_t gpiobus_driver, gpioc_driver;
384
385DRIVER_MODULE(zy7_gpio, simplebus, zy7_gpio_driver, zy7_gpio_devclass, \
386 NULL, NULL);
387DRIVER_MODULE(gpiobus, zy7_gpio, gpiobus_driver, gpiobus_devclass, 0, 0);
388DRIVER_MODULE(gpioc, zy7_gpio, gpioc_driver, gpioc_devclass, 0, 0);
| 334
335 return (bus_generic_attach(dev));
336}
337
338static int
339zy7_gpio_detach(device_t dev)
340{
341 struct zy7_gpio_softc *sc = device_get_softc(dev);
342
343 bus_generic_detach(dev);
344
345 if (sc->mem_res != NULL) {
346 /* Release memory resource. */
347 bus_release_resource(dev, SYS_RES_MEMORY,
348 rman_get_rid(sc->mem_res), sc->mem_res);
349 }
350
351 ZGPIO_LOCK_DESTROY(sc);
352
353 return (0);
354}
355
356static device_method_t zy7_gpio_methods[] = {
357 /* device_if */
358 DEVMETHOD(device_probe, zy7_gpio_probe),
359 DEVMETHOD(device_attach, zy7_gpio_attach),
360 DEVMETHOD(device_detach, zy7_gpio_detach),
361
362 /* GPIO protocol */
363 DEVMETHOD(gpio_pin_max, zy7_gpio_pin_max),
364 DEVMETHOD(gpio_pin_getname, zy7_gpio_pin_getname),
365 DEVMETHOD(gpio_pin_getflags, zy7_gpio_pin_getflags),
366 DEVMETHOD(gpio_pin_getcaps, zy7_gpio_pin_getcaps),
367 DEVMETHOD(gpio_pin_setflags, zy7_gpio_pin_setflags),
368 DEVMETHOD(gpio_pin_get, zy7_gpio_pin_get),
369 DEVMETHOD(gpio_pin_set, zy7_gpio_pin_set),
370 DEVMETHOD(gpio_pin_toggle, zy7_gpio_pin_toggle),
371
372 DEVMETHOD_END
373};
374
375static driver_t zy7_gpio_driver = {
376 "zy7_gpio",
377 zy7_gpio_methods,
378 sizeof(struct zy7_gpio_softc),
379};
380static devclass_t zy7_gpio_devclass;
381
382extern devclass_t gpiobus_devclass, gpioc_devclass;
383extern driver_t gpiobus_driver, gpioc_driver;
384
385DRIVER_MODULE(zy7_gpio, simplebus, zy7_gpio_driver, zy7_gpio_devclass, \
386 NULL, NULL);
387DRIVER_MODULE(gpiobus, zy7_gpio, gpiobus_driver, gpiobus_devclass, 0, 0);
388DRIVER_MODULE(gpioc, zy7_gpio, gpioc_driver, gpioc_devclass, 0, 0);
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