44
45#include <sys/param.h>
46#include <sys/systm.h>
47#include <sys/bus.h>
48
49#include <sys/kernel.h>
50#include <sys/module.h>
51#include <sys/rman.h>
52#include <sys/lock.h>
53#include <sys/mutex.h>
54#include <sys/gpio.h>
55
56#include <machine/bus.h>
57#include <machine/resource.h>
58
59#include <arm/ti/ti_scm.h>
60#include <arm/ti/ti_prcm.h>
61
62#include <dev/fdt/fdt_common.h>
63#include <dev/ofw/openfirm.h>
64#include <dev/ofw/ofw_bus.h>
65#include <dev/ofw/ofw_bus_subr.h>
66
67#include "gpio_if.h"
68
69/* Register definitions */
70#define TI_GPIO_REVISION 0x0000
71#define TI_GPIO_SYSCONFIG 0x0010
72#if defined(SOC_OMAP3)
73#define TI_GPIO_SYSSTATUS 0x0014
74#define TI_GPIO_IRQSTATUS1 0x0018
75#define TI_GPIO_IRQENABLE1 0x001C
76#define TI_GPIO_WAKEUPENABLE 0x0020
77#define TI_GPIO_IRQSTATUS2 0x0028
78#define TI_GPIO_IRQENABLE2 0x002C
79#define TI_GPIO_CTRL 0x0030
80#define TI_GPIO_OE 0x0034
81#define TI_GPIO_DATAIN 0x0038
82#define TI_GPIO_DATAOUT 0x003C
83#define TI_GPIO_LEVELDETECT0 0x0040
84#define TI_GPIO_LEVELDETECT1 0x0044
85#define TI_GPIO_RISINGDETECT 0x0048
86#define TI_GPIO_FALLINGDETECT 0x004C
87#define TI_GPIO_DEBOUNCENABLE 0x0050
88#define TI_GPIO_DEBOUNCINGTIME 0x0054
89#define TI_GPIO_CLEARIRQENABLE1 0x0060
90#define TI_GPIO_SETIRQENABLE1 0x0064
91#define TI_GPIO_CLEARIRQENABLE2 0x0070
92#define TI_GPIO_SETIRQENABLE2 0x0074
93#define TI_GPIO_CLEARWKUENA 0x0080
94#define TI_GPIO_SETWKUENA 0x0084
95#define TI_GPIO_CLEARDATAOUT 0x0090
96#define TI_GPIO_SETDATAOUT 0x0094
97#elif defined(SOC_OMAP4) || defined(SOC_TI_AM335X)
98#define TI_GPIO_IRQSTATUS_RAW_0 0x0024
99#define TI_GPIO_IRQSTATUS_RAW_1 0x0028
100#define TI_GPIO_IRQSTATUS_0 0x002C
101#define TI_GPIO_IRQSTATUS_1 0x0030
102#define TI_GPIO_IRQSTATUS_SET_0 0x0034
103#define TI_GPIO_IRQSTATUS_SET_1 0x0038
104#define TI_GPIO_IRQSTATUS_CLR_0 0x003C
105#define TI_GPIO_IRQSTATUS_CLR_1 0x0040
106#define TI_GPIO_IRQWAKEN_0 0x0044
107#define TI_GPIO_IRQWAKEN_1 0x0048
108#define TI_GPIO_SYSSTATUS 0x0114
109#define TI_GPIO_IRQSTATUS1 0x0118
110#define TI_GPIO_IRQENABLE1 0x011C
111#define TI_GPIO_WAKEUPENABLE 0x0120
112#define TI_GPIO_IRQSTATUS2 0x0128
113#define TI_GPIO_IRQENABLE2 0x012C
114#define TI_GPIO_CTRL 0x0130
115#define TI_GPIO_OE 0x0134
116#define TI_GPIO_DATAIN 0x0138
117#define TI_GPIO_DATAOUT 0x013C
118#define TI_GPIO_LEVELDETECT0 0x0140
119#define TI_GPIO_LEVELDETECT1 0x0144
120#define TI_GPIO_RISINGDETECT 0x0148
121#define TI_GPIO_FALLINGDETECT 0x014C
122#define TI_GPIO_DEBOUNCENABLE 0x0150
123#define TI_GPIO_DEBOUNCINGTIME 0x0154
124#define TI_GPIO_CLEARWKUPENA 0x0180
125#define TI_GPIO_SETWKUENA 0x0184
126#define TI_GPIO_CLEARDATAOUT 0x0190
127#define TI_GPIO_SETDATAOUT 0x0194
128#else
129#error "Unknown SoC"
130#endif
131
132/* Other SoC Specific definitions */
133#if defined(SOC_OMAP3)
134#define MAX_GPIO_BANKS 6
135#define FIRST_GPIO_BANK 1
136#define INTR_PER_BANK 1
137#define TI_GPIO_REV 0x00000025
138#elif defined(SOC_OMAP4)
139#define MAX_GPIO_BANKS 6
140#define FIRST_GPIO_BANK 1
141#define INTR_PER_BANK 1
142#define TI_GPIO_REV 0x50600801
143#elif defined(SOC_TI_AM335X)
144#define MAX_GPIO_BANKS 4
145#define FIRST_GPIO_BANK 0
146#define INTR_PER_BANK 2
147#define TI_GPIO_REV 0x50600801
148#endif
149#define PINS_PER_BANK 32
150#define MAX_GPIO_INTRS MAX_GPIO_BANKS * INTR_PER_BANK
151
152/**
153 * ti_gpio_mem_spec - Resource specification used when allocating resources
154 * ti_gpio_irq_spec - Resource specification used when allocating resources
155 *
156 * This driver module can have up to six independent memory regions, each
157 * region typically controls 32 GPIO pins.
158 *
159 * On OMAP3 and OMAP4 there is only one physical interrupt line per bank,
160 * but there are two set of registers which control the interrupt delivery
161 * to internal subsystems. The first set of registers control the
162 * interrupts delivery to the MPU and the second set control the
163 * interrupts delivery to the DSP.
164 *
165 * On AM335x there are two physical interrupt lines for each GPIO module.
166 * Each interrupt line is controlled by a set of registers.
167 */
168static struct resource_spec ti_gpio_mem_spec[] = {
169 { SYS_RES_MEMORY, 0, RF_ACTIVE },
170 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL },
171 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL },
172 { SYS_RES_MEMORY, 3, RF_ACTIVE | RF_OPTIONAL },
173#if !defined(SOC_TI_AM335X)
174 { SYS_RES_MEMORY, 4, RF_ACTIVE | RF_OPTIONAL },
175 { SYS_RES_MEMORY, 5, RF_ACTIVE | RF_OPTIONAL },
176#endif
177 { -1, 0, 0 }
178};
179static struct resource_spec ti_gpio_irq_spec[] = {
180 { SYS_RES_IRQ, 0, RF_ACTIVE },
181 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL },
182 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL },
183 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL },
184 { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL },
185 { SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL },
186#if defined(SOC_TI_AM335X)
187 { SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL },
188 { SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL },
189#endif
190 { -1, 0, 0 }
191};
192
193/**
194 * Structure that stores the driver context.
195 *
196 * This structure is allocated during driver attach.
197 */
198struct ti_gpio_softc {
199 device_t sc_dev;
200
201 /*
202 * The memory resource(s) for the PRCM register set, when the device is
203 * created the caller can assign up to 6 memory regions depending on
204 * the SoC type.
205 */
206 struct resource *sc_mem_res[MAX_GPIO_BANKS];
207 struct resource *sc_irq_res[MAX_GPIO_INTRS];
208
209 /* The handle for the register IRQ handlers. */
210 void *sc_irq_hdl[MAX_GPIO_INTRS];
211
212 /*
213 * The following describes the H/W revision of each of the GPIO banks.
214 */
215 uint32_t sc_revision[MAX_GPIO_BANKS];
216
217 struct mtx sc_mtx;
218};
219
220/**
221 * Macros for driver mutex locking
222 */
223#define TI_GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
224#define TI_GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
225#define TI_GPIO_LOCK_INIT(_sc) \
226 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
227 "ti_gpio", MTX_DEF)
228#define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
229#define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
230#define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
231
232/**
233 * ti_gpio_read_4 - reads a 16-bit value from one of the PADCONFS registers
234 * @sc: GPIO device context
235 * @bank: The bank to read from
236 * @off: The offset of a register from the GPIO register address range
237 *
238 *
239 * RETURNS:
240 * 32-bit value read from the register.
241 */
242static inline uint32_t
243ti_gpio_read_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off)
244{
245 return (bus_read_4(sc->sc_mem_res[bank], off));
246}
247
248/**
249 * ti_gpio_write_4 - writes a 32-bit value to one of the PADCONFS registers
250 * @sc: GPIO device context
251 * @bank: The bank to write to
252 * @off: The offset of a register from the GPIO register address range
253 * @val: The value to write into the register
254 *
255 * RETURNS:
256 * nothing
257 */
258static inline void
259ti_gpio_write_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off,
260 uint32_t val)
261{
262 bus_write_4(sc->sc_mem_res[bank], off, val);
263}
264
265static inline void
266ti_gpio_intr_clr(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask)
267{
268
269 /* We clear both set of registers. */
270#if defined(SOC_OMAP4) || defined(SOC_TI_AM335X)
271 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_0, mask);
272 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_1, mask);
273#else
274 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE1, mask);
275 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE2, mask);
276#endif
277}
278
279/**
280 * ti_gpio_pin_max - Returns the maximum number of GPIO pins
281 * @dev: gpio device handle
282 * @maxpin: pointer to a value that upon return will contain the maximum number
283 * of pins in the device.
284 *
285 *
286 * LOCKING:
287 * Internally locks the context
288 *
289 * RETURNS:
290 * Returns 0 on success otherwise an error code
291 */
292static int
293ti_gpio_pin_max(device_t dev, int *maxpin)
294{
295 struct ti_gpio_softc *sc = device_get_softc(dev);
296 unsigned int i;
297 unsigned int banks = 0;
298
299 TI_GPIO_LOCK(sc);
300
301 /* Calculate how many valid banks we have and then multiply that by 32 to
302 * give use the total number of pins.
303 */
304 for (i = 0; i < MAX_GPIO_BANKS; i++) {
305 if (sc->sc_mem_res[i] != NULL)
306 banks++;
307 }
308
309 *maxpin = (banks * PINS_PER_BANK) - 1;
310
311 TI_GPIO_UNLOCK(sc);
312
313 return (0);
314}
315
316/**
317 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin
318 * @dev: gpio device handle
319 * @pin: the number of the pin
320 * @caps: pointer to a value that upon return will contain the capabilities
321 *
322 * Currently all pins have the same capability, notably:
323 * - GPIO_PIN_INPUT
324 * - GPIO_PIN_OUTPUT
325 * - GPIO_PIN_PULLUP
326 * - GPIO_PIN_PULLDOWN
327 *
328 * LOCKING:
329 * Internally locks the context
330 *
331 * RETURNS:
332 * Returns 0 on success otherwise an error code
333 */
334static int
335ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
336{
337 struct ti_gpio_softc *sc = device_get_softc(dev);
338 uint32_t bank = (pin / PINS_PER_BANK);
339
340 TI_GPIO_LOCK(sc);
341
342 /* Sanity check the pin number is valid */
343 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
344 TI_GPIO_UNLOCK(sc);
345 return (EINVAL);
346 }
347
348 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |GPIO_PIN_PULLUP |
349 GPIO_PIN_PULLDOWN);
350
351 TI_GPIO_UNLOCK(sc);
352
353 return (0);
354}
355
356/**
357 * ti_gpio_pin_getflags - Gets the current flags of a given pin
358 * @dev: gpio device handle
359 * @pin: the number of the pin
360 * @flags: upon return will contain the current flags of the pin
361 *
362 * Reads the current flags of a given pin, here we actually read the H/W
363 * registers to determine the flags, rather than storing the value in the
364 * setflags call.
365 *
366 * LOCKING:
367 * Internally locks the context
368 *
369 * RETURNS:
370 * Returns 0 on success otherwise an error code
371 */
372static int
373ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
374{
375 struct ti_gpio_softc *sc = device_get_softc(dev);
376 uint32_t bank = (pin / PINS_PER_BANK);
377
378 TI_GPIO_LOCK(sc);
379
380 /* Sanity check the pin number is valid */
381 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
382 TI_GPIO_UNLOCK(sc);
383 return (EINVAL);
384 }
385
386 /* Get the current pin state */
387 ti_scm_padconf_get_gpioflags(pin, flags);
388
389 TI_GPIO_UNLOCK(sc);
390
391 return (0);
392}
393
394/**
395 * ti_gpio_pin_getname - Gets the name of a given pin
396 * @dev: gpio device handle
397 * @pin: the number of the pin
398 * @name: buffer to put the name in
399 *
400 * The driver simply calls the pins gpio_n, where 'n' is obviously the number
401 * of the pin.
402 *
403 * LOCKING:
404 * Internally locks the context
405 *
406 * RETURNS:
407 * Returns 0 on success otherwise an error code
408 */
409static int
410ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
411{
412 struct ti_gpio_softc *sc = device_get_softc(dev);
413 uint32_t bank = (pin / PINS_PER_BANK);
414
415 TI_GPIO_LOCK(sc);
416
417 /* Sanity check the pin number is valid */
418 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
419 TI_GPIO_UNLOCK(sc);
420 return (EINVAL);
421 }
422
423 /* Set a very simple name */
424 snprintf(name, GPIOMAXNAME, "gpio_%u", pin);
425 name[GPIOMAXNAME - 1] = '\0';
426
427 TI_GPIO_UNLOCK(sc);
428
429 return (0);
430}
431
432/**
433 * ti_gpio_pin_setflags - Sets the flags for a given pin
434 * @dev: gpio device handle
435 * @pin: the number of the pin
436 * @flags: the flags to set
437 *
438 * The flags of the pin correspond to things like input/output mode, pull-ups,
439 * pull-downs, etc. This driver doesn't support all flags, only the following:
440 * - GPIO_PIN_INPUT
441 * - GPIO_PIN_OUTPUT
442 * - GPIO_PIN_PULLUP
443 * - GPIO_PIN_PULLDOWN
444 *
445 * LOCKING:
446 * Internally locks the context
447 *
448 * RETURNS:
449 * Returns 0 on success otherwise an error code
450 */
451static int
452ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
453{
454 struct ti_gpio_softc *sc = device_get_softc(dev);
455 uint32_t bank = (pin / PINS_PER_BANK);
456 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
457 uint32_t reg_val;
458
459 /* Sanity check the flags supplied are valid, i.e. not input and output */
460 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0x0000)
461 return (EINVAL);
462 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) ==
463 (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT))
464 return (EINVAL);
465 if ((flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) ==
466 (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN))
467 return (EINVAL);
468
469 TI_GPIO_LOCK(sc);
470
471 /* Sanity check the pin number is valid */
472 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
473 TI_GPIO_UNLOCK(sc);
474 return (EINVAL);
475 }
476
477 /* Set the GPIO mode and state */
478 if (ti_scm_padconf_set_gpioflags(pin, flags) != 0) {
479 TI_GPIO_UNLOCK(sc);
480 return (EINVAL);
481 }
482
483 /* If configuring as an output set the "output enable" bit */
484 reg_val = ti_gpio_read_4(sc, bank, TI_GPIO_OE);
485 if (flags & GPIO_PIN_INPUT)
486 reg_val |= mask;
487 else
488 reg_val &= ~mask;
489 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_val);
490
491 TI_GPIO_UNLOCK(sc);
492
493 return (0);
494}
495
496/**
497 * ti_gpio_pin_set - Sets the current level on a GPIO pin
498 * @dev: gpio device handle
499 * @pin: the number of the pin
500 * @value: non-zero value will drive the pin high, otherwise the pin is
501 * driven low.
502 *
503 *
504 * LOCKING:
505 * Internally locks the context
506 *
507 * RETURNS:
508 * Returns 0 on success otherwise a error code
509 */
510static int
511ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
512{
513 struct ti_gpio_softc *sc = device_get_softc(dev);
514 uint32_t bank = (pin / PINS_PER_BANK);
515 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
516
517 TI_GPIO_LOCK(sc);
518
519 /* Sanity check the pin number is valid */
520 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
521 TI_GPIO_UNLOCK(sc);
522 return (EINVAL);
523 }
524
525 ti_gpio_write_4(sc, bank, (value == GPIO_PIN_LOW) ? TI_GPIO_CLEARDATAOUT
526 : TI_GPIO_SETDATAOUT, mask);
527
528 TI_GPIO_UNLOCK(sc);
529
530 return (0);
531}
532
533/**
534 * ti_gpio_pin_get - Gets the current level on a GPIO pin
535 * @dev: gpio device handle
536 * @pin: the number of the pin
537 * @value: pointer to a value that upond return will contain the pin value
538 *
539 * The pin must be configured as an input pin beforehand, otherwise this
540 * function will fail.
541 *
542 * LOCKING:
543 * Internally locks the context
544 *
545 * RETURNS:
546 * Returns 0 on success otherwise a error code
547 */
548static int
549ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
550{
551 struct ti_gpio_softc *sc = device_get_softc(dev);
552 uint32_t bank = (pin / PINS_PER_BANK);
553 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
554 uint32_t val = 0;
555
556 TI_GPIO_LOCK(sc);
557
558 /* Sanity check the pin number is valid */
559 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
560 TI_GPIO_UNLOCK(sc);
561 return (EINVAL);
562 }
563
564 /* Sanity check the pin is not configured as an output */
565 val = ti_gpio_read_4(sc, bank, TI_GPIO_OE);
566
567 /* Read the value on the pin */
568 if (val & mask)
569 *value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAIN) & mask) ? 1 : 0;
570 else
571 *value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT) & mask) ? 1 : 0;
572
573 TI_GPIO_UNLOCK(sc);
574
575 return (0);
576}
577
578/**
579 * ti_gpio_pin_toggle - Toggles a given GPIO pin
580 * @dev: gpio device handle
581 * @pin: the number of the pin
582 *
583 *
584 * LOCKING:
585 * Internally locks the context
586 *
587 * RETURNS:
588 * Returns 0 on success otherwise a error code
589 */
590static int
591ti_gpio_pin_toggle(device_t dev, uint32_t pin)
592{
593 struct ti_gpio_softc *sc = device_get_softc(dev);
594 uint32_t bank = (pin / PINS_PER_BANK);
595 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
596 uint32_t val;
597
598 TI_GPIO_LOCK(sc);
599
600 /* Sanity check the pin number is valid */
601 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
602 TI_GPIO_UNLOCK(sc);
603 return (EINVAL);
604 }
605
606 /* Toggle the pin */
607 val = ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT);
608 if (val & mask)
609 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARDATAOUT, mask);
610 else
611 ti_gpio_write_4(sc, bank, TI_GPIO_SETDATAOUT, mask);
612
613 TI_GPIO_UNLOCK(sc);
614
615 return (0);
616}
617
618/**
619 * ti_gpio_intr - ISR for all GPIO modules
620 * @arg: the soft context pointer
621 *
622 * Unsused
623 *
624 * LOCKING:
625 * Internally locks the context
626 *
627 */
628static void
629ti_gpio_intr(void *arg)
630{
631 struct ti_gpio_softc *sc = arg;
632
633 TI_GPIO_LOCK(sc);
634 /* TODO: something useful */
635 TI_GPIO_UNLOCK(sc);
636}
637
638/**
639 * ti_gpio_probe - probe function for the driver
640 * @dev: gpio device handle
641 *
642 * Simply sets the name of the driver
643 *
644 * LOCKING:
645 * None
646 *
647 * RETURNS:
648 * Always returns 0
649 */
650static int
651ti_gpio_probe(device_t dev)
652{
653
654 if (!ofw_bus_status_okay(dev))
655 return (ENXIO);
656
657 if (!ofw_bus_is_compatible(dev, "ti,gpio"))
658 return (ENXIO);
659
660 device_set_desc(dev, "TI General Purpose I/O (GPIO)");
661
662 return (0);
663}
664
665static int
666ti_gpio_attach_intr(device_t dev)
667{
668 int i;
669 struct ti_gpio_softc *sc;
670
671 sc = device_get_softc(dev);
672 for (i = 0; i < MAX_GPIO_INTRS; i++) {
673 if (sc->sc_irq_res[i] == NULL)
674 break;
675
676 /*
677 * Register our interrupt handler for each of the IRQ resources.
678 */
679 if (bus_setup_intr(dev, sc->sc_irq_res[i],
680 INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_gpio_intr, sc,
681 &sc->sc_irq_hdl[i]) != 0) {
682 device_printf(dev,
683 "WARNING: unable to register interrupt handler\n");
684 return (-1);
685 }
686 }
687
688 return (0);
689}
690
691static int
692ti_gpio_detach_intr(device_t dev)
693{
694 int i;
695 struct ti_gpio_softc *sc;
696
697 /* Teardown our interrupt handlers. */
698 sc = device_get_softc(dev);
699 for (i = 0; i < MAX_GPIO_INTRS; i++) {
700 if (sc->sc_irq_res[i] == NULL)
701 break;
702
703 if (sc->sc_irq_hdl[i]) {
704 bus_teardown_intr(dev, sc->sc_irq_res[i],
705 sc->sc_irq_hdl[i]);
706 }
707 }
708
709 return (0);
710}
711
712static int
713ti_gpio_bank_init(device_t dev, int bank)
714{
715 int pin;
716 struct ti_gpio_softc *sc;
717 uint32_t flags, reg_oe;
718
719 sc = device_get_softc(dev);
720
721 /* Enable the interface and functional clocks for the module. */
722 ti_prcm_clk_enable(GPIO0_CLK + FIRST_GPIO_BANK + bank);
723
724 /*
725 * Read the revision number of the module. TI don't publish the
726 * actual revision numbers, so instead the values have been
727 * determined by experimentation.
728 */
729 sc->sc_revision[bank] = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION);
730
731 /* Check the revision. */
732 if (sc->sc_revision[bank] != TI_GPIO_REV) {
733 device_printf(dev, "Warning: could not determine the revision "
734 "of %u GPIO module (revision:0x%08x)\n",
735 bank, sc->sc_revision[bank]);
736 return (EINVAL);
737 }
738
739 /* Disable interrupts for all pins. */
740 ti_gpio_intr_clr(sc, bank, 0xffffffff);
741
742 /* Init OE register based on pads configuration. */
743 reg_oe = 0xffffffff;
744 for (pin = 0; pin < PINS_PER_BANK; pin++) {
745 ti_scm_padconf_get_gpioflags(PINS_PER_BANK * bank + pin,
746 &flags);
747 if (flags & GPIO_PIN_OUTPUT)
748 reg_oe &= ~(1UL << pin);
749 }
750 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe);
751
752 return (0);
753}
754
755/**
756 * ti_gpio_attach - attach function for the driver
757 * @dev: gpio device handle
758 *
759 * Allocates and sets up the driver context for all GPIO banks. This function
760 * expects the memory ranges and IRQs to already be allocated to the driver.
761 *
762 * LOCKING:
763 * None
764 *
765 * RETURNS:
766 * Always returns 0
767 */
768static int
769ti_gpio_attach(device_t dev)
770{
771 struct ti_gpio_softc *sc;
772 unsigned int i;
773 int err;
774
775 sc = device_get_softc(dev);
776 sc->sc_dev = dev;
777
778 TI_GPIO_LOCK_INIT(sc);
779
780 /* There are up to 6 different GPIO register sets located in different
781 * memory areas on the chip. The memory range should have been set for
782 * the driver when it was added as a child.
783 */
784 if (bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res) != 0) {
785 device_printf(dev, "Error: could not allocate mem resources\n");
786 return (ENXIO);
787 }
788
789 /* Request the IRQ resources */
790 if (bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res) != 0) {
791 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
792 device_printf(dev, "Error: could not allocate irq resources\n");
793 return (ENXIO);
794 }
795
796 /* Setup the IRQ resources */
797 if (ti_gpio_attach_intr(dev) != 0) {
798 ti_gpio_detach_intr(dev);
799 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
800 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
801 return (ENXIO);
802 }
803
804 /* We need to go through each block and ensure the clocks are running and
805 * the module is enabled. It might be better to do this only when the
806 * pins are configured which would result in less power used if the GPIO
807 * pins weren't used ...
808 */
809 for (i = 0; i < MAX_GPIO_BANKS; i++) {
810 if (sc->sc_mem_res[i] != NULL) {
811 /* Initialize the GPIO module. */
812 err = ti_gpio_bank_init(dev, i);
813 if (err != 0) {
814 ti_gpio_detach_intr(dev);
815 bus_release_resources(dev, ti_gpio_irq_spec,
816 sc->sc_irq_res);
817 bus_release_resources(dev, ti_gpio_mem_spec,
818 sc->sc_mem_res);
819 return (err);
820 }
821 }
822 }
823
824 /* Finish of the probe call */
| 44
45#include <sys/param.h>
46#include <sys/systm.h>
47#include <sys/bus.h>
48
49#include <sys/kernel.h>
50#include <sys/module.h>
51#include <sys/rman.h>
52#include <sys/lock.h>
53#include <sys/mutex.h>
54#include <sys/gpio.h>
55
56#include <machine/bus.h>
57#include <machine/resource.h>
58
59#include <arm/ti/ti_scm.h>
60#include <arm/ti/ti_prcm.h>
61
62#include <dev/fdt/fdt_common.h>
63#include <dev/ofw/openfirm.h>
64#include <dev/ofw/ofw_bus.h>
65#include <dev/ofw/ofw_bus_subr.h>
66
67#include "gpio_if.h"
68
69/* Register definitions */
70#define TI_GPIO_REVISION 0x0000
71#define TI_GPIO_SYSCONFIG 0x0010
72#if defined(SOC_OMAP3)
73#define TI_GPIO_SYSSTATUS 0x0014
74#define TI_GPIO_IRQSTATUS1 0x0018
75#define TI_GPIO_IRQENABLE1 0x001C
76#define TI_GPIO_WAKEUPENABLE 0x0020
77#define TI_GPIO_IRQSTATUS2 0x0028
78#define TI_GPIO_IRQENABLE2 0x002C
79#define TI_GPIO_CTRL 0x0030
80#define TI_GPIO_OE 0x0034
81#define TI_GPIO_DATAIN 0x0038
82#define TI_GPIO_DATAOUT 0x003C
83#define TI_GPIO_LEVELDETECT0 0x0040
84#define TI_GPIO_LEVELDETECT1 0x0044
85#define TI_GPIO_RISINGDETECT 0x0048
86#define TI_GPIO_FALLINGDETECT 0x004C
87#define TI_GPIO_DEBOUNCENABLE 0x0050
88#define TI_GPIO_DEBOUNCINGTIME 0x0054
89#define TI_GPIO_CLEARIRQENABLE1 0x0060
90#define TI_GPIO_SETIRQENABLE1 0x0064
91#define TI_GPIO_CLEARIRQENABLE2 0x0070
92#define TI_GPIO_SETIRQENABLE2 0x0074
93#define TI_GPIO_CLEARWKUENA 0x0080
94#define TI_GPIO_SETWKUENA 0x0084
95#define TI_GPIO_CLEARDATAOUT 0x0090
96#define TI_GPIO_SETDATAOUT 0x0094
97#elif defined(SOC_OMAP4) || defined(SOC_TI_AM335X)
98#define TI_GPIO_IRQSTATUS_RAW_0 0x0024
99#define TI_GPIO_IRQSTATUS_RAW_1 0x0028
100#define TI_GPIO_IRQSTATUS_0 0x002C
101#define TI_GPIO_IRQSTATUS_1 0x0030
102#define TI_GPIO_IRQSTATUS_SET_0 0x0034
103#define TI_GPIO_IRQSTATUS_SET_1 0x0038
104#define TI_GPIO_IRQSTATUS_CLR_0 0x003C
105#define TI_GPIO_IRQSTATUS_CLR_1 0x0040
106#define TI_GPIO_IRQWAKEN_0 0x0044
107#define TI_GPIO_IRQWAKEN_1 0x0048
108#define TI_GPIO_SYSSTATUS 0x0114
109#define TI_GPIO_IRQSTATUS1 0x0118
110#define TI_GPIO_IRQENABLE1 0x011C
111#define TI_GPIO_WAKEUPENABLE 0x0120
112#define TI_GPIO_IRQSTATUS2 0x0128
113#define TI_GPIO_IRQENABLE2 0x012C
114#define TI_GPIO_CTRL 0x0130
115#define TI_GPIO_OE 0x0134
116#define TI_GPIO_DATAIN 0x0138
117#define TI_GPIO_DATAOUT 0x013C
118#define TI_GPIO_LEVELDETECT0 0x0140
119#define TI_GPIO_LEVELDETECT1 0x0144
120#define TI_GPIO_RISINGDETECT 0x0148
121#define TI_GPIO_FALLINGDETECT 0x014C
122#define TI_GPIO_DEBOUNCENABLE 0x0150
123#define TI_GPIO_DEBOUNCINGTIME 0x0154
124#define TI_GPIO_CLEARWKUPENA 0x0180
125#define TI_GPIO_SETWKUENA 0x0184
126#define TI_GPIO_CLEARDATAOUT 0x0190
127#define TI_GPIO_SETDATAOUT 0x0194
128#else
129#error "Unknown SoC"
130#endif
131
132/* Other SoC Specific definitions */
133#if defined(SOC_OMAP3)
134#define MAX_GPIO_BANKS 6
135#define FIRST_GPIO_BANK 1
136#define INTR_PER_BANK 1
137#define TI_GPIO_REV 0x00000025
138#elif defined(SOC_OMAP4)
139#define MAX_GPIO_BANKS 6
140#define FIRST_GPIO_BANK 1
141#define INTR_PER_BANK 1
142#define TI_GPIO_REV 0x50600801
143#elif defined(SOC_TI_AM335X)
144#define MAX_GPIO_BANKS 4
145#define FIRST_GPIO_BANK 0
146#define INTR_PER_BANK 2
147#define TI_GPIO_REV 0x50600801
148#endif
149#define PINS_PER_BANK 32
150#define MAX_GPIO_INTRS MAX_GPIO_BANKS * INTR_PER_BANK
151
152/**
153 * ti_gpio_mem_spec - Resource specification used when allocating resources
154 * ti_gpio_irq_spec - Resource specification used when allocating resources
155 *
156 * This driver module can have up to six independent memory regions, each
157 * region typically controls 32 GPIO pins.
158 *
159 * On OMAP3 and OMAP4 there is only one physical interrupt line per bank,
160 * but there are two set of registers which control the interrupt delivery
161 * to internal subsystems. The first set of registers control the
162 * interrupts delivery to the MPU and the second set control the
163 * interrupts delivery to the DSP.
164 *
165 * On AM335x there are two physical interrupt lines for each GPIO module.
166 * Each interrupt line is controlled by a set of registers.
167 */
168static struct resource_spec ti_gpio_mem_spec[] = {
169 { SYS_RES_MEMORY, 0, RF_ACTIVE },
170 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL },
171 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL },
172 { SYS_RES_MEMORY, 3, RF_ACTIVE | RF_OPTIONAL },
173#if !defined(SOC_TI_AM335X)
174 { SYS_RES_MEMORY, 4, RF_ACTIVE | RF_OPTIONAL },
175 { SYS_RES_MEMORY, 5, RF_ACTIVE | RF_OPTIONAL },
176#endif
177 { -1, 0, 0 }
178};
179static struct resource_spec ti_gpio_irq_spec[] = {
180 { SYS_RES_IRQ, 0, RF_ACTIVE },
181 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL },
182 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL },
183 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL },
184 { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL },
185 { SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL },
186#if defined(SOC_TI_AM335X)
187 { SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL },
188 { SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL },
189#endif
190 { -1, 0, 0 }
191};
192
193/**
194 * Structure that stores the driver context.
195 *
196 * This structure is allocated during driver attach.
197 */
198struct ti_gpio_softc {
199 device_t sc_dev;
200
201 /*
202 * The memory resource(s) for the PRCM register set, when the device is
203 * created the caller can assign up to 6 memory regions depending on
204 * the SoC type.
205 */
206 struct resource *sc_mem_res[MAX_GPIO_BANKS];
207 struct resource *sc_irq_res[MAX_GPIO_INTRS];
208
209 /* The handle for the register IRQ handlers. */
210 void *sc_irq_hdl[MAX_GPIO_INTRS];
211
212 /*
213 * The following describes the H/W revision of each of the GPIO banks.
214 */
215 uint32_t sc_revision[MAX_GPIO_BANKS];
216
217 struct mtx sc_mtx;
218};
219
220/**
221 * Macros for driver mutex locking
222 */
223#define TI_GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
224#define TI_GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
225#define TI_GPIO_LOCK_INIT(_sc) \
226 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
227 "ti_gpio", MTX_DEF)
228#define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
229#define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
230#define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
231
232/**
233 * ti_gpio_read_4 - reads a 16-bit value from one of the PADCONFS registers
234 * @sc: GPIO device context
235 * @bank: The bank to read from
236 * @off: The offset of a register from the GPIO register address range
237 *
238 *
239 * RETURNS:
240 * 32-bit value read from the register.
241 */
242static inline uint32_t
243ti_gpio_read_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off)
244{
245 return (bus_read_4(sc->sc_mem_res[bank], off));
246}
247
248/**
249 * ti_gpio_write_4 - writes a 32-bit value to one of the PADCONFS registers
250 * @sc: GPIO device context
251 * @bank: The bank to write to
252 * @off: The offset of a register from the GPIO register address range
253 * @val: The value to write into the register
254 *
255 * RETURNS:
256 * nothing
257 */
258static inline void
259ti_gpio_write_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off,
260 uint32_t val)
261{
262 bus_write_4(sc->sc_mem_res[bank], off, val);
263}
264
265static inline void
266ti_gpio_intr_clr(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask)
267{
268
269 /* We clear both set of registers. */
270#if defined(SOC_OMAP4) || defined(SOC_TI_AM335X)
271 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_0, mask);
272 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_1, mask);
273#else
274 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE1, mask);
275 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE2, mask);
276#endif
277}
278
279/**
280 * ti_gpio_pin_max - Returns the maximum number of GPIO pins
281 * @dev: gpio device handle
282 * @maxpin: pointer to a value that upon return will contain the maximum number
283 * of pins in the device.
284 *
285 *
286 * LOCKING:
287 * Internally locks the context
288 *
289 * RETURNS:
290 * Returns 0 on success otherwise an error code
291 */
292static int
293ti_gpio_pin_max(device_t dev, int *maxpin)
294{
295 struct ti_gpio_softc *sc = device_get_softc(dev);
296 unsigned int i;
297 unsigned int banks = 0;
298
299 TI_GPIO_LOCK(sc);
300
301 /* Calculate how many valid banks we have and then multiply that by 32 to
302 * give use the total number of pins.
303 */
304 for (i = 0; i < MAX_GPIO_BANKS; i++) {
305 if (sc->sc_mem_res[i] != NULL)
306 banks++;
307 }
308
309 *maxpin = (banks * PINS_PER_BANK) - 1;
310
311 TI_GPIO_UNLOCK(sc);
312
313 return (0);
314}
315
316/**
317 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin
318 * @dev: gpio device handle
319 * @pin: the number of the pin
320 * @caps: pointer to a value that upon return will contain the capabilities
321 *
322 * Currently all pins have the same capability, notably:
323 * - GPIO_PIN_INPUT
324 * - GPIO_PIN_OUTPUT
325 * - GPIO_PIN_PULLUP
326 * - GPIO_PIN_PULLDOWN
327 *
328 * LOCKING:
329 * Internally locks the context
330 *
331 * RETURNS:
332 * Returns 0 on success otherwise an error code
333 */
334static int
335ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
336{
337 struct ti_gpio_softc *sc = device_get_softc(dev);
338 uint32_t bank = (pin / PINS_PER_BANK);
339
340 TI_GPIO_LOCK(sc);
341
342 /* Sanity check the pin number is valid */
343 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
344 TI_GPIO_UNLOCK(sc);
345 return (EINVAL);
346 }
347
348 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |GPIO_PIN_PULLUP |
349 GPIO_PIN_PULLDOWN);
350
351 TI_GPIO_UNLOCK(sc);
352
353 return (0);
354}
355
356/**
357 * ti_gpio_pin_getflags - Gets the current flags of a given pin
358 * @dev: gpio device handle
359 * @pin: the number of the pin
360 * @flags: upon return will contain the current flags of the pin
361 *
362 * Reads the current flags of a given pin, here we actually read the H/W
363 * registers to determine the flags, rather than storing the value in the
364 * setflags call.
365 *
366 * LOCKING:
367 * Internally locks the context
368 *
369 * RETURNS:
370 * Returns 0 on success otherwise an error code
371 */
372static int
373ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
374{
375 struct ti_gpio_softc *sc = device_get_softc(dev);
376 uint32_t bank = (pin / PINS_PER_BANK);
377
378 TI_GPIO_LOCK(sc);
379
380 /* Sanity check the pin number is valid */
381 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
382 TI_GPIO_UNLOCK(sc);
383 return (EINVAL);
384 }
385
386 /* Get the current pin state */
387 ti_scm_padconf_get_gpioflags(pin, flags);
388
389 TI_GPIO_UNLOCK(sc);
390
391 return (0);
392}
393
394/**
395 * ti_gpio_pin_getname - Gets the name of a given pin
396 * @dev: gpio device handle
397 * @pin: the number of the pin
398 * @name: buffer to put the name in
399 *
400 * The driver simply calls the pins gpio_n, where 'n' is obviously the number
401 * of the pin.
402 *
403 * LOCKING:
404 * Internally locks the context
405 *
406 * RETURNS:
407 * Returns 0 on success otherwise an error code
408 */
409static int
410ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
411{
412 struct ti_gpio_softc *sc = device_get_softc(dev);
413 uint32_t bank = (pin / PINS_PER_BANK);
414
415 TI_GPIO_LOCK(sc);
416
417 /* Sanity check the pin number is valid */
418 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
419 TI_GPIO_UNLOCK(sc);
420 return (EINVAL);
421 }
422
423 /* Set a very simple name */
424 snprintf(name, GPIOMAXNAME, "gpio_%u", pin);
425 name[GPIOMAXNAME - 1] = '\0';
426
427 TI_GPIO_UNLOCK(sc);
428
429 return (0);
430}
431
432/**
433 * ti_gpio_pin_setflags - Sets the flags for a given pin
434 * @dev: gpio device handle
435 * @pin: the number of the pin
436 * @flags: the flags to set
437 *
438 * The flags of the pin correspond to things like input/output mode, pull-ups,
439 * pull-downs, etc. This driver doesn't support all flags, only the following:
440 * - GPIO_PIN_INPUT
441 * - GPIO_PIN_OUTPUT
442 * - GPIO_PIN_PULLUP
443 * - GPIO_PIN_PULLDOWN
444 *
445 * LOCKING:
446 * Internally locks the context
447 *
448 * RETURNS:
449 * Returns 0 on success otherwise an error code
450 */
451static int
452ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
453{
454 struct ti_gpio_softc *sc = device_get_softc(dev);
455 uint32_t bank = (pin / PINS_PER_BANK);
456 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
457 uint32_t reg_val;
458
459 /* Sanity check the flags supplied are valid, i.e. not input and output */
460 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0x0000)
461 return (EINVAL);
462 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) ==
463 (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT))
464 return (EINVAL);
465 if ((flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) ==
466 (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN))
467 return (EINVAL);
468
469 TI_GPIO_LOCK(sc);
470
471 /* Sanity check the pin number is valid */
472 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
473 TI_GPIO_UNLOCK(sc);
474 return (EINVAL);
475 }
476
477 /* Set the GPIO mode and state */
478 if (ti_scm_padconf_set_gpioflags(pin, flags) != 0) {
479 TI_GPIO_UNLOCK(sc);
480 return (EINVAL);
481 }
482
483 /* If configuring as an output set the "output enable" bit */
484 reg_val = ti_gpio_read_4(sc, bank, TI_GPIO_OE);
485 if (flags & GPIO_PIN_INPUT)
486 reg_val |= mask;
487 else
488 reg_val &= ~mask;
489 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_val);
490
491 TI_GPIO_UNLOCK(sc);
492
493 return (0);
494}
495
496/**
497 * ti_gpio_pin_set - Sets the current level on a GPIO pin
498 * @dev: gpio device handle
499 * @pin: the number of the pin
500 * @value: non-zero value will drive the pin high, otherwise the pin is
501 * driven low.
502 *
503 *
504 * LOCKING:
505 * Internally locks the context
506 *
507 * RETURNS:
508 * Returns 0 on success otherwise a error code
509 */
510static int
511ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
512{
513 struct ti_gpio_softc *sc = device_get_softc(dev);
514 uint32_t bank = (pin / PINS_PER_BANK);
515 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
516
517 TI_GPIO_LOCK(sc);
518
519 /* Sanity check the pin number is valid */
520 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
521 TI_GPIO_UNLOCK(sc);
522 return (EINVAL);
523 }
524
525 ti_gpio_write_4(sc, bank, (value == GPIO_PIN_LOW) ? TI_GPIO_CLEARDATAOUT
526 : TI_GPIO_SETDATAOUT, mask);
527
528 TI_GPIO_UNLOCK(sc);
529
530 return (0);
531}
532
533/**
534 * ti_gpio_pin_get - Gets the current level on a GPIO pin
535 * @dev: gpio device handle
536 * @pin: the number of the pin
537 * @value: pointer to a value that upond return will contain the pin value
538 *
539 * The pin must be configured as an input pin beforehand, otherwise this
540 * function will fail.
541 *
542 * LOCKING:
543 * Internally locks the context
544 *
545 * RETURNS:
546 * Returns 0 on success otherwise a error code
547 */
548static int
549ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
550{
551 struct ti_gpio_softc *sc = device_get_softc(dev);
552 uint32_t bank = (pin / PINS_PER_BANK);
553 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
554 uint32_t val = 0;
555
556 TI_GPIO_LOCK(sc);
557
558 /* Sanity check the pin number is valid */
559 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
560 TI_GPIO_UNLOCK(sc);
561 return (EINVAL);
562 }
563
564 /* Sanity check the pin is not configured as an output */
565 val = ti_gpio_read_4(sc, bank, TI_GPIO_OE);
566
567 /* Read the value on the pin */
568 if (val & mask)
569 *value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAIN) & mask) ? 1 : 0;
570 else
571 *value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT) & mask) ? 1 : 0;
572
573 TI_GPIO_UNLOCK(sc);
574
575 return (0);
576}
577
578/**
579 * ti_gpio_pin_toggle - Toggles a given GPIO pin
580 * @dev: gpio device handle
581 * @pin: the number of the pin
582 *
583 *
584 * LOCKING:
585 * Internally locks the context
586 *
587 * RETURNS:
588 * Returns 0 on success otherwise a error code
589 */
590static int
591ti_gpio_pin_toggle(device_t dev, uint32_t pin)
592{
593 struct ti_gpio_softc *sc = device_get_softc(dev);
594 uint32_t bank = (pin / PINS_PER_BANK);
595 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
596 uint32_t val;
597
598 TI_GPIO_LOCK(sc);
599
600 /* Sanity check the pin number is valid */
601 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
602 TI_GPIO_UNLOCK(sc);
603 return (EINVAL);
604 }
605
606 /* Toggle the pin */
607 val = ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT);
608 if (val & mask)
609 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARDATAOUT, mask);
610 else
611 ti_gpio_write_4(sc, bank, TI_GPIO_SETDATAOUT, mask);
612
613 TI_GPIO_UNLOCK(sc);
614
615 return (0);
616}
617
618/**
619 * ti_gpio_intr - ISR for all GPIO modules
620 * @arg: the soft context pointer
621 *
622 * Unsused
623 *
624 * LOCKING:
625 * Internally locks the context
626 *
627 */
628static void
629ti_gpio_intr(void *arg)
630{
631 struct ti_gpio_softc *sc = arg;
632
633 TI_GPIO_LOCK(sc);
634 /* TODO: something useful */
635 TI_GPIO_UNLOCK(sc);
636}
637
638/**
639 * ti_gpio_probe - probe function for the driver
640 * @dev: gpio device handle
641 *
642 * Simply sets the name of the driver
643 *
644 * LOCKING:
645 * None
646 *
647 * RETURNS:
648 * Always returns 0
649 */
650static int
651ti_gpio_probe(device_t dev)
652{
653
654 if (!ofw_bus_status_okay(dev))
655 return (ENXIO);
656
657 if (!ofw_bus_is_compatible(dev, "ti,gpio"))
658 return (ENXIO);
659
660 device_set_desc(dev, "TI General Purpose I/O (GPIO)");
661
662 return (0);
663}
664
665static int
666ti_gpio_attach_intr(device_t dev)
667{
668 int i;
669 struct ti_gpio_softc *sc;
670
671 sc = device_get_softc(dev);
672 for (i = 0; i < MAX_GPIO_INTRS; i++) {
673 if (sc->sc_irq_res[i] == NULL)
674 break;
675
676 /*
677 * Register our interrupt handler for each of the IRQ resources.
678 */
679 if (bus_setup_intr(dev, sc->sc_irq_res[i],
680 INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_gpio_intr, sc,
681 &sc->sc_irq_hdl[i]) != 0) {
682 device_printf(dev,
683 "WARNING: unable to register interrupt handler\n");
684 return (-1);
685 }
686 }
687
688 return (0);
689}
690
691static int
692ti_gpio_detach_intr(device_t dev)
693{
694 int i;
695 struct ti_gpio_softc *sc;
696
697 /* Teardown our interrupt handlers. */
698 sc = device_get_softc(dev);
699 for (i = 0; i < MAX_GPIO_INTRS; i++) {
700 if (sc->sc_irq_res[i] == NULL)
701 break;
702
703 if (sc->sc_irq_hdl[i]) {
704 bus_teardown_intr(dev, sc->sc_irq_res[i],
705 sc->sc_irq_hdl[i]);
706 }
707 }
708
709 return (0);
710}
711
712static int
713ti_gpio_bank_init(device_t dev, int bank)
714{
715 int pin;
716 struct ti_gpio_softc *sc;
717 uint32_t flags, reg_oe;
718
719 sc = device_get_softc(dev);
720
721 /* Enable the interface and functional clocks for the module. */
722 ti_prcm_clk_enable(GPIO0_CLK + FIRST_GPIO_BANK + bank);
723
724 /*
725 * Read the revision number of the module. TI don't publish the
726 * actual revision numbers, so instead the values have been
727 * determined by experimentation.
728 */
729 sc->sc_revision[bank] = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION);
730
731 /* Check the revision. */
732 if (sc->sc_revision[bank] != TI_GPIO_REV) {
733 device_printf(dev, "Warning: could not determine the revision "
734 "of %u GPIO module (revision:0x%08x)\n",
735 bank, sc->sc_revision[bank]);
736 return (EINVAL);
737 }
738
739 /* Disable interrupts for all pins. */
740 ti_gpio_intr_clr(sc, bank, 0xffffffff);
741
742 /* Init OE register based on pads configuration. */
743 reg_oe = 0xffffffff;
744 for (pin = 0; pin < PINS_PER_BANK; pin++) {
745 ti_scm_padconf_get_gpioflags(PINS_PER_BANK * bank + pin,
746 &flags);
747 if (flags & GPIO_PIN_OUTPUT)
748 reg_oe &= ~(1UL << pin);
749 }
750 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe);
751
752 return (0);
753}
754
755/**
756 * ti_gpio_attach - attach function for the driver
757 * @dev: gpio device handle
758 *
759 * Allocates and sets up the driver context for all GPIO banks. This function
760 * expects the memory ranges and IRQs to already be allocated to the driver.
761 *
762 * LOCKING:
763 * None
764 *
765 * RETURNS:
766 * Always returns 0
767 */
768static int
769ti_gpio_attach(device_t dev)
770{
771 struct ti_gpio_softc *sc;
772 unsigned int i;
773 int err;
774
775 sc = device_get_softc(dev);
776 sc->sc_dev = dev;
777
778 TI_GPIO_LOCK_INIT(sc);
779
780 /* There are up to 6 different GPIO register sets located in different
781 * memory areas on the chip. The memory range should have been set for
782 * the driver when it was added as a child.
783 */
784 if (bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res) != 0) {
785 device_printf(dev, "Error: could not allocate mem resources\n");
786 return (ENXIO);
787 }
788
789 /* Request the IRQ resources */
790 if (bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res) != 0) {
791 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
792 device_printf(dev, "Error: could not allocate irq resources\n");
793 return (ENXIO);
794 }
795
796 /* Setup the IRQ resources */
797 if (ti_gpio_attach_intr(dev) != 0) {
798 ti_gpio_detach_intr(dev);
799 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
800 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
801 return (ENXIO);
802 }
803
804 /* We need to go through each block and ensure the clocks are running and
805 * the module is enabled. It might be better to do this only when the
806 * pins are configured which would result in less power used if the GPIO
807 * pins weren't used ...
808 */
809 for (i = 0; i < MAX_GPIO_BANKS; i++) {
810 if (sc->sc_mem_res[i] != NULL) {
811 /* Initialize the GPIO module. */
812 err = ti_gpio_bank_init(dev, i);
813 if (err != 0) {
814 ti_gpio_detach_intr(dev);
815 bus_release_resources(dev, ti_gpio_irq_spec,
816 sc->sc_irq_res);
817 bus_release_resources(dev, ti_gpio_mem_spec,
818 sc->sc_mem_res);
819 return (err);
820 }
821 }
822 }
823
824 /* Finish of the probe call */
|
827
828 return (bus_generic_attach(dev));
829}
830
831/**
832 * ti_gpio_detach - detach function for the driver
833 * @dev: scm device handle
834 *
835 * Allocates and sets up the driver context, this simply entails creating a
836 * bus mappings for the SCM register set.
837 *
838 * LOCKING:
839 * None
840 *
841 * RETURNS:
842 * Always returns 0
843 */
844static int
845ti_gpio_detach(device_t dev)
846{
847 struct ti_gpio_softc *sc = device_get_softc(dev);
848 unsigned int i;
849
850 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
851
852 /* Disable all interrupts */
853 for (i = 0; i < MAX_GPIO_BANKS; i++) {
854 if (sc->sc_mem_res[i] != NULL)
855 ti_gpio_intr_clr(sc, i, 0xffffffff);
856 }
857
858 bus_generic_detach(dev);
859
860 /* Release the memory and IRQ resources. */
861 ti_gpio_detach_intr(dev);
862 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
863 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
864
865 TI_GPIO_LOCK_DESTROY(sc);
866
867 return (0);
868}
869
870static phandle_t
871ti_gpio_get_node(device_t bus, device_t dev)
872{
873
874 /* We only have one child, the GPIO bus, which needs our own node. */
875 return (ofw_bus_get_node(bus));
876}
877
878static device_method_t ti_gpio_methods[] = {
879 DEVMETHOD(device_probe, ti_gpio_probe),
880 DEVMETHOD(device_attach, ti_gpio_attach),
881 DEVMETHOD(device_detach, ti_gpio_detach),
882
883 /* GPIO protocol */
884 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max),
885 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname),
886 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags),
887 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps),
888 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags),
889 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get),
890 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set),
891 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle),
892
893 /* ofw_bus interface */
894 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node),
895
896 {0, 0},
897};
898
899static driver_t ti_gpio_driver = {
900 "gpio",
901 ti_gpio_methods,
902 sizeof(struct ti_gpio_softc),
903};
904static devclass_t ti_gpio_devclass;
905
906DRIVER_MODULE(ti_gpio, simplebus, ti_gpio_driver, ti_gpio_devclass, 0, 0);
| 827
828 return (bus_generic_attach(dev));
829}
830
831/**
832 * ti_gpio_detach - detach function for the driver
833 * @dev: scm device handle
834 *
835 * Allocates and sets up the driver context, this simply entails creating a
836 * bus mappings for the SCM register set.
837 *
838 * LOCKING:
839 * None
840 *
841 * RETURNS:
842 * Always returns 0
843 */
844static int
845ti_gpio_detach(device_t dev)
846{
847 struct ti_gpio_softc *sc = device_get_softc(dev);
848 unsigned int i;
849
850 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
851
852 /* Disable all interrupts */
853 for (i = 0; i < MAX_GPIO_BANKS; i++) {
854 if (sc->sc_mem_res[i] != NULL)
855 ti_gpio_intr_clr(sc, i, 0xffffffff);
856 }
857
858 bus_generic_detach(dev);
859
860 /* Release the memory and IRQ resources. */
861 ti_gpio_detach_intr(dev);
862 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
863 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
864
865 TI_GPIO_LOCK_DESTROY(sc);
866
867 return (0);
868}
869
870static phandle_t
871ti_gpio_get_node(device_t bus, device_t dev)
872{
873
874 /* We only have one child, the GPIO bus, which needs our own node. */
875 return (ofw_bus_get_node(bus));
876}
877
878static device_method_t ti_gpio_methods[] = {
879 DEVMETHOD(device_probe, ti_gpio_probe),
880 DEVMETHOD(device_attach, ti_gpio_attach),
881 DEVMETHOD(device_detach, ti_gpio_detach),
882
883 /* GPIO protocol */
884 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max),
885 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname),
886 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags),
887 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps),
888 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags),
889 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get),
890 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set),
891 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle),
892
893 /* ofw_bus interface */
894 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node),
895
896 {0, 0},
897};
898
899static driver_t ti_gpio_driver = {
900 "gpio",
901 ti_gpio_methods,
902 sizeof(struct ti_gpio_softc),
903};
904static devclass_t ti_gpio_devclass;
905
906DRIVER_MODULE(ti_gpio, simplebus, ti_gpio_driver, ti_gpio_devclass, 0, 0);
|