| s3c24x0reg.h (210397) | s3c24x0reg.h (210458) |
|---|---|
| 1/* $NetBSD: s3c24x0reg.h,v 1.7 2004/02/12 03:52:46 bsh Exp $ */ 2 3/*- 4 * Copyright (c) 2003 Genetec corporation All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 14 unchanged lines hidden (view full) --- 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * | 1/* $NetBSD: s3c24x0reg.h,v 1.7 2004/02/12 03:52:46 bsh Exp $ */ 2 3/*- 4 * Copyright (c) 2003 Genetec corporation All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 14 unchanged lines hidden (view full) --- 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * |
| 31 * $FreeBSD: head/sys/arm/s3c2xx0/s3c24x0reg.h 210397 2010-07-22 23:23:39Z andrew $ | 31 * $FreeBSD: head/sys/arm/s3c2xx0/s3c24x0reg.h 210458 2010-07-24 23:41:09Z andrew $ |
| 32 */ 33 34 35/* 36 * Samsung S3C2410X/2400 processor is ARM920T based integrated CPU 37 * 38 * Reference: 39 * S3C2410X User's Manual --- 162 unchanged lines hidden (view full) --- 202#define S3C24X0_INT_TIMER1 11 203#define S3C24X0_INT_TIMER0 10 204#define S3C24X0_INT_TIMER(n) (10+(n)) /* timer interrupt [4:0] */ 205#define S3C24X0_INT_WDT 9 /* Watch dog timer */ 206#define S3C24X0_INT_TICK 8 207#define S3C24X0_INT_BFLT 7 /* Battery fault */ 208#define S3C24X0_INT_8_23 5 /* Ext int 8..23 */ 209#define S3C24X0_INT_4_7 4 /* Ext int 4..7 */ | 32 */ 33 34 35/* 36 * Samsung S3C2410X/2400 processor is ARM920T based integrated CPU 37 * 38 * Reference: 39 * S3C2410X User's Manual --- 162 unchanged lines hidden (view full) --- 202#define S3C24X0_INT_TIMER1 11 203#define S3C24X0_INT_TIMER0 10 204#define S3C24X0_INT_TIMER(n) (10+(n)) /* timer interrupt [4:0] */ 205#define S3C24X0_INT_WDT 9 /* Watch dog timer */ 206#define S3C24X0_INT_TICK 8 207#define S3C24X0_INT_BFLT 7 /* Battery fault */ 208#define S3C24X0_INT_8_23 5 /* Ext int 8..23 */ 209#define S3C24X0_INT_4_7 4 /* Ext int 4..7 */ |
| 210#define S3C24X0_INT_EXT(n) (n) /* External interrupt [3:0] for 24{1,4}0 */ | 210#define S3C24X0_INT_3 3 211#define S3C24X0_INT_2 2 212#define S3C24X0_INT_1 1 213#define S3C24X0_INT_0 0 |
| 211 212/* 24{1,4}0 has more than 32 interrupt sources. These are sub-sources 213 * that are OR-ed into main interrupt sources, and controlled via 214 * SUBSRCPND and SUBSRCMSK registers */ 215#define S3C24X0_SUBIRQ_MIN 32 216 217/* cascaded to INT_ADCTC */ 218#define S3C24X0_INT_ADC (S3C24X0_SUBIRQ_MIN+10) /* AD converter */ --- 6 unchanged lines hidden (view full) --- 225#define S3C24X0_INT_ERR1 (S3C24X0_SUBIRQ_MIN+5) /* UART1 Error */ 226#define S3C24X0_INT_TXD1 (S3C24X0_SUBIRQ_MIN+4) /* UART1 Tx */ 227#define S3C24X0_INT_RXD1 (S3C24X0_SUBIRQ_MIN+3) /* UART1 Rx */ 228/* cascaded to INT_UART0 */ 229#define S3C24X0_INT_ERR0 (S3C24X0_SUBIRQ_MIN+2) /* UART0 Error */ 230#define S3C24X0_INT_TXD0 (S3C24X0_SUBIRQ_MIN+1) /* UART0 Tx */ 231#define S3C24X0_INT_RXD0 (S3C24X0_SUBIRQ_MIN+0) /* UART0 Rx */ 232 | 214 215/* 24{1,4}0 has more than 32 interrupt sources. These are sub-sources 216 * that are OR-ed into main interrupt sources, and controlled via 217 * SUBSRCPND and SUBSRCMSK registers */ 218#define S3C24X0_SUBIRQ_MIN 32 219 220/* cascaded to INT_ADCTC */ 221#define S3C24X0_INT_ADC (S3C24X0_SUBIRQ_MIN+10) /* AD converter */ --- 6 unchanged lines hidden (view full) --- 228#define S3C24X0_INT_ERR1 (S3C24X0_SUBIRQ_MIN+5) /* UART1 Error */ 229#define S3C24X0_INT_TXD1 (S3C24X0_SUBIRQ_MIN+4) /* UART1 Tx */ 230#define S3C24X0_INT_RXD1 (S3C24X0_SUBIRQ_MIN+3) /* UART1 Rx */ 231/* cascaded to INT_UART0 */ 232#define S3C24X0_INT_ERR0 (S3C24X0_SUBIRQ_MIN+2) /* UART0 Error */ 233#define S3C24X0_INT_TXD0 (S3C24X0_SUBIRQ_MIN+1) /* UART0 Tx */ 234#define S3C24X0_INT_RXD0 (S3C24X0_SUBIRQ_MIN+0) /* UART0 Rx */ 235 |
| 236/* 237 * Support for external interrupts. We use values from 48 238 * to allow new CPU's to allocate new subirq's. 239 */ 240#define S3C24X0_EXTIRQ_MIN 48 241#define S3C24X0_EXTIRQ_COUNT 24 242#define S3C24X0_EXTIRQ_MAX (S3C24X0_EXTIRQ_MIN + S3C24X0_EXTIRQ_COUNT - 1) 243#define S3C24X0_INT_EXT(n) (S3C24X0_EXTIRQ_MIN + (n)) 244 |
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| 233/* DMA controller */ 234/* XXX */ 235 236/* Clock & power manager */ 237#define CLKMAN_LOCKTIME 0x00 /* PLL lock time */ 238#define CLKMAN_MPLLCON 0x04 /* MPLL control */ 239#define CLKMAN_UPLLCON 0x08 /* UPLL control */ 240#define PLLCON_MDIV_SHIFT 12 --- 466 unchanged lines hidden --- | 245/* DMA controller */ 246/* XXX */ 247 248/* Clock & power manager */ 249#define CLKMAN_LOCKTIME 0x00 /* PLL lock time */ 250#define CLKMAN_MPLLCON 0x04 /* MPLL control */ 251#define CLKMAN_UPLLCON 0x08 /* UPLL control */ 252#define PLLCON_MDIV_SHIFT 12 --- 466 unchanged lines hidden --- |