| s3c24x0reg.h (205354) | s3c24x0reg.h (210396) |
|---|---|
| 1/* $NetBSD: s3c24x0reg.h,v 1.7 2004/02/12 03:52:46 bsh Exp $ */ 2 3/*- 4 * Copyright (c) 2003 Genetec corporation All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 14 unchanged lines hidden (view full) --- 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * | 1/* $NetBSD: s3c24x0reg.h,v 1.7 2004/02/12 03:52:46 bsh Exp $ */ 2 3/*- 4 * Copyright (c) 2003 Genetec corporation All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 14 unchanged lines hidden (view full) --- 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * |
| 31 * $FreeBSD: head/sys/arm/s3c2xx0/s3c24x0reg.h 205354 2010-03-20 03:39:35Z imp $ | 31 * $FreeBSD: head/sys/arm/s3c2xx0/s3c24x0reg.h 210396 2010-07-22 23:12:19Z andrew $ |
| 32 */ 33 34 35/* 36 * Samsung S3C2410X/2400 processor is ARM920T based integrated CPU 37 * 38 * Reference: 39 * S3C2410X User's Manual 40 * S3C2400 User's Manual 41 */ 42#ifndef _ARM_S3C2XX0_S3C24X0REG_H_ 43#define _ARM_S3C2XX0_S3C24X0REG_H_ 44 45/* common definitions for S3C2800, S3C2410 and S3C2440 */ 46#include <arm/s3c2xx0/s3c2xx0reg.h> 47 48/* | 32 */ 33 34 35/* 36 * Samsung S3C2410X/2400 processor is ARM920T based integrated CPU 37 * 38 * Reference: 39 * S3C2410X User's Manual 40 * S3C2400 User's Manual 41 */ 42#ifndef _ARM_S3C2XX0_S3C24X0REG_H_ 43#define _ARM_S3C2XX0_S3C24X0REG_H_ 44 45/* common definitions for S3C2800, S3C2410 and S3C2440 */ 46#include <arm/s3c2xx0/s3c2xx0reg.h> 47 48/* |
| 49 * Map the device registers into kernel space | 49 * Map the device registers into kernel space. 50 * 51 * As most devices use less than 1 page of memory reduce 52 * the distance between allocations by right shifting 53 * S3C24X0_DEV_SHIFT bits. Because the UART takes 3*0x4000 54 * bytes the upper limit on S3C24X0_DEV_SHIFT is 4. 55 * TODO: Fix the UART code so we can increase this value. |
| 50 */ 51#define S3C24X0_DEV_START 0x48000000 52#define S3C24X0_DEV_STOP 0x60000000 | 56 */ 57#define S3C24X0_DEV_START 0x48000000 58#define S3C24X0_DEV_STOP 0x60000000 |
| 53#define S3C24X0_DEV_VA_OFFSET 0xD0000000 54#define S3C24X0_DEV_VA_SIZE (S3C24X0_DEV_STOP - S3C24X0_DEV_START) 55#define S3C24X0_DEV_PA_TO_VA(x) (x - S3C24X0_DEV_START + S3C24X0_DEV_VA_OFFSET) | 59#define S3C24X0_DEV_VA_OFFSET 0xD8000000 60#define S3C24X0_DEV_SHIFT 4 61#define S3C24X0_DEV_PA_SIZE (S3C24X0_DEV_STOP - S3C24X0_DEV_START) 62#define S3C24X0_DEV_VA_SIZE (S3C24X0_DEV_PA_SIZE >> S3C24X0_DEV_SHIFT) 63#define S3C24X0_DEV_PA_TO_VA(x) ((x >> S3C24X0_DEV_SHIFT) - S3C24X0_DEV_START + S3C24X0_DEV_VA_OFFSET) |
| 56 57/* 58 * Physical address of integrated peripherals 59 */ 60#define S3C24X0_MEMCTL_PA_BASE 0x48000000 /* memory controller */ 61#define S3C24X0_MEMCTL_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_MEMCTL_PA_BASE) 62#define S3C24X0_USBHC_PA_BASE 0x49000000 /* USB Host controller */ 63#define S3C24X0_USBHC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_USBHC_PA_BASE) --- 8 unchanged lines hidden (view full) --- 72#define S3C24X0_LCDC_PA_BASE 0x4d000000 /* LCD controller */ 73#define S3C24X0_LCDC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_LCDC_PA_BASE) 74#define S3C24X0_LCDC_SIZE 0x64 75#define S3C24X0_NANDFC_PA_BASE 0x4e000000 /* NAND Flash controller */ 76#define S3C24X0_NANDFC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_NANDFC_PA_BASE) 77#define S3C24X0_UART0_PA_BASE 0x50000000 78#define S3C24X0_UART0_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_UART0_PA_BASE) 79#define S3C24X0_UART_PA_BASE(n) (S3C24X0_UART0_PA_BASE+0x4000*(n)) | 64 65/* 66 * Physical address of integrated peripherals 67 */ 68#define S3C24X0_MEMCTL_PA_BASE 0x48000000 /* memory controller */ 69#define S3C24X0_MEMCTL_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_MEMCTL_PA_BASE) 70#define S3C24X0_USBHC_PA_BASE 0x49000000 /* USB Host controller */ 71#define S3C24X0_USBHC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_USBHC_PA_BASE) --- 8 unchanged lines hidden (view full) --- 80#define S3C24X0_LCDC_PA_BASE 0x4d000000 /* LCD controller */ 81#define S3C24X0_LCDC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_LCDC_PA_BASE) 82#define S3C24X0_LCDC_SIZE 0x64 83#define S3C24X0_NANDFC_PA_BASE 0x4e000000 /* NAND Flash controller */ 84#define S3C24X0_NANDFC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_NANDFC_PA_BASE) 85#define S3C24X0_UART0_PA_BASE 0x50000000 86#define S3C24X0_UART0_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_UART0_PA_BASE) 87#define S3C24X0_UART_PA_BASE(n) (S3C24X0_UART0_PA_BASE+0x4000*(n)) |
| 80#define S3C24X0_UART_BASE(n) S3C24X0_DEV_PA_TO_VA(S3C24X0_UART_PA_BASE(n)) | 88#define S3C24X0_UART_BASE(n) (S3C24X0_UART0_BASE+0x4000*(n)) |
| 81#define S3C24X0_TIMER_PA_BASE 0x51000000 82#define S3C24X0_TIMER_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_TIMER_PA_BASE) 83#define S3C24X0_USBDC_PA_BASE 0x5200140 84#define S3C24X0_USBDC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_USBDC_PA_BASE) 85#define S3C24X0_USBDC_SIZE 0x130 86#define S3C24X0_WDT_PA_BASE 0x53000000 87#define S3C24X0_WDT_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_WDT_PA_BASE) 88#define S3C24X0_IIC_PA_BASE 0x54000000 --- 584 unchanged lines hidden --- | 89#define S3C24X0_TIMER_PA_BASE 0x51000000 90#define S3C24X0_TIMER_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_TIMER_PA_BASE) 91#define S3C24X0_USBDC_PA_BASE 0x5200140 92#define S3C24X0_USBDC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_USBDC_PA_BASE) 93#define S3C24X0_USBDC_SIZE 0x130 94#define S3C24X0_WDT_PA_BASE 0x53000000 95#define S3C24X0_WDT_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_WDT_PA_BASE) 96#define S3C24X0_IIC_PA_BASE 0x54000000 --- 584 unchanged lines hidden --- |