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s3c24x0.c (210397) s3c24x0.c (210458)
1/* $NetBSD: s3c2410.c,v 1.4 2003/08/27 03:46:05 bsh Exp $ */
2
3/*
4 * Copyright (c) 2003 Genetec corporation. All rights reserved.
5 * Written by Hiroyuki Bessho for Genetec corporation.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
1/* $NetBSD: s3c2410.c,v 1.4 2003/08/27 03:46:05 bsh Exp $ */
2
3/*
4 * Copyright (c) 2003 Genetec corporation. All rights reserved.
5 * Written by Hiroyuki Bessho for Genetec corporation.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/arm/s3c2xx0/s3c24x0.c 210397 2010-07-22 23:23:39Z andrew $");
33__FBSDID("$FreeBSD: head/sys/arm/s3c2xx0/s3c24x0.c 210458 2010-07-24 23:41:09Z andrew $");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/reboot.h>
39#include <sys/malloc.h>
40#include <sys/module.h>
41#include <sys/bus.h>

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113
114static int s3c24x0_probe(device_t);
115static int s3c24x0_attach(device_t);
116static void s3c24x0_identify(driver_t *, device_t);
117static int s3c24x0_setup_intr(device_t, device_t, struct resource *, int,
118 driver_filter_t *, driver_intr_t *, void *, void **);
119static int s3c24x0_teardown_intr(device_t, device_t, struct resource *,
120 void *);
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/reboot.h>
39#include <sys/malloc.h>
40#include <sys/module.h>
41#include <sys/bus.h>

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113
114static int s3c24x0_probe(device_t);
115static int s3c24x0_attach(device_t);
116static void s3c24x0_identify(driver_t *, device_t);
117static int s3c24x0_setup_intr(device_t, device_t, struct resource *, int,
118 driver_filter_t *, driver_intr_t *, void *, void **);
119static int s3c24x0_teardown_intr(device_t, device_t, struct resource *,
120 void *);
121static int s3c24x0_config_intr(device_t, int, enum intr_trigger,
122 enum intr_polarity);
121static struct resource *s3c24x0_alloc_resource(device_t, device_t, int, int *,
122 u_long, u_long, u_long, u_int);
123static int s3c24x0_activate_resource(device_t, device_t, int, int,
124 struct resource *);
125static int s3c24x0_release_resource(device_t, device_t, int, int,
126 struct resource *);
127static struct resource_list *s3c24x0_get_resource_list(device_t, device_t);
128
129static void s3c24x0_identify_cpu(device_t);
130
131static device_method_t s3c24x0_methods[] = {
132 DEVMETHOD(device_probe, s3c24x0_probe),
133 DEVMETHOD(device_attach, s3c24x0_attach),
134 DEVMETHOD(device_identify, s3c24x0_identify),
135 DEVMETHOD(bus_setup_intr, s3c24x0_setup_intr),
136 DEVMETHOD(bus_teardown_intr, s3c24x0_teardown_intr),
123static struct resource *s3c24x0_alloc_resource(device_t, device_t, int, int *,
124 u_long, u_long, u_long, u_int);
125static int s3c24x0_activate_resource(device_t, device_t, int, int,
126 struct resource *);
127static int s3c24x0_release_resource(device_t, device_t, int, int,
128 struct resource *);
129static struct resource_list *s3c24x0_get_resource_list(device_t, device_t);
130
131static void s3c24x0_identify_cpu(device_t);
132
133static device_method_t s3c24x0_methods[] = {
134 DEVMETHOD(device_probe, s3c24x0_probe),
135 DEVMETHOD(device_attach, s3c24x0_attach),
136 DEVMETHOD(device_identify, s3c24x0_identify),
137 DEVMETHOD(bus_setup_intr, s3c24x0_setup_intr),
138 DEVMETHOD(bus_teardown_intr, s3c24x0_teardown_intr),
139 DEVMETHOD(bus_config_intr, s3c24x0_config_intr),
137 DEVMETHOD(bus_alloc_resource, s3c24x0_alloc_resource),
138 DEVMETHOD(bus_activate_resource, s3c24x0_activate_resource),
139 DEVMETHOD(bus_release_resource, s3c24x0_release_resource),
140 DEVMETHOD(bus_get_resource_list,s3c24x0_get_resource_list),
141 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
142 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
143 {0, 0},
144};

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171 return (NULL);
172 }
173 device_set_ivars(child, ivar);
174 resource_list_init(&ivar->resources);
175
176 return (child);
177}
178
140 DEVMETHOD(bus_alloc_resource, s3c24x0_alloc_resource),
141 DEVMETHOD(bus_activate_resource, s3c24x0_activate_resource),
142 DEVMETHOD(bus_release_resource, s3c24x0_release_resource),
143 DEVMETHOD(bus_get_resource_list,s3c24x0_get_resource_list),
144 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
145 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
146 {0, 0},
147};

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174 return (NULL);
175 }
176 device_set_ivars(child, ivar);
177 resource_list_init(&ivar->resources);
178
179 return (child);
180}
181
182static void
183s3c24x0_enable_ext_intr(unsigned int irq)
184{
185 uint32_t reg, value;
186 int offset;
187
188 if (irq <= 7) {
189 reg = GPIO_PFCON;
190 offset = irq * 2;
191 } else if (irq <= 23) {
192 reg = GPIO_PGCON;
193 offset = (irq - 8) * 2;
194 } else
195 return;
196
197 /* Make the pin an interrupt source */
198 value = bus_space_read_4(s3c2xx0_softc->sc_iot,
199 s3c2xx0_softc->sc_gpio_ioh, reg);
200 value &= ~(3 << offset);
201 value |= 2 << offset;
202 bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh,
203 reg, value);
204}
205
179static int
180s3c24x0_setup_intr(device_t dev, device_t child,
181 struct resource *ires, int flags, driver_filter_t *filt,
182 driver_intr_t *intr, void *arg, void **cookiep)
183{
184 int error, irq;
185
186 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt,
187 intr, arg, cookiep);
188 if (error != 0)
189 return (error);
190
191 for (irq = rman_get_start(ires); irq <= rman_get_end(ires); irq++) {
206static int
207s3c24x0_setup_intr(device_t dev, device_t child,
208 struct resource *ires, int flags, driver_filter_t *filt,
209 driver_intr_t *intr, void *arg, void **cookiep)
210{
211 int error, irq;
212
213 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt,
214 intr, arg, cookiep);
215 if (error != 0)
216 return (error);
217
218 for (irq = rman_get_start(ires); irq <= rman_get_end(ires); irq++) {
219 if (irq >= S3C24X0_EXTIRQ_MIN && irq <= S3C24X0_EXTIRQ_MAX) {
220 /* Enable the external interrupt pin */
221 s3c24x0_enable_ext_intr(irq - S3C24X0_EXTIRQ_MIN);
222 }
192 arm_unmask_irq(irq);
193 }
194 return (0);
195}
196
197static int
198s3c24x0_teardown_intr(device_t dev, device_t child, struct resource *res,
199 void *cookie)
200{
201 return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
202}
203
223 arm_unmask_irq(irq);
224 }
225 return (0);
226}
227
228static int
229s3c24x0_teardown_intr(device_t dev, device_t child, struct resource *res,
230 void *cookie)
231{
232 return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
233}
234
235static int
236s3c24x0_config_intr(device_t dev, int irq, enum intr_trigger trig,
237 enum intr_polarity pol)
238{
239 uint32_t mask, reg, value;
240 int offset;
241
242 /* Only external interrupts can be configured */
243 if (irq < S3C24X0_EXTIRQ_MIN || irq > S3C24X0_EXTIRQ_MAX)
244 return (EINVAL);
245
246 /* There is no standard trigger or polarity for the bus */
247 if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM)
248 return (EINVAL);
249
250 irq -= S3C24X0_EXTIRQ_MIN;
251
252 /* Get the bits to set */
253 mask = 0;
254 if (pol == INTR_POLARITY_LOW) {
255 mask = 2;
256 } else if (pol == INTR_POLARITY_HIGH) {
257 mask = 4;
258 }
259 if (trig == INTR_TRIGGER_LEVEL) {
260 mask >>= 2;
261 }
262
263 /* Get the register to set */
264 if (irq <= 7) {
265 reg = GPIO_EXTINT(0);
266 offset = irq * 4;
267 } else if (irq <= 15) {
268 reg = GPIO_EXTINT(1);
269 offset = (irq - 8) * 4;
270 } else if (irq <= 23) {
271 reg = GPIO_EXTINT(2);
272 offset = (irq - 16) * 4;
273 } else {
274 return (EINVAL);
275 }
276
277 /* Set the new signaling method */
278 value = bus_space_read_4(s3c2xx0_softc->sc_iot,
279 s3c2xx0_softc->sc_gpio_ioh, reg);
280 value &= ~(7 << offset);
281 value |= mask << offset;
282 bus_space_write_4(s3c2xx0_softc->sc_iot,
283 s3c2xx0_softc->sc_gpio_ioh, reg, value);
284
285 return (0);
286}
287
204static struct resource *
205s3c24x0_alloc_resource(device_t bus, device_t child, int type, int *rid,
206 u_long start, u_long end, u_long count, u_int flags)
207{
208 struct resource_list_entry *rle;
209 struct s3c2xx0_ivar *ivar = device_get_ivars(child);
210 struct resource_list *rl = &ivar->resources;
211 struct resource *res = NULL;

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351
352int
353s3c24x0_attach(device_t dev)
354{
355 struct s3c24x0_softc *sc = device_get_softc(dev);
356 bus_space_tag_t iot;
357 device_t child;
358 unsigned int i, j;
288static struct resource *
289s3c24x0_alloc_resource(device_t bus, device_t child, int type, int *rid,
290 u_long start, u_long end, u_long count, u_int flags)
291{
292 struct resource_list_entry *rle;
293 struct s3c2xx0_ivar *ivar = device_get_ivars(child);
294 struct resource_list *rl = &ivar->resources;
295 struct resource *res = NULL;

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435
436int
437s3c24x0_attach(device_t dev)
438{
439 struct s3c24x0_softc *sc = device_get_softc(dev);
440 bus_space_tag_t iot;
441 device_t child;
442 unsigned int i, j;
443 u_long irqmax;
359
360 s3c2xx0_softc = &(sc->sc_sx);
361 sc->sc_sx.sc_iot = iot = &s3c2xx0_bs_tag;
362 s3c2xx0_softc->s3c2xx0_irq_rman.rm_type = RMAN_ARRAY;
363 s3c2xx0_softc->s3c2xx0_irq_rman.rm_descr = "S3C24X0 IRQs";
364 s3c2xx0_softc->s3c2xx0_mem_rman.rm_type = RMAN_ARRAY;
365 s3c2xx0_softc->s3c2xx0_mem_rman.rm_descr = "S3C24X0 Device Registers";
444
445 s3c2xx0_softc = &(sc->sc_sx);
446 sc->sc_sx.sc_iot = iot = &s3c2xx0_bs_tag;
447 s3c2xx0_softc->s3c2xx0_irq_rman.rm_type = RMAN_ARRAY;
448 s3c2xx0_softc->s3c2xx0_irq_rman.rm_descr = "S3C24X0 IRQs";
449 s3c2xx0_softc->s3c2xx0_mem_rman.rm_type = RMAN_ARRAY;
450 s3c2xx0_softc->s3c2xx0_mem_rman.rm_descr = "S3C24X0 Device Registers";
366 if (rman_init(&s3c2xx0_softc->s3c2xx0_irq_rman) != 0 ||
367 rman_manage_region(&s3c2xx0_softc->s3c2xx0_irq_rman, 0,
368 S3C2410_SUBIRQ_MAX) != 0) /* XXX Change S3C2440_SUBIRQ_MAX depending on micro */
369 panic("s3c24x0_attach: failed to set up IRQ rman");
370 /* Manage the registor memory space */
371 if ((rman_init(&s3c2xx0_softc->s3c2xx0_mem_rman) != 0) ||
372 (rman_manage_region(&s3c2xx0_softc->s3c2xx0_mem_rman,
373 S3C24X0_DEV_VA_OFFSET,
374 S3C24X0_DEV_VA_OFFSET + S3C24X0_DEV_VA_SIZE) != 0) ||
375 (rman_manage_region(&s3c2xx0_softc->s3c2xx0_mem_rman,
376 S3C24X0_DEV_START, S3C24X0_DEV_STOP) != 0))
377 panic("s3c24x0_attach: failed to set up register rman");

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383 sc->sc_sx.sc_wdt_ioh = S3C24X0_WDT_BASE;
384 sc->sc_timer_ioh = S3C24X0_TIMER_BASE;
385
386 /*
387 * Identify the CPU
388 */
389 s3c24x0_identify_cpu(dev);
390
451 /* Manage the registor memory space */
452 if ((rman_init(&s3c2xx0_softc->s3c2xx0_mem_rman) != 0) ||
453 (rman_manage_region(&s3c2xx0_softc->s3c2xx0_mem_rman,
454 S3C24X0_DEV_VA_OFFSET,
455 S3C24X0_DEV_VA_OFFSET + S3C24X0_DEV_VA_SIZE) != 0) ||
456 (rman_manage_region(&s3c2xx0_softc->s3c2xx0_mem_rman,
457 S3C24X0_DEV_START, S3C24X0_DEV_STOP) != 0))
458 panic("s3c24x0_attach: failed to set up register rman");

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464 sc->sc_sx.sc_wdt_ioh = S3C24X0_WDT_BASE;
465 sc->sc_timer_ioh = S3C24X0_TIMER_BASE;
466
467 /*
468 * Identify the CPU
469 */
470 s3c24x0_identify_cpu(dev);
471
472 /*
473 * Manage the interrupt space.
474 * We need to put this after s3c24x0_identify_cpu as the avaliable
475 * interrupts change depending on which CPU we have.
476 */
477 if (sc->sc_sx.sc_cpu == CPU_S3C2410)
478 irqmax = S3C2410_SUBIRQ_MAX;
479 else
480 irqmax = S3C2440_SUBIRQ_MAX;
481 if (rman_init(&s3c2xx0_softc->s3c2xx0_irq_rman) != 0 ||
482 rman_manage_region(&s3c2xx0_softc->s3c2xx0_irq_rman, 0,
483 irqmax) != 0 ||
484 rman_manage_region(&s3c2xx0_softc->s3c2xx0_irq_rman,
485 S3C24X0_EXTIRQ_MIN, S3C24X0_EXTIRQ_MAX))
486 panic("s3c24x0_attach: failed to set up IRQ rman");
487
391 /* calculate current clock frequency */
392 s3c24x0_clock_freq(&sc->sc_sx);
393 device_printf(dev, "fclk %d MHz hclk %d MHz pclk %d MHz\n",
394 sc->sc_sx.sc_fclk / 1000000, sc->sc_sx.sc_hclk / 1000000,
395 sc->sc_sx.sc_pclk / 1000000);
396
397 /*
398 * Attach children devices

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602 /*
603 * Return the parent IRQ for UART
604 * as it is all we ever need
605 */
606 if (subirq <= 8)
607 return (irq);
608
609 return (S3C24X0_SUBIRQ_MIN + subirq);
488 /* calculate current clock frequency */
489 s3c24x0_clock_freq(&sc->sc_sx);
490 device_printf(dev, "fclk %d MHz hclk %d MHz pclk %d MHz\n",
491 sc->sc_sx.sc_fclk / 1000000, sc->sc_sx.sc_hclk / 1000000,
492 sc->sc_sx.sc_pclk / 1000000);
493
494 /*
495 * Attach children devices

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699 /*
700 * Return the parent IRQ for UART
701 * as it is all we ever need
702 */
703 if (subirq <= 8)
704 return (irq);
705
706 return (S3C24X0_SUBIRQ_MIN + subirq);
707
708 case S3C24X0_INT_0:
709 case S3C24X0_INT_1:
710 case S3C24X0_INT_2:
711 case S3C24X0_INT_3:
712 /* There is a 1:1 mapping to the IRQ we are handling */
713 return S3C24X0_INT_EXT(irq);
714
715 case S3C24X0_INT_4_7:
716 case S3C24X0_INT_8_23:
717 /* Find the external interrupt being called */
718 subirq = 0x7fffff;
719 subirq &= bus_space_read_4(&s3c2xx0_bs_tag,
720 s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTPEND);
721 subirq &= ~bus_space_read_4(&s3c2xx0_bs_tag,
722 s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK);
723 if (subirq == 0)
724 return (irq);
725
726 subirq = ffs(subirq) - 1;
727
728 /* Clear the external irq pending bit */
729 bus_space_write_4(&s3c2xx0_bs_tag,
730 s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTPEND,
731 (1 << subirq));
732
733 return S3C24X0_INT_EXT(subirq);
610 }
611
612 return (irq);
613 }
614 return (-1);
615}
616
617void
618arm_mask_irq(uintptr_t irq)
619{
620 u_int32_t mask;
621
734 }
735
736 return (irq);
737 }
738 return (-1);
739}
740
741void
742arm_mask_irq(uintptr_t irq)
743{
744 u_int32_t mask;
745
746 if (irq >= S3C24X0_INT_EXT(0) && irq <= S3C24X0_INT_EXT(3)) {
747 /* External interrupt 0..3 are directly mapped to irq 0..3 */
748 irq -= S3C24X0_EXTIRQ_MIN;
749 }
622 if (irq < S3C24X0_SUBIRQ_MIN) {
623 mask = bus_space_read_4(&s3c2xx0_bs_tag,
624 s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK);
625 mask |= (1 << irq);
626 bus_space_write_4(&s3c2xx0_bs_tag,
627 s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK, mask);
750 if (irq < S3C24X0_SUBIRQ_MIN) {
751 mask = bus_space_read_4(&s3c2xx0_bs_tag,
752 s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK);
753 mask |= (1 << irq);
754 bus_space_write_4(&s3c2xx0_bs_tag,
755 s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK, mask);
628 } else {
756 } else if (irq < S3C24X0_EXTIRQ_MIN) {
629 mask = bus_space_read_4(&s3c2xx0_bs_tag,
630 s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK);
631 mask |= (1 << (irq - S3C24X0_SUBIRQ_MIN));
632 bus_space_write_4(&s3c2xx0_bs_tag,
633 s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK, mask);
757 mask = bus_space_read_4(&s3c2xx0_bs_tag,
758 s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK);
759 mask |= (1 << (irq - S3C24X0_SUBIRQ_MIN));
760 bus_space_write_4(&s3c2xx0_bs_tag,
761 s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK, mask);
762 } else {
763 mask = bus_space_read_4(&s3c2xx0_bs_tag,
764 s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK);
765 mask |= (1 << (irq - S3C24X0_EXTIRQ_MIN));
766 bus_space_write_4(&s3c2xx0_bs_tag,
767 s3c2xx0_softc->sc_intctl_ioh, GPIO_EINTMASK, mask);
634 }
635}
636
637void
638arm_unmask_irq(uintptr_t irq)
639{
640 u_int32_t mask;
641
768 }
769}
770
771void
772arm_unmask_irq(uintptr_t irq)
773{
774 u_int32_t mask;
775
776 if (irq >= S3C24X0_INT_EXT(0) && irq <= S3C24X0_INT_EXT(3)) {
777 /* External interrupt 0..3 are directly mapped to irq 0..3 */
778 irq -= S3C24X0_EXTIRQ_MIN;
779 }
642 if (irq < S3C24X0_SUBIRQ_MIN) {
643 mask = bus_space_read_4(&s3c2xx0_bs_tag,
644 s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK);
645 mask &= ~(1 << irq);
646 bus_space_write_4(&s3c2xx0_bs_tag,
647 s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK, mask);
780 if (irq < S3C24X0_SUBIRQ_MIN) {
781 mask = bus_space_read_4(&s3c2xx0_bs_tag,
782 s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK);
783 mask &= ~(1 << irq);
784 bus_space_write_4(&s3c2xx0_bs_tag,
785 s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK, mask);
648 } else {
786 } else if (irq < S3C24X0_EXTIRQ_MIN) {
649 mask = bus_space_read_4(&s3c2xx0_bs_tag,
650 s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK);
651 mask &= ~(1 << (irq - S3C24X0_SUBIRQ_MIN));
652 bus_space_write_4(&s3c2xx0_bs_tag,
653 s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK, mask);
787 mask = bus_space_read_4(&s3c2xx0_bs_tag,
788 s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK);
789 mask &= ~(1 << (irq - S3C24X0_SUBIRQ_MIN));
790 bus_space_write_4(&s3c2xx0_bs_tag,
791 s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK, mask);
792 } else {
793 mask = bus_space_read_4(&s3c2xx0_bs_tag,
794 s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK);
795 mask &= ~(1 << (irq - S3C24X0_EXTIRQ_MIN));
796 bus_space_write_4(&s3c2xx0_bs_tag,
797 s3c2xx0_softc->sc_intctl_ioh, GPIO_EINTMASK, mask);
654 }
655}
798 }
799}