| mvwin.h (209131) | mvwin.h (235609) |
|---|---|
| 1/*- 2 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 14 unchanged lines hidden (view full) --- 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * | 1/*- 2 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 14 unchanged lines hidden (view full) --- 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * |
| 31 * $FreeBSD: head/sys/arm/mv/mvwin.h 209131 2010-06-13 13:28:53Z raj $ | 31 * $FreeBSD: head/sys/arm/mv/mvwin.h 235609 2012-05-18 14:41:14Z gber $ |
| 32 */ 33 34#ifndef _MVWIN_H_ 35#define _MVWIN_H_ 36 37/* 38 * Physical addresses of integrated SoC peripherals 39 */ --- 12 unchanged lines hidden (view full) --- 52 53#define MV_PCIE_MEM_PHYS_BASE (MV_PCI_IO_PHYS_BASE + MV_PCI_IO_SIZE) 54#define MV_PCIE_MEM_BASE MV_PCIE_MEM_PHYS_BASE 55#define MV_PCIE_MEM_SIZE (64 * 1024 * 1024) 56#define MV_PCI_MEM_PHYS_BASE (MV_PCIE_MEM_PHYS_BASE + MV_PCIE_MEM_SIZE) 57#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 58#define MV_PCI_MEM_SIZE (64 * 1024 * 1024) 59 | 32 */ 33 34#ifndef _MVWIN_H_ 35#define _MVWIN_H_ 36 37/* 38 * Physical addresses of integrated SoC peripherals 39 */ --- 12 unchanged lines hidden (view full) --- 52 53#define MV_PCIE_MEM_PHYS_BASE (MV_PCI_IO_PHYS_BASE + MV_PCI_IO_SIZE) 54#define MV_PCIE_MEM_BASE MV_PCIE_MEM_PHYS_BASE 55#define MV_PCIE_MEM_SIZE (64 * 1024 * 1024) 56#define MV_PCI_MEM_PHYS_BASE (MV_PCIE_MEM_PHYS_BASE + MV_PCIE_MEM_SIZE) 57#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 58#define MV_PCI_MEM_SIZE (64 * 1024 * 1024) 59 |
| 60/* XXX DEV_BOOT, CSx are board specific, should be defined per platform */ | 60#define MV_DEV_BOOT_BASE 0xF9300000 61#define MV_DEV_BOOT_SIZE (1024 * 1024) /* 1 MB */ |
| 61 | 62 |
| 62/* 512KB NOR FLASH */ 63#define MV_DEV_BOOT_PHYS_BASE (MV_PCI_MEM_PHYS_BASE + MV_PCI_MEM_SIZE) 64#define MV_DEV_BOOT_SIZE (512 * 1024) 65/* CS0: 7-seg LED */ 66#define MV_DEV_CS0_PHYS_BASE 0xFA000000 67#define MV_DEV_CS0_SIZE (1024 * 1024) /* XXX u-boot has 2MB */ 68/* CS1: 32MB NOR FLASH */ 69#define MV_DEV_CS1_PHYS_BASE (MV_DEV_CS0_PHYS_BASE + MV_DEV_CS0_SIZE) 70#define MV_DEV_CS1_SIZE (32 * 1024 * 1024) 71/* CS2: 32MB NAND FLASH */ 72#define MV_DEV_CS2_PHYS_BASE (MV_DEV_CS1_PHYS_BASE + MV_DEV_CS1_SIZE) 73#define MV_DEV_CS2_SIZE 1024 /* XXX u-boot has 1MB */ | 63#define MV_DEV_CS0_BASE 0xF9400000 64#define MV_DEV_CS0_SIZE (1024 * 1024) /* 1 MB */ |
| 74 | 65 |
| 66#define MV_DEV_CS1_BASE 0xF9500000 67#define MV_DEV_CS1_SIZE (32 * 1024 * 1024) /* 32 MB */ 68 69#define MV_DEV_CS2_BASE 0xFB500000 70#define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */ 71 |
|
| 75#define MV_CESA_SRAM_PHYS_BASE 0xFD000000 76#define MV_CESA_SRAM_BASE MV_CESA_SRAM_PHYS_BASE /* VA == PA mapping */ 77#define MV_CESA_SRAM_SIZE (1024 * 1024) 78 79/* XXX this is probably not robust against wraparounds... */ 80#if ((MV_CESA_SRAM_PHYS_BASE + MV_CESA_SRAM_SIZE) > 0xFFFEFFFF) 81#error Devices memory layout overlaps reset vectors range! 82#endif --- 19 unchanged lines hidden (view full) --- 102#define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) 103#define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) 104#define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) 105#define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) 106#define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) 107#define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) 108#define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) 109 | 72#define MV_CESA_SRAM_PHYS_BASE 0xFD000000 73#define MV_CESA_SRAM_BASE MV_CESA_SRAM_PHYS_BASE /* VA == PA mapping */ 74#define MV_CESA_SRAM_SIZE (1024 * 1024) 75 76/* XXX this is probably not robust against wraparounds... */ 77#if ((MV_CESA_SRAM_PHYS_BASE + MV_CESA_SRAM_SIZE) > 0xFFFEFFFF) 78#error Devices memory layout overlaps reset vectors range! 79#endif --- 19 unchanged lines hidden (view full) --- 99#define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) 100#define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) 101#define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) 102#define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) 103#define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) 104#define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) 105#define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) 106 |
| 110#define MV_DEV_CS0_BASE MV_DEV_CS0_PHYS_BASE 111 | |
| 112/* 113 * Decode windows definitions and macros 114 */ 115#define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 116#define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 117#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 118#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 119#if defined(SOC_MV_DISCOVERY) --- 167 unchanged lines hidden --- | 107/* 108 * Decode windows definitions and macros 109 */ 110#define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 111#define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 112#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 113#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 114#if defined(SOC_MV_DISCOVERY) --- 167 unchanged lines hidden --- |