| pte.h (139735) | pte.h (170582) |
|---|---|
| 1/* $NetBSD: pte.h,v 1.1 2001/11/23 17:39:04 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1994 Mark Brinicombe. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 17 unchanged lines hidden (view full) --- 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * | 1/* $NetBSD: pte.h,v 1.1 2001/11/23 17:39:04 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1994 Mark Brinicombe. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 17 unchanged lines hidden (view full) --- 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * |
| 34 * $FreeBSD: head/sys/arm/include/pte.h 139735 2005-01-05 21:58:49Z imp $ | 34 * $FreeBSD: head/sys/arm/include/pte.h 170582 2007-06-11 21:29:26Z cognet $ |
| 35 */ 36 37#ifndef _MACHINE_PTE_H_ 38#define _MACHINE_PTE_H_ 39 40#define PDSHIFT 20 /* LOG2(NBPDR) */ 41#define NBPD (1 << PDSHIFT) /* bytes/page dir */ 42#define NPTEPD (NBPD / PAGE_SIZE) --- 92 unchanged lines hidden (view full) --- 135 * 136 * In addition, the Fast Context Switching Extension (FCSE) is available 137 * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating 138 * TLB/cache flushes on context switch by use of a smaller address space 139 * and a "process ID" that modifies the virtual address before being 140 * presented to the translation logic. 141 */ 142 | 35 */ 36 37#ifndef _MACHINE_PTE_H_ 38#define _MACHINE_PTE_H_ 39 40#define PDSHIFT 20 /* LOG2(NBPDR) */ 41#define NBPD (1 << PDSHIFT) /* bytes/page dir */ 42#define NPTEPD (NBPD / PAGE_SIZE) --- 92 unchanged lines hidden (view full) --- 135 * 136 * In addition, the Fast Context Switching Extension (FCSE) is available 137 * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating 138 * TLB/cache flushes on context switch by use of a smaller address space 139 * and a "process ID" that modifies the virtual address before being 140 * presented to the translation logic. 141 */ 142 |
| 143/* ARMv6 super-sections. */ 144#define L1_SUP_SIZE 0x01000000 /* 16M */ 145#define L1_SUP_OFFSET (L1_SUP_SIZE - 1) 146#define L1_SUP_FRAME (~L1_SUP_OFFSET) 147#define L1_SUP_SHIFT 24 148 |
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| 143#define L1_S_SIZE 0x00100000 /* 1M */ 144#define L1_S_OFFSET (L1_S_SIZE - 1) 145#define L1_S_FRAME (~L1_S_OFFSET) 146#define L1_S_SHIFT 20 147 148#define L2_L_SIZE 0x00010000 /* 64K */ 149#define L2_L_OFFSET (L2_L_SIZE - 1) 150#define L2_L_FRAME (~L2_L_OFFSET) --- 43 unchanged lines hidden (view full) --- 194/* L1 Section Descriptor */ 195#define L1_S_B 0x00000004 /* bufferable Section */ 196#define L1_S_C 0x00000008 /* cacheable Section */ 197#define L1_S_IMP 0x00000010 /* implementation defined */ 198#define L1_S_DOM(x) ((x) << 5) /* domain */ 199#define L1_S_DOM_MASK L1_S_DOM(0xf) 200#define L1_S_AP(x) ((x) << 10) /* access permissions */ 201#define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */ | 149#define L1_S_SIZE 0x00100000 /* 1M */ 150#define L1_S_OFFSET (L1_S_SIZE - 1) 151#define L1_S_FRAME (~L1_S_OFFSET) 152#define L1_S_SHIFT 20 153 154#define L2_L_SIZE 0x00010000 /* 64K */ 155#define L2_L_OFFSET (L2_L_SIZE - 1) 156#define L2_L_FRAME (~L2_L_OFFSET) --- 43 unchanged lines hidden (view full) --- 200/* L1 Section Descriptor */ 201#define L1_S_B 0x00000004 /* bufferable Section */ 202#define L1_S_C 0x00000008 /* cacheable Section */ 203#define L1_S_IMP 0x00000010 /* implementation defined */ 204#define L1_S_DOM(x) ((x) << 5) /* domain */ 205#define L1_S_DOM_MASK L1_S_DOM(0xf) 206#define L1_S_AP(x) ((x) << 10) /* access permissions */ 207#define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */ |
| 208#define L1_SHARED (1 << 16) |
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| 202 203#define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */ 204#define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */ 205 | 209 210#define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */ 211#define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */ 212 |
| 213#define L1_S_SUPERSEC ((1) << 18) /* Section is a super-section. */ 214 |
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| 206/* L1 Coarse Descriptor */ 207#define L1_C_IMP0 0x00000004 /* implementation defined */ 208#define L1_C_IMP1 0x00000008 /* implementation defined */ 209#define L1_C_IMP2 0x00000010 /* implementation defined */ 210#define L1_C_DOM(x) ((x) << 5) /* domain */ 211#define L1_C_DOM_MASK L1_C_DOM(0xf) 212#define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */ 213 --- 31 unchanged lines hidden (view full) --- 245#define L2_C 0x00000008 /* Cacheable page */ 246#define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */ 247#define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */ 248#define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */ 249#define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */ 250#define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) 251 252#define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */ | 215/* L1 Coarse Descriptor */ 216#define L1_C_IMP0 0x00000004 /* implementation defined */ 217#define L1_C_IMP1 0x00000008 /* implementation defined */ 218#define L1_C_IMP2 0x00000010 /* implementation defined */ 219#define L1_C_DOM(x) ((x) << 5) /* domain */ 220#define L1_C_DOM_MASK L1_C_DOM(0xf) 221#define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */ 222 --- 31 unchanged lines hidden (view full) --- 254#define L2_C 0x00000008 /* Cacheable page */ 255#define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */ 256#define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */ 257#define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */ 258#define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */ 259#define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) 260 261#define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */ |
| 262#define L2_XSCALE_L_S(x) (1 << 15) /* Shared */ |
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| 253#define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */ 254 255/* 256 * Access Permissions for L1 and L2 Descriptors. 257 */ 258#define AP_W 0x01 /* writable */ 259#define AP_U 0x02 /* user */ 260 --- 30 unchanged lines hidden (view full) --- 291 * Behavior of C and B when X == 1: 292 * C B Cacheable Bufferable Write Policy Line Allocate Policy 293 * 0 0 - - - - DO NOT USE 294 * 0 1 N Y - - 295 * 1 0 Mini-Data - - - 296 * 1 1 Y Y Write-back R/W Allocate 297 */ 298#define TEX_XSCALE_X 0x01 /* X modifies C and B */ | 263#define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */ 264 265/* 266 * Access Permissions for L1 and L2 Descriptors. 267 */ 268#define AP_W 0x01 /* writable */ 269#define AP_U 0x02 /* user */ 270 --- 30 unchanged lines hidden (view full) --- 301 * Behavior of C and B when X == 1: 302 * C B Cacheable Bufferable Write Policy Line Allocate Policy 303 * 0 0 - - - - DO NOT USE 304 * 0 1 N Y - - 305 * 1 0 Mini-Data - - - 306 * 1 1 Y Y Write-back R/W Allocate 307 */ 308#define TEX_XSCALE_X 0x01 /* X modifies C and B */ |
| 309#define TEX_XSCALE_E 0x02 310#define TEX_XSCALE_T 0x04 311 312/* Xscale core 3 */ 313 314/* 315 * 316 * Cache attributes with L2 present, S = 0 317 * T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce 318 * 0 0 0 0 0 N N - N N 319 * 0 0 0 0 1 N N - N Y 320 * 0 0 0 1 0 Y Y WT N Y 321 * 0 0 0 1 1 Y Y WB Y Y 322 * 0 0 1 0 0 N N - Y Y 323 * 0 0 1 0 1 N N - N N 324 * 0 0 1 1 0 Y Y - - N 325 * 0 0 1 1 1 Y Y WT Y Y 326 * 0 1 0 0 0 N N - N N 327 * 0 1 0 0 1 N/A N/A N/A N/A N/A 328 * 0 1 0 1 0 N/A N/A N/A N/A N/A 329 * 0 1 0 1 1 N/A N/A N/A N/A N/A 330 * 0 1 1 X X N/A N/A N/A N/A N/A 331 * 1 X 0 0 0 N N - N Y 332 * 1 X 0 0 1 Y N - N Y 333 * 1 X 0 1 0 Y N - N Y 334 * 1 X 0 1 1 Y N - Y Y 335 * 1 X 1 0 0 N N - Y Y 336 * 1 X 1 0 1 Y Y WT Y Y 337 * 1 X 1 1 0 Y Y WT Y Y 338 * 1 X 1 1 1 Y Y WT Y Y 339 * 340 * 341 * 342 * 343 * Cache attributes with L2 present, S = 1 344 * T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce 345 * 0 0 0 0 0 N N - N N 346 * 0 0 0 0 1 N N - N Y 347 * 0 0 0 1 0 Y Y - N Y 348 * 0 0 0 1 1 Y Y WT Y Y 349 * 0 0 1 0 0 N N - Y Y 350 * 0 0 1 0 1 N N - N N 351 * 0 0 1 1 0 Y Y - - N 352 * 0 0 1 1 1 Y Y WT Y Y 353 * 0 1 0 0 0 N N - N N 354 * 0 1 0 0 1 N/A N/A N/A N/A N/A 355 * 0 1 0 1 0 N/A N/A N/A N/A N/A 356 * 0 1 0 1 1 N/A N/A N/A N/A N/A 357 * 0 1 1 X X N/A N/A N/A N/A N/A 358 * 1 X 0 0 0 N N - N Y 359 * 1 X 0 0 1 Y N - N Y 360 * 1 X 0 1 0 Y N - N Y 361 * 1 X 0 1 1 Y N - Y Y 362 * 1 X 1 0 0 N N - Y Y 363 * 1 X 1 0 1 Y Y WT Y Y 364 * 1 X 1 1 0 Y Y WT Y Y 365 * 1 X 1 1 1 Y Y WT Y Y 366 */ |
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| 299#endif /* !_MACHINE_PTE_H_ */ 300 301/* End of pte.h */ | 367#endif /* !_MACHINE_PTE_H_ */ 368 369/* End of pte.h */ |