1/*-
2 * Copyright (c) 2012 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Oleksandr Rybalko under sponsorship
6 * from the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30/*
31 * Freescale i.MX515 GPIO driver.
32 */
33
34#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2012 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Oleksandr Rybalko under sponsorship
6 * from the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30/*
31 * Freescale i.MX515 GPIO driver.
32 */
33
34#include <sys/cdefs.h>
|
35__FBSDID("$FreeBSD: head/sys/arm/freescale/imx/imx51_gpio.c 248557 2013-03-20 15:39:27Z ray $");
| 35__FBSDID("$FreeBSD: head/sys/arm/freescale/imx/imx51_gpio.c 249449 2013-04-13 21:21:13Z dim $");
|
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/bus.h>
40
41#include <sys/kernel.h>
42#include <sys/module.h>
43#include <sys/rman.h>
44#include <sys/lock.h>
45#include <sys/mutex.h>
46#include <sys/gpio.h>
47
48#include <machine/bus.h>
49#include <machine/resource.h>
50
51#include <dev/fdt/fdt_common.h>
52#include <dev/ofw/openfirm.h>
53#include <dev/ofw/ofw_bus.h>
54#include <dev/ofw/ofw_bus_subr.h>
55
56#include "gpio_if.h"
57
58#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
59#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
60#define GPIO_LOCK_INIT(_sc) mtx_init(&_sc->sc_mtx, \
61 device_get_nameunit(_sc->sc_dev), "imx_gpio", MTX_DEF)
62#define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
63#define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
64#define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
65
66#define WRITE4(_sc, _r, _v) \
67 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v))
68#define READ4(_sc, _r) \
69 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r))
70#define SET4(_sc, _r, _m) \
71 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
72#define CLEAR4(_sc, _r, _m) \
73 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
74
75/* Registers definition for Freescale i.MX515 GPIO controller */
76
77#define IMX_GPIO_DR_REG 0x000 /* Pin Data */
78#define IMX_GPIO_OE_REG 0x004 /* Set Pin Output */
79#define IMX_GPIO_PSR_REG 0x008 /* Pad Status */
80#define IMX_GPIO_ICR1_REG 0x00C /* Interrupt Configuration */
81#define IMX_GPIO_ICR2_REG 0x010 /* Interrupt Configuration */
82#define GPIO_ICR_COND_LOW 0
83#define GPIO_ICR_COND_HIGH 1
84#define GPIO_ICR_COND_RISE 2
85#define GPIO_ICR_COND_FALL 3
86#define IMX_GPIO_IMR_REG 0x014 /* Interrupt Mask Register */
87#define IMX_GPIO_ISR_REG 0x018 /* Interrupt Status Register */
88#define IMX_GPIO_EDGE_REG 0x01C /* Edge Detect Register */
89
90#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
91#define NGPIO 32
92
93struct imx51_gpio_softc {
94 device_t dev;
95 struct mtx sc_mtx;
96 struct resource *sc_res[11]; /* 1 x mem, 2 x IRQ, 8 x IRQ */
97 void *gpio_ih[11]; /* 1 ptr is not a big waste */
98 int sc_l_irq; /* Last irq resource */
99 bus_space_tag_t sc_iot;
100 bus_space_handle_t sc_ioh;
101 int gpio_npins;
102 struct gpio_pin gpio_pins[NGPIO];
103};
104
105static struct resource_spec imx_gpio_spec[] = {
106 { SYS_RES_MEMORY, 0, RF_ACTIVE },
107 { SYS_RES_IRQ, 0, RF_ACTIVE },
108 { SYS_RES_IRQ, 1, RF_ACTIVE },
109 { -1, 0 }
110};
111
112static struct resource_spec imx_gpio0irq_spec[] = {
113 { SYS_RES_IRQ, 2, RF_ACTIVE },
114 { SYS_RES_IRQ, 3, RF_ACTIVE },
115 { SYS_RES_IRQ, 4, RF_ACTIVE },
116 { SYS_RES_IRQ, 5, RF_ACTIVE },
117 { SYS_RES_IRQ, 6, RF_ACTIVE },
118 { SYS_RES_IRQ, 7, RF_ACTIVE },
119 { SYS_RES_IRQ, 8, RF_ACTIVE },
120 { SYS_RES_IRQ, 9, RF_ACTIVE },
121 { -1, 0 }
122};
123
124/*
125 * Helpers
126 */
127static void imx51_gpio_pin_configure(struct imx51_gpio_softc *,
128 struct gpio_pin *, uint32_t);
129
130/*
131 * Driver stuff
132 */
133static int imx51_gpio_probe(device_t);
134static int imx51_gpio_attach(device_t);
135static int imx51_gpio_detach(device_t);
136static int imx51_gpio_intr(void *);
137
138/*
139 * GPIO interface
140 */
141static int imx51_gpio_pin_max(device_t, int *);
142static int imx51_gpio_pin_getcaps(device_t, uint32_t, uint32_t *);
143static int imx51_gpio_pin_getflags(device_t, uint32_t, uint32_t *);
144static int imx51_gpio_pin_getname(device_t, uint32_t, char *);
145static int imx51_gpio_pin_setflags(device_t, uint32_t, uint32_t);
146static int imx51_gpio_pin_set(device_t, uint32_t, unsigned int);
147static int imx51_gpio_pin_get(device_t, uint32_t, unsigned int *);
148static int imx51_gpio_pin_toggle(device_t, uint32_t pin);
149
150static void
151imx51_gpio_pin_configure(struct imx51_gpio_softc *sc, struct gpio_pin *pin,
152 unsigned int flags)
153{
154
155 GPIO_LOCK(sc);
156
157 /*
158 * Manage input/output
159 */
160 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
161 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
162 if (flags & GPIO_PIN_OUTPUT) {
163 pin->gp_flags |= GPIO_PIN_OUTPUT;
164 SET4(sc, IMX_GPIO_OE_REG, (1 << pin->gp_pin));
165 }
166 else {
167 pin->gp_flags |= GPIO_PIN_INPUT;
168 CLEAR4(sc, IMX_GPIO_OE_REG, (1 << pin->gp_pin));
169 }
170 }
171
172 GPIO_UNLOCK(sc);
173}
174
175static int
176imx51_gpio_pin_max(device_t dev, int *maxpin)
177{
178
179 *maxpin = NGPIO - 1;
180 return (0);
181}
182
183static int
184imx51_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
185{
186 struct imx51_gpio_softc *sc;
187 int i;
188
189 sc = device_get_softc(dev);
190 for (i = 0; i < sc->gpio_npins; i++) {
191 if (sc->gpio_pins[i].gp_pin == pin)
192 break;
193 }
194
195 if (i >= sc->gpio_npins)
196 return (EINVAL);
197
198 GPIO_LOCK(sc);
199 *caps = sc->gpio_pins[i].gp_caps;
200 GPIO_UNLOCK(sc);
201
202 return (0);
203}
204
205static int
206imx51_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
207{
208 struct imx51_gpio_softc *sc;
209 int i;
210
211 sc = device_get_softc(dev);
212 for (i = 0; i < sc->gpio_npins; i++) {
213 if (sc->gpio_pins[i].gp_pin == pin)
214 break;
215 }
216
217 if (i >= sc->gpio_npins)
218 return (EINVAL);
219
220 GPIO_LOCK(sc);
221 *flags = sc->gpio_pins[i].gp_flags;
222 GPIO_UNLOCK(sc);
223
224 return (0);
225}
226
227static int
228imx51_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
229{
230 struct imx51_gpio_softc *sc;
231 int i;
232
233 sc = device_get_softc(dev);
234 for (i = 0; i < sc->gpio_npins; i++) {
235 if (sc->gpio_pins[i].gp_pin == pin)
236 break;
237 }
238
239 if (i >= sc->gpio_npins)
240 return (EINVAL);
241
242 GPIO_LOCK(sc);
243 memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
244 GPIO_UNLOCK(sc);
245
246 return (0);
247}
248
249static int
250imx51_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
251{
252 struct imx51_gpio_softc *sc;
253 int i;
254
255 sc = device_get_softc(dev);
256 for (i = 0; i < sc->gpio_npins; i++) {
257 if (sc->gpio_pins[i].gp_pin == pin)
258 break;
259 }
260
261 if (i >= sc->gpio_npins)
262 return (EINVAL);
263
| 36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/bus.h>
40
41#include <sys/kernel.h>
42#include <sys/module.h>
43#include <sys/rman.h>
44#include <sys/lock.h>
45#include <sys/mutex.h>
46#include <sys/gpio.h>
47
48#include <machine/bus.h>
49#include <machine/resource.h>
50
51#include <dev/fdt/fdt_common.h>
52#include <dev/ofw/openfirm.h>
53#include <dev/ofw/ofw_bus.h>
54#include <dev/ofw/ofw_bus_subr.h>
55
56#include "gpio_if.h"
57
58#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
59#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
60#define GPIO_LOCK_INIT(_sc) mtx_init(&_sc->sc_mtx, \
61 device_get_nameunit(_sc->sc_dev), "imx_gpio", MTX_DEF)
62#define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
63#define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
64#define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
65
66#define WRITE4(_sc, _r, _v) \
67 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v))
68#define READ4(_sc, _r) \
69 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r))
70#define SET4(_sc, _r, _m) \
71 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
72#define CLEAR4(_sc, _r, _m) \
73 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
74
75/* Registers definition for Freescale i.MX515 GPIO controller */
76
77#define IMX_GPIO_DR_REG 0x000 /* Pin Data */
78#define IMX_GPIO_OE_REG 0x004 /* Set Pin Output */
79#define IMX_GPIO_PSR_REG 0x008 /* Pad Status */
80#define IMX_GPIO_ICR1_REG 0x00C /* Interrupt Configuration */
81#define IMX_GPIO_ICR2_REG 0x010 /* Interrupt Configuration */
82#define GPIO_ICR_COND_LOW 0
83#define GPIO_ICR_COND_HIGH 1
84#define GPIO_ICR_COND_RISE 2
85#define GPIO_ICR_COND_FALL 3
86#define IMX_GPIO_IMR_REG 0x014 /* Interrupt Mask Register */
87#define IMX_GPIO_ISR_REG 0x018 /* Interrupt Status Register */
88#define IMX_GPIO_EDGE_REG 0x01C /* Edge Detect Register */
89
90#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
91#define NGPIO 32
92
93struct imx51_gpio_softc {
94 device_t dev;
95 struct mtx sc_mtx;
96 struct resource *sc_res[11]; /* 1 x mem, 2 x IRQ, 8 x IRQ */
97 void *gpio_ih[11]; /* 1 ptr is not a big waste */
98 int sc_l_irq; /* Last irq resource */
99 bus_space_tag_t sc_iot;
100 bus_space_handle_t sc_ioh;
101 int gpio_npins;
102 struct gpio_pin gpio_pins[NGPIO];
103};
104
105static struct resource_spec imx_gpio_spec[] = {
106 { SYS_RES_MEMORY, 0, RF_ACTIVE },
107 { SYS_RES_IRQ, 0, RF_ACTIVE },
108 { SYS_RES_IRQ, 1, RF_ACTIVE },
109 { -1, 0 }
110};
111
112static struct resource_spec imx_gpio0irq_spec[] = {
113 { SYS_RES_IRQ, 2, RF_ACTIVE },
114 { SYS_RES_IRQ, 3, RF_ACTIVE },
115 { SYS_RES_IRQ, 4, RF_ACTIVE },
116 { SYS_RES_IRQ, 5, RF_ACTIVE },
117 { SYS_RES_IRQ, 6, RF_ACTIVE },
118 { SYS_RES_IRQ, 7, RF_ACTIVE },
119 { SYS_RES_IRQ, 8, RF_ACTIVE },
120 { SYS_RES_IRQ, 9, RF_ACTIVE },
121 { -1, 0 }
122};
123
124/*
125 * Helpers
126 */
127static void imx51_gpio_pin_configure(struct imx51_gpio_softc *,
128 struct gpio_pin *, uint32_t);
129
130/*
131 * Driver stuff
132 */
133static int imx51_gpio_probe(device_t);
134static int imx51_gpio_attach(device_t);
135static int imx51_gpio_detach(device_t);
136static int imx51_gpio_intr(void *);
137
138/*
139 * GPIO interface
140 */
141static int imx51_gpio_pin_max(device_t, int *);
142static int imx51_gpio_pin_getcaps(device_t, uint32_t, uint32_t *);
143static int imx51_gpio_pin_getflags(device_t, uint32_t, uint32_t *);
144static int imx51_gpio_pin_getname(device_t, uint32_t, char *);
145static int imx51_gpio_pin_setflags(device_t, uint32_t, uint32_t);
146static int imx51_gpio_pin_set(device_t, uint32_t, unsigned int);
147static int imx51_gpio_pin_get(device_t, uint32_t, unsigned int *);
148static int imx51_gpio_pin_toggle(device_t, uint32_t pin);
149
150static void
151imx51_gpio_pin_configure(struct imx51_gpio_softc *sc, struct gpio_pin *pin,
152 unsigned int flags)
153{
154
155 GPIO_LOCK(sc);
156
157 /*
158 * Manage input/output
159 */
160 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
161 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
162 if (flags & GPIO_PIN_OUTPUT) {
163 pin->gp_flags |= GPIO_PIN_OUTPUT;
164 SET4(sc, IMX_GPIO_OE_REG, (1 << pin->gp_pin));
165 }
166 else {
167 pin->gp_flags |= GPIO_PIN_INPUT;
168 CLEAR4(sc, IMX_GPIO_OE_REG, (1 << pin->gp_pin));
169 }
170 }
171
172 GPIO_UNLOCK(sc);
173}
174
175static int
176imx51_gpio_pin_max(device_t dev, int *maxpin)
177{
178
179 *maxpin = NGPIO - 1;
180 return (0);
181}
182
183static int
184imx51_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
185{
186 struct imx51_gpio_softc *sc;
187 int i;
188
189 sc = device_get_softc(dev);
190 for (i = 0; i < sc->gpio_npins; i++) {
191 if (sc->gpio_pins[i].gp_pin == pin)
192 break;
193 }
194
195 if (i >= sc->gpio_npins)
196 return (EINVAL);
197
198 GPIO_LOCK(sc);
199 *caps = sc->gpio_pins[i].gp_caps;
200 GPIO_UNLOCK(sc);
201
202 return (0);
203}
204
205static int
206imx51_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
207{
208 struct imx51_gpio_softc *sc;
209 int i;
210
211 sc = device_get_softc(dev);
212 for (i = 0; i < sc->gpio_npins; i++) {
213 if (sc->gpio_pins[i].gp_pin == pin)
214 break;
215 }
216
217 if (i >= sc->gpio_npins)
218 return (EINVAL);
219
220 GPIO_LOCK(sc);
221 *flags = sc->gpio_pins[i].gp_flags;
222 GPIO_UNLOCK(sc);
223
224 return (0);
225}
226
227static int
228imx51_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
229{
230 struct imx51_gpio_softc *sc;
231 int i;
232
233 sc = device_get_softc(dev);
234 for (i = 0; i < sc->gpio_npins; i++) {
235 if (sc->gpio_pins[i].gp_pin == pin)
236 break;
237 }
238
239 if (i >= sc->gpio_npins)
240 return (EINVAL);
241
242 GPIO_LOCK(sc);
243 memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
244 GPIO_UNLOCK(sc);
245
246 return (0);
247}
248
249static int
250imx51_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
251{
252 struct imx51_gpio_softc *sc;
253 int i;
254
255 sc = device_get_softc(dev);
256 for (i = 0; i < sc->gpio_npins; i++) {
257 if (sc->gpio_pins[i].gp_pin == pin)
258 break;
259 }
260
261 if (i >= sc->gpio_npins)
262 return (EINVAL);
263
|
264 /* Filter out unwanted flags */
265 if ((flags &= sc->gpio_pins[i].gp_caps) != flags)
| 264 /* Check for unwanted flags. */
265 if ((flags & sc->gpio_pins[i].gp_caps) != flags)
|
266 return (EINVAL);
267
268 /* Can't mix input/output together */
269 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) ==
270 (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT))
271 return (EINVAL);
272
273 imx51_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
274
275
276 return (0);
277}
278
279static int
280imx51_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
281{
282 struct imx51_gpio_softc *sc;
283 int i;
284
285 sc = device_get_softc(dev);
286 for (i = 0; i < sc->gpio_npins; i++) {
287 if (sc->gpio_pins[i].gp_pin == pin)
288 break;
289 }
290
291 if (i >= sc->gpio_npins)
292 return (EINVAL);
293
294 GPIO_LOCK(sc);
295 if (value)
296 SET4(sc, IMX_GPIO_DR_REG, (1 << i));
297 else
298 CLEAR4(sc, IMX_GPIO_DR_REG, (1 << i));
299 GPIO_UNLOCK(sc);
300
301 return (0);
302}
303
304static int
305imx51_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
306{
307 struct imx51_gpio_softc *sc;
308 int i;
309
310 sc = device_get_softc(dev);
311 for (i = 0; i < sc->gpio_npins; i++) {
312 if (sc->gpio_pins[i].gp_pin == pin)
313 break;
314 }
315
316 if (i >= sc->gpio_npins)
317 return (EINVAL);
318
319 GPIO_LOCK(sc);
320 *val = (READ4(sc, IMX_GPIO_DR_REG) >> i) & 1;
321 GPIO_UNLOCK(sc);
322
323 return (0);
324}
325
326static int
327imx51_gpio_pin_toggle(device_t dev, uint32_t pin)
328{
329 struct imx51_gpio_softc *sc;
330 int i;
331
332 sc = device_get_softc(dev);
333 for (i = 0; i < sc->gpio_npins; i++) {
334 if (sc->gpio_pins[i].gp_pin == pin)
335 break;
336 }
337
338 if (i >= sc->gpio_npins)
339 return (EINVAL);
340
341 GPIO_LOCK(sc);
342 WRITE4(sc, IMX_GPIO_DR_REG,
343 (READ4(sc, IMX_GPIO_DR_REG) ^ (1 << i)));
344 GPIO_UNLOCK(sc);
345
346 return (0);
347}
348
349static int
350imx51_gpio_intr(void *arg)
351{
352 struct imx51_gpio_softc *sc;
353 uint32_t input, value;
354
355 sc = arg;
356 input = READ4(sc, IMX_GPIO_ISR_REG);
357 value = input & READ4(sc, IMX_GPIO_IMR_REG);
358 WRITE4(sc, IMX_GPIO_DR_REG, input);
359
360 if (!value)
361 goto intr_done;
362
363 /* TODO: interrupt handling */
364
365intr_done:
366 return (FILTER_HANDLED);
367}
368
369static int
370imx51_gpio_probe(device_t dev)
371{
372
373 if (ofw_bus_is_compatible(dev, "fsl,imx51-gpio")) {
374 device_set_desc(dev, "i.MX515 GPIO Controller");
375 return (BUS_PROBE_DEFAULT);
376 }
377
378 return (ENXIO);
379}
380
381static int
382imx51_gpio_attach(device_t dev)
383{
384 struct imx51_gpio_softc *sc;
385 int i, irq;
386
387 sc = device_get_softc(dev);
388 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
389
390 if (bus_alloc_resources(dev, imx_gpio_spec, sc->sc_res)) {
391 device_printf(dev, "could not allocate resources\n");
392 return (ENXIO);
393 }
394
395 sc->dev = dev;
396 sc->gpio_npins = NGPIO;
397 sc->sc_l_irq = 2;
398 sc->sc_iot = rman_get_bustag(sc->sc_res[0]);
399 sc->sc_ioh = rman_get_bushandle(sc->sc_res[0]);
400
401 if (bus_alloc_resources(dev, imx_gpio0irq_spec, &sc->sc_res[3]) == 0) {
402 /*
403 * First GPIO unit able to serve +8 interrupts for 8 first
404 * pins.
405 */
406 sc->sc_l_irq = 10;
407 }
408
409 for (irq = 1; irq <= sc->sc_l_irq; irq ++) {
410 if ((bus_setup_intr(dev, sc->sc_res[irq], INTR_TYPE_MISC,
411 imx51_gpio_intr, NULL, sc, &sc->gpio_ih[irq]))) {
412 device_printf(dev,
413 "WARNING: unable to register interrupt handler\n");
414 return (ENXIO);
415 }
416 }
417
418 for (i = 0; i < sc->gpio_npins; i++) {
419 sc->gpio_pins[i].gp_pin = i;
420 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
421 sc->gpio_pins[i].gp_flags =
422 (READ4(sc, IMX_GPIO_OE_REG) & (1 << i)) ? GPIO_PIN_OUTPUT:
423 GPIO_PIN_INPUT;
424 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
425 "imx_gpio%d.%d", device_get_unit(dev), i);
426 }
427
428 device_add_child(dev, "gpioc", device_get_unit(dev));
429 device_add_child(dev, "gpiobus", device_get_unit(dev));
430
431 return (bus_generic_attach(dev));
432}
433
434static int
435imx51_gpio_detach(device_t dev)
436{
437 struct imx51_gpio_softc *sc;
438
439 sc = device_get_softc(dev);
440
441 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
442
443 bus_generic_detach(dev);
444
445 if (sc->sc_res[3])
446 bus_release_resources(dev, imx_gpio0irq_spec, &sc->sc_res[3]);
447
448 if (sc->sc_res[0])
449 bus_release_resources(dev, imx_gpio_spec, sc->sc_res);
450
451 mtx_destroy(&sc->sc_mtx);
452
453 return(0);
454}
455
456static device_method_t imx51_gpio_methods[] = {
457 DEVMETHOD(device_probe, imx51_gpio_probe),
458 DEVMETHOD(device_attach, imx51_gpio_attach),
459 DEVMETHOD(device_detach, imx51_gpio_detach),
460
461 /* GPIO protocol */
462 DEVMETHOD(gpio_pin_max, imx51_gpio_pin_max),
463 DEVMETHOD(gpio_pin_getname, imx51_gpio_pin_getname),
464 DEVMETHOD(gpio_pin_getflags, imx51_gpio_pin_getflags),
465 DEVMETHOD(gpio_pin_getcaps, imx51_gpio_pin_getcaps),
466 DEVMETHOD(gpio_pin_setflags, imx51_gpio_pin_setflags),
467 DEVMETHOD(gpio_pin_get, imx51_gpio_pin_get),
468 DEVMETHOD(gpio_pin_set, imx51_gpio_pin_set),
469 DEVMETHOD(gpio_pin_toggle, imx51_gpio_pin_toggle),
470 {0, 0},
471};
472
473static driver_t imx51_gpio_driver = {
474 "gpio",
475 imx51_gpio_methods,
476 sizeof(struct imx51_gpio_softc),
477};
478static devclass_t imx51_gpio_devclass;
479
480DRIVER_MODULE(imx51_gpio, simplebus, imx51_gpio_driver, imx51_gpio_devclass,
481 0, 0);
| 266 return (EINVAL);
267
268 /* Can't mix input/output together */
269 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) ==
270 (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT))
271 return (EINVAL);
272
273 imx51_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
274
275
276 return (0);
277}
278
279static int
280imx51_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
281{
282 struct imx51_gpio_softc *sc;
283 int i;
284
285 sc = device_get_softc(dev);
286 for (i = 0; i < sc->gpio_npins; i++) {
287 if (sc->gpio_pins[i].gp_pin == pin)
288 break;
289 }
290
291 if (i >= sc->gpio_npins)
292 return (EINVAL);
293
294 GPIO_LOCK(sc);
295 if (value)
296 SET4(sc, IMX_GPIO_DR_REG, (1 << i));
297 else
298 CLEAR4(sc, IMX_GPIO_DR_REG, (1 << i));
299 GPIO_UNLOCK(sc);
300
301 return (0);
302}
303
304static int
305imx51_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
306{
307 struct imx51_gpio_softc *sc;
308 int i;
309
310 sc = device_get_softc(dev);
311 for (i = 0; i < sc->gpio_npins; i++) {
312 if (sc->gpio_pins[i].gp_pin == pin)
313 break;
314 }
315
316 if (i >= sc->gpio_npins)
317 return (EINVAL);
318
319 GPIO_LOCK(sc);
320 *val = (READ4(sc, IMX_GPIO_DR_REG) >> i) & 1;
321 GPIO_UNLOCK(sc);
322
323 return (0);
324}
325
326static int
327imx51_gpio_pin_toggle(device_t dev, uint32_t pin)
328{
329 struct imx51_gpio_softc *sc;
330 int i;
331
332 sc = device_get_softc(dev);
333 for (i = 0; i < sc->gpio_npins; i++) {
334 if (sc->gpio_pins[i].gp_pin == pin)
335 break;
336 }
337
338 if (i >= sc->gpio_npins)
339 return (EINVAL);
340
341 GPIO_LOCK(sc);
342 WRITE4(sc, IMX_GPIO_DR_REG,
343 (READ4(sc, IMX_GPIO_DR_REG) ^ (1 << i)));
344 GPIO_UNLOCK(sc);
345
346 return (0);
347}
348
349static int
350imx51_gpio_intr(void *arg)
351{
352 struct imx51_gpio_softc *sc;
353 uint32_t input, value;
354
355 sc = arg;
356 input = READ4(sc, IMX_GPIO_ISR_REG);
357 value = input & READ4(sc, IMX_GPIO_IMR_REG);
358 WRITE4(sc, IMX_GPIO_DR_REG, input);
359
360 if (!value)
361 goto intr_done;
362
363 /* TODO: interrupt handling */
364
365intr_done:
366 return (FILTER_HANDLED);
367}
368
369static int
370imx51_gpio_probe(device_t dev)
371{
372
373 if (ofw_bus_is_compatible(dev, "fsl,imx51-gpio")) {
374 device_set_desc(dev, "i.MX515 GPIO Controller");
375 return (BUS_PROBE_DEFAULT);
376 }
377
378 return (ENXIO);
379}
380
381static int
382imx51_gpio_attach(device_t dev)
383{
384 struct imx51_gpio_softc *sc;
385 int i, irq;
386
387 sc = device_get_softc(dev);
388 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
389
390 if (bus_alloc_resources(dev, imx_gpio_spec, sc->sc_res)) {
391 device_printf(dev, "could not allocate resources\n");
392 return (ENXIO);
393 }
394
395 sc->dev = dev;
396 sc->gpio_npins = NGPIO;
397 sc->sc_l_irq = 2;
398 sc->sc_iot = rman_get_bustag(sc->sc_res[0]);
399 sc->sc_ioh = rman_get_bushandle(sc->sc_res[0]);
400
401 if (bus_alloc_resources(dev, imx_gpio0irq_spec, &sc->sc_res[3]) == 0) {
402 /*
403 * First GPIO unit able to serve +8 interrupts for 8 first
404 * pins.
405 */
406 sc->sc_l_irq = 10;
407 }
408
409 for (irq = 1; irq <= sc->sc_l_irq; irq ++) {
410 if ((bus_setup_intr(dev, sc->sc_res[irq], INTR_TYPE_MISC,
411 imx51_gpio_intr, NULL, sc, &sc->gpio_ih[irq]))) {
412 device_printf(dev,
413 "WARNING: unable to register interrupt handler\n");
414 return (ENXIO);
415 }
416 }
417
418 for (i = 0; i < sc->gpio_npins; i++) {
419 sc->gpio_pins[i].gp_pin = i;
420 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
421 sc->gpio_pins[i].gp_flags =
422 (READ4(sc, IMX_GPIO_OE_REG) & (1 << i)) ? GPIO_PIN_OUTPUT:
423 GPIO_PIN_INPUT;
424 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
425 "imx_gpio%d.%d", device_get_unit(dev), i);
426 }
427
428 device_add_child(dev, "gpioc", device_get_unit(dev));
429 device_add_child(dev, "gpiobus", device_get_unit(dev));
430
431 return (bus_generic_attach(dev));
432}
433
434static int
435imx51_gpio_detach(device_t dev)
436{
437 struct imx51_gpio_softc *sc;
438
439 sc = device_get_softc(dev);
440
441 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
442
443 bus_generic_detach(dev);
444
445 if (sc->sc_res[3])
446 bus_release_resources(dev, imx_gpio0irq_spec, &sc->sc_res[3]);
447
448 if (sc->sc_res[0])
449 bus_release_resources(dev, imx_gpio_spec, sc->sc_res);
450
451 mtx_destroy(&sc->sc_mtx);
452
453 return(0);
454}
455
456static device_method_t imx51_gpio_methods[] = {
457 DEVMETHOD(device_probe, imx51_gpio_probe),
458 DEVMETHOD(device_attach, imx51_gpio_attach),
459 DEVMETHOD(device_detach, imx51_gpio_detach),
460
461 /* GPIO protocol */
462 DEVMETHOD(gpio_pin_max, imx51_gpio_pin_max),
463 DEVMETHOD(gpio_pin_getname, imx51_gpio_pin_getname),
464 DEVMETHOD(gpio_pin_getflags, imx51_gpio_pin_getflags),
465 DEVMETHOD(gpio_pin_getcaps, imx51_gpio_pin_getcaps),
466 DEVMETHOD(gpio_pin_setflags, imx51_gpio_pin_setflags),
467 DEVMETHOD(gpio_pin_get, imx51_gpio_pin_get),
468 DEVMETHOD(gpio_pin_set, imx51_gpio_pin_set),
469 DEVMETHOD(gpio_pin_toggle, imx51_gpio_pin_toggle),
470 {0, 0},
471};
472
473static driver_t imx51_gpio_driver = {
474 "gpio",
475 imx51_gpio_methods,
476 sizeof(struct imx51_gpio_softc),
477};
478static devclass_t imx51_gpio_devclass;
479
480DRIVER_MODULE(imx51_gpio, simplebus, imx51_gpio_driver, imx51_gpio_devclass,
481 0, 0);
|