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at91sam9g45reg.h (256281) at91sam9g45reg.h (266110)
1/*-
2 * Copyright (c) 2009 Sylvestre Gallon. All rights reserved.
3 * Copyright (c) 2010 Greg Ansley. All rights reserved.
4 * Copyright (c) 2012 Andrew Turner. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
1/*-
2 * Copyright (c) 2009 Sylvestre Gallon. All rights reserved.
3 * Copyright (c) 2010 Greg Ansley. All rights reserved.
4 * Copyright (c) 2012 Andrew Turner. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 11 unchanged lines hidden (view full) ---

20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28/* $FreeBSD: stable/10/sys/arm/at91/at91sam9g45reg.h 238788 2012-07-26 08:01:25Z andrew $ */
28/* $FreeBSD: stable/10/sys/arm/at91/at91sam9g45reg.h 266110 2014-05-15 02:41:23Z ian $ */
29
30#ifndef AT91SAM9G45REG_H_
31#define AT91SAM9G45REG_H_
32
33/* Chip Specific limits */
34#define SAM9G45_PLL_A_MIN_IN_FREQ 2000000 /* 2 Mhz */
35#define SAM9G45_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */
36#define SAM9G45_PLL_A_MIN_OUT_FREQ 400000000 /* 400 Mhz */

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238#define AT91SAM9G45_TWI0_SIZE 0x4000
239#define AT91SAM9G45_TWI1_BASE 0xff88000
240#define AT91SAM9G45_TWI1_SIZE 0x4000
241
242/* XXX Needs to be carfully coordinated with
243 * other * soc's so phyical and vm address
244 * mapping are unique. XXX
245 */
29
30#ifndef AT91SAM9G45REG_H_
31#define AT91SAM9G45REG_H_
32
33/* Chip Specific limits */
34#define SAM9G45_PLL_A_MIN_IN_FREQ 2000000 /* 2 Mhz */
35#define SAM9G45_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */
36#define SAM9G45_PLL_A_MIN_OUT_FREQ 400000000 /* 400 Mhz */

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238#define AT91SAM9G45_TWI0_SIZE 0x4000
239#define AT91SAM9G45_TWI1_BASE 0xff88000
240#define AT91SAM9G45_TWI1_SIZE 0x4000
241
242/* XXX Needs to be carfully coordinated with
243 * other * soc's so phyical and vm address
244 * mapping are unique. XXX
245 */
246#define AT91SAM9G45_OHCI_BASE 0xdfb00000
247#define AT91SAM9G45_OHCI_PA_BASE 0x00700000
248#define AT91SAM9G45_OHCI_SIZE 0x00100000
246#define AT91SAM9G45_OHCI_VA_BASE 0xdfb00000
247#define AT91SAM9G45_OHCI_BASE 0x00700000
248#define AT91SAM9G45_OHCI_SIZE 0x00100000
249
249
250#define AT91SAM9G45_NAND_BASE 0xe0000000
251#define AT91SAM9G45_NAND_PA_BASE 0x40000000
252#define AT91SAM9G45_NAND_SIZE 0x10000000
250#define AT91SAM9G45_NAND_VA_BASE 0xe0000000
251#define AT91SAM9G45_NAND_BASE 0x40000000
252#define AT91SAM9G45_NAND_SIZE 0x10000000
253
254
255/* DDRSDRC */
256#define AT91SAM9G45_DDRSDRC1_BASE 0xfffea00
257#define AT91SAM9G45_DDRSDRC0_BASE 0xfffe600
258#define AT91SAM9G45_DDRSDRC_MR 0x00
259#define AT91SAM9G45_DDRSDRC_TR 0x04
260#define AT91SAM9G45_DDRSDRC_CR 0x08

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253
254
255/* DDRSDRC */
256#define AT91SAM9G45_DDRSDRC1_BASE 0xfffea00
257#define AT91SAM9G45_DDRSDRC0_BASE 0xfffe600
258#define AT91SAM9G45_DDRSDRC_MR 0x00
259#define AT91SAM9G45_DDRSDRC_TR 0x04
260#define AT91SAM9G45_DDRSDRC_CR 0x08

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