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< * $FreeBSD: stable/10/sys/amd64/vmm/io/vioapic.c 262350 2014-02-23 00:46:05Z jhb $
---
> * $FreeBSD: stable/10/sys/amd64/vmm/io/vioapic.c 266339 2014-05-17 19:11:08Z jhb $
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< __FBSDID("$FreeBSD: stable/10/sys/amd64/vmm/io/vioapic.c 262350 2014-02-23 00:46:05Z jhb $");
---
> __FBSDID("$FreeBSD: stable/10/sys/amd64/vmm/io/vioapic.c 266339 2014-05-17 19:11:08Z jhb $");
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> /*
> * Reset the vlapic's trigger-mode register to reflect the ioapic pin
> * configuration.
> */
> static void
> vioapic_update_tmr(struct vm *vm, int vcpuid, void *arg)
> {
> struct vioapic *vioapic;
> struct vlapic *vlapic;
> uint32_t low, high, dest;
> int delmode, pin, vector;
> bool level, phys;
>
> vlapic = vm_lapic(vm, vcpuid);
> vioapic = vm_ioapic(vm);
>
> VIOAPIC_LOCK(vioapic);
> /*
> * Reset all vectors to be edge-triggered.
> */
> vlapic_reset_tmr(vlapic);
> for (pin = 0; pin < REDIR_ENTRIES; pin++) {
> low = vioapic->rtbl[pin].reg;
> high = vioapic->rtbl[pin].reg >> 32;
>
> level = low & IOART_TRGRLVL ? true : false;
> if (!level)
> continue;
>
> /*
> * For a level-triggered 'pin' let the vlapic figure out if
> * an assertion on this 'pin' would result in an interrupt
> * being delivered to it. If yes, then it will modify the
> * TMR bit associated with this vector to level-triggered.
> */
> phys = ((low & IOART_DESTMOD) == IOART_DESTPHY);
> delmode = low & IOART_DELMOD;
> vector = low & IOART_INTVEC;
> dest = high >> APIC_ID_SHIFT;
> vlapic_set_tmr_level(vlapic, dest, phys, delmode, vector);
> }
> VIOAPIC_UNLOCK(vioapic);
> }
>
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< vioapic_read(struct vioapic *vioapic, uint32_t addr)
---
> vioapic_read(struct vioapic *vioapic, int vcpuid, uint32_t addr)
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< vioapic_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
---
> vioapic_write(struct vioapic *vioapic, int vcpuid, uint32_t addr, uint32_t data)
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> uint64_t last, changed;
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> cpuset_t allvcpus;
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> last = vioapic->rtbl[pin].reg;
>
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> * If any fields in the redirection table entry (except mask
> * or polarity) have changed then rendezvous all the vcpus
> * to update their vlapic trigger-mode registers.
> */
> changed = last ^ vioapic->rtbl[pin].reg;
> if (changed & ~(IOART_INTMASK | IOART_INTPOL)) {
> VIOAPIC_CTR1(vioapic, "ioapic pin%d: recalculate "
> "vlapic trigger-mode register", pin);
> VIOAPIC_UNLOCK(vioapic);
> allvcpus = vm_active_cpus(vioapic->vm);
> vm_smp_rendezvous(vioapic->vm, vcpuid, allvcpus,
> vioapic_update_tmr, NULL);
> VIOAPIC_LOCK(vioapic);
> }
>
> /*
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< vioapic_mmio_rw(struct vioapic *vioapic, uint64_t gpa, uint64_t *data,
< int size, bool doread)
---
> vioapic_mmio_rw(struct vioapic *vioapic, int vcpuid, uint64_t gpa,
> uint64_t *data, int size, bool doread)
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< if (doread)
< *data = vioapic_read(vioapic, vioapic->ioregsel);
< else
< vioapic_write(vioapic, vioapic->ioregsel, *data);
---
> if (doread) {
> *data = vioapic_read(vioapic, vcpuid,
> vioapic->ioregsel);
> } else {
> vioapic_write(vioapic, vcpuid, vioapic->ioregsel,
> *data);
> }
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< error = vioapic_mmio_rw(vioapic, gpa, rval, size, true);
---
> error = vioapic_mmio_rw(vioapic, vcpuid, gpa, rval, size, true);
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< error = vioapic_mmio_rw(vioapic, gpa, &wval, size, false);
---
> error = vioapic_mmio_rw(vioapic, vcpuid, gpa, &wval, size, false);