1/************************************************************************** 2**
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3** $Id: pcibus.c,v 1.10 1995/06/30 16:11:42 se Exp $
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3** $Id: pcibus.c,v 1.11 1995/09/13 17:03:47 se Exp $ |
4** 5** pci bus subroutines for i386 architecture. 6** 7** FreeBSD 8** 9**------------------------------------------------------------------------- 10** 11** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved. 12** 13** Redistribution and use in source and binary forms, with or without 14** modification, are permitted provided that the following conditions 15** are met: 16** 1. Redistributions of source code must retain the above copyright 17** notice, this list of conditions and the following disclaimer. 18** 2. Redistributions in binary form must reproduce the above copyright 19** notice, this list of conditions and the following disclaimer in the 20** documentation and/or other materials provided with the distribution. 21** 3. The name of the author may not be used to endorse or promote products 22** derived from this software without specific prior written permission. 23** 24** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34** 35*************************************************************************** 36*/ 37 38#define __PCIBUS_C___ "pl4 95/03/21" 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> 43 44#include <i386/isa/icu.h> 45#include <i386/isa/isa.h> 46#include <i386/isa/isa_device.h> 47 48#include <pci/pcivar.h> 49#include <pci/pcireg.h> 50#include <pci/pcibus.h> 51 52/*----------------------------------------------------------------- 53** 54** The following functions are provided by the pci bios. 55** They are used only by the pci configuration. 56** 57** pcibus_setup(): 58** Probes for a pci system. 59** Sets pci_maxdevice and pci_mechanism. 60** 61** pcibus_tag(): 62** Creates a handle for pci configuration space access. 63** This handle is given to the read/write functions. 64** 65** pcibus_ftag(): 66** Creates a modified handle. 67** 68** pcibus_read(): 69** Read a long word from the pci configuration space. 70** Requires a tag (from pcitag) and the register 71** number (should be a long word alligned one). 72** 73** pcibus_write(): 74** Writes a long word to the pci configuration space. 75** Requires a tag (from pcitag), the register number 76** (should be a long word alligned one), and a value. 77** 78** pcibus_regirq(): 79** Register an interupt handler for a pci device. 80** Requires a tag (from pcitag), the register number 81** (should be a long word alligned one), and a value. 82** 83**----------------------------------------------------------------- 84*/ 85
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86static int 87pcibus_check (void); 88 |
89static void 90pcibus_setup (void); 91 92static pcici_t 93pcibus_tag (u_char bus, u_char device, u_char func); 94 95static pcici_t 96pcibus_ftag (pcici_t tag, u_char func); 97 98static u_long 99pcibus_read (pcici_t tag, u_long reg); 100 101static void 102pcibus_write (pcici_t tag, u_long reg, u_long data); 103 104static int 105pcibus_ihandler_attach (int irq, void(*ihandler)(), int arg, unsigned* maskp); 106 107static int 108pcibus_ihandler_detach (int irq, void(*handler)()); 109 110static int 111pcibus_imask_include (int irq, unsigned* maskptr); 112 113static int 114pcibus_imask_exclude (int irq, unsigned* maskptr); 115 116struct pcibus i386pci = { 117 "pci", 118 pcibus_setup, 119 pcibus_tag, 120 pcibus_ftag, 121 pcibus_read, 122 pcibus_write, 123 ICU_LEN, 124 pcibus_ihandler_attach, 125 pcibus_ihandler_detach, 126 pcibus_imask_include, 127 pcibus_imask_exclude, 128}; 129 130/* 131** Announce structure to generic driver 132*/ 133 134DATA_SET (pcibus_set, i386pci); 135 136/*-------------------------------------------------------------------- 137** 138** Determine configuration mode 139** 140**-------------------------------------------------------------------- 141*/ 142 143 144#define CONF1_ENABLE 0x80000000ul 145#define CONF1_ENABLE_CHK1 0xF0000000ul 146#define CONF1_ENABLE_CHK2 0xfffffffful 147#define CONF1_ENABLE_RES2 0x80fffffcul 148#define CONF1_ADDR_PORT 0x0cf8 149#define CONF1_DATA_PORT 0x0cfc 150 151 152#define CONF2_ENABLE_PORT 0x0cf8 153#define CONF2_FORWARD_PORT 0x0cfa 154 155
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156static int 157pcibus_check (void) 158{ 159 u_char device; 160 161 for (device = 0; device < pci_maxdevice; device++) { 162 if (pcibus_read (pcibus_tag (0,device,0), 0) != 0xfffffffful) 163 return 1; 164 } 165 return 0; 166} 167 |
168static void 169pcibus_setup (void) 170{ 171 u_long result, oldval; 172 173 /*--------------------------------------- 174 ** Configuration mode 1 ? 175 **--------------------------------------- 176 */ 177 178 oldval = inl (CONF1_ADDR_PORT); 179 outl (CONF1_ADDR_PORT, CONF1_ENABLE_CHK1); 180 outb (CONF1_ADDR_PORT +3, 0); 181 result = inl (CONF1_ADDR_PORT); 182 outl (CONF1_ADDR_PORT, oldval); 183 184 if (result & CONF1_ENABLE) { 185 pci_mechanism = 1; 186 pci_maxdevice = 32;
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172 if (pcibus_read (pcibus_tag (0,0,0), 0) != 0xfffffffful)
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187 if (pcibus_check()) |
188 return; 189 }; 190 191 /*--------------------------------------- 192 ** Configuration mode 2 ? 193 **--------------------------------------- 194 */ 195 196 outb (CONF2_ENABLE_PORT, 0); 197 outb (CONF2_FORWARD_PORT, 0); 198 if (!inb (CONF2_ENABLE_PORT) && !inb (CONF2_FORWARD_PORT)) { 199 pci_mechanism = 2; 200 pci_maxdevice = 16;
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186 if (pcibus_read (pcibus_tag (0,0,0), 0) != 0xfffffffful)
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201 if (pcibus_check()) |
202 return; 203 }; 204 205 206 /*----------------------------------------------------- 207 ** Well, is it Configuration mode 1, after all ? 208 **----------------------------------------------------- 209 */ 210 211 oldval = inl (CONF1_ADDR_PORT); 212 outl (CONF1_ADDR_PORT, CONF1_ENABLE_CHK2); 213 result = inl (CONF1_ADDR_PORT); 214 outl (CONF1_ADDR_PORT, oldval); 215 216 if (result == CONF1_ENABLE_RES2) { 217 pci_mechanism = 1; 218 pci_maxdevice = 32;
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204 if (pcibus_read (pcibus_tag (0,0,0), 0) != 0xfffffffful)
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219 if (pcibus_check()) |
220 return; 221 } 222 if (result != 0xfffffffful) 223 printf ("pcibus_setup: " 224 "wrote 0x%08x, read back 0x%08x, expected 0x%08x\n", 225 CONF1_ENABLE_CHK2, result, CONF1_ENABLE_RES2); 226 227 /*--------------------------------------- 228 ** No PCI bus host bridge found 229 **--------------------------------------- 230 */ 231 232 pci_mechanism = 0; 233 pci_maxdevice = 0; 234} 235 236/*-------------------------------------------------------------------- 237** 238** Build a pcitag from bus, device and function number 239** 240**-------------------------------------------------------------------- 241*/ 242 243static pcici_t 244pcibus_tag (unsigned char bus, unsigned char device, unsigned char func) 245{ 246 pcici_t tag; 247 248 tag.cfg1 = 0; 249 if (device >= 32) return tag; 250 if (func >= 8) return tag; 251 252 switch (pci_mechanism) { 253 254 case 1: 255 tag.cfg1 = CONF1_ENABLE 256 | (((u_long) bus ) << 16ul) 257 | (((u_long) device) << 11ul) 258 | (((u_long) func ) << 8ul); 259 break; 260 case 2: 261 if (device >= 16) break; 262 tag.cfg2.port = 0xc000 | (device << 8ul); 263 tag.cfg2.enable = 0xf1 | (func << 1ul); 264 tag.cfg2.forward = bus; 265 break; 266 }; 267 return tag; 268} 269 270static pcici_t 271pcibus_ftag (pcici_t tag, u_char func) 272{ 273 switch (pci_mechanism) { 274 275 case 1: 276 tag.cfg1 &= ~0x700ul; 277 tag.cfg1 |= (((u_long) func) << 8ul); 278 break; 279 case 2: 280 tag.cfg2.enable = 0xf1 | (func << 1ul); 281 break; 282 }; 283 return tag; 284} 285 286/*-------------------------------------------------------------------- 287** 288** Read register from configuration space. 289** 290**-------------------------------------------------------------------- 291*/ 292 293static u_long 294pcibus_read (pcici_t tag, u_long reg) 295{ 296 u_long addr, data = 0; 297 298 if (!tag.cfg1) return (0xfffffffful); 299 300 switch (pci_mechanism) { 301 302 case 1: 303 addr = tag.cfg1 | (reg & 0xfc); 304#ifdef PCI_DEBUG 305 printf ("pci_conf_read(1): addr=%x ", addr); 306#endif 307 outl (CONF1_ADDR_PORT, addr); 308 data = inl (CONF1_DATA_PORT); 309 outl (CONF1_ADDR_PORT, 0 ); 310 break; 311 312 case 2: 313 addr = tag.cfg2.port | (reg & 0xfc); 314#ifdef PCI_DEBUG 315 printf ("pci_conf_read(2): addr=%x ", addr); 316#endif 317 outb (CONF2_ENABLE_PORT , tag.cfg2.enable ); 318 outb (CONF2_FORWARD_PORT, tag.cfg2.forward); 319 320 data = inl ((u_short) addr); 321 322 outb (CONF2_ENABLE_PORT, 0); 323 outb (CONF2_FORWARD_PORT, 0); 324 break; 325 }; 326 327#ifdef PCI_DEBUG 328 printf ("data=%x\n", data); 329#endif 330 331 return (data); 332} 333 334/*-------------------------------------------------------------------- 335** 336** Write register into configuration space. 337** 338**-------------------------------------------------------------------- 339*/ 340 341static void 342pcibus_write (pcici_t tag, u_long reg, u_long data) 343{ 344 u_long addr; 345 346 if (!tag.cfg1) return; 347 348 switch (pci_mechanism) { 349 350 case 1: 351 addr = tag.cfg1 | (reg & 0xfc); 352#ifdef PCI_DEBUG 353 printf ("pci_conf_write(1): addr=%x data=%x\n", 354 addr, data); 355#endif 356 outl (CONF1_ADDR_PORT, addr); 357 outl (CONF1_DATA_PORT, data); 358 outl (CONF1_ADDR_PORT, 0 ); 359 break; 360 361 case 2: 362 addr = tag.cfg2.port | (reg & 0xfc); 363#ifdef PCI_DEBUG 364 printf ("pci_conf_write(2): addr=%x data=%x\n", 365 addr, data); 366#endif 367 outb (CONF2_ENABLE_PORT, tag.cfg2.enable); 368 outb (CONF2_FORWARD_PORT, tag.cfg2.forward); 369 370 outl ((u_short) addr, data); 371 372 outb (CONF2_ENABLE_PORT, 0); 373 outb (CONF2_FORWARD_PORT, 0); 374 break; 375 }; 376} 377 378/*----------------------------------------------------------------------- 379** 380** Register an interupt handler for a pci device. 381** 382**----------------------------------------------------------------------- 383*/ 384 385static int 386pcibus_ihandler_attach (int irq, void(*func)(), int arg, unsigned * maskptr) 387{ 388 int result; 389 result = register_intr( 390 irq, /* isa irq */ 391 0, /* deviced?? */ 392 0, /* flags? */ 393 (inthand2_t*) func, /* handler */ 394 maskptr, /* mask pointer */ 395 arg); /* handler arg */ 396 397 if (result) { 398 printf ("@@@ pcibus_ihandler_attach: result=%d\n", result); 399 return (result); 400 }; 401 update_intr_masks(); 402 403 INTREN ((1ul<<irq)); 404 return (0); 405} 406 407static int 408pcibus_ihandler_detach (int irq, void(*func)()) 409{ 410 int result; 411 412 INTRDIS ((1ul<<irq)); 413 414 result = unregister_intr (irq, (inthand2_t*) func); 415 416 if (result) 417 printf ("@@@ pcibus_ihandler_detach: result=%d\n", result); 418 419 update_intr_masks(); 420 421 return (result); 422} 423 424static int 425pcibus_imask_include (int irq, unsigned* maskptr) 426{ 427 unsigned mask; 428 429 if (!maskptr) return (0); 430 431 mask = 1ul << irq; 432 433 if (*maskptr & mask) 434 return (-1); 435 436 INTRMASK (*maskptr, mask); 437 update_intr_masks(); 438 439 return (0); 440} 441 442static int 443pcibus_imask_exclude (int irq, unsigned* maskptr) 444{ 445 unsigned mask; 446 447 if (!maskptr) return (0); 448 449 mask = 1ul << irq; 450 451 if (! (*maskptr & mask)) 452 return (-1); 453 454 *maskptr &= ~mask; 455 update_intr_masks(); 456 457 return (0); 458}
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