| gcc.1 (218895) | gcc.1 (219374) |
|---|---|
| 1.\" Automatically generated by Pod::Man v1.37, Pod::Parser v1.14 2.\" 3.\" Standard preamble: 4.\" ======================================================================== 5.de Sh \" Subsection heading 6.br 7.if t .Sp 8.ne 5 --- 115 unchanged lines hidden (view full) --- 124. ds Th \o'LP' 125. ds ae ae 126. ds Ae AE 127.\} 128.rm #[ #] #H #V #F C 129.\" ======================================================================== 130.\" 131.IX Title "GCC 1" | 1.\" Automatically generated by Pod::Man v1.37, Pod::Parser v1.14 2.\" 3.\" Standard preamble: 4.\" ======================================================================== 5.de Sh \" Subsection heading 6.br 7.if t .Sp 8.ne 5 --- 115 unchanged lines hidden (view full) --- 124. ds Th \o'LP' 125. ds ae ae 126. ds Ae AE 127.\} 128.rm #[ #] #H #V #F C 129.\" ======================================================================== 130.\" 131.IX Title "GCC 1" |
| 132.TH GCC 1 "2011-02-20" "gcc-4.2.1" "GNU" | 132.TH GCC 1 "2011-03-07" "gcc-4.2.1" "GNU" |
| 133.SH "NAME" 134gcc \- GNU project C and C++ compiler 135.SH "SYNOPSIS" 136.IX Header "SYNOPSIS" 137gcc [\fB\-c\fR|\fB\-S\fR|\fB\-E\fR] [\fB\-std=\fR\fIstandard\fR] 138 [\fB\-g\fR] [\fB\-pg\fR] [\fB\-O\fR\fIlevel\fR] 139 [\fB\-W\fR\fIwarn\fR...] [\fB\-pedantic\fR] 140 [\fB\-I\fR\fIdir\fR...] [\fB\-L\fR\fIdir\fR...] --- 8587 unchanged lines hidden (view full) --- 8728.IP "\fIprescott\fR" 4 8729.IX Item "prescott" 8730Improved version of Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 instruction 8731set support. 8732.IP "\fInocona\fR" 4 8733.IX Item "nocona" 8734Improved version of Intel Pentium4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, 8735\&\s-1SSE2\s0 and \s-1SSE3\s0 instruction set support. | 133.SH "NAME" 134gcc \- GNU project C and C++ compiler 135.SH "SYNOPSIS" 136.IX Header "SYNOPSIS" 137gcc [\fB\-c\fR|\fB\-S\fR|\fB\-E\fR] [\fB\-std=\fR\fIstandard\fR] 138 [\fB\-g\fR] [\fB\-pg\fR] [\fB\-O\fR\fIlevel\fR] 139 [\fB\-W\fR\fIwarn\fR...] [\fB\-pedantic\fR] 140 [\fB\-I\fR\fIdir\fR...] [\fB\-L\fR\fIdir\fR...] --- 8587 unchanged lines hidden (view full) --- 8728.IP "\fIprescott\fR" 4 8729.IX Item "prescott" 8730Improved version of Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 instruction 8731set support. 8732.IP "\fInocona\fR" 4 8733.IX Item "nocona" 8734Improved version of Intel Pentium4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, 8735\&\s-1SSE2\s0 and \s-1SSE3\s0 instruction set support. |
| 8736.IP "\fIcore2\fR" 4 8737.IX Item "core2" 8738Intel Core2 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 8739instruction set support. |
|
| 8736.IP "\fIk6\fR" 4 8737.IX Item "k6" 8738\&\s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 instruction set support. 8739.IP "\fIk6\-2, k6\-3\fR" 4 8740.IX Item "k6-2, k6-3" 8741Improved versions of \s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW! instruction set support. 8742.IP "\fIathlon, athlon-tbird\fR" 4 8743.IX Item "athlon, athlon-tbird" --- 21 unchanged lines hidden (view full) --- 8765.IP "\fIc3\fR" 4 8766.IX Item "c3" 8767Via C3 \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW! instruction set support. (No scheduling is 8768implemented for this chip.) 8769.IP "\fIc3\-2\fR" 4 8770.IX Item "c3-2" 8771Via C3\-2 \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. (No scheduling is 8772implemented for this chip.) | 8740.IP "\fIk6\fR" 4 8741.IX Item "k6" 8742\&\s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 instruction set support. 8743.IP "\fIk6\-2, k6\-3\fR" 4 8744.IX Item "k6-2, k6-3" 8745Improved versions of \s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW! instruction set support. 8746.IP "\fIathlon, athlon-tbird\fR" 4 8747.IX Item "athlon, athlon-tbird" --- 21 unchanged lines hidden (view full) --- 8769.IP "\fIc3\fR" 4 8770.IX Item "c3" 8771Via C3 \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW! instruction set support. (No scheduling is 8772implemented for this chip.) 8773.IP "\fIc3\-2\fR" 4 8774.IX Item "c3-2" 8775Via C3\-2 \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. (No scheduling is 8776implemented for this chip.) |
| 8777.IP "\fIgeode\fR" 4 8778.IX Item "geode" 8779Embedded AMD \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW! instruction set support. |
|
| 8773.RE 8774.RS 4 8775.Sp 8776While picking a specific \fIcpu-type\fR will schedule things appropriately 8777for that particular chip, the compiler will not generate any code that 8778does not run on the i386 without the \fB\-march=\fR\fIcpu-type\fR option 8779being used. 8780.RE --- 4341 unchanged lines hidden --- | 8780.RE 8781.RS 4 8782.Sp 8783While picking a specific \fIcpu-type\fR will schedule things appropriately 8784for that particular chip, the compiler will not generate any code that 8785does not run on the i386 without the \fB\-march=\fR\fIcpu-type\fR option 8786being used. 8787.RE --- 4341 unchanged lines hidden --- |