Deleted Added
sdiff udiff text old ( 237021 ) new ( 251212 )
full compact
sse.md (237021) sse.md (251212)
1;; GCC machine description for SSE instructions
1;; GCC machine description for SSE instructions
2;; Copyright (C) 2005, 2006
2;; Copyright (C) 2005, 2006, 2007
3;; Free Software Foundation, Inc.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify
8;; it under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 2, or (at your option)
10;; any later version.

--- 904 unchanged lines hidden (view full) ---

915 (vec_duplicate:V4SF
916 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,m")))
917 (match_operand:V4SF 1 "register_operand" "0,0")
918 (const_int 1)))]
919 "TARGET_SSE"
920 "cvtsi2ss\t{%2, %0|%0, %2}"
921 [(set_attr "type" "sseicvt")
922 (set_attr "athlon_decode" "vector,double")
3;; Free Software Foundation, Inc.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify
8;; it under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 2, or (at your option)
10;; any later version.

--- 904 unchanged lines hidden (view full) ---

915 (vec_duplicate:V4SF
916 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,m")))
917 (match_operand:V4SF 1 "register_operand" "0,0")
918 (const_int 1)))]
919 "TARGET_SSE"
920 "cvtsi2ss\t{%2, %0|%0, %2}"
921 [(set_attr "type" "sseicvt")
922 (set_attr "athlon_decode" "vector,double")
923 (set_attr "amdfam10_decode" "vector,double")
923 (set_attr "mode" "SF")])
924
925(define_insn "sse_cvtsi2ssq"
926 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
927 (vec_merge:V4SF
928 (vec_duplicate:V4SF
929 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
930 (match_operand:V4SF 1 "register_operand" "0,0")
931 (const_int 1)))]
932 "TARGET_SSE && TARGET_64BIT"
933 "cvtsi2ssq\t{%2, %0|%0, %2}"
934 [(set_attr "type" "sseicvt")
935 (set_attr "athlon_decode" "vector,double")
924 (set_attr "mode" "SF")])
925
926(define_insn "sse_cvtsi2ssq"
927 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
928 (vec_merge:V4SF
929 (vec_duplicate:V4SF
930 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
931 (match_operand:V4SF 1 "register_operand" "0,0")
932 (const_int 1)))]
933 "TARGET_SSE && TARGET_64BIT"
934 "cvtsi2ssq\t{%2, %0|%0, %2}"
935 [(set_attr "type" "sseicvt")
936 (set_attr "athlon_decode" "vector,double")
937 (set_attr "amdfam10_decode" "vector,double")
936 (set_attr "mode" "SF")])
937
938(define_insn "sse_cvtss2si"
939 [(set (match_operand:SI 0 "register_operand" "=r,r")
940 (unspec:SI
941 [(vec_select:SF
942 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
943 (parallel [(const_int 0)]))]
944 UNSPEC_FIX_NOTRUNC))]
945 "TARGET_SSE"
946 "cvtss2si\t{%1, %0|%0, %1}"
947 [(set_attr "type" "sseicvt")
948 (set_attr "athlon_decode" "double,vector")
938 (set_attr "mode" "SF")])
939
940(define_insn "sse_cvtss2si"
941 [(set (match_operand:SI 0 "register_operand" "=r,r")
942 (unspec:SI
943 [(vec_select:SF
944 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
945 (parallel [(const_int 0)]))]
946 UNSPEC_FIX_NOTRUNC))]
947 "TARGET_SSE"
948 "cvtss2si\t{%1, %0|%0, %1}"
949 [(set_attr "type" "sseicvt")
950 (set_attr "athlon_decode" "double,vector")
951 (set_attr "amdfam10_decode" "double,double")
949 (set_attr "mode" "SI")])
950
951(define_insn "sse_cvtss2siq"
952 [(set (match_operand:DI 0 "register_operand" "=r,r")
953 (unspec:DI
954 [(vec_select:SF
955 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
956 (parallel [(const_int 0)]))]
957 UNSPEC_FIX_NOTRUNC))]
958 "TARGET_SSE && TARGET_64BIT"
959 "cvtss2siq\t{%1, %0|%0, %1}"
960 [(set_attr "type" "sseicvt")
961 (set_attr "athlon_decode" "double,vector")
952 (set_attr "mode" "SI")])
953
954(define_insn "sse_cvtss2siq"
955 [(set (match_operand:DI 0 "register_operand" "=r,r")
956 (unspec:DI
957 [(vec_select:SF
958 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
959 (parallel [(const_int 0)]))]
960 UNSPEC_FIX_NOTRUNC))]
961 "TARGET_SSE && TARGET_64BIT"
962 "cvtss2siq\t{%1, %0|%0, %1}"
963 [(set_attr "type" "sseicvt")
964 (set_attr "athlon_decode" "double,vector")
965 (set_attr "amdfam10_decode" "double,double")
962 (set_attr "mode" "DI")])
963
964(define_insn "sse_cvttss2si"
965 [(set (match_operand:SI 0 "register_operand" "=r,r")
966 (fix:SI
967 (vec_select:SF
968 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
969 (parallel [(const_int 0)]))))]
970 "TARGET_SSE"
971 "cvttss2si\t{%1, %0|%0, %1}"
972 [(set_attr "type" "sseicvt")
973 (set_attr "athlon_decode" "double,vector")
966 (set_attr "mode" "DI")])
967
968(define_insn "sse_cvttss2si"
969 [(set (match_operand:SI 0 "register_operand" "=r,r")
970 (fix:SI
971 (vec_select:SF
972 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
973 (parallel [(const_int 0)]))))]
974 "TARGET_SSE"
975 "cvttss2si\t{%1, %0|%0, %1}"
976 [(set_attr "type" "sseicvt")
977 (set_attr "athlon_decode" "double,vector")
978 (set_attr "amdfam10_decode" "double,double")
974 (set_attr "mode" "SI")])
975
976(define_insn "sse_cvttss2siq"
977 [(set (match_operand:DI 0 "register_operand" "=r,r")
978 (fix:DI
979 (vec_select:SF
980 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
981 (parallel [(const_int 0)]))))]
982 "TARGET_SSE && TARGET_64BIT"
983 "cvttss2siq\t{%1, %0|%0, %1}"
984 [(set_attr "type" "sseicvt")
985 (set_attr "athlon_decode" "double,vector")
979 (set_attr "mode" "SI")])
980
981(define_insn "sse_cvttss2siq"
982 [(set (match_operand:DI 0 "register_operand" "=r,r")
983 (fix:DI
984 (vec_select:SF
985 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
986 (parallel [(const_int 0)]))))]
987 "TARGET_SSE && TARGET_64BIT"
988 "cvttss2siq\t{%1, %0|%0, %1}"
989 [(set_attr "type" "sseicvt")
990 (set_attr "athlon_decode" "double,vector")
991 (set_attr "amdfam10_decode" "double,double")
986 (set_attr "mode" "DI")])
987
988(define_insn "sse2_cvtdq2ps"
989 [(set (match_operand:V4SF 0 "register_operand" "=x")
990 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
991 "TARGET_SSE2"
992 "cvtdq2ps\t{%1, %0|%0, %1}"
993 [(set_attr "type" "ssecvt")

--- 853 unchanged lines hidden (view full) ---

1847 (vec_duplicate:V2DF
1848 (float:DF (match_operand:SI 2 "nonimmediate_operand" "r,m")))
1849 (match_operand:V2DF 1 "register_operand" "0,0")
1850 (const_int 1)))]
1851 "TARGET_SSE2"
1852 "cvtsi2sd\t{%2, %0|%0, %2}"
1853 [(set_attr "type" "sseicvt")
1854 (set_attr "mode" "DF")
992 (set_attr "mode" "DI")])
993
994(define_insn "sse2_cvtdq2ps"
995 [(set (match_operand:V4SF 0 "register_operand" "=x")
996 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
997 "TARGET_SSE2"
998 "cvtdq2ps\t{%1, %0|%0, %1}"
999 [(set_attr "type" "ssecvt")

--- 853 unchanged lines hidden (view full) ---

1853 (vec_duplicate:V2DF
1854 (float:DF (match_operand:SI 2 "nonimmediate_operand" "r,m")))
1855 (match_operand:V2DF 1 "register_operand" "0,0")
1856 (const_int 1)))]
1857 "TARGET_SSE2"
1858 "cvtsi2sd\t{%2, %0|%0, %2}"
1859 [(set_attr "type" "sseicvt")
1860 (set_attr "mode" "DF")
1855 (set_attr "athlon_decode" "double,direct")])
1861 (set_attr "athlon_decode" "double,direct")
1862 (set_attr "amdfam10_decode" "vector,double")])
1856
1857(define_insn "sse2_cvtsi2sdq"
1858 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
1859 (vec_merge:V2DF
1860 (vec_duplicate:V2DF
1861 (float:DF (match_operand:DI 2 "nonimmediate_operand" "r,m")))
1862 (match_operand:V2DF 1 "register_operand" "0,0")
1863 (const_int 1)))]
1864 "TARGET_SSE2 && TARGET_64BIT"
1865 "cvtsi2sdq\t{%2, %0|%0, %2}"
1866 [(set_attr "type" "sseicvt")
1867 (set_attr "mode" "DF")
1863
1864(define_insn "sse2_cvtsi2sdq"
1865 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
1866 (vec_merge:V2DF
1867 (vec_duplicate:V2DF
1868 (float:DF (match_operand:DI 2 "nonimmediate_operand" "r,m")))
1869 (match_operand:V2DF 1 "register_operand" "0,0")
1870 (const_int 1)))]
1871 "TARGET_SSE2 && TARGET_64BIT"
1872 "cvtsi2sdq\t{%2, %0|%0, %2}"
1873 [(set_attr "type" "sseicvt")
1874 (set_attr "mode" "DF")
1868 (set_attr "athlon_decode" "double,direct")])
1875 (set_attr "athlon_decode" "double,direct")
1876 (set_attr "amdfam10_decode" "vector,double")])
1869
1870(define_insn "sse2_cvtsd2si"
1871 [(set (match_operand:SI 0 "register_operand" "=r,r")
1872 (unspec:SI
1873 [(vec_select:DF
1874 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
1875 (parallel [(const_int 0)]))]
1876 UNSPEC_FIX_NOTRUNC))]
1877 "TARGET_SSE2"
1878 "cvtsd2si\t{%1, %0|%0, %1}"
1879 [(set_attr "type" "sseicvt")
1880 (set_attr "athlon_decode" "double,vector")
1877
1878(define_insn "sse2_cvtsd2si"
1879 [(set (match_operand:SI 0 "register_operand" "=r,r")
1880 (unspec:SI
1881 [(vec_select:DF
1882 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
1883 (parallel [(const_int 0)]))]
1884 UNSPEC_FIX_NOTRUNC))]
1885 "TARGET_SSE2"
1886 "cvtsd2si\t{%1, %0|%0, %1}"
1887 [(set_attr "type" "sseicvt")
1888 (set_attr "athlon_decode" "double,vector")
1889 (set_attr "amdfam10_decode" "double,double")
1881 (set_attr "mode" "SI")])
1882
1883(define_insn "sse2_cvtsd2siq"
1884 [(set (match_operand:DI 0 "register_operand" "=r,r")
1885 (unspec:DI
1886 [(vec_select:DF
1887 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
1888 (parallel [(const_int 0)]))]
1889 UNSPEC_FIX_NOTRUNC))]
1890 "TARGET_SSE2 && TARGET_64BIT"
1891 "cvtsd2siq\t{%1, %0|%0, %1}"
1892 [(set_attr "type" "sseicvt")
1893 (set_attr "athlon_decode" "double,vector")
1890 (set_attr "mode" "SI")])
1891
1892(define_insn "sse2_cvtsd2siq"
1893 [(set (match_operand:DI 0 "register_operand" "=r,r")
1894 (unspec:DI
1895 [(vec_select:DF
1896 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
1897 (parallel [(const_int 0)]))]
1898 UNSPEC_FIX_NOTRUNC))]
1899 "TARGET_SSE2 && TARGET_64BIT"
1900 "cvtsd2siq\t{%1, %0|%0, %1}"
1901 [(set_attr "type" "sseicvt")
1902 (set_attr "athlon_decode" "double,vector")
1903 (set_attr "amdfam10_decode" "double,double")
1894 (set_attr "mode" "DI")])
1895
1896(define_insn "sse2_cvttsd2si"
1897 [(set (match_operand:SI 0 "register_operand" "=r,r")
1898 (fix:SI
1899 (vec_select:DF
1900 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
1901 (parallel [(const_int 0)]))))]
1902 "TARGET_SSE2"
1903 "cvttsd2si\t{%1, %0|%0, %1}"
1904 [(set_attr "type" "sseicvt")
1905 (set_attr "mode" "SI")
1904 (set_attr "mode" "DI")])
1905
1906(define_insn "sse2_cvttsd2si"
1907 [(set (match_operand:SI 0 "register_operand" "=r,r")
1908 (fix:SI
1909 (vec_select:DF
1910 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
1911 (parallel [(const_int 0)]))))]
1912 "TARGET_SSE2"
1913 "cvttsd2si\t{%1, %0|%0, %1}"
1914 [(set_attr "type" "sseicvt")
1915 (set_attr "mode" "SI")
1906 (set_attr "athlon_decode" "double,vector")])
1916 (set_attr "athlon_decode" "double,vector")
1917 (set_attr "amdfam10_decode" "double,double")])
1907
1908(define_insn "sse2_cvttsd2siq"
1909 [(set (match_operand:DI 0 "register_operand" "=r,r")
1910 (fix:DI
1911 (vec_select:DF
1912 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
1913 (parallel [(const_int 0)]))))]
1914 "TARGET_SSE2 && TARGET_64BIT"
1915 "cvttsd2siq\t{%1, %0|%0, %1}"
1916 [(set_attr "type" "sseicvt")
1917 (set_attr "mode" "DI")
1918
1919(define_insn "sse2_cvttsd2siq"
1920 [(set (match_operand:DI 0 "register_operand" "=r,r")
1921 (fix:DI
1922 (vec_select:DF
1923 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
1924 (parallel [(const_int 0)]))))]
1925 "TARGET_SSE2 && TARGET_64BIT"
1926 "cvttsd2siq\t{%1, %0|%0, %1}"
1927 [(set_attr "type" "sseicvt")
1928 (set_attr "mode" "DI")
1918 (set_attr "athlon_decode" "double,vector")])
1929 (set_attr "athlon_decode" "double,vector")
1930 (set_attr "amdfam10_decode" "double,double")])
1919
1920(define_insn "sse2_cvtdq2pd"
1921 [(set (match_operand:V2DF 0 "register_operand" "=x")
1922 (float:V2DF
1923 (vec_select:V2SI
1924 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
1925 (parallel [(const_int 0) (const_int 1)]))))]
1926 "TARGET_SSE2"

--- 14 unchanged lines hidden (view full) ---

1941 [(set (match_operand:V4SI 0 "register_operand" "=x")
1942 (vec_concat:V4SI
1943 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
1944 UNSPEC_FIX_NOTRUNC)
1945 (match_operand:V2SI 2 "const0_operand" "")))]
1946 "TARGET_SSE2"
1947 "cvtpd2dq\t{%1, %0|%0, %1}"
1948 [(set_attr "type" "ssecvt")
1931
1932(define_insn "sse2_cvtdq2pd"
1933 [(set (match_operand:V2DF 0 "register_operand" "=x")
1934 (float:V2DF
1935 (vec_select:V2SI
1936 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
1937 (parallel [(const_int 0) (const_int 1)]))))]
1938 "TARGET_SSE2"

--- 14 unchanged lines hidden (view full) ---

1953 [(set (match_operand:V4SI 0 "register_operand" "=x")
1954 (vec_concat:V4SI
1955 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
1956 UNSPEC_FIX_NOTRUNC)
1957 (match_operand:V2SI 2 "const0_operand" "")))]
1958 "TARGET_SSE2"
1959 "cvtpd2dq\t{%1, %0|%0, %1}"
1960 [(set_attr "type" "ssecvt")
1949 (set_attr "mode" "TI")])
1961 (set_attr "mode" "TI")
1962 (set_attr "amdfam10_decode" "double")])
1950
1951(define_expand "sse2_cvttpd2dq"
1952 [(set (match_operand:V4SI 0 "register_operand" "")
1953 (vec_concat:V4SI
1954 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" ""))
1955 (match_dup 2)))]
1956 "TARGET_SSE2"
1957 "operands[2] = CONST0_RTX (V2SImode);")
1958
1959(define_insn "*sse2_cvttpd2dq"
1960 [(set (match_operand:V4SI 0 "register_operand" "=x")
1961 (vec_concat:V4SI
1962 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
1963 (match_operand:V2SI 2 "const0_operand" "")))]
1964 "TARGET_SSE2"
1965 "cvttpd2dq\t{%1, %0|%0, %1}"
1966 [(set_attr "type" "ssecvt")
1963
1964(define_expand "sse2_cvttpd2dq"
1965 [(set (match_operand:V4SI 0 "register_operand" "")
1966 (vec_concat:V4SI
1967 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" ""))
1968 (match_dup 2)))]
1969 "TARGET_SSE2"
1970 "operands[2] = CONST0_RTX (V2SImode);")
1971
1972(define_insn "*sse2_cvttpd2dq"
1973 [(set (match_operand:V4SI 0 "register_operand" "=x")
1974 (vec_concat:V4SI
1975 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
1976 (match_operand:V2SI 2 "const0_operand" "")))]
1977 "TARGET_SSE2"
1978 "cvttpd2dq\t{%1, %0|%0, %1}"
1979 [(set_attr "type" "ssecvt")
1967 (set_attr "mode" "TI")])
1980 (set_attr "mode" "TI")
1981 (set_attr "amdfam10_decode" "double")])
1968
1969(define_insn "sse2_cvtsd2ss"
1970 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
1971 (vec_merge:V4SF
1972 (vec_duplicate:V4SF
1973 (float_truncate:V2SF
1974 (match_operand:V2DF 2 "nonimmediate_operand" "x,m")))
1975 (match_operand:V4SF 1 "register_operand" "0,0")
1976 (const_int 1)))]
1977 "TARGET_SSE2"
1978 "cvtsd2ss\t{%2, %0|%0, %2}"
1979 [(set_attr "type" "ssecvt")
1980 (set_attr "athlon_decode" "vector,double")
1982
1983(define_insn "sse2_cvtsd2ss"
1984 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
1985 (vec_merge:V4SF
1986 (vec_duplicate:V4SF
1987 (float_truncate:V2SF
1988 (match_operand:V2DF 2 "nonimmediate_operand" "x,m")))
1989 (match_operand:V4SF 1 "register_operand" "0,0")
1990 (const_int 1)))]
1991 "TARGET_SSE2"
1992 "cvtsd2ss\t{%2, %0|%0, %2}"
1993 [(set_attr "type" "ssecvt")
1994 (set_attr "athlon_decode" "vector,double")
1995 (set_attr "amdfam10_decode" "vector,double")
1981 (set_attr "mode" "SF")])
1982
1983(define_insn "sse2_cvtss2sd"
1996 (set_attr "mode" "SF")])
1997
1998(define_insn "sse2_cvtss2sd"
1984 [(set (match_operand:V2DF 0 "register_operand" "=x")
1999 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
1985 (vec_merge:V2DF
1986 (float_extend:V2DF
1987 (vec_select:V2SF
2000 (vec_merge:V2DF
2001 (float_extend:V2DF
2002 (vec_select:V2SF
1988 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
2003 (match_operand:V4SF 2 "nonimmediate_operand" "x,m")
1989 (parallel [(const_int 0) (const_int 1)])))
2004 (parallel [(const_int 0) (const_int 1)])))
1990 (match_operand:V2DF 1 "register_operand" "0")
2005 (match_operand:V2DF 1 "register_operand" "0,0")
1991 (const_int 1)))]
1992 "TARGET_SSE2"
1993 "cvtss2sd\t{%2, %0|%0, %2}"
1994 [(set_attr "type" "ssecvt")
2006 (const_int 1)))]
2007 "TARGET_SSE2"
2008 "cvtss2sd\t{%2, %0|%0, %2}"
2009 [(set_attr "type" "ssecvt")
2010 (set_attr "amdfam10_decode" "vector,double")
1995 (set_attr "mode" "DF")])
1996
1997(define_expand "sse2_cvtpd2ps"
1998 [(set (match_operand:V4SF 0 "register_operand" "")
1999 (vec_concat:V4SF
2000 (float_truncate:V2SF
2001 (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
2002 (match_dup 2)))]

--- 4 unchanged lines hidden (view full) ---

2007 [(set (match_operand:V4SF 0 "register_operand" "=x")
2008 (vec_concat:V4SF
2009 (float_truncate:V2SF
2010 (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
2011 (match_operand:V2SF 2 "const0_operand" "")))]
2012 "TARGET_SSE2"
2013 "cvtpd2ps\t{%1, %0|%0, %1}"
2014 [(set_attr "type" "ssecvt")
2011 (set_attr "mode" "DF")])
2012
2013(define_expand "sse2_cvtpd2ps"
2014 [(set (match_operand:V4SF 0 "register_operand" "")
2015 (vec_concat:V4SF
2016 (float_truncate:V2SF
2017 (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
2018 (match_dup 2)))]

--- 4 unchanged lines hidden (view full) ---

2023 [(set (match_operand:V4SF 0 "register_operand" "=x")
2024 (vec_concat:V4SF
2025 (float_truncate:V2SF
2026 (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
2027 (match_operand:V2SF 2 "const0_operand" "")))]
2028 "TARGET_SSE2"
2029 "cvtpd2ps\t{%1, %0|%0, %1}"
2030 [(set_attr "type" "ssecvt")
2015 (set_attr "mode" "V4SF")])
2031 (set_attr "mode" "V4SF")
2032 (set_attr "amdfam10_decode" "double")])
2016
2017(define_insn "sse2_cvtps2pd"
2018 [(set (match_operand:V2DF 0 "register_operand" "=x")
2019 (float_extend:V2DF
2020 (vec_select:V2SF
2021 (match_operand:V4SF 1 "nonimmediate_operand" "xm")
2022 (parallel [(const_int 0) (const_int 1)]))))]
2023 "TARGET_SSE2"
2024 "cvtps2pd\t{%1, %0|%0, %1}"
2025 [(set_attr "type" "ssecvt")
2033
2034(define_insn "sse2_cvtps2pd"
2035 [(set (match_operand:V2DF 0 "register_operand" "=x")
2036 (float_extend:V2DF
2037 (vec_select:V2SF
2038 (match_operand:V4SF 1 "nonimmediate_operand" "xm")
2039 (parallel [(const_int 0) (const_int 1)]))))]
2040 "TARGET_SSE2"
2041 "cvtps2pd\t{%1, %0|%0, %1}"
2042 [(set_attr "type" "ssecvt")
2026 (set_attr "mode" "V2DF")])
2043 (set_attr "mode" "V2DF")
2044 (set_attr "amdfam10_decode" "direct")])
2027
2028;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2029;;
2030;; Parallel double-precision floating point element swizzling
2031;;
2032;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2033
2034(define_insn "sse2_unpckhpd"

--- 2484 unchanged lines hidden (view full) ---

4519
4520(define_insn "abs<mode>2"
4521 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
4522 (abs:MMXMODEI (match_operand:MMXMODEI 1 "nonimmediate_operand" "ym")))]
4523 "TARGET_SSSE3"
4524 "pabs<mmxvecsize>\t{%1, %0|%0, %1}";
4525 [(set_attr "type" "sselog1")
4526 (set_attr "mode" "DI")])
2045
2046;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2047;;
2048;; Parallel double-precision floating point element swizzling
2049;;
2050;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2051
2052(define_insn "sse2_unpckhpd"

--- 2484 unchanged lines hidden (view full) ---

4537
4538(define_insn "abs<mode>2"
4539 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
4540 (abs:MMXMODEI (match_operand:MMXMODEI 1 "nonimmediate_operand" "ym")))]
4541 "TARGET_SSSE3"
4542 "pabs<mmxvecsize>\t{%1, %0|%0, %1}";
4543 [(set_attr "type" "sselog1")
4544 (set_attr "mode" "DI")])
4545
4546;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4547;;
4548;; AMD SSE4A instructions
4549;;
4550;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4551
4552(define_insn "sse4a_vmmovntv2df"
4553 [(set (match_operand:DF 0 "memory_operand" "=m")
4554 (unspec:DF [(vec_select:DF
4555 (match_operand:V2DF 1 "register_operand" "x")
4556 (parallel [(const_int 0)]))]
4557 UNSPEC_MOVNT))]
4558 "TARGET_SSE4A"
4559 "movntsd\t{%1, %0|%0, %1}"
4560 [(set_attr "type" "ssemov")
4561 (set_attr "mode" "DF")])
4562
4563(define_insn "sse4a_movntdf"
4564 [(set (match_operand:DF 0 "memory_operand" "=m")
4565 (unspec:DF [(match_operand:DF 1 "register_operand" "x")]
4566 UNSPEC_MOVNT))]
4567 "TARGET_SSE4A"
4568 "movntsd\t{%1, %0|%0, %1}"
4569 [(set_attr "type" "ssemov")
4570 (set_attr "mode" "DF")])
4571
4572(define_insn "sse4a_vmmovntv4sf"
4573 [(set (match_operand:SF 0 "memory_operand" "=m")
4574 (unspec:SF [(vec_select:SF
4575 (match_operand:V4SF 1 "register_operand" "x")
4576 (parallel [(const_int 0)]))]
4577 UNSPEC_MOVNT))]
4578 "TARGET_SSE4A"
4579 "movntss\t{%1, %0|%0, %1}"
4580 [(set_attr "type" "ssemov")
4581 (set_attr "mode" "SF")])
4582
4583(define_insn "sse4a_movntsf"
4584 [(set (match_operand:SF 0 "memory_operand" "=m")
4585 (unspec:SF [(match_operand:SF 1 "register_operand" "x")]
4586 UNSPEC_MOVNT))]
4587 "TARGET_SSE4A"
4588 "movntss\t{%1, %0|%0, %1}"
4589 [(set_attr "type" "ssemov")
4590 (set_attr "mode" "SF")])
4591
4592(define_insn "sse4a_extrqi"
4593 [(set (match_operand:V2DI 0 "register_operand" "=x")
4594 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
4595 (match_operand 2 "const_int_operand" "")
4596 (match_operand 3 "const_int_operand" "")]
4597 UNSPEC_EXTRQI))]
4598 "TARGET_SSE4A"
4599 "extrq\t{%3, %2, %0|%0, %2, %3}"
4600 [(set_attr "type" "sse")
4601 (set_attr "mode" "TI")])
4602
4603(define_insn "sse4a_extrq"
4604 [(set (match_operand:V2DI 0 "register_operand" "=x")
4605 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
4606 (match_operand:V16QI 2 "register_operand" "x")]
4607 UNSPEC_EXTRQ))]
4608 "TARGET_SSE4A"
4609 "extrq\t{%2, %0|%0, %2}"
4610 [(set_attr "type" "sse")
4611 (set_attr "mode" "TI")])
4612
4613(define_insn "sse4a_insertqi"
4614 [(set (match_operand:V2DI 0 "register_operand" "=x")
4615 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
4616 (match_operand:V2DI 2 "register_operand" "x")
4617 (match_operand 3 "const_int_operand" "")
4618 (match_operand 4 "const_int_operand" "")]
4619 UNSPEC_INSERTQI))]
4620 "TARGET_SSE4A"
4621 "insertq\t{%4, %3, %2, %0|%0, %2, %3, %4}"
4622 [(set_attr "type" "sseins")
4623 (set_attr "mode" "TI")])
4624
4625(define_insn "sse4a_insertq"
4626 [(set (match_operand:V2DI 0 "register_operand" "=x")
4627 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
4628 (match_operand:V2DI 2 "register_operand" "x")]
4629 UNSPEC_INSERTQ))]
4630 "TARGET_SSE4A"
4631 "insertq\t{%2, %0|%0, %2}"
4632 [(set_attr "type" "sseins")
4633 (set_attr "mode" "TI")])