| i386.md (96294) | i386.md (102802) |
|---|---|
| 1;; GCC machine description for IA-32 and x86-64. 2;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 3;; Free Software Foundation, Inc. 4;; Mostly by William Schelter. 5;; x86_64 support added by Jan Hubicka 6;; 7;; This file is part of GNU CC. 8;; --- 99 unchanged lines hidden (view full) --- 108;; "reload_completed && TARGET_64BIT". 109 110 111;; Processor type. This attribute must exactly match the processor_type 112;; enumeration in i386.h. 113(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4" 114 (const (symbol_ref "ix86_cpu"))) 115 | 1;; GCC machine description for IA-32 and x86-64. 2;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 3;; Free Software Foundation, Inc. 4;; Mostly by William Schelter. 5;; x86_64 support added by Jan Hubicka 6;; 7;; This file is part of GNU CC. 8;; --- 99 unchanged lines hidden (view full) --- 108;; "reload_completed && TARGET_64BIT". 109 110 111;; Processor type. This attribute must exactly match the processor_type 112;; enumeration in i386.h. 113(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4" 114 (const (symbol_ref "ix86_cpu"))) 115 |
| 116;; $FreeBSD: head/contrib/gcc/config/i386/i386.md 96294 2002-05-09 22:44:32Z obrien $ | 116;; $FreeBSD: head/contrib/gcc/config/i386/i386.md 102802 2002-09-01 21:13:32Z kan $ |
| 117 118;; A basic instruction type. Refinements due to arguments to be 119;; provided in other attributes. 120(define_attr "type" 121 "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx,fistp" 122 (const_string "other")) 123 124;; Main data type used by the insn --- 1886 unchanged lines hidden (view full) --- 2011 push{w}\t{|word ptr }%1 2012 push{w}\t%w1" 2013 [(set_attr "type" "push") 2014 (set_attr "mode" "HI")]) 2015 2016;; For 64BIT abi we always round up to 8 bytes. 2017(define_insn "*pushqi2_rex64" 2018 [(set (match_operand:QI 0 "push_operand" "=X") | 117 118;; A basic instruction type. Refinements due to arguments to be 119;; provided in other attributes. 120(define_attr "type" 121 "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx,fistp" 122 (const_string "other")) 123 124;; Main data type used by the insn --- 1886 unchanged lines hidden (view full) --- 2011 push{w}\t{|word ptr }%1 2012 push{w}\t%w1" 2013 [(set_attr "type" "push") 2014 (set_attr "mode" "HI")]) 2015 2016;; For 64BIT abi we always round up to 8 bytes. 2017(define_insn "*pushqi2_rex64" 2018 [(set (match_operand:QI 0 "push_operand" "=X") |
| 2019 (match_operand:QI 1 "nonmemory_no_elim_operand" "ri"))] | 2019 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))] |
| 2020 "TARGET_64BIT" 2021 "push{q}\t%q1" 2022 [(set_attr "type" "push") 2023 (set_attr "mode" "QI")]) 2024 2025;; Situation is quite tricky about when to choose full sized (SImode) move 2026;; over QImode moves. For Q_REG -> Q_REG move we use full size only for 2027;; partial register dependency machines (such as AMD Athlon), where QImode --- 524 unchanged lines hidden (view full) --- 2552 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*") 2553 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*") 2554 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI")]) 2555 2556;; Stores and loads of ax to arbitary constant address. 2557;; We fake an second form of instruction to force reload to load address 2558;; into register when rax is not available 2559(define_insn "*movabsdi_1_rex64" | 2020 "TARGET_64BIT" 2021 "push{q}\t%q1" 2022 [(set_attr "type" "push") 2023 (set_attr "mode" "QI")]) 2024 2025;; Situation is quite tricky about when to choose full sized (SImode) move 2026;; over QImode moves. For Q_REG -> Q_REG move we use full size only for 2027;; partial register dependency machines (such as AMD Athlon), where QImode --- 524 unchanged lines hidden (view full) --- 2552 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*") 2553 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*") 2554 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI")]) 2555 2556;; Stores and loads of ax to arbitary constant address. 2557;; We fake an second form of instruction to force reload to load address 2558;; into register when rax is not available 2559(define_insn "*movabsdi_1_rex64" |
| 2560 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r")) 2561 (match_operand:DI 1 "nonmemory_operand" "a,er,i"))] | 2560 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r")) 2561 (match_operand:DI 1 "nonmemory_operand" "a,er"))] |
| 2562 "TARGET_64BIT" 2563 "@ 2564 movabs{q}\t{%1, %P0|%P0, %1} | 2562 "TARGET_64BIT" 2563 "@ 2564 movabs{q}\t{%1, %P0|%P0, %1} |
| 2565 mov{q}\t{%1, %a0|%a0, %1} 2566 movabs{q}\t{%1, %a0|%a0, %1}" | 2565 mov{q}\t{%1, %a0|%a0, %1}" |
| 2567 [(set_attr "type" "imov") | 2566 [(set_attr "type" "imov") |
| 2568 (set_attr "modrm" "0,*,*") 2569 (set_attr "length_address" "8,0,0") 2570 (set_attr "length_immediate" "0,*,*") | 2567 (set_attr "modrm" "0,*") 2568 (set_attr "length_address" "8,0") 2569 (set_attr "length_immediate" "0,*") |
| 2571 (set_attr "memory" "store") 2572 (set_attr "mode" "DI")]) 2573 2574(define_insn "*movabsdi_2_rex64" 2575 [(set (match_operand:DI 0 "register_operand" "=a,r") 2576 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] 2577 "TARGET_64BIT" 2578 "@ --- 8369 unchanged lines hidden (view full) --- 10948 10949;; This pattern can't accept a variable shift count, since shifts by 10950;; zero don't affect the flags. We assume that shifts by constant 10951;; zero are optimized away. 10952(define_insn "*ashlsi3_cmp" 10953 [(set (reg 17) 10954 (compare 10955 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0") | 2570 (set_attr "memory" "store") 2571 (set_attr "mode" "DI")]) 2572 2573(define_insn "*movabsdi_2_rex64" 2574 [(set (match_operand:DI 0 "register_operand" "=a,r") 2575 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] 2576 "TARGET_64BIT" 2577 "@ --- 8369 unchanged lines hidden (view full) --- 10947 10948;; This pattern can't accept a variable shift count, since shifts by 10949;; zero don't affect the flags. We assume that shifts by constant 10950;; zero are optimized away. 10951(define_insn "*ashlsi3_cmp" 10952 [(set (reg 17) 10953 (compare 10954 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
| 10956 (match_operand:QI 2 "immediate_operand" "I")) | 10955 (match_operand:QI 2 "const_int_1_31_operand" "I")) |
| 10957 (const_int 0))) 10958 (set (match_operand:SI 0 "nonimmediate_operand" "=rm") 10959 (ashift:SI (match_dup 1) (match_dup 2)))] 10960 "ix86_match_ccmode (insn, CCGOCmode) 10961 && ix86_binary_operator_ok (ASHIFT, SImode, operands)" 10962{ 10963 switch (get_attr_type (insn)) 10964 { --- 22 unchanged lines hidden (view full) --- 10987 ] 10988 (const_string "ishift"))) 10989 (set_attr "mode" "SI")]) 10990 10991(define_insn "*ashlsi3_cmp_zext" 10992 [(set (reg 17) 10993 (compare 10994 (ashift:SI (match_operand:SI 1 "register_operand" "0") | 10956 (const_int 0))) 10957 (set (match_operand:SI 0 "nonimmediate_operand" "=rm") 10958 (ashift:SI (match_dup 1) (match_dup 2)))] 10959 "ix86_match_ccmode (insn, CCGOCmode) 10960 && ix86_binary_operator_ok (ASHIFT, SImode, operands)" 10961{ 10962 switch (get_attr_type (insn)) 10963 { --- 22 unchanged lines hidden (view full) --- 10986 ] 10987 (const_string "ishift"))) 10988 (set_attr "mode" "SI")]) 10989 10990(define_insn "*ashlsi3_cmp_zext" 10991 [(set (reg 17) 10992 (compare 10993 (ashift:SI (match_operand:SI 1 "register_operand" "0") |
| 10995 (match_operand:QI 2 "immediate_operand" "I")) | 10994 (match_operand:QI 2 "const_int_1_31_operand" "I")) |
| 10996 (const_int 0))) 10997 (set (match_operand:DI 0 "register_operand" "=r") 10998 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))] 10999 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 11000 && ix86_binary_operator_ok (ASHIFT, SImode, operands)" 11001{ 11002 switch (get_attr_type (insn)) 11003 { --- 108 unchanged lines hidden (view full) --- 11112 11113;; This pattern can't accept a variable shift count, since shifts by 11114;; zero don't affect the flags. We assume that shifts by constant 11115;; zero are optimized away. 11116(define_insn "*ashlhi3_cmp" 11117 [(set (reg 17) 11118 (compare 11119 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0") | 10995 (const_int 0))) 10996 (set (match_operand:DI 0 "register_operand" "=r") 10997 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))] 10998 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 10999 && ix86_binary_operator_ok (ASHIFT, SImode, operands)" 11000{ 11001 switch (get_attr_type (insn)) 11002 { --- 108 unchanged lines hidden (view full) --- 11111 11112;; This pattern can't accept a variable shift count, since shifts by 11113;; zero don't affect the flags. We assume that shifts by constant 11114;; zero are optimized away. 11115(define_insn "*ashlhi3_cmp" 11116 [(set (reg 17) 11117 (compare 11118 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0") |
| 11120 (match_operand:QI 2 "immediate_operand" "I")) | 11119 (match_operand:QI 2 "const_int_1_31_operand" "I")) |
| 11121 (const_int 0))) 11122 (set (match_operand:HI 0 "nonimmediate_operand" "=rm") 11123 (ashift:HI (match_dup 1) (match_dup 2)))] 11124 "ix86_match_ccmode (insn, CCGOCmode) 11125 && ix86_binary_operator_ok (ASHIFT, HImode, operands)" 11126{ 11127 switch (get_attr_type (insn)) 11128 { --- 147 unchanged lines hidden (view full) --- 11276 11277;; This pattern can't accept a variable shift count, since shifts by 11278;; zero don't affect the flags. We assume that shifts by constant 11279;; zero are optimized away. 11280(define_insn "*ashlqi3_cmp" 11281 [(set (reg 17) 11282 (compare 11283 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0") | 11120 (const_int 0))) 11121 (set (match_operand:HI 0 "nonimmediate_operand" "=rm") 11122 (ashift:HI (match_dup 1) (match_dup 2)))] 11123 "ix86_match_ccmode (insn, CCGOCmode) 11124 && ix86_binary_operator_ok (ASHIFT, HImode, operands)" 11125{ 11126 switch (get_attr_type (insn)) 11127 { --- 147 unchanged lines hidden (view full) --- 11275 11276;; This pattern can't accept a variable shift count, since shifts by 11277;; zero don't affect the flags. We assume that shifts by constant 11278;; zero are optimized away. 11279(define_insn "*ashlqi3_cmp" 11280 [(set (reg 17) 11281 (compare 11282 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0") |
| 11284 (match_operand:QI 2 "immediate_operand" "I")) | 11283 (match_operand:QI 2 "const_int_1_31_operand" "I")) |
| 11285 (const_int 0))) 11286 (set (match_operand:QI 0 "nonimmediate_operand" "=qm") 11287 (ashift:QI (match_dup 1) (match_dup 2)))] 11288 "ix86_match_ccmode (insn, CCGOCmode) 11289 && ix86_binary_operator_ok (ASHIFT, QImode, operands)" 11290{ 11291 switch (get_attr_type (insn)) 11292 { --- 333 unchanged lines hidden (view full) --- 11626 11627;; This pattern can't accept a variable shift count, since shifts by 11628;; zero don't affect the flags. We assume that shifts by constant 11629;; zero are optimized away. 11630(define_insn "*ashrsi3_cmp" 11631 [(set (reg 17) 11632 (compare 11633 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") | 11284 (const_int 0))) 11285 (set (match_operand:QI 0 "nonimmediate_operand" "=qm") 11286 (ashift:QI (match_dup 1) (match_dup 2)))] 11287 "ix86_match_ccmode (insn, CCGOCmode) 11288 && ix86_binary_operator_ok (ASHIFT, QImode, operands)" 11289{ 11290 switch (get_attr_type (insn)) 11291 { --- 333 unchanged lines hidden (view full) --- 11625 11626;; This pattern can't accept a variable shift count, since shifts by 11627;; zero don't affect the flags. We assume that shifts by constant 11628;; zero are optimized away. 11629(define_insn "*ashrsi3_cmp" 11630 [(set (reg 17) 11631 (compare 11632 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
| 11634 (match_operand:QI 2 "immediate_operand" "I")) | 11633 (match_operand:QI 2 "const_int_1_31_operand" "I")) |
| 11635 (const_int 0))) 11636 (set (match_operand:SI 0 "nonimmediate_operand" "=rm") 11637 (ashiftrt:SI (match_dup 1) (match_dup 2)))] 11638 "ix86_match_ccmode (insn, CCGOCmode) 11639 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" 11640 "sar{l}\t{%2, %0|%0, %2}" 11641 [(set_attr "type" "ishift") 11642 (set_attr "mode" "SI")]) 11643 11644(define_insn "*ashrsi3_cmp_zext" 11645 [(set (reg 17) 11646 (compare 11647 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | 11634 (const_int 0))) 11635 (set (match_operand:SI 0 "nonimmediate_operand" "=rm") 11636 (ashiftrt:SI (match_dup 1) (match_dup 2)))] 11637 "ix86_match_ccmode (insn, CCGOCmode) 11638 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" 11639 "sar{l}\t{%2, %0|%0, %2}" 11640 [(set_attr "type" "ishift") 11641 (set_attr "mode" "SI")]) 11642 11643(define_insn "*ashrsi3_cmp_zext" 11644 [(set (reg 17) 11645 (compare 11646 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
| 11648 (match_operand:QI 2 "immediate_operand" "I")) | 11647 (match_operand:QI 2 "const_int_1_31_operand" "I")) |
| 11649 (const_int 0))) 11650 (set (match_operand:DI 0 "register_operand" "=r") 11651 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))] 11652 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 11653 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" 11654 "sar{l}\t{%2, %k0|%k0, %2}" 11655 [(set_attr "type" "ishift") 11656 (set_attr "mode" "SI")]) --- 55 unchanged lines hidden (view full) --- 11712 11713;; This pattern can't accept a variable shift count, since shifts by 11714;; zero don't affect the flags. We assume that shifts by constant 11715;; zero are optimized away. 11716(define_insn "*ashrhi3_cmp" 11717 [(set (reg 17) 11718 (compare 11719 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") | 11648 (const_int 0))) 11649 (set (match_operand:DI 0 "register_operand" "=r") 11650 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))] 11651 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 11652 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" 11653 "sar{l}\t{%2, %k0|%k0, %2}" 11654 [(set_attr "type" "ishift") 11655 (set_attr "mode" "SI")]) --- 55 unchanged lines hidden (view full) --- 11711 11712;; This pattern can't accept a variable shift count, since shifts by 11713;; zero don't affect the flags. We assume that shifts by constant 11714;; zero are optimized away. 11715(define_insn "*ashrhi3_cmp" 11716 [(set (reg 17) 11717 (compare 11718 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") |
| 11720 (match_operand:QI 2 "immediate_operand" "I")) | 11719 (match_operand:QI 2 "const_int_1_31_operand" "I")) |
| 11721 (const_int 0))) 11722 (set (match_operand:HI 0 "nonimmediate_operand" "=rm") 11723 (ashiftrt:HI (match_dup 1) (match_dup 2)))] 11724 "ix86_match_ccmode (insn, CCGOCmode) 11725 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" 11726 "sar{w}\t{%2, %0|%0, %2}" 11727 [(set_attr "type" "ishift") 11728 (set_attr "mode" "HI")]) --- 36 unchanged lines hidden (view full) --- 11765;; zero don't affect the flags. We assume that shifts by constant 11766;; zero are optimized away. 11767(define_insn "*ashrqi3_one_bit_cmp" 11768 [(set (reg 17) 11769 (compare 11770 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") 11771 (match_operand:QI 2 "const_int_1_operand" "I")) 11772 (const_int 0))) | 11720 (const_int 0))) 11721 (set (match_operand:HI 0 "nonimmediate_operand" "=rm") 11722 (ashiftrt:HI (match_dup 1) (match_dup 2)))] 11723 "ix86_match_ccmode (insn, CCGOCmode) 11724 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" 11725 "sar{w}\t{%2, %0|%0, %2}" 11726 [(set_attr "type" "ishift") 11727 (set_attr "mode" "HI")]) --- 36 unchanged lines hidden (view full) --- 11764;; zero don't affect the flags. We assume that shifts by constant 11765;; zero are optimized away. 11766(define_insn "*ashrqi3_one_bit_cmp" 11767 [(set (reg 17) 11768 (compare 11769 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") 11770 (match_operand:QI 2 "const_int_1_operand" "I")) 11771 (const_int 0))) |
| 11773 (set (match_operand:QI 0 "nonimmediate_operand" "=rm") | 11772 (set (match_operand:QI 0 "nonimmediate_operand" "=qm") |
| 11774 (ashiftrt:QI (match_dup 1) (match_dup 2)))] 11775 "ix86_match_ccmode (insn, CCGOCmode) 11776 && (TARGET_PENTIUM || TARGET_PENTIUMPRO) 11777 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" 11778 "sar{b}\t%0" 11779 [(set_attr "type" "ishift") 11780 (set (attr "length") 11781 (if_then_else (match_operand 0 "register_operand" "") 11782 (const_string "2") 11783 (const_string "*")))]) 11784 11785;; This pattern can't accept a variable shift count, since shifts by 11786;; zero don't affect the flags. We assume that shifts by constant 11787;; zero are optimized away. 11788(define_insn "*ashrqi3_cmp" 11789 [(set (reg 17) 11790 (compare 11791 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") | 11773 (ashiftrt:QI (match_dup 1) (match_dup 2)))] 11774 "ix86_match_ccmode (insn, CCGOCmode) 11775 && (TARGET_PENTIUM || TARGET_PENTIUMPRO) 11776 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" 11777 "sar{b}\t%0" 11778 [(set_attr "type" "ishift") 11779 (set (attr "length") 11780 (if_then_else (match_operand 0 "register_operand" "") 11781 (const_string "2") 11782 (const_string "*")))]) 11783 11784;; This pattern can't accept a variable shift count, since shifts by 11785;; zero don't affect the flags. We assume that shifts by constant 11786;; zero are optimized away. 11787(define_insn "*ashrqi3_cmp" 11788 [(set (reg 17) 11789 (compare 11790 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") |
| 11792 (match_operand:QI 2 "immediate_operand" "I")) | 11791 (match_operand:QI 2 "const_int_1_31_operand" "I")) |
| 11793 (const_int 0))) | 11792 (const_int 0))) |
| 11794 (set (match_operand:QI 0 "nonimmediate_operand" "=rm") | 11793 (set (match_operand:QI 0 "nonimmediate_operand" "=qm") |
| 11795 (ashiftrt:QI (match_dup 1) (match_dup 2)))] 11796 "ix86_match_ccmode (insn, CCGOCmode) 11797 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" 11798 "sar{b}\t{%2, %0|%0, %2}" 11799 [(set_attr "type" "ishift") 11800 (set_attr "mode" "QI")]) 11801 11802;; Logical shift instructions --- 214 unchanged lines hidden (view full) --- 12017 12018;; This pattern can't accept a variable shift count, since shifts by 12019;; zero don't affect the flags. We assume that shifts by constant 12020;; zero are optimized away. 12021(define_insn "*lshrsi3_cmp" 12022 [(set (reg 17) 12023 (compare 12024 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") | 11794 (ashiftrt:QI (match_dup 1) (match_dup 2)))] 11795 "ix86_match_ccmode (insn, CCGOCmode) 11796 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" 11797 "sar{b}\t{%2, %0|%0, %2}" 11798 [(set_attr "type" "ishift") 11799 (set_attr "mode" "QI")]) 11800 11801;; Logical shift instructions --- 214 unchanged lines hidden (view full) --- 12016 12017;; This pattern can't accept a variable shift count, since shifts by 12018;; zero don't affect the flags. We assume that shifts by constant 12019;; zero are optimized away. 12020(define_insn "*lshrsi3_cmp" 12021 [(set (reg 17) 12022 (compare 12023 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
| 12025 (match_operand:QI 2 "immediate_operand" "I")) | 12024 (match_operand:QI 2 "const_int_1_31_operand" "I")) |
| 12026 (const_int 0))) 12027 (set (match_operand:SI 0 "nonimmediate_operand" "=rm") 12028 (lshiftrt:SI (match_dup 1) (match_dup 2)))] 12029 "ix86_match_ccmode (insn, CCGOCmode) 12030 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 12031 "shr{l}\t{%2, %0|%0, %2}" 12032 [(set_attr "type" "ishift") 12033 (set_attr "mode" "SI")]) 12034 12035(define_insn "*lshrsi3_cmp_zext" 12036 [(set (reg 17) 12037 (compare 12038 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | 12025 (const_int 0))) 12026 (set (match_operand:SI 0 "nonimmediate_operand" "=rm") 12027 (lshiftrt:SI (match_dup 1) (match_dup 2)))] 12028 "ix86_match_ccmode (insn, CCGOCmode) 12029 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 12030 "shr{l}\t{%2, %0|%0, %2}" 12031 [(set_attr "type" "ishift") 12032 (set_attr "mode" "SI")]) 12033 12034(define_insn "*lshrsi3_cmp_zext" 12035 [(set (reg 17) 12036 (compare 12037 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") |
| 12039 (match_operand:QI 2 "immediate_operand" "I")) | 12038 (match_operand:QI 2 "const_int_1_31_operand" "I")) |
| 12040 (const_int 0))) 12041 (set (match_operand:DI 0 "register_operand" "=r") 12042 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))] 12043 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 12044 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 12045 "shr{l}\t{%2, %k0|%k0, %2}" 12046 [(set_attr "type" "ishift") 12047 (set_attr "mode" "SI")]) --- 55 unchanged lines hidden (view full) --- 12103 12104;; This pattern can't accept a variable shift count, since shifts by 12105;; zero don't affect the flags. We assume that shifts by constant 12106;; zero are optimized away. 12107(define_insn "*lshrhi3_cmp" 12108 [(set (reg 17) 12109 (compare 12110 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") | 12039 (const_int 0))) 12040 (set (match_operand:DI 0 "register_operand" "=r") 12041 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))] 12042 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 12043 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 12044 "shr{l}\t{%2, %k0|%k0, %2}" 12045 [(set_attr "type" "ishift") 12046 (set_attr "mode" "SI")]) --- 55 unchanged lines hidden (view full) --- 12102 12103;; This pattern can't accept a variable shift count, since shifts by 12104;; zero don't affect the flags. We assume that shifts by constant 12105;; zero are optimized away. 12106(define_insn "*lshrhi3_cmp" 12107 [(set (reg 17) 12108 (compare 12109 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") |
| 12111 (match_operand:QI 2 "immediate_operand" "I")) | 12110 (match_operand:QI 2 "const_int_1_31_operand" "I")) |
| 12112 (const_int 0))) 12113 (set (match_operand:HI 0 "nonimmediate_operand" "=rm") 12114 (lshiftrt:HI (match_dup 1) (match_dup 2)))] 12115 "ix86_match_ccmode (insn, CCGOCmode) 12116 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 12117 "shr{w}\t{%2, %0|%0, %2}" 12118 [(set_attr "type" "ishift") 12119 (set_attr "mode" "HI")]) --- 55 unchanged lines hidden (view full) --- 12175 12176;; This pattern can't accept a variable shift count, since shifts by 12177;; zero don't affect the flags. We assume that shifts by constant 12178;; zero are optimized away. 12179(define_insn "*lshrqi2_cmp" 12180 [(set (reg 17) 12181 (compare 12182 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") | 12111 (const_int 0))) 12112 (set (match_operand:HI 0 "nonimmediate_operand" "=rm") 12113 (lshiftrt:HI (match_dup 1) (match_dup 2)))] 12114 "ix86_match_ccmode (insn, CCGOCmode) 12115 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 12116 "shr{w}\t{%2, %0|%0, %2}" 12117 [(set_attr "type" "ishift") 12118 (set_attr "mode" "HI")]) --- 55 unchanged lines hidden (view full) --- 12174 12175;; This pattern can't accept a variable shift count, since shifts by 12176;; zero don't affect the flags. We assume that shifts by constant 12177;; zero are optimized away. 12178(define_insn "*lshrqi2_cmp" 12179 [(set (reg 17) 12180 (compare 12181 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") |
| 12183 (match_operand:QI 2 "immediate_operand" "I")) | 12182 (match_operand:QI 2 "const_int_1_31_operand" "I")) |
| 12184 (const_int 0))) 12185 (set (match_operand:QI 0 "nonimmediate_operand" "=qm") 12186 (lshiftrt:QI (match_dup 1) (match_dup 2)))] 12187 "ix86_match_ccmode (insn, CCGOCmode) 12188 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)" 12189 "shr{b}\t{%2, %0|%0, %2}" 12190 [(set_attr "type" "ishift") 12191 (set_attr "mode" "QI")]) --- 1621 unchanged lines hidden (view full) --- 13813{ 13814 if (GET_CODE (operands[1]) == LABEL_REF) 13815 operands[1] = XEXP (operands[1], 0); 13816 output_asm_insn ("call\t%X1", operands); 13817 if (! TARGET_DEEP_BRANCH_PREDICTION) 13818 { 13819 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", 13820 CODE_LABEL_NUMBER (operands[1])); | 12183 (const_int 0))) 12184 (set (match_operand:QI 0 "nonimmediate_operand" "=qm") 12185 (lshiftrt:QI (match_dup 1) (match_dup 2)))] 12186 "ix86_match_ccmode (insn, CCGOCmode) 12187 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)" 12188 "shr{b}\t{%2, %0|%0, %2}" 12189 [(set_attr "type" "ishift") 12190 (set_attr "mode" "QI")]) --- 1621 unchanged lines hidden (view full) --- 13812{ 13813 if (GET_CODE (operands[1]) == LABEL_REF) 13814 operands[1] = XEXP (operands[1], 0); 13815 output_asm_insn ("call\t%X1", operands); 13816 if (! TARGET_DEEP_BRANCH_PREDICTION) 13817 { 13818 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", 13819 CODE_LABEL_NUMBER (operands[1])); |
| 13820 return "pop{l}\t%0"; |
|
| 13821 } 13822 RET; 13823} 13824 [(set_attr "type" "multi")]) 13825 13826(define_expand "epilogue" 13827 [(const_int 1)] 13828 "" --- 2744 unchanged lines hidden (view full) --- 16573 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx"))) 16574 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X")) 16575 (clobber (reg:CC 17))] 16576 "TARGET_SSE 16577 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 16578 "#") 16579 16580(define_insn "sse_movdfcc" | 13821 } 13822 RET; 13823} 13824 [(set_attr "type" "multi")]) 13825 13826(define_expand "epilogue" 13827 [(const_int 1)] 13828 "" --- 2744 unchanged lines hidden (view full) --- 16573 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx"))) 16574 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X")) 16575 (clobber (reg:CC 17))] 16576 "TARGET_SSE 16577 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 16578 "#") 16579 16580(define_insn "sse_movdfcc" |
| 16581 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf") | 16581 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf") |
| 16582 (if_then_else:DF (match_operator 1 "sse_comparison_operator" | 16582 (if_then_else:DF (match_operator 1 "sse_comparison_operator" |
| 16583 [(match_operand:DF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f") 16584 (match_operand:DF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")]) 16585 (match_operand:DF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx") 16586 (match_operand:DF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx"))) | 16583 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f") 16584 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")]) 16585 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY") 16586 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY"))) |
| 16587 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X")) 16588 (clobber (reg:CC 17))] 16589 "TARGET_SSE2 16590 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM) 16591 && (!TARGET_IEEE_FP 16592 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))" 16593 "#") 16594 16595(define_insn "sse_movdfcc_eq" | 16587 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X")) 16588 (clobber (reg:CC 17))] 16589 "TARGET_SSE2 16590 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM) 16591 && (!TARGET_IEEE_FP 16592 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))" 16593 "#") 16594 16595(define_insn "sse_movdfcc_eq" |
| 16596 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf") 16597 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f") 16598 (match_operand:DF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f")) 16599 (match_operand:DF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx") 16600 (match_operand:DF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx"))) | 16596 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf") 16597 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f") 16598 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f")) 16599 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY") 16600 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY"))) |
| 16601 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X")) 16602 (clobber (reg:CC 17))] 16603 "TARGET_SSE 16604 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 16605 "#") 16606 16607;; For non-sse moves just expand the usual cmove sequence. 16608(define_split --- 35 unchanged lines hidden (view full) --- 16644 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)])) 16645 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0) 16646 (subreg:TI (match_dup 4) 0))) 16647 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0)) 16648 (subreg:TI (match_dup 3) 0))) 16649 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0) 16650 (subreg:TI (match_dup 7) 0)))] 16651{ | 16601 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X")) 16602 (clobber (reg:CC 17))] 16603 "TARGET_SSE 16604 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 16605 "#") 16606 16607;; For non-sse moves just expand the usual cmove sequence. 16608(define_split --- 35 unchanged lines hidden (view full) --- 16644 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)])) 16645 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0) 16646 (subreg:TI (match_dup 4) 0))) 16647 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0)) 16648 (subreg:TI (match_dup 3) 0))) 16649 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0) 16650 (subreg:TI (match_dup 7) 0)))] 16651{ |
| 16652 /* If op2 == op3, op3 will be clobbered before it is used. 16653 This should be optimized out though. */ 16654 if (operands_match_p (operands[2], operands[3])) 16655 abort (); |
|
| 16652 PUT_MODE (operands[1], GET_MODE (operands[0])); 16653 if (operands_match_p (operands[0], operands[4])) 16654 operands[6] = operands[4], operands[7] = operands[2]; 16655 else 16656 operands[6] = operands[2], operands[7] = operands[4]; 16657}) 16658 16659;; Special case of conditional move we can handle effectivly. 16660;; Do not brother with the integer/floating point case, since these are 16661;; bot considerably slower, unlike in the generic case. 16662(define_insn "*sse_movsfcc_const0_1" | 16656 PUT_MODE (operands[1], GET_MODE (operands[0])); 16657 if (operands_match_p (operands[0], operands[4])) 16658 operands[6] = operands[4], operands[7] = operands[2]; 16659 else 16660 operands[6] = operands[2], operands[7] = operands[4]; 16661}) 16662 16663;; Special case of conditional move we can handle effectivly. 16664;; Do not brother with the integer/floating point case, since these are 16665;; bot considerably slower, unlike in the generic case. 16666(define_insn "*sse_movsfcc_const0_1" |
| 16663 [(set (match_operand:SF 0 "register_operand" "=x") | 16667 [(set (match_operand:SF 0 "register_operand" "=&x") |
| 16664 (if_then_else:SF (match_operator 1 "sse_comparison_operator" 16665 [(match_operand:SF 4 "register_operand" "0") 16666 (match_operand:SF 5 "nonimmediate_operand" "xm")]) 16667 (match_operand:SF 2 "register_operand" "x") 16668 (match_operand:SF 3 "const0_operand" "X")))] 16669 "TARGET_SSE" 16670 "#") 16671 16672(define_insn "*sse_movsfcc_const0_2" | 16668 (if_then_else:SF (match_operator 1 "sse_comparison_operator" 16669 [(match_operand:SF 4 "register_operand" "0") 16670 (match_operand:SF 5 "nonimmediate_operand" "xm")]) 16671 (match_operand:SF 2 "register_operand" "x") 16672 (match_operand:SF 3 "const0_operand" "X")))] 16673 "TARGET_SSE" 16674 "#") 16675 16676(define_insn "*sse_movsfcc_const0_2" |
| 16673 [(set (match_operand:SF 0 "register_operand" "=x") | 16677 [(set (match_operand:SF 0 "register_operand" "=&x") |
| 16674 (if_then_else:SF (match_operator 1 "sse_comparison_operator" 16675 [(match_operand:SF 4 "register_operand" "0") 16676 (match_operand:SF 5 "nonimmediate_operand" "xm")]) 16677 (match_operand:SF 2 "const0_operand" "X") 16678 (match_operand:SF 3 "register_operand" "x")))] 16679 "TARGET_SSE" 16680 "#") 16681 16682(define_insn "*sse_movsfcc_const0_3" | 16678 (if_then_else:SF (match_operator 1 "sse_comparison_operator" 16679 [(match_operand:SF 4 "register_operand" "0") 16680 (match_operand:SF 5 "nonimmediate_operand" "xm")]) 16681 (match_operand:SF 2 "const0_operand" "X") 16682 (match_operand:SF 3 "register_operand" "x")))] 16683 "TARGET_SSE" 16684 "#") 16685 16686(define_insn "*sse_movsfcc_const0_3" |
| 16683 [(set (match_operand:SF 0 "register_operand" "=x") | 16687 [(set (match_operand:SF 0 "register_operand" "=&x") |
| 16684 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" 16685 [(match_operand:SF 4 "nonimmediate_operand" "xm") 16686 (match_operand:SF 5 "register_operand" "0")]) 16687 (match_operand:SF 2 "register_operand" "x") 16688 (match_operand:SF 3 "const0_operand" "X")))] 16689 "TARGET_SSE" 16690 "#") 16691 16692(define_insn "*sse_movsfcc_const0_4" | 16688 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" 16689 [(match_operand:SF 4 "nonimmediate_operand" "xm") 16690 (match_operand:SF 5 "register_operand" "0")]) 16691 (match_operand:SF 2 "register_operand" "x") 16692 (match_operand:SF 3 "const0_operand" "X")))] 16693 "TARGET_SSE" 16694 "#") 16695 16696(define_insn "*sse_movsfcc_const0_4" |
| 16693 [(set (match_operand:SF 0 "register_operand" "=x") | 16697 [(set (match_operand:SF 0 "register_operand" "=&x") |
| 16694 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" 16695 [(match_operand:SF 4 "nonimmediate_operand" "xm") 16696 (match_operand:SF 5 "register_operand" "0")]) 16697 (match_operand:SF 2 "const0_operand" "X") 16698 (match_operand:SF 3 "register_operand" "x")))] 16699 "TARGET_SSE" 16700 "#") 16701 16702(define_insn "*sse_movdfcc_const0_1" | 16698 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" 16699 [(match_operand:SF 4 "nonimmediate_operand" "xm") 16700 (match_operand:SF 5 "register_operand" "0")]) 16701 (match_operand:SF 2 "const0_operand" "X") 16702 (match_operand:SF 3 "register_operand" "x")))] 16703 "TARGET_SSE" 16704 "#") 16705 16706(define_insn "*sse_movdfcc_const0_1" |
| 16703 [(set (match_operand:SF 0 "register_operand" "=x") 16704 (if_then_else:SF (match_operator 1 "sse_comparison_operator" 16705 [(match_operand:SF 4 "register_operand" "0") 16706 (match_operand:SF 5 "nonimmediate_operand" "xm")]) 16707 (match_operand:SF 2 "register_operand" "x") 16708 (match_operand:SF 3 "const0_operand" "X")))] | 16707 [(set (match_operand:DF 0 "register_operand" "=&Y") 16708 (if_then_else:DF (match_operator 1 "sse_comparison_operator" 16709 [(match_operand:DF 4 "register_operand" "0") 16710 (match_operand:DF 5 "nonimmediate_operand" "Ym")]) 16711 (match_operand:DF 2 "register_operand" "Y") 16712 (match_operand:DF 3 "const0_operand" "X")))] |
| 16709 "TARGET_SSE2" 16710 "#") 16711 16712(define_insn "*sse_movdfcc_const0_2" | 16713 "TARGET_SSE2" 16714 "#") 16715 16716(define_insn "*sse_movdfcc_const0_2" |
| 16713 [(set (match_operand:SF 0 "register_operand" "=x") 16714 (if_then_else:SF (match_operator 1 "sse_comparison_operator" 16715 [(match_operand:SF 4 "register_operand" "0") 16716 (match_operand:SF 5 "nonimmediate_operand" "xm")]) 16717 (match_operand:SF 2 "const0_operand" "X") 16718 (match_operand:SF 3 "register_operand" "x")))] | 16717 [(set (match_operand:DF 0 "register_operand" "=&Y") 16718 (if_then_else:DF (match_operator 1 "sse_comparison_operator" 16719 [(match_operand:DF 4 "register_operand" "0") 16720 (match_operand:DF 5 "nonimmediate_operand" "Ym")]) 16721 (match_operand:DF 2 "const0_operand" "X") 16722 (match_operand:DF 3 "register_operand" "Y")))] |
| 16719 "TARGET_SSE2" 16720 "#") 16721 16722(define_insn "*sse_movdfcc_const0_3" | 16723 "TARGET_SSE2" 16724 "#") 16725 16726(define_insn "*sse_movdfcc_const0_3" |
| 16723 [(set (match_operand:SF 0 "register_operand" "=x") 16724 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" 16725 [(match_operand:SF 4 "nonimmediate_operand" "xm") 16726 (match_operand:SF 5 "register_operand" "0")]) 16727 (match_operand:SF 2 "register_operand" "x") 16728 (match_operand:SF 3 "const0_operand" "X")))] | 16727 [(set (match_operand:DF 0 "register_operand" "=&Y") 16728 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 16729 [(match_operand:DF 4 "nonimmediate_operand" "Ym") 16730 (match_operand:DF 5 "register_operand" "0")]) 16731 (match_operand:DF 2 "register_operand" "Y") 16732 (match_operand:DF 3 "const0_operand" "X")))] |
| 16729 "TARGET_SSE2" 16730 "#") 16731 16732(define_insn "*sse_movdfcc_const0_4" | 16733 "TARGET_SSE2" 16734 "#") 16735 16736(define_insn "*sse_movdfcc_const0_4" |
| 16733 [(set (match_operand:SF 0 "register_operand" "=x") 16734 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" 16735 [(match_operand:SF 4 "nonimmediate_operand" "xm") 16736 (match_operand:SF 5 "register_operand" "0")]) 16737 (match_operand:SF 2 "const0_operand" "X") 16738 (match_operand:SF 3 "register_operand" "x")))] | 16737 [(set (match_operand:DF 0 "register_operand" "=&Y") 16738 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 16739 [(match_operand:DF 4 "nonimmediate_operand" "Ym") 16740 (match_operand:DF 5 "register_operand" "0")]) 16741 (match_operand:DF 2 "const0_operand" "X") 16742 (match_operand:DF 3 "register_operand" "Y")))] |
| 16739 "TARGET_SSE2" 16740 "#") 16741 16742(define_split 16743 [(set (match_operand 0 "register_operand" "") 16744 (if_then_else (match_operator 1 "comparison_operator" 16745 [(match_operand 4 "register_operand" "") 16746 (match_operand 5 "nonimmediate_operand" "")]) --- 3029 unchanged lines hidden (view full) --- 19776 [(set (match_operand:V2SF 0 "register_operand" "=y") 19777 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym") 19778 (parallel [(const_int 1) (const_int 0)])))] 19779 "TARGET_3DNOW_A" 19780 "pswapd\\t{%1, %0|%0, %1}" 19781 [(set_attr "type" "mmx")]) 19782 19783(define_expand "prefetch" | 16743 "TARGET_SSE2" 16744 "#") 16745 16746(define_split 16747 [(set (match_operand 0 "register_operand" "") 16748 (if_then_else (match_operator 1 "comparison_operator" 16749 [(match_operand 4 "register_operand" "") 16750 (match_operand 5 "nonimmediate_operand" "")]) --- 3029 unchanged lines hidden (view full) --- 19780 [(set (match_operand:V2SF 0 "register_operand" "=y") 19781 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym") 19782 (parallel [(const_int 1) (const_int 0)])))] 19783 "TARGET_3DNOW_A" 19784 "pswapd\\t{%1, %0|%0, %1}" 19785 [(set_attr "type" "mmx")]) 19786 19787(define_expand "prefetch" |
| 19784 [(prefetch (match_operand:SI 0 "address_operand" "") | 19788 [(prefetch (match_operand 0 "address_operand" "") |
| 19785 (match_operand:SI 1 "const_int_operand" "") 19786 (match_operand:SI 2 "const_int_operand" ""))] 19787 "TARGET_PREFETCH_SSE || TARGET_3DNOW" 19788{ 19789 int rw = INTVAL (operands[1]); 19790 int locality = INTVAL (operands[2]); 19791 19792 if (rw != 0 && rw != 1) 19793 abort (); 19794 if (locality < 0 || locality > 3) 19795 abort (); | 19789 (match_operand:SI 1 "const_int_operand" "") 19790 (match_operand:SI 2 "const_int_operand" ""))] 19791 "TARGET_PREFETCH_SSE || TARGET_3DNOW" 19792{ 19793 int rw = INTVAL (operands[1]); 19794 int locality = INTVAL (operands[2]); 19795 19796 if (rw != 0 && rw != 1) 19797 abort (); 19798 if (locality < 0 || locality > 3) 19799 abort (); |
| 19800 if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode) 19801 abort (); |
|
| 19796 19797 /* Use 3dNOW prefetch in case we are asking for write prefetch not 19798 suported by SSE counterpart or the SSE prefetch is not available 19799 (K6 machines). Otherwise use SSE prefetch as it allows specifying 19800 of locality. */ 19801 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw)) 19802 operands[2] = GEN_INT (3); 19803 else 19804 operands[1] = const0_rtx; 19805}) 19806 19807(define_insn "*prefetch_sse" 19808 [(prefetch (match_operand:SI 0 "address_operand" "p") 19809 (const_int 0) 19810 (match_operand:SI 1 "const_int_operand" ""))] | 19802 19803 /* Use 3dNOW prefetch in case we are asking for write prefetch not 19804 suported by SSE counterpart or the SSE prefetch is not available 19805 (K6 machines). Otherwise use SSE prefetch as it allows specifying 19806 of locality. */ 19807 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw)) 19808 operands[2] = GEN_INT (3); 19809 else 19810 operands[1] = const0_rtx; 19811}) 19812 19813(define_insn "*prefetch_sse" 19814 [(prefetch (match_operand:SI 0 "address_operand" "p") 19815 (const_int 0) 19816 (match_operand:SI 1 "const_int_operand" ""))] |
| 19811 "TARGET_PREFETCH_SSE" | 19817 "TARGET_PREFETCH_SSE && !TARGET_64BIT" |
| 19812{ 19813 static const char * const patterns[4] = { 19814 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0" 19815 }; 19816 19817 int locality = INTVAL (operands[1]); 19818 if (locality < 0 || locality > 3) 19819 abort (); 19820 19821 return patterns[locality]; 19822} | 19818{ 19819 static const char * const patterns[4] = { 19820 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0" 19821 }; 19822 19823 int locality = INTVAL (operands[1]); 19824 if (locality < 0 || locality > 3) 19825 abort (); 19826 19827 return patterns[locality]; 19828} |
| 19829 [(set_attr "type" "sse") 19830 (set_attr "memory" "none")]) 19831 19832(define_insn "*prefetch_sse_rex" 19833 [(prefetch (match_operand:DI 0 "address_operand" "p") 19834 (const_int 0) 19835 (match_operand:SI 1 "const_int_operand" ""))] 19836 "TARGET_PREFETCH_SSE && TARGET_64BIT" 19837{ 19838 static const char * const patterns[4] = { 19839 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0" 19840 }; 19841 19842 int locality = INTVAL (operands[1]); 19843 if (locality < 0 || locality > 3) 19844 abort (); 19845 19846 return patterns[locality]; 19847} |
|
| 19823 [(set_attr "type" "sse")]) 19824 19825(define_insn "*prefetch_3dnow" 19826 [(prefetch (match_operand:SI 0 "address_operand" "p") 19827 (match_operand:SI 1 "const_int_operand" "n") 19828 (const_int 3))] | 19848 [(set_attr "type" "sse")]) 19849 19850(define_insn "*prefetch_3dnow" 19851 [(prefetch (match_operand:SI 0 "address_operand" "p") 19852 (match_operand:SI 1 "const_int_operand" "n") 19853 (const_int 3))] |
| 19829 "TARGET_3DNOW" | 19854 "TARGET_3DNOW && !TARGET_64BIT" |
| 19830{ 19831 if (INTVAL (operands[1]) == 0) 19832 return "prefetch\t%a0"; 19833 else 19834 return "prefetchw\t%a0"; 19835} | 19855{ 19856 if (INTVAL (operands[1]) == 0) 19857 return "prefetch\t%a0"; 19858 else 19859 return "prefetchw\t%a0"; 19860} |
| 19861 [(set_attr "type" "mmx") 19862 (set_attr "memory" "none")]) 19863 19864(define_insn "*prefetch_3dnow_rex" 19865 [(prefetch (match_operand:DI 0 "address_operand" "p") 19866 (match_operand:SI 1 "const_int_operand" "n") 19867 (const_int 3))] 19868 "TARGET_3DNOW && TARGET_64BIT" 19869{ 19870 if (INTVAL (operands[1]) == 0) 19871 return "prefetch\t%a0"; 19872 else 19873 return "prefetchw\t%a0"; 19874} |
|
| 19836 [(set_attr "type" "mmx")]) | 19875 [(set_attr "type" "mmx")]) |