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i386.md (90286) i386.md (96294)
1;; GCC machine description for IA-32 and x86-64.
2;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3;; Free Software Foundation, Inc.
4;; Mostly by William Schelter.
5;; x86_64 support added by Jan Hubicka
6;;
7;; This file is part of GNU CC.
8;;

--- 99 unchanged lines hidden (view full) ---

108;; "reload_completed && TARGET_64BIT".
109
110
111;; Processor type. This attribute must exactly match the processor_type
112;; enumeration in i386.h.
113(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
114 (const (symbol_ref "ix86_cpu")))
115
1;; GCC machine description for IA-32 and x86-64.
2;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3;; Free Software Foundation, Inc.
4;; Mostly by William Schelter.
5;; x86_64 support added by Jan Hubicka
6;;
7;; This file is part of GNU CC.
8;;

--- 99 unchanged lines hidden (view full) ---

108;; "reload_completed && TARGET_64BIT".
109
110
111;; Processor type. This attribute must exactly match the processor_type
112;; enumeration in i386.h.
113(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
114 (const (symbol_ref "ix86_cpu")))
115
116;; $FreeBSD: head/contrib/gcc/config/i386/i386.md 90286 2002-02-06 05:02:18Z obrien $
116;; $FreeBSD: head/contrib/gcc/config/i386/i386.md 96294 2002-05-09 22:44:32Z obrien $
117
118;; A basic instruction type. Refinements due to arguments to be
119;; provided in other attributes.
120(define_attr "type"
121 "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx,fistp"
122 (const_string "other"))
123
124;; Main data type used by the insn

--- 1605 unchanged lines hidden (view full) ---

1730{
1731 operands[1] = constm1_rtx;
1732 return "or{l}\t{%1, %0|%0, %1}";
1733}
1734 [(set_attr "type" "alu1")
1735 (set_attr "mode" "SI")
1736 (set_attr "length_immediate" "1")])
1737
117
118;; A basic instruction type. Refinements due to arguments to be
119;; provided in other attributes.
120(define_attr "type"
121 "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx,fistp"
122 (const_string "other"))
123
124;; Main data type used by the insn

--- 1605 unchanged lines hidden (view full) ---

1730{
1731 operands[1] = constm1_rtx;
1732 return "or{l}\t{%1, %0|%0, %1}";
1733}
1734 [(set_attr "type" "alu1")
1735 (set_attr "mode" "SI")
1736 (set_attr "length_immediate" "1")])
1737
1738; The first alternative is used only to compute proper length of instruction.
1739; Reload's algorithm does not take into account the cost of spill instructions
1740; needed to free register in given class, so avoid it from choosing the first
1741; alternative when eax is not available.
1742
1738(define_insn "*movsi_1"
1743(define_insn "*movsi_1"
1739 [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!rm,!*Y,!rm,!*Y")
1740 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,rm,*Y,*Y"))]
1744 [(set (match_operand:SI 0 "nonimmediate_operand" "=*?a,r,*?a,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
1745 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,*y,rm,*Y,*Y"))]
1741 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1742{
1743 switch (get_attr_type (insn))
1744 {
1745 case TYPE_SSE:
1746 if (get_attr_mode (insn) == TImode)
1747 return "movdqa\t{%1, %0|%0, %1}";
1748 return "movd\t{%1, %0|%0, %1}";
1749
1750 case TYPE_MMX:
1746 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1747{
1748 switch (get_attr_type (insn))
1749 {
1750 case TYPE_SSE:
1751 if (get_attr_mode (insn) == TImode)
1752 return "movdqa\t{%1, %0|%0, %1}";
1753 return "movd\t{%1, %0|%0, %1}";
1754
1755 case TYPE_MMX:
1756 if (get_attr_mode (insn) == DImode)
1757 return "movq\t{%1, %0|%0, %1}";
1751 return "movd\t{%1, %0|%0, %1}";
1752
1753 case TYPE_LEA:
1754 return "lea{l}\t{%1, %0|%0, %1}";
1755
1756 default:
1757 if (flag_pic && SYMBOLIC_CONST (operands[1]))
1758 abort();
1759 return "mov{l}\t{%1, %0|%0, %1}";
1760 }
1761}
1762 [(set (attr "type")
1758 return "movd\t{%1, %0|%0, %1}";
1759
1760 case TYPE_LEA:
1761 return "lea{l}\t{%1, %0|%0, %1}";
1762
1763 default:
1764 if (flag_pic && SYMBOLIC_CONST (operands[1]))
1765 abort();
1766 return "mov{l}\t{%1, %0|%0, %1}";
1767 }
1768}
1769 [(set (attr "type")
1763 (cond [(eq_attr "alternative" "4,5")
1770 (cond [(eq_attr "alternative" "4,5,6")
1764 (const_string "mmx")
1771 (const_string "mmx")
1765 (eq_attr "alternative" "6,7,8")
1772 (eq_attr "alternative" "7,8,9")
1766 (const_string "sse")
1767 (and (ne (symbol_ref "flag_pic") (const_int 0))
1768 (match_operand:SI 1 "symbolic_operand" ""))
1769 (const_string "lea")
1770 ]
1771 (const_string "imov")))
1773 (const_string "sse")
1774 (and (ne (symbol_ref "flag_pic") (const_int 0))
1775 (match_operand:SI 1 "symbolic_operand" ""))
1776 (const_string "lea")
1777 ]
1778 (const_string "imov")))
1772 (set_attr "modrm" "0,*,0,*,*,*,*,*,*")
1773 (set_attr "mode" "SI,SI,SI,SI,SI,SI,TI,SI,SI")])
1779 (set_attr "modrm" "0,*,0,*,*,*,*,*,*,*")
1780 (set_attr "mode" "SI,SI,SI,SI,SI,SI,DI,TI,SI,SI")])
1774
1775;; Stores and loads of ax to arbitary constant address.
1776;; We fake an second form of instruction to force reload to load address
1777;; into register when rax is not available
1778(define_insn "*movabssi_1_rex64"
1779 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1780 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1781 "TARGET_64BIT"

--- 56 unchanged lines hidden (view full) ---

1838(define_insn "*pushhi2_rex64"
1839 [(set (match_operand:HI 0 "push_operand" "=X")
1840 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1841 "TARGET_64BIT"
1842 "push{q}\t%q1"
1843 [(set_attr "type" "push")
1844 (set_attr "mode" "QI")])
1845
1781
1782;; Stores and loads of ax to arbitary constant address.
1783;; We fake an second form of instruction to force reload to load address
1784;; into register when rax is not available
1785(define_insn "*movabssi_1_rex64"
1786 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1787 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1788 "TARGET_64BIT"

--- 56 unchanged lines hidden (view full) ---

1845(define_insn "*pushhi2_rex64"
1846 [(set (match_operand:HI 0 "push_operand" "=X")
1847 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1848 "TARGET_64BIT"
1849 "push{q}\t%q1"
1850 [(set_attr "type" "push")
1851 (set_attr "mode" "QI")])
1852
1853; The first alternative is used only to compute proper length of instruction.
1854; Reload's algorithm does not take into account the cost of spill instructions
1855; needed to free register in given class, so avoid it from choosing the first
1856; alternative when eax is not available.
1857
1846(define_insn "*movhi_1"
1858(define_insn "*movhi_1"
1847 [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m")
1859 [(set (match_operand:HI 0 "nonimmediate_operand" "=*?a,r,r,*?a,r,m")
1848 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1849 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1850{
1851 switch (get_attr_type (insn))
1852 {
1853 case TYPE_IMOVX:
1854 /* movzwl is faster than movw on p2 due to partial word stalls,
1855 though not as fast as an aligned movl. */

--- 601 unchanged lines hidden (view full) ---

2457 operands[1] = constm1_rtx;
2458 return "or{q}\t{%1, %0|%0, %1}";
2459}
2460 [(set_attr "type" "alu1")
2461 (set_attr "mode" "DI")
2462 (set_attr "length_immediate" "1")])
2463
2464(define_insn "*movdi_2"
1860 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1861 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1862{
1863 switch (get_attr_type (insn))
1864 {
1865 case TYPE_IMOVX:
1866 /* movzwl is faster than movw on p2 due to partial word stalls,
1867 though not as fast as an aligned movl. */

--- 601 unchanged lines hidden (view full) ---

2469 operands[1] = constm1_rtx;
2470 return "or{q}\t{%1, %0|%0, %1}";
2471}
2472 [(set_attr "type" "alu1")
2473 (set_attr "mode" "DI")
2474 (set_attr "length_immediate" "1")])
2475
2476(define_insn "*movdi_2"
2465 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,*Y,!*Y")
2477 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
2466 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
2467 "!TARGET_64BIT
2468 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2469 "@
2470 #
2471 #
2472 movq\t{%1, %0|%0, %1}
2473 movq\t{%1, %0|%0, %1}

--- 236 unchanged lines hidden (view full) ---

2710(define_split
2711 [(set (match_operand:SF 0 "push_operand" "")
2712 (match_operand:SF 1 "register_operand" ""))]
2713 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2714 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2715 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2716
2717(define_insn "*movsf_1"
2478 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
2479 "!TARGET_64BIT
2480 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2481 "@
2482 #
2483 #
2484 movq\t{%1, %0|%0, %1}
2485 movq\t{%1, %0|%0, %1}

--- 236 unchanged lines hidden (view full) ---

2722(define_split
2723 [(set (match_operand:SF 0 "push_operand" "")
2724 (match_operand:SF 1 "register_operand" ""))]
2725 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2726 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2727 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2728
2729(define_insn "*movsf_1"
2718 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m")
2719 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf"))]
2730 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
2731 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf,rm,*y,*y"))]
2720 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2721 && (reload_in_progress || reload_completed
2722 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2723 || GET_CODE (operands[1]) != CONST_DOUBLE
2724 || memory_operand (operands[0], SFmode))"
2725{
2726 switch (which_alternative)
2727 {

--- 21 unchanged lines hidden (view full) ---

2749 return "fld1";
2750 }
2751 abort();
2752
2753 case 3:
2754 case 4:
2755 return "mov{l}\t{%1, %0|%0, %1}";
2756 case 5:
2732 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2733 && (reload_in_progress || reload_completed
2734 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2735 || GET_CODE (operands[1]) != CONST_DOUBLE
2736 || memory_operand (operands[0], SFmode))"
2737{
2738 switch (which_alternative)
2739 {

--- 21 unchanged lines hidden (view full) ---

2761 return "fld1";
2762 }
2763 abort();
2764
2765 case 3:
2766 case 4:
2767 return "mov{l}\t{%1, %0|%0, %1}";
2768 case 5:
2757 return "pxor\t%0, %0";
2769 if (TARGET_SSE2)
2770 return "pxor\t%0, %0";
2771 else
2772 return "xorps\t%0, %0";
2758 case 6:
2759 if (TARGET_PARTIAL_REG_DEPENDENCY)
2760 return "movaps\t{%1, %0|%0, %1}";
2761 else
2762 return "movss\t{%1, %0|%0, %1}";
2763 case 7:
2764 case 8:
2765 return "movss\t{%1, %0|%0, %1}";
2766
2773 case 6:
2774 if (TARGET_PARTIAL_REG_DEPENDENCY)
2775 return "movaps\t{%1, %0|%0, %1}";
2776 else
2777 return "movss\t{%1, %0|%0, %1}";
2778 case 7:
2779 case 8:
2780 return "movss\t{%1, %0|%0, %1}";
2781
2782 case 9:
2783 case 10:
2784 return "movd\t{%1, %0|%0, %1}";
2785
2786 case 11:
2787 return "movq\t{%1, %0|%0, %1}";
2788
2767 default:
2768 abort();
2769 }
2770}
2789 default:
2790 abort();
2791 }
2792}
2771 [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse")
2772 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF")])
2793 [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse,mmx,mmx,mmx")
2794 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF,SI,SI,DI")])
2773
2774(define_insn "*swapsf"
2775 [(set (match_operand:SF 0 "register_operand" "+f")
2776 (match_operand:SF 1 "register_operand" "+f"))
2777 (set (match_dup 1)
2778 (match_dup 0))]
2779 "reload_completed || !TARGET_SSE"
2780{

--- 2343 unchanged lines hidden (view full) ---

5124 #"
5125 [(set_attr "type" "fmov,multi")
5126 (set_attr "mode" "DF")
5127 (set_attr "fp_int_src" "true")])
5128
5129(define_expand "floatsidf2"
5130 [(set (match_operand:DF 0 "register_operand" "")
5131 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
2795
2796(define_insn "*swapsf"
2797 [(set (match_operand:SF 0 "register_operand" "+f")
2798 (match_operand:SF 1 "register_operand" "+f"))
2799 (set (match_dup 1)
2800 (match_dup 0))]
2801 "reload_completed || !TARGET_SSE"
2802{

--- 2343 unchanged lines hidden (view full) ---

5146 #"
5147 [(set_attr "type" "fmov,multi")
5148 (set_attr "mode" "DF")
5149 (set_attr "fp_int_src" "true")])
5150
5151(define_expand "floatsidf2"
5152 [(set (match_operand:DF 0 "register_operand" "")
5153 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
5132 ""
5154 "TARGET_80387 || TARGET_SSE2"
5133 "")
5134
5135(define_insn "*floatsidf2_i387"
5136 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
5137 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
5138 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5139 "@
5140 fild%z1\t%1

--- 2186 unchanged lines hidden (view full) ---

7327 "@
7328 imul{w}\t{%2, %1, %0|%0, %1, %2}
7329 imul{w}\t{%2, %1, %0|%0, %1, %2}
7330 imul{w}\t{%2, %0|%0, %2}"
7331 [(set_attr "type" "imul")
7332 (set_attr "prefix_0f" "0,0,1")
7333 (set_attr "mode" "HI")])
7334
5155 "")
5156
5157(define_insn "*floatsidf2_i387"
5158 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
5159 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
5160 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5161 "@
5162 fild%z1\t%1

--- 2186 unchanged lines hidden (view full) ---

7349 "@
7350 imul{w}\t{%2, %1, %0|%0, %1, %2}
7351 imul{w}\t{%2, %1, %0|%0, %1, %2}
7352 imul{w}\t{%2, %0|%0, %2}"
7353 [(set_attr "type" "imul")
7354 (set_attr "prefix_0f" "0,0,1")
7355 (set_attr "mode" "HI")])
7356
7335(define_insn "mulqi3"
7357(define_expand "mulqi3"
7358 [(parallel [(set (match_operand:QI 0 "register_operand" "")
7359 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
7360 (match_operand:QI 2 "register_operand" "")))
7361 (clobber (reg:CC 17))])]
7362 "TARGET_QIMODE_MATH"
7363 "")
7364
7365(define_insn "*mulqi3_1"
7336 [(set (match_operand:QI 0 "register_operand" "=a")
7366 [(set (match_operand:QI 0 "register_operand" "=a")
7337 (mult:QI (match_operand:QI 1 "register_operand" "%0")
7367 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7338 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7339 (clobber (reg:CC 17))]
7368 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7369 (clobber (reg:CC 17))]
7340 "TARGET_QIMODE_MATH"
7370 "TARGET_QIMODE_MATH
7371 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7341 "mul{b}\t%2"
7342 [(set_attr "type" "imul")
7343 (set_attr "length_immediate" "0")
7344 (set_attr "mode" "QI")])
7345
7372 "mul{b}\t%2"
7373 [(set_attr "type" "imul")
7374 (set_attr "length_immediate" "0")
7375 (set_attr "mode" "QI")])
7376
7346(define_insn "umulqihi3"
7377(define_expand "umulqihi3"
7378 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7379 (mult:HI (zero_extend:HI
7380 (match_operand:QI 1 "nonimmediate_operand" ""))
7381 (zero_extend:HI
7382 (match_operand:QI 2 "register_operand" ""))))
7383 (clobber (reg:CC 17))])]
7384 "TARGET_QIMODE_MATH"
7385 "")
7386
7387(define_insn "*umulqihi3_1"
7347 [(set (match_operand:HI 0 "register_operand" "=a")
7388 [(set (match_operand:HI 0 "register_operand" "=a")
7348 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7389 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7349 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7350 (clobber (reg:CC 17))]
7390 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7391 (clobber (reg:CC 17))]
7351 "TARGET_QIMODE_MATH"
7392 "TARGET_QIMODE_MATH
7393 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7352 "mul{b}\t%2"
7353 [(set_attr "type" "imul")
7354 (set_attr "length_immediate" "0")
7355 (set_attr "mode" "QI")])
7356
7394 "mul{b}\t%2"
7395 [(set_attr "type" "imul")
7396 (set_attr "length_immediate" "0")
7397 (set_attr "mode" "QI")])
7398
7357(define_insn "mulqihi3"
7399(define_expand "mulqihi3"
7400 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7401 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
7402 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
7403 (clobber (reg:CC 17))])]
7404 "TARGET_QIMODE_MATH"
7405 "")
7406
7407(define_insn "*mulqihi3_insn"
7358 [(set (match_operand:HI 0 "register_operand" "=a")
7408 [(set (match_operand:HI 0 "register_operand" "=a")
7359 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7409 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7360 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7361 (clobber (reg:CC 17))]
7410 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7411 (clobber (reg:CC 17))]
7362 "TARGET_QIMODE_MATH"
7412 "TARGET_QIMODE_MATH
7413 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7363 "imul{b}\t%2"
7364 [(set_attr "type" "imul")
7365 (set_attr "length_immediate" "0")
7366 (set_attr "mode" "QI")])
7367
7414 "imul{b}\t%2"
7415 [(set_attr "type" "imul")
7416 (set_attr "length_immediate" "0")
7417 (set_attr "mode" "QI")])
7418
7368(define_insn "umulditi3"
7419(define_expand "umulditi3"
7420 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7421 (mult:TI (zero_extend:TI
7422 (match_operand:DI 1 "nonimmediate_operand" ""))
7423 (zero_extend:TI
7424 (match_operand:DI 2 "register_operand" ""))))
7425 (clobber (reg:CC 17))])]
7426 "TARGET_64BIT"
7427 "")
7428
7429(define_insn "*umulditi3_insn"
7369 [(set (match_operand:TI 0 "register_operand" "=A")
7430 [(set (match_operand:TI 0 "register_operand" "=A")
7370 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7431 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7371 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7372 (clobber (reg:CC 17))]
7432 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7433 (clobber (reg:CC 17))]
7373 "TARGET_64BIT"
7434 "TARGET_64BIT
7435 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7374 "mul{q}\t%2"
7375 [(set_attr "type" "imul")
7376 (set_attr "ppro_uops" "few")
7377 (set_attr "length_immediate" "0")
7378 (set_attr "mode" "DI")])
7379
7380;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7436 "mul{q}\t%2"
7437 [(set_attr "type" "imul")
7438 (set_attr "ppro_uops" "few")
7439 (set_attr "length_immediate" "0")
7440 (set_attr "mode" "DI")])
7441
7442;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7381(define_insn "umulsidi3"
7443(define_expand "umulsidi3"
7444 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7445 (mult:DI (zero_extend:DI
7446 (match_operand:SI 1 "nonimmediate_operand" ""))
7447 (zero_extend:DI
7448 (match_operand:SI 2 "register_operand" ""))))
7449 (clobber (reg:CC 17))])]
7450 "!TARGET_64BIT"
7451 "")
7452
7453(define_insn "*umulsidi3_insn"
7382 [(set (match_operand:DI 0 "register_operand" "=A")
7454 [(set (match_operand:DI 0 "register_operand" "=A")
7383 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7455 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7384 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7385 (clobber (reg:CC 17))]
7456 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7457 (clobber (reg:CC 17))]
7386 "!TARGET_64BIT"
7458 "!TARGET_64BIT
7459 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7387 "mul{l}\t%2"
7388 [(set_attr "type" "imul")
7389 (set_attr "ppro_uops" "few")
7390 (set_attr "length_immediate" "0")
7391 (set_attr "mode" "SI")])
7392
7460 "mul{l}\t%2"
7461 [(set_attr "type" "imul")
7462 (set_attr "ppro_uops" "few")
7463 (set_attr "length_immediate" "0")
7464 (set_attr "mode" "SI")])
7465
7393(define_insn "mulditi3"
7466(define_expand "mulditi3"
7467 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7468 (mult:TI (sign_extend:TI
7469 (match_operand:DI 1 "nonimmediate_operand" ""))
7470 (sign_extend:TI
7471 (match_operand:DI 2 "register_operand" ""))))
7472 (clobber (reg:CC 17))])]
7473 "TARGET_64BIT"
7474 "")
7475
7476(define_insn "*mulditi3_insn"
7394 [(set (match_operand:TI 0 "register_operand" "=A")
7477 [(set (match_operand:TI 0 "register_operand" "=A")
7395 (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7478 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7396 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7397 (clobber (reg:CC 17))]
7479 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7480 (clobber (reg:CC 17))]
7398 "TARGET_64BIT"
7481 "TARGET_64BIT
7482 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7399 "imul{q}\t%2"
7400 [(set_attr "type" "imul")
7401 (set_attr "length_immediate" "0")
7402 (set_attr "mode" "DI")])
7403
7483 "imul{q}\t%2"
7484 [(set_attr "type" "imul")
7485 (set_attr "length_immediate" "0")
7486 (set_attr "mode" "DI")])
7487
7404(define_insn "mulsidi3"
7488(define_expand "mulsidi3"
7489 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7490 (mult:DI (sign_extend:DI
7491 (match_operand:SI 1 "nonimmediate_operand" ""))
7492 (sign_extend:DI
7493 (match_operand:SI 2 "register_operand" ""))))
7494 (clobber (reg:CC 17))])]
7495 "!TARGET_64BIT"
7496 "")
7497
7498(define_insn "*mulsidi3_insn"
7405 [(set (match_operand:DI 0 "register_operand" "=A")
7499 [(set (match_operand:DI 0 "register_operand" "=A")
7406 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7500 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7407 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7408 (clobber (reg:CC 17))]
7501 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7502 (clobber (reg:CC 17))]
7409 "!TARGET_64BIT"
7503 "!TARGET_64BIT
7504 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7410 "imul{l}\t%2"
7411 [(set_attr "type" "imul")
7412 (set_attr "length_immediate" "0")
7413 (set_attr "mode" "SI")])
7414
7505 "imul{l}\t%2"
7506 [(set_attr "type" "imul")
7507 (set_attr "length_immediate" "0")
7508 (set_attr "mode" "SI")])
7509
7510(define_expand "umuldi3_highpart"
7511 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7512 (truncate:DI
7513 (lshiftrt:TI
7514 (mult:TI (zero_extend:TI
7515 (match_operand:DI 1 "nonimmediate_operand" ""))
7516 (zero_extend:TI
7517 (match_operand:DI 2 "register_operand" "")))
7518 (const_int 64))))
7519 (clobber (match_scratch:DI 3 ""))
7520 (clobber (reg:CC 17))])]
7521 "TARGET_64BIT"
7522 "")
7523
7415(define_insn "*umuldi3_highpart_rex64"
7416 [(set (match_operand:DI 0 "register_operand" "=d")
7417 (truncate:DI
7418 (lshiftrt:TI
7419 (mult:TI (zero_extend:TI
7524(define_insn "*umuldi3_highpart_rex64"
7525 [(set (match_operand:DI 0 "register_operand" "=d")
7526 (truncate:DI
7527 (lshiftrt:TI
7528 (mult:TI (zero_extend:TI
7420 (match_operand:DI 1 "register_operand" "%a"))
7529 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7421 (zero_extend:TI
7422 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7423 (const_int 64))))
7530 (zero_extend:TI
7531 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7532 (const_int 64))))
7424 (clobber (match_scratch:DI 3 "=a"))
7533 (clobber (match_scratch:DI 3 "=1"))
7425 (clobber (reg:CC 17))]
7534 (clobber (reg:CC 17))]
7426 "TARGET_64BIT"
7535 "TARGET_64BIT
7536 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7427 "mul{q}\t%2"
7428 [(set_attr "type" "imul")
7429 (set_attr "ppro_uops" "few")
7430 (set_attr "length_immediate" "0")
7431 (set_attr "mode" "DI")])
7432
7537 "mul{q}\t%2"
7538 [(set_attr "type" "imul")
7539 (set_attr "ppro_uops" "few")
7540 (set_attr "length_immediate" "0")
7541 (set_attr "mode" "DI")])
7542
7433(define_insn "umulsi3_highpart"
7543(define_expand "umulsi3_highpart"
7544 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7545 (truncate:SI
7546 (lshiftrt:DI
7547 (mult:DI (zero_extend:DI
7548 (match_operand:SI 1 "nonimmediate_operand" ""))
7549 (zero_extend:DI
7550 (match_operand:SI 2 "register_operand" "")))
7551 (const_int 32))))
7552 (clobber (match_scratch:SI 3 ""))
7553 (clobber (reg:CC 17))])]
7554 ""
7555 "")
7556
7557(define_insn "*umulsi3_highpart_insn"
7434 [(set (match_operand:SI 0 "register_operand" "=d")
7435 (truncate:SI
7436 (lshiftrt:DI
7437 (mult:DI (zero_extend:DI
7558 [(set (match_operand:SI 0 "register_operand" "=d")
7559 (truncate:SI
7560 (lshiftrt:DI
7561 (mult:DI (zero_extend:DI
7438 (match_operand:SI 1 "register_operand" "%a"))
7562 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7439 (zero_extend:DI
7440 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7441 (const_int 32))))
7563 (zero_extend:DI
7564 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7565 (const_int 32))))
7442 (clobber (match_scratch:SI 3 "=a"))
7566 (clobber (match_scratch:SI 3 "=1"))
7443 (clobber (reg:CC 17))]
7567 (clobber (reg:CC 17))]
7444 ""
7568 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7445 "mul{l}\t%2"
7446 [(set_attr "type" "imul")
7447 (set_attr "ppro_uops" "few")
7448 (set_attr "length_immediate" "0")
7449 (set_attr "mode" "SI")])
7450
7451(define_insn "*umulsi3_highpart_zext"
7452 [(set (match_operand:DI 0 "register_operand" "=d")
7453 (zero_extend:DI (truncate:SI
7454 (lshiftrt:DI
7455 (mult:DI (zero_extend:DI
7569 "mul{l}\t%2"
7570 [(set_attr "type" "imul")
7571 (set_attr "ppro_uops" "few")
7572 (set_attr "length_immediate" "0")
7573 (set_attr "mode" "SI")])
7574
7575(define_insn "*umulsi3_highpart_zext"
7576 [(set (match_operand:DI 0 "register_operand" "=d")
7577 (zero_extend:DI (truncate:SI
7578 (lshiftrt:DI
7579 (mult:DI (zero_extend:DI
7456 (match_operand:SI 1 "register_operand" "%a"))
7580 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7457 (zero_extend:DI
7458 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7459 (const_int 32)))))
7581 (zero_extend:DI
7582 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7583 (const_int 32)))))
7460 (clobber (match_scratch:SI 3 "=a"))
7584 (clobber (match_scratch:SI 3 "=1"))
7461 (clobber (reg:CC 17))]
7585 (clobber (reg:CC 17))]
7462 "TARGET_64BIT"
7586 "TARGET_64BIT
7587 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7463 "mul{l}\t%2"
7464 [(set_attr "type" "imul")
7465 (set_attr "ppro_uops" "few")
7466 (set_attr "length_immediate" "0")
7467 (set_attr "mode" "SI")])
7468
7588 "mul{l}\t%2"
7589 [(set_attr "type" "imul")
7590 (set_attr "ppro_uops" "few")
7591 (set_attr "length_immediate" "0")
7592 (set_attr "mode" "SI")])
7593
7594(define_expand "smuldi3_highpart"
7595 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
7596 (truncate:DI
7597 (lshiftrt:TI
7598 (mult:TI (sign_extend:TI
7599 (match_operand:DI 1 "nonimmediate_operand" ""))
7600 (sign_extend:TI
7601 (match_operand:DI 2 "register_operand" "")))
7602 (const_int 64))))
7603 (clobber (match_scratch:DI 3 ""))
7604 (clobber (reg:CC 17))])]
7605 "TARGET_64BIT"
7606 "")
7607
7469(define_insn "*smuldi3_highpart_rex64"
7470 [(set (match_operand:DI 0 "register_operand" "=d")
7471 (truncate:DI
7472 (lshiftrt:TI
7473 (mult:TI (sign_extend:TI
7608(define_insn "*smuldi3_highpart_rex64"
7609 [(set (match_operand:DI 0 "register_operand" "=d")
7610 (truncate:DI
7611 (lshiftrt:TI
7612 (mult:TI (sign_extend:TI
7474 (match_operand:DI 1 "register_operand" "%a"))
7613 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7475 (sign_extend:TI
7476 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7477 (const_int 64))))
7614 (sign_extend:TI
7615 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7616 (const_int 64))))
7478 (clobber (match_scratch:DI 3 "=a"))
7617 (clobber (match_scratch:DI 3 "=1"))
7479 (clobber (reg:CC 17))]
7618 (clobber (reg:CC 17))]
7480 "TARGET_64BIT"
7619 "TARGET_64BIT
7620 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7481 "imul{q}\t%2"
7482 [(set_attr "type" "imul")
7483 (set_attr "ppro_uops" "few")
7484 (set_attr "mode" "DI")])
7485
7621 "imul{q}\t%2"
7622 [(set_attr "type" "imul")
7623 (set_attr "ppro_uops" "few")
7624 (set_attr "mode" "DI")])
7625
7486(define_insn "smulsi3_highpart"
7626(define_expand "smulsi3_highpart"
7627 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7628 (truncate:SI
7629 (lshiftrt:DI
7630 (mult:DI (sign_extend:DI
7631 (match_operand:SI 1 "nonimmediate_operand" ""))
7632 (sign_extend:DI
7633 (match_operand:SI 2 "register_operand" "")))
7634 (const_int 32))))
7635 (clobber (match_scratch:SI 3 ""))
7636 (clobber (reg:CC 17))])]
7637 ""
7638 "")
7639
7640(define_insn "*smulsi3_highpart_insn"
7487 [(set (match_operand:SI 0 "register_operand" "=d")
7488 (truncate:SI
7489 (lshiftrt:DI
7490 (mult:DI (sign_extend:DI
7641 [(set (match_operand:SI 0 "register_operand" "=d")
7642 (truncate:SI
7643 (lshiftrt:DI
7644 (mult:DI (sign_extend:DI
7491 (match_operand:SI 1 "register_operand" "%a"))
7645 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7492 (sign_extend:DI
7493 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7494 (const_int 32))))
7646 (sign_extend:DI
7647 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7648 (const_int 32))))
7495 (clobber (match_scratch:SI 3 "=a"))
7649 (clobber (match_scratch:SI 3 "=1"))
7496 (clobber (reg:CC 17))]
7650 (clobber (reg:CC 17))]
7497 ""
7651 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7498 "imul{l}\t%2"
7499 [(set_attr "type" "imul")
7500 (set_attr "ppro_uops" "few")
7501 (set_attr "mode" "SI")])
7502
7503(define_insn "*smulsi3_highpart_zext"
7504 [(set (match_operand:DI 0 "register_operand" "=d")
7505 (zero_extend:DI (truncate:SI
7506 (lshiftrt:DI
7507 (mult:DI (sign_extend:DI
7652 "imul{l}\t%2"
7653 [(set_attr "type" "imul")
7654 (set_attr "ppro_uops" "few")
7655 (set_attr "mode" "SI")])
7656
7657(define_insn "*smulsi3_highpart_zext"
7658 [(set (match_operand:DI 0 "register_operand" "=d")
7659 (zero_extend:DI (truncate:SI
7660 (lshiftrt:DI
7661 (mult:DI (sign_extend:DI
7508 (match_operand:SI 1 "register_operand" "%a"))
7662 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7509 (sign_extend:DI
7510 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7511 (const_int 32)))))
7663 (sign_extend:DI
7664 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7665 (const_int 32)))))
7512 (clobber (match_scratch:SI 3 "=a"))
7666 (clobber (match_scratch:SI 3 "=1"))
7513 (clobber (reg:CC 17))]
7667 (clobber (reg:CC 17))]
7514 "TARGET_64BIT"
7668 "TARGET_64BIT
7669 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7515 "imul{l}\t%2"
7516 [(set_attr "type" "imul")
7517 (set_attr "ppro_uops" "few")
7518 (set_attr "mode" "SI")])
7519
7520;; The patterns that match these are at the end of this file.
7521
7522(define_expand "mulxf3"

--- 6013 unchanged lines hidden (view full) ---

13536{
13537 int i;
13538
13539 /* In order to give reg-stack an easier job in validating two
13540 coprocessor registers as containing a possible return value,
13541 simply pretend the untyped call returns a complex long double
13542 value. */
13543
7670 "imul{l}\t%2"
7671 [(set_attr "type" "imul")
7672 (set_attr "ppro_uops" "few")
7673 (set_attr "mode" "SI")])
7674
7675;; The patterns that match these are at the end of this file.
7676
7677(define_expand "mulxf3"

--- 6013 unchanged lines hidden (view full) ---

13691{
13692 int i;
13693
13694 /* In order to give reg-stack an easier job in validating two
13695 coprocessor registers as containing a possible return value,
13696 simply pretend the untyped call returns a complex long double
13697 value. */
13698
13544 emit_call_insn (TARGET_80387
13699 emit_call_insn (TARGET_FLOAT_RETURNS_IN_80387
13545 ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG),
13546 operands[0], const0_rtx,
13547 GEN_INT (SSE_REGPARM_MAX - 1))
13548 : gen_call (operands[0], const0_rtx,
13549 GEN_INT (SSE_REGPARM_MAX - 1)));
13550
13551 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13552 {

--- 298 unchanged lines hidden (view full) ---

13851;; SImode if the target mode DFmode, but only SImode if the target mode
13852;; is SFmode.
13853
13854;; Gcc is slightly more smart about handling normal two address instructions
13855;; so use special patterns for add and mull.
13856(define_insn "*fop_sf_comm_nosse"
13857 [(set (match_operand:SF 0 "register_operand" "=f")
13858 (match_operator:SF 3 "binary_fp_operator"
13700 ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG),
13701 operands[0], const0_rtx,
13702 GEN_INT (SSE_REGPARM_MAX - 1))
13703 : gen_call (operands[0], const0_rtx,
13704 GEN_INT (SSE_REGPARM_MAX - 1)));
13705
13706 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13707 {

--- 298 unchanged lines hidden (view full) ---

14006;; SImode if the target mode DFmode, but only SImode if the target mode
14007;; is SFmode.
14008
14009;; Gcc is slightly more smart about handling normal two address instructions
14010;; so use special patterns for add and mull.
14011(define_insn "*fop_sf_comm_nosse"
14012 [(set (match_operand:SF 0 "register_operand" "=f")
14013 (match_operator:SF 3 "binary_fp_operator"
13859 [(match_operand:SF 1 "register_operand" "%0")
14014 [(match_operand:SF 1 "nonimmediate_operand" "%0")
13860 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
13861 "TARGET_80387 && !TARGET_SSE_MATH
14015 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
14016 "TARGET_80387 && !TARGET_SSE_MATH
13862 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14017 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14018 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13863 "* return output_387_binary_op (insn, operands);"
13864 [(set (attr "type")
13865 (if_then_else (match_operand:SF 3 "mult_operator" "")
13866 (const_string "fmul")
13867 (const_string "fop")))
13868 (set_attr "mode" "SF")])
13869
13870(define_insn "*fop_sf_comm"
13871 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
13872 (match_operator:SF 3 "binary_fp_operator"
14019 "* return output_387_binary_op (insn, operands);"
14020 [(set (attr "type")
14021 (if_then_else (match_operand:SF 3 "mult_operator" "")
14022 (const_string "fmul")
14023 (const_string "fop")))
14024 (set_attr "mode" "SF")])
14025
14026(define_insn "*fop_sf_comm"
14027 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14028 (match_operator:SF 3 "binary_fp_operator"
13873 [(match_operand:SF 1 "register_operand" "%0,0")
14029 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
13874 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
13875 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14030 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
14031 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
13876 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14032 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14033 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13877 "* return output_387_binary_op (insn, operands);"
13878 [(set (attr "type")
13879 (if_then_else (eq_attr "alternative" "1")
13880 (const_string "sse")
13881 (if_then_else (match_operand:SF 3 "mult_operator" "")
13882 (const_string "fmul")
13883 (const_string "fop"))))
13884 (set_attr "mode" "SF")])
13885
13886(define_insn "*fop_sf_comm_sse"
13887 [(set (match_operand:SF 0 "register_operand" "=x")
13888 (match_operator:SF 3 "binary_fp_operator"
14034 "* return output_387_binary_op (insn, operands);"
14035 [(set (attr "type")
14036 (if_then_else (eq_attr "alternative" "1")
14037 (const_string "sse")
14038 (if_then_else (match_operand:SF 3 "mult_operator" "")
14039 (const_string "fmul")
14040 (const_string "fop"))))
14041 (set_attr "mode" "SF")])
14042
14043(define_insn "*fop_sf_comm_sse"
14044 [(set (match_operand:SF 0 "register_operand" "=x")
14045 (match_operator:SF 3 "binary_fp_operator"
13889 [(match_operand:SF 1 "register_operand" "%0")
14046 [(match_operand:SF 1 "nonimmediate_operand" "%0")
13890 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14047 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13891 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14048 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14049 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13892 "* return output_387_binary_op (insn, operands);"
13893 [(set_attr "type" "sse")
13894 (set_attr "mode" "SF")])
13895
13896(define_insn "*fop_df_comm_nosse"
13897 [(set (match_operand:DF 0 "register_operand" "=f")
13898 (match_operator:DF 3 "binary_fp_operator"
14050 "* return output_387_binary_op (insn, operands);"
14051 [(set_attr "type" "sse")
14052 (set_attr "mode" "SF")])
14053
14054(define_insn "*fop_df_comm_nosse"
14055 [(set (match_operand:DF 0 "register_operand" "=f")
14056 (match_operator:DF 3 "binary_fp_operator"
13899 [(match_operand:DF 1 "register_operand" "%0")
14057 [(match_operand:DF 1 "nonimmediate_operand" "%0")
13900 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
13901 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14058 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
14059 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
13902 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14060 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14061 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13903 "* return output_387_binary_op (insn, operands);"
13904 [(set (attr "type")
13905 (if_then_else (match_operand:SF 3 "mult_operator" "")
13906 (const_string "fmul")
13907 (const_string "fop")))
13908 (set_attr "mode" "DF")])
13909
13910(define_insn "*fop_df_comm"
13911 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
13912 (match_operator:DF 3 "binary_fp_operator"
14062 "* return output_387_binary_op (insn, operands);"
14063 [(set (attr "type")
14064 (if_then_else (match_operand:SF 3 "mult_operator" "")
14065 (const_string "fmul")
14066 (const_string "fop")))
14067 (set_attr "mode" "DF")])
14068
14069(define_insn "*fop_df_comm"
14070 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14071 (match_operator:DF 3 "binary_fp_operator"
13913 [(match_operand:DF 1 "register_operand" "%0,0")
14072 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
13914 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
13915 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
14073 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
14074 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
13916 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14075 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14076 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13917 "* return output_387_binary_op (insn, operands);"
13918 [(set (attr "type")
13919 (if_then_else (eq_attr "alternative" "1")
13920 (const_string "sse")
13921 (if_then_else (match_operand:SF 3 "mult_operator" "")
13922 (const_string "fmul")
13923 (const_string "fop"))))
13924 (set_attr "mode" "DF")])
13925
13926(define_insn "*fop_df_comm_sse"
13927 [(set (match_operand:DF 0 "register_operand" "=Y")
13928 (match_operator:DF 3 "binary_fp_operator"
14077 "* return output_387_binary_op (insn, operands);"
14078 [(set (attr "type")
14079 (if_then_else (eq_attr "alternative" "1")
14080 (const_string "sse")
14081 (if_then_else (match_operand:SF 3 "mult_operator" "")
14082 (const_string "fmul")
14083 (const_string "fop"))))
14084 (set_attr "mode" "DF")])
14085
14086(define_insn "*fop_df_comm_sse"
14087 [(set (match_operand:DF 0 "register_operand" "=Y")
14088 (match_operator:DF 3 "binary_fp_operator"
13929 [(match_operand:DF 1 "register_operand" "%0")
14089 [(match_operand:DF 1 "nonimmediate_operand" "%0")
13930 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13931 "TARGET_SSE2 && TARGET_SSE_MATH
14090 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14091 "TARGET_SSE2 && TARGET_SSE_MATH
13932 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14092 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14093 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13933 "* return output_387_binary_op (insn, operands);"
13934 [(set_attr "type" "sse")
13935 (set_attr "mode" "DF")])
13936
13937(define_insn "*fop_xf_comm"
13938 [(set (match_operand:XF 0 "register_operand" "=f")
13939 (match_operator:XF 3 "binary_fp_operator"
13940 [(match_operand:XF 1 "register_operand" "%0")

--- 617 unchanged lines hidden (view full) ---

14558 [(set_attr "type" "fpspc")
14559 (set_attr "mode" "XF")
14560 (set_attr "athlon_decode" "direct")])
14561
14562(define_insn "*sqrtextenddfxf2"
14563 [(set (match_operand:XF 0 "register_operand" "=f")
14564 (sqrt:XF (float_extend:XF
14565 (match_operand:DF 1 "register_operand" "0"))))]
14094 "* return output_387_binary_op (insn, operands);"
14095 [(set_attr "type" "sse")
14096 (set_attr "mode" "DF")])
14097
14098(define_insn "*fop_xf_comm"
14099 [(set (match_operand:XF 0 "register_operand" "=f")
14100 (match_operator:XF 3 "binary_fp_operator"
14101 [(match_operand:XF 1 "register_operand" "%0")

--- 617 unchanged lines hidden (view full) ---

14719 [(set_attr "type" "fpspc")
14720 (set_attr "mode" "XF")
14721 (set_attr "athlon_decode" "direct")])
14722
14723(define_insn "*sqrtextenddfxf2"
14724 [(set (match_operand:XF 0 "register_operand" "=f")
14725 (sqrt:XF (float_extend:XF
14726 (match_operand:DF 1 "register_operand" "0"))))]
14566 "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387"
14727 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14567 "fsqrt"
14568 [(set_attr "type" "fpspc")
14569 (set_attr "mode" "XF")
14570 (set_attr "athlon_decode" "direct")])
14571
14572(define_insn "*sqrtextenddftf2"
14573 [(set (match_operand:TF 0 "register_operand" "=f")
14574 (sqrt:TF (float_extend:TF
14575 (match_operand:DF 1 "register_operand" "0"))))]
14576 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14577 "fsqrt"
14578 [(set_attr "type" "fpspc")
14579 (set_attr "mode" "XF")
14580 (set_attr "athlon_decode" "direct")])
14581
14582(define_insn "*sqrtextendsfxf2"
14583 [(set (match_operand:XF 0 "register_operand" "=f")
14584 (sqrt:XF (float_extend:XF
14585 (match_operand:SF 1 "register_operand" "0"))))]
14728 "fsqrt"
14729 [(set_attr "type" "fpspc")
14730 (set_attr "mode" "XF")
14731 (set_attr "athlon_decode" "direct")])
14732
14733(define_insn "*sqrtextenddftf2"
14734 [(set (match_operand:TF 0 "register_operand" "=f")
14735 (sqrt:TF (float_extend:TF
14736 (match_operand:DF 1 "register_operand" "0"))))]
14737 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14738 "fsqrt"
14739 [(set_attr "type" "fpspc")
14740 (set_attr "mode" "XF")
14741 (set_attr "athlon_decode" "direct")])
14742
14743(define_insn "*sqrtextendsfxf2"
14744 [(set (match_operand:XF 0 "register_operand" "=f")
14745 (sqrt:XF (float_extend:XF
14746 (match_operand:SF 1 "register_operand" "0"))))]
14586 "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387"
14747 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14587 "fsqrt"
14588 [(set_attr "type" "fpspc")
14589 (set_attr "mode" "XF")
14590 (set_attr "athlon_decode" "direct")])
14591
14592(define_insn "*sqrtextendsftf2"
14593 [(set (match_operand:TF 0 "register_operand" "=f")
14594 (sqrt:TF (float_extend:TF

--- 30 unchanged lines hidden (view full) ---

14625 && flag_unsafe_math_optimizations"
14626 "fsin"
14627 [(set_attr "type" "fpspc")
14628 (set_attr "mode" "DF")])
14629
14630(define_insn "sinxf2"
14631 [(set (match_operand:XF 0 "register_operand" "=f")
14632 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
14748 "fsqrt"
14749 [(set_attr "type" "fpspc")
14750 (set_attr "mode" "XF")
14751 (set_attr "athlon_decode" "direct")])
14752
14753(define_insn "*sqrtextendsftf2"
14754 [(set (match_operand:TF 0 "register_operand" "=f")
14755 (sqrt:TF (float_extend:TF

--- 30 unchanged lines hidden (view full) ---

14786 && flag_unsafe_math_optimizations"
14787 "fsin"
14788 [(set_attr "type" "fpspc")
14789 (set_attr "mode" "DF")])
14790
14791(define_insn "sinxf2"
14792 [(set (match_operand:XF 0 "register_operand" "=f")
14793 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
14633 "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387
14794 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
14634 && flag_unsafe_math_optimizations"
14635 "fsin"
14636 [(set_attr "type" "fpspc")
14637 (set_attr "mode" "XF")])
14638
14639(define_insn "sintf2"
14640 [(set (match_operand:TF 0 "register_operand" "=f")
14641 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))]

--- 1103 unchanged lines hidden (view full) ---

15745 [(set (match_operand:DI 0 "register_operand" "=r,r")
15746 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
15747 [(reg 17) (const_int 0)])
15748 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
15749 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
15750 "TARGET_64BIT && TARGET_CMOVE
15751 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15752 "@
14795 && flag_unsafe_math_optimizations"
14796 "fsin"
14797 [(set_attr "type" "fpspc")
14798 (set_attr "mode" "XF")])
14799
14800(define_insn "sintf2"
14801 [(set (match_operand:TF 0 "register_operand" "=f")
14802 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))]

--- 1103 unchanged lines hidden (view full) ---

15906 [(set (match_operand:DI 0 "register_operand" "=r,r")
15907 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
15908 [(reg 17) (const_int 0)])
15909 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
15910 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
15911 "TARGET_64BIT && TARGET_CMOVE
15912 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15913 "@
15753 cmov%C1\t{%2, %0|%0, %2}
15754 cmov%c1\t{%3, %0|%0, %3}"
15914 cmov%O2%C1\t{%2, %0|%0, %2}
15915 cmov%O2%c1\t{%3, %0|%0, %3}"
15755 [(set_attr "type" "icmov")
15756 (set_attr "mode" "DI")])
15757
15758(define_expand "movsicc"
15759 [(set (match_operand:SI 0 "register_operand" "")
15760 (if_then_else:SI (match_operand 1 "comparison_operator" "")
15761 (match_operand:SI 2 "general_operand" "")
15762 (match_operand:SI 3 "general_operand" "")))]

--- 24 unchanged lines hidden (view full) ---

15787 [(set (match_operand:SI 0 "register_operand" "=r,r")
15788 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
15789 [(reg 17) (const_int 0)])
15790 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
15791 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
15792 "TARGET_CMOVE
15793 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15794 "@
15916 [(set_attr "type" "icmov")
15917 (set_attr "mode" "DI")])
15918
15919(define_expand "movsicc"
15920 [(set (match_operand:SI 0 "register_operand" "")
15921 (if_then_else:SI (match_operand 1 "comparison_operator" "")
15922 (match_operand:SI 2 "general_operand" "")
15923 (match_operand:SI 3 "general_operand" "")))]

--- 24 unchanged lines hidden (view full) ---

15948 [(set (match_operand:SI 0 "register_operand" "=r,r")
15949 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
15950 [(reg 17) (const_int 0)])
15951 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
15952 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
15953 "TARGET_CMOVE
15954 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15955 "@
15795 cmov%C1\t{%2, %0|%0, %2}
15796 cmov%c1\t{%3, %0|%0, %3}"
15956 cmov%O2%C1\t{%2, %0|%0, %2}
15957 cmov%O2%c1\t{%3, %0|%0, %3}"
15797 [(set_attr "type" "icmov")
15798 (set_attr "mode" "SI")])
15799
15800(define_expand "movhicc"
15801 [(set (match_operand:HI 0 "register_operand" "")
15802 (if_then_else:HI (match_operand 1 "comparison_operator" "")
15803 (match_operand:HI 2 "nonimmediate_operand" "")
15804 (match_operand:HI 3 "nonimmediate_operand" "")))]

--- 4 unchanged lines hidden (view full) ---

15809 [(set (match_operand:HI 0 "register_operand" "=r,r")
15810 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
15811 [(reg 17) (const_int 0)])
15812 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
15813 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
15814 "TARGET_CMOVE
15815 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15816 "@
15958 [(set_attr "type" "icmov")
15959 (set_attr "mode" "SI")])
15960
15961(define_expand "movhicc"
15962 [(set (match_operand:HI 0 "register_operand" "")
15963 (if_then_else:HI (match_operand 1 "comparison_operator" "")
15964 (match_operand:HI 2 "nonimmediate_operand" "")
15965 (match_operand:HI 3 "nonimmediate_operand" "")))]

--- 4 unchanged lines hidden (view full) ---

15970 [(set (match_operand:HI 0 "register_operand" "=r,r")
15971 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
15972 [(reg 17) (const_int 0)])
15973 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
15974 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
15975 "TARGET_CMOVE
15976 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15977 "@
15817 cmov%C1\t{%2, %0|%0, %2}
15818 cmov%c1\t{%3, %0|%0, %3}"
15978 cmov%O2%C1\t{%2, %0|%0, %2}
15979 cmov%O2%c1\t{%3, %0|%0, %3}"
15819 [(set_attr "type" "icmov")
15820 (set_attr "mode" "HI")])
15821
15822(define_expand "movsfcc"
15823 [(set (match_operand:SF 0 "register_operand" "")
15824 (if_then_else:SF (match_operand 1 "comparison_operator" "")
15825 (match_operand:SF 2 "register_operand" "")
15826 (match_operand:SF 3 "register_operand" "")))]

--- 6 unchanged lines hidden (view full) ---

15833 [(reg 17) (const_int 0)])
15834 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
15835 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
15836 "TARGET_CMOVE
15837 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15838 "@
15839 fcmov%F1\t{%2, %0|%0, %2}
15840 fcmov%f1\t{%3, %0|%0, %3}
15980 [(set_attr "type" "icmov")
15981 (set_attr "mode" "HI")])
15982
15983(define_expand "movsfcc"
15984 [(set (match_operand:SF 0 "register_operand" "")
15985 (if_then_else:SF (match_operand 1 "comparison_operator" "")
15986 (match_operand:SF 2 "register_operand" "")
15987 (match_operand:SF 3 "register_operand" "")))]

--- 6 unchanged lines hidden (view full) ---

15994 [(reg 17) (const_int 0)])
15995 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
15996 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
15997 "TARGET_CMOVE
15998 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15999 "@
16000 fcmov%F1\t{%2, %0|%0, %2}
16001 fcmov%f1\t{%3, %0|%0, %3}
15841 cmov%C1\t{%2, %0|%0, %2}
15842 cmov%c1\t{%3, %0|%0, %3}"
16002 cmov%O2%C1\t{%2, %0|%0, %2}
16003 cmov%O2%c1\t{%3, %0|%0, %3}"
15843 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15844 (set_attr "mode" "SF,SF,SI,SI")])
15845
15846(define_expand "movdfcc"
15847 [(set (match_operand:DF 0 "register_operand" "")
15848 (if_then_else:DF (match_operand 1 "comparison_operator" "")
15849 (match_operand:DF 2 "register_operand" "")
15850 (match_operand:DF 3 "register_operand" "")))]

--- 22 unchanged lines hidden (view full) ---

15873 [(reg 17) (const_int 0)])
15874 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15875 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15876 "TARGET_64BIT && TARGET_CMOVE
15877 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15878 "@
15879 fcmov%F1\t{%2, %0|%0, %2}
15880 fcmov%f1\t{%3, %0|%0, %3}
16004 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16005 (set_attr "mode" "SF,SF,SI,SI")])
16006
16007(define_expand "movdfcc"
16008 [(set (match_operand:DF 0 "register_operand" "")
16009 (if_then_else:DF (match_operand 1 "comparison_operator" "")
16010 (match_operand:DF 2 "register_operand" "")
16011 (match_operand:DF 3 "register_operand" "")))]

--- 22 unchanged lines hidden (view full) ---

16034 [(reg 17) (const_int 0)])
16035 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
16036 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
16037 "TARGET_64BIT && TARGET_CMOVE
16038 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16039 "@
16040 fcmov%F1\t{%2, %0|%0, %2}
16041 fcmov%f1\t{%3, %0|%0, %3}
15881 cmov%C1\t{%2, %0|%0, %2}
15882 cmov%c1\t{%3, %0|%0, %3}"
16042 cmov%O2%C1\t{%2, %0|%0, %2}
16043 cmov%O2%c1\t{%3, %0|%0, %3}"
15883 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15884 (set_attr "mode" "DF")])
15885
15886(define_split
15887 [(set (match_operand:DF 0 "register_operand" "")
15888 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15889 [(match_operand 4 "" "") (const_int 0)])
15890 (match_operand:DF 2 "nonimmediate_operand" "")

--- 71 unchanged lines hidden (view full) ---

15962 (match_dup 1)
15963 (match_dup 2)))
15964 (clobber (reg:CC 17))]
15965 "TARGET_SSE && TARGET_IEEE_FP"
15966 "#")
15967
15968(define_insn "*minsf_nonieee"
15969 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16044 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16045 (set_attr "mode" "DF")])
16046
16047(define_split
16048 [(set (match_operand:DF 0 "register_operand" "")
16049 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16050 [(match_operand 4 "" "") (const_int 0)])
16051 (match_operand:DF 2 "nonimmediate_operand" "")

--- 71 unchanged lines hidden (view full) ---

16123 (match_dup 1)
16124 (match_dup 2)))
16125 (clobber (reg:CC 17))]
16126 "TARGET_SSE && TARGET_IEEE_FP"
16127 "#")
16128
16129(define_insn "*minsf_nonieee"
16130 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
15970 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0")
16131 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
15971 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
15972 (match_dup 1)
15973 (match_dup 2)))
15974 (clobber (reg:CC 17))]
16132 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16133 (match_dup 1)
16134 (match_dup 2)))
16135 (clobber (reg:CC 17))]
15975 "TARGET_SSE && !TARGET_IEEE_FP"
16136 "TARGET_SSE && !TARGET_IEEE_FP
16137 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
15976 "#")
15977
15978(define_split
15979 [(set (match_operand:SF 0 "register_operand" "")
15980 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15981 (match_operand:SF 2 "nonimmediate_operand" ""))
15982 (match_operand:SF 3 "register_operand" "")
15983 (match_operand:SF 4 "nonimmediate_operand" "")))

--- 60 unchanged lines hidden (view full) ---

16044 (match_dup 1)
16045 (match_dup 2)))
16046 (clobber (reg:CC 17))]
16047 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
16048 "#")
16049
16050(define_insn "*mindf_nonieee"
16051 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16138 "#")
16139
16140(define_split
16141 [(set (match_operand:SF 0 "register_operand" "")
16142 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16143 (match_operand:SF 2 "nonimmediate_operand" ""))
16144 (match_operand:SF 3 "register_operand" "")
16145 (match_operand:SF 4 "nonimmediate_operand" "")))

--- 60 unchanged lines hidden (view full) ---

16206 (match_dup 1)
16207 (match_dup 2)))
16208 (clobber (reg:CC 17))]
16209 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
16210 "#")
16211
16212(define_insn "*mindf_nonieee"
16213 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16052 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0")
16214 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16053 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16054 (match_dup 1)
16055 (match_dup 2)))
16056 (clobber (reg:CC 17))]
16215 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16216 (match_dup 1)
16217 (match_dup 2)))
16218 (clobber (reg:CC 17))]
16057 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
16219 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
16220 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16058 "#")
16059
16060(define_split
16061 [(set (match_operand:DF 0 "register_operand" "")
16062 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16063 (match_operand:DF 2 "nonimmediate_operand" ""))
16064 (match_operand:DF 3 "register_operand" "")
16065 (match_operand:DF 4 "nonimmediate_operand" "")))

--- 59 unchanged lines hidden (view full) ---

16125 (match_dup 1)
16126 (match_dup 2)))
16127 (clobber (reg:CC 17))]
16128 "TARGET_SSE && TARGET_IEEE_FP"
16129 "#")
16130
16131(define_insn "*maxsf_nonieee"
16132 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16221 "#")
16222
16223(define_split
16224 [(set (match_operand:DF 0 "register_operand" "")
16225 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16226 (match_operand:DF 2 "nonimmediate_operand" ""))
16227 (match_operand:DF 3 "register_operand" "")
16228 (match_operand:DF 4 "nonimmediate_operand" "")))

--- 59 unchanged lines hidden (view full) ---

16288 (match_dup 1)
16289 (match_dup 2)))
16290 (clobber (reg:CC 17))]
16291 "TARGET_SSE && TARGET_IEEE_FP"
16292 "#")
16293
16294(define_insn "*maxsf_nonieee"
16295 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16133 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0")
16296 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
16134 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16135 (match_dup 1)
16136 (match_dup 2)))
16137 (clobber (reg:CC 17))]
16297 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16298 (match_dup 1)
16299 (match_dup 2)))
16300 (clobber (reg:CC 17))]
16138 "TARGET_SSE && !TARGET_IEEE_FP"
16301 "TARGET_SSE && !TARGET_IEEE_FP
16302 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16139 "#")
16140
16141(define_split
16142 [(set (match_operand:SF 0 "register_operand" "")
16143 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16144 (match_operand:SF 2 "nonimmediate_operand" ""))
16145 (match_operand:SF 3 "register_operand" "")
16146 (match_operand:SF 4 "nonimmediate_operand" "")))

--- 58 unchanged lines hidden (view full) ---

16205 (match_dup 1)
16206 (match_dup 2)))
16207 (clobber (reg:CC 17))]
16208 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
16209 "#")
16210
16211(define_insn "*maxdf_nonieee"
16212 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16303 "#")
16304
16305(define_split
16306 [(set (match_operand:SF 0 "register_operand" "")
16307 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16308 (match_operand:SF 2 "nonimmediate_operand" ""))
16309 (match_operand:SF 3 "register_operand" "")
16310 (match_operand:SF 4 "nonimmediate_operand" "")))

--- 58 unchanged lines hidden (view full) ---

16369 (match_dup 1)
16370 (match_dup 2)))
16371 (clobber (reg:CC 17))]
16372 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
16373 "#")
16374
16375(define_insn "*maxdf_nonieee"
16376 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16213 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0")
16377 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16214 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16215 (match_dup 1)
16216 (match_dup 2)))
16217 (clobber (reg:CC 17))]
16378 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16379 (match_dup 1)
16380 (match_dup 2)))
16381 (clobber (reg:CC 17))]
16218 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
16382 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
16383 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16219 "#")
16220
16221(define_split
16222 [(set (match_operand:DF 0 "register_operand" "")
16223 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16224 (match_operand:DF 2 "nonimmediate_operand" ""))
16225 (match_operand:DF 3 "register_operand" "")
16226 (match_operand:DF 4 "nonimmediate_operand" "")))

--- 1715 unchanged lines hidden (view full) ---

17942 "TARGET_SSE || TARGET_3DNOW_A"
17943 "pmovmskb\t{%1, %0|%0, %1}"
17944 [(set_attr "type" "sse")])
17945
17946(define_insn "mmx_maskmovq"
17947 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
17948 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
17949 (match_operand:V8QI 2 "register_operand" "y")] 32))]
16384 "#")
16385
16386(define_split
16387 [(set (match_operand:DF 0 "register_operand" "")
16388 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16389 (match_operand:DF 2 "nonimmediate_operand" ""))
16390 (match_operand:DF 3 "register_operand" "")
16391 (match_operand:DF 4 "nonimmediate_operand" "")))

--- 1715 unchanged lines hidden (view full) ---

18107 "TARGET_SSE || TARGET_3DNOW_A"
18108 "pmovmskb\t{%1, %0|%0, %1}"
18109 [(set_attr "type" "sse")])
18110
18111(define_insn "mmx_maskmovq"
18112 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
18113 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
18114 (match_operand:V8QI 2 "register_operand" "y")] 32))]
17950 "TARGET_SSE || TARGET_3DNOW_A"
18115 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
17951 ;; @@@ check ordering of operands in intel/nonintel syntax
17952 "maskmovq\t{%2, %1|%1, %2}"
17953 [(set_attr "type" "sse")])
17954
18116 ;; @@@ check ordering of operands in intel/nonintel syntax
18117 "maskmovq\t{%2, %1|%1, %2}"
18118 [(set_attr "type" "sse")])
18119
18120(define_insn "mmx_maskmovq_rex"
18121 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
18122 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
18123 (match_operand:V8QI 2 "register_operand" "y")] 32))]
18124 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
18125 ;; @@@ check ordering of operands in intel/nonintel syntax
18126 "maskmovq\t{%2, %1|%1, %2}"
18127 [(set_attr "type" "sse")])
18128
17955(define_insn "sse_movntv4sf"
17956 [(set (match_operand:V4SF 0 "memory_operand" "=m")
17957 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
17958 "TARGET_SSE"
17959 "movntps\t{%1, %0|%0, %1}"
17960 [(set_attr "type" "sse")])
17961
17962(define_insn "sse_movntdi"

--- 263 unchanged lines hidden (view full) ---

18226 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18227 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18228 "TARGET_SSE"
18229 "andps\t{%2, %0|%0, %2}"
18230 [(set_attr "type" "sse")])
18231
18232(define_insn "sse_andti3"
18233 [(set (match_operand:TI 0 "register_operand" "=x")
18129(define_insn "sse_movntv4sf"
18130 [(set (match_operand:V4SF 0 "memory_operand" "=m")
18131 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
18132 "TARGET_SSE"
18133 "movntps\t{%1, %0|%0, %1}"
18134 [(set_attr "type" "sse")])
18135
18136(define_insn "sse_movntdi"

--- 263 unchanged lines hidden (view full) ---

18400 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18401 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18402 "TARGET_SSE"
18403 "andps\t{%2, %0|%0, %2}"
18404 [(set_attr "type" "sse")])
18405
18406(define_insn "sse_andti3"
18407 [(set (match_operand:TI 0 "register_operand" "=x")
18234 (and:TI (match_operand:TI 1 "register_operand" "%0")
18408 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18235 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18409 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18236 "TARGET_SSE && !TARGET_SSE2"
18410 "TARGET_SSE && !TARGET_SSE2
18411 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18237 "andps\t{%2, %0|%0, %2}"
18238 [(set_attr "type" "sse")])
18239
18240(define_insn "*sse_andti3_sse2"
18241 [(set (match_operand:TI 0 "register_operand" "=x")
18412 "andps\t{%2, %0|%0, %2}"
18413 [(set_attr "type" "sse")])
18414
18415(define_insn "*sse_andti3_sse2"
18416 [(set (match_operand:TI 0 "register_operand" "=x")
18242 (and:TI (match_operand:TI 1 "register_operand" "%0")
18417 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18243 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18418 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18244 "TARGET_SSE2"
18419 "TARGET_SSE2
18420 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18245 "pand\t{%2, %0|%0, %2}"
18246 [(set_attr "type" "sse")])
18247
18248(define_insn "*sse_nandti3_df"
18249 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18250 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
18251 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18252 "TARGET_SSE2"

--- 53 unchanged lines hidden (view full) ---

18306 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18307 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18308 "TARGET_SSE"
18309 "orps\t{%2, %0|%0, %2}"
18310 [(set_attr "type" "sse")])
18311
18312(define_insn "sse_iorti3"
18313 [(set (match_operand:TI 0 "register_operand" "=x")
18421 "pand\t{%2, %0|%0, %2}"
18422 [(set_attr "type" "sse")])
18423
18424(define_insn "*sse_nandti3_df"
18425 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18426 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
18427 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18428 "TARGET_SSE2"

--- 53 unchanged lines hidden (view full) ---

18482 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18483 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18484 "TARGET_SSE"
18485 "orps\t{%2, %0|%0, %2}"
18486 [(set_attr "type" "sse")])
18487
18488(define_insn "sse_iorti3"
18489 [(set (match_operand:TI 0 "register_operand" "=x")
18314 (ior:TI (match_operand:TI 1 "register_operand" "%0")
18490 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18315 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18491 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18316 "TARGET_SSE && !TARGET_SSE2"
18492 "TARGET_SSE && !TARGET_SSE2
18493 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18317 "orps\t{%2, %0|%0, %2}"
18318 [(set_attr "type" "sse")])
18319
18320(define_insn "*sse_iorti3_sse2"
18321 [(set (match_operand:TI 0 "register_operand" "=x")
18494 "orps\t{%2, %0|%0, %2}"
18495 [(set_attr "type" "sse")])
18496
18497(define_insn "*sse_iorti3_sse2"
18498 [(set (match_operand:TI 0 "register_operand" "=x")
18322 (ior:TI (match_operand:TI 1 "register_operand" "%0")
18499 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18323 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18500 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18324 "TARGET_SSE2"
18501 "TARGET_SSE2
18502 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18325 "por\t{%2, %0|%0, %2}"
18326 [(set_attr "type" "sse")])
18327
18328(define_insn "*sse_xorti3_df_1"
18329 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18330 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18331 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18332 "TARGET_SSE2"

--- 21 unchanged lines hidden (view full) ---

18354 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18355 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18356 "TARGET_SSE"
18357 "xorps\t{%2, %0|%0, %2}"
18358 [(set_attr "type" "sse")])
18359
18360(define_insn "sse_xorti3"
18361 [(set (match_operand:TI 0 "register_operand" "=x")
18503 "por\t{%2, %0|%0, %2}"
18504 [(set_attr "type" "sse")])
18505
18506(define_insn "*sse_xorti3_df_1"
18507 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18508 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18509 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18510 "TARGET_SSE2"

--- 21 unchanged lines hidden (view full) ---

18532 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18533 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18534 "TARGET_SSE"
18535 "xorps\t{%2, %0|%0, %2}"
18536 [(set_attr "type" "sse")])
18537
18538(define_insn "sse_xorti3"
18539 [(set (match_operand:TI 0 "register_operand" "=x")
18362 (xor:TI (match_operand:TI 1 "register_operand" "%0")
18540 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18363 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18541 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18364 "TARGET_SSE && !TARGET_SSE2"
18542 "TARGET_SSE && !TARGET_SSE2
18543 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18365 "xorps\t{%2, %0|%0, %2}"
18366 [(set_attr "type" "sse")])
18367
18368(define_insn "*sse_xorti3_sse2"
18369 [(set (match_operand:TI 0 "register_operand" "=x")
18544 "xorps\t{%2, %0|%0, %2}"
18545 [(set_attr "type" "sse")])
18546
18547(define_insn "*sse_xorti3_sse2"
18548 [(set (match_operand:TI 0 "register_operand" "=x")
18370 (xor:TI (match_operand:TI 1 "register_operand" "%0")
18549 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18371 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18550 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18372 "TARGET_SSE2"
18551 "TARGET_SSE2
18552 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18373 "pxor\t{%2, %0|%0, %2}"
18374 [(set_attr "type" "sse")])
18375
18376;; Use xor, but don't show input operands so they aren't live before
18377;; this insn.
18378(define_insn "sse_clrv4sf"
18379 [(set (match_operand:V4SF 0 "register_operand" "=x")
18380 (unspec:V4SF [(const_int 0)] 45))]

--- 453 unchanged lines hidden (view full) ---

18834;; MMX unsigned averages/sum of absolute differences
18835
18836(define_insn "mmx_uavgv8qi3"
18837 [(set (match_operand:V8QI 0 "register_operand" "=y")
18838 (ashiftrt:V8QI
18839 (plus:V8QI (plus:V8QI
18840 (match_operand:V8QI 1 "register_operand" "0")
18841 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
18553 "pxor\t{%2, %0|%0, %2}"
18554 [(set_attr "type" "sse")])
18555
18556;; Use xor, but don't show input operands so they aren't live before
18557;; this insn.
18558(define_insn "sse_clrv4sf"
18559 [(set (match_operand:V4SF 0 "register_operand" "=x")
18560 (unspec:V4SF [(const_int 0)] 45))]

--- 453 unchanged lines hidden (view full) ---

19014;; MMX unsigned averages/sum of absolute differences
19015
19016(define_insn "mmx_uavgv8qi3"
19017 [(set (match_operand:V8QI 0 "register_operand" "=y")
19018 (ashiftrt:V8QI
19019 (plus:V8QI (plus:V8QI
19020 (match_operand:V8QI 1 "register_operand" "0")
19021 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
18842 (vec_const:V8QI (parallel [(const_int 1)
18843 (const_int 1)
18844 (const_int 1)
18845 (const_int 1)
18846 (const_int 1)
18847 (const_int 1)
18848 (const_int 1)
18849 (const_int 1)])))
19022 (const_vector:V8QI [(const_int 1)
19023 (const_int 1)
19024 (const_int 1)
19025 (const_int 1)
19026 (const_int 1)
19027 (const_int 1)
19028 (const_int 1)
19029 (const_int 1)]))
18850 (const_int 1)))]
18851 "TARGET_SSE || TARGET_3DNOW_A"
18852 "pavgb\t{%2, %0|%0, %2}"
18853 [(set_attr "type" "sse")])
18854
18855(define_insn "mmx_uavgv4hi3"
18856 [(set (match_operand:V4HI 0 "register_operand" "=y")
18857 (ashiftrt:V4HI
18858 (plus:V4HI (plus:V4HI
18859 (match_operand:V4HI 1 "register_operand" "0")
18860 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
19030 (const_int 1)))]
19031 "TARGET_SSE || TARGET_3DNOW_A"
19032 "pavgb\t{%2, %0|%0, %2}"
19033 [(set_attr "type" "sse")])
19034
19035(define_insn "mmx_uavgv4hi3"
19036 [(set (match_operand:V4HI 0 "register_operand" "=y")
19037 (ashiftrt:V4HI
19038 (plus:V4HI (plus:V4HI
19039 (match_operand:V4HI 1 "register_operand" "0")
19040 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
18861 (vec_const:V4HI (parallel [(const_int 1)
18862 (const_int 1)
18863 (const_int 1)
18864 (const_int 1)])))
19041 (const_vector:V4HI [(const_int 1)
19042 (const_int 1)
19043 (const_int 1)
19044 (const_int 1)]))
18865 (const_int 1)))]
18866 "TARGET_SSE || TARGET_3DNOW_A"
18867 "pavgw\t{%2, %0|%0, %2}"
18868 [(set_attr "type" "sse")])
18869
18870(define_insn "mmx_psadbw"
18871 [(set (match_operand:V8QI 0 "register_operand" "=y")
18872 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")

--- 697 unchanged lines hidden (view full) ---

19570 (truncate:V4HI
19571 (lshiftrt:V4SI
19572 (plus:V4SI
19573 (mult:V4SI
19574 (sign_extend:V4SI
19575 (match_operand:V4HI 1 "register_operand" "0"))
19576 (sign_extend:V4SI
19577 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
19045 (const_int 1)))]
19046 "TARGET_SSE || TARGET_3DNOW_A"
19047 "pavgw\t{%2, %0|%0, %2}"
19048 [(set_attr "type" "sse")])
19049
19050(define_insn "mmx_psadbw"
19051 [(set (match_operand:V8QI 0 "register_operand" "=y")
19052 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")

--- 697 unchanged lines hidden (view full) ---

19750 (truncate:V4HI
19751 (lshiftrt:V4SI
19752 (plus:V4SI
19753 (mult:V4SI
19754 (sign_extend:V4SI
19755 (match_operand:V4HI 1 "register_operand" "0"))
19756 (sign_extend:V4SI
19757 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
19578 (vec_const:V4SI
19579 (parallel [(const_int 32768)
19580 (const_int 32768)
19581 (const_int 32768)
19582 (const_int 32768)])))
19583 (const_int 16))))]
19758 (const_vector:V4SI [(const_int 32768)
19759 (const_int 32768)
19760 (const_int 32768)
19761 (const_int 32768)]))
19762 (const_int 16))))]
19584 "TARGET_3DNOW"
19585 "pmulhrw\\t{%2, %0|%0, %2}"
19586 [(set_attr "type" "mmx")])
19587
19588(define_insn "pswapdv2si2"
19589 [(set (match_operand:V2SI 0 "register_operand" "=y")
19590 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
19591 (parallel [(const_int 1) (const_int 0)])))]

--- 66 unchanged lines hidden --- 		19763 "TARGET_3DNOW"
19764 "pmulhrw\\t{%2, %0|%0, %2}"
19765 [(set_attr "type" "mmx")])
19766
19767(define_insn "pswapdv2si2"
19768 [(set (match_operand:V2SI 0 "register_operand" "=y")
19769 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
19770 (parallel [(const_int 1) (const_int 0)])))]

--- 66 unchanged lines hidden ---