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i386.md (50650) i386.md (52296)
1; GCC machine description for Intel X86.
2;; Copyright (C) 1988, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3;; Mostly by William Schelter.
4
5;; This file is part of GNU CC.
6
7;; GNU CC is free software; you can redistribute it and/or modify
8;; it under the terms of the GNU General Public License as published by

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59;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
60;; operand 0 is the argument for `cos'.
61;; 3 This is part of a `stack probe' operation. The mode of the UNSPEC is
62;; always SImode. operand 0 is the size of the stack allocation.
63;; 4 This is the source of a fake SET of the frame pointer which is used to
64;; prevent insns referencing it being scheduled across the initial
65;; decrement of the stack pointer.
66;; 5 This is a `bsf' operation.
1; GCC machine description for Intel X86.
2;; Copyright (C) 1988, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3;; Mostly by William Schelter.
4
5;; This file is part of GNU CC.
6
7;; GNU CC is free software; you can redistribute it and/or modify
8;; it under the terms of the GNU General Public License as published by

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59;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
60;; operand 0 is the argument for `cos'.
61;; 3 This is part of a `stack probe' operation. The mode of the UNSPEC is
62;; always SImode. operand 0 is the size of the stack allocation.
63;; 4 This is the source of a fake SET of the frame pointer which is used to
64;; prevent insns referencing it being scheduled across the initial
65;; decrement of the stack pointer.
66;; 5 This is a `bsf' operation.
67;; 6 This is the @GOT offset of a PIC address.
68;; 7 This is the @GOTOFF offset of a PIC address.
69;; 8 This is a reference to a symbol's @PLT address.
67
68;; This shadows the processor_type enumeration, so changes must be made
69;; to i386.h at the same time.
70
70
71;; This shadows the processor_type enumeration, so changes must be made
72;; to i386.h at the same time.
73
71(define_attr "type" "integer,idiv,imul,fld,fpop,fpdiv,fpmul"
74;; $FreeBSD: head/contrib/gcc/config/i386/i386.md 52296 1999-10-16 08:12:02Z obrien $
75
76(define_attr "type"
77 "integer,binary,memory,test,compare,fcompare,idiv,imul,lea,fld,fpop,fpdiv,fpmul"
72 (const_string "integer"))
73
78 (const_string "integer"))
79
80(define_attr "memory" "none,load,store"
81 (cond [(eq_attr "type" "idiv,lea")
82 (const_string "none")
83
84 (eq_attr "type" "fld")
85 (const_string "load")
86
87 (eq_attr "type" "test")
88 (if_then_else (match_operand 0 "memory_operand" "")
89 (const_string "load")
90 (const_string "none"))
91
92 (eq_attr "type" "compare,fcompare")
93 (if_then_else (ior (match_operand 0 "memory_operand" "")
94 (match_operand 1 "memory_operand" ""))
95 (const_string "load")
96 (const_string "none"))
97
98 (and (eq_attr "type" "integer,memory,fpop")
99 (match_operand 0 "memory_operand" ""))
100 (const_string "store")
101
102 (and (eq_attr "type" "integer,memory,fpop")
103 (match_operand 1 "memory_operand" ""))
104 (const_string "load")
105
106 (and (eq_attr "type" "binary,imul,fpmul,fpdiv")
107 (ior (match_operand 1 "memory_operand" "")
108 (match_operand 2 "memory_operand" "")))
109 (const_string "load")]
110
111 (const_string "none")))
112
74;; Functional units
75
76; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
77; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
78
79; pentiumpro has a reservation station with 5 ports
80; port 0 has integer, float add, integer divide, float divide, float
81; multiply, and shifter units.
82; port 1 has integer, and jump units.
83; port 2 has the load address generation unit
84; ports 3 and 4 have the store address generation units
85
86; pentium has two integer pipelines, the main u pipe and the secondary v pipe.
87; and a float pipeline
88
89;; Floating point
90
91(define_function_unit "fp" 1 0
113;; Functional units
114
115; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
116; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
117
118; pentiumpro has a reservation station with 5 ports
119; port 0 has integer, float add, integer divide, float divide, float
120; multiply, and shifter units.
121; port 1 has integer, and jump units.
122; port 2 has the load address generation unit
123; ports 3 and 4 have the store address generation units
124
125; pentium has two integer pipelines, the main u pipe and the secondary v pipe.
126; and a float pipeline
127
128;; Floating point
129
130(define_function_unit "fp" 1 0
92 (and (eq_attr "type" "fpop") (eq_attr "cpu" "i386,i486"))
131 (and (eq_attr "type" "fpop,fcompare") (eq_attr "cpu" "i386,i486"))
93 5 5)
94
95(define_function_unit "fp" 1 0
132 5 5)
133
134(define_function_unit "fp" 1 0
96 (and (eq_attr "type" "fpop") (eq_attr "cpu" "pentium,pentiumpro"))
135 (and (eq_attr "type" "fpop,fcompare") (eq_attr "cpu" "pentium,pentiumpro"))
97 3 0)
98
99(define_function_unit "fp" 1 0
100 (and (eq_attr "type" "fpmul") (eq_attr "cpu" "pentium"))
101 7 0)
102
103(define_function_unit "fp" 1 0
104 (and (eq_attr "type" "fpmul") (eq_attr "cpu" "pentiumpro"))

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112 (and (eq_attr "type" "imul") (eq_attr "cpu" "pentiumpro"))
113 6 0)
114
115(define_function_unit "fp" 1 0
116 (eq_attr "type" "fpdiv")
117 10 10)
118
119(define_function_unit "fp" 1 0
136 3 0)
137
138(define_function_unit "fp" 1 0
139 (and (eq_attr "type" "fpmul") (eq_attr "cpu" "pentium"))
140 7 0)
141
142(define_function_unit "fp" 1 0
143 (and (eq_attr "type" "fpmul") (eq_attr "cpu" "pentiumpro"))

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151 (and (eq_attr "type" "imul") (eq_attr "cpu" "pentiumpro"))
152 6 0)
153
154(define_function_unit "fp" 1 0
155 (eq_attr "type" "fpdiv")
156 10 10)
157
158(define_function_unit "fp" 1 0
120 (eq_attr "type" "fld")
159 (and (eq_attr "type" "fld") (eq_attr "cpu" "!pentiumpro,k6"))
121 1 0)
122
160 1 0)
161
123(define_function_unit "integer" 1 0
124 (and (eq_attr "type" "integer") (eq_attr "cpu" "!i386"))
125 2 0)
162;; K6 FPU is not pipelined.
163(define_function_unit "fp" 1 0
164 (and (eq_attr "type" "fpop,fpmul,fcompare") (eq_attr "cpu" "k6"))
165 2 2)
126
166
167;; i386 and i486 have one integer unit, which need not be modeled
168
169(define_function_unit "integer" 2 0
170 (and (eq_attr "type" "integer,binary,test,compare,lea") (eq_attr "cpu" "pentium,pentiumpro"))
171 1 0)
172
173(define_function_unit "integer" 2 0
174 (and (eq_attr "cpu" "k6")
175 (and (eq_attr "type" "integer,binary,test,compare")
176 (eq_attr "memory" "!load")))
177 1 0)
178
179;; Internally, K6 converts REG OP MEM instructions into a load (2 cycles)
180;; and a register operation (1 cycle).
181(define_function_unit "integer" 2 0
182 (and (eq_attr "cpu" "k6")
183 (and (eq_attr "type" "integer,binary,test,compare")
184 (eq_attr "memory" "load")))
185 3 0)
186
187;; Multiplies use one of the integer units
188(define_function_unit "integer" 2 0
189 (and (eq_attr "cpu" "pentium") (eq_attr "type" "imul"))
190 11 11)
191
192(define_function_unit "integer" 2 0
193 (and (eq_attr "cpu" "k6") (eq_attr "type" "imul"))
194 2 2)
195
196(define_function_unit "integer" 2 0
197 (and (eq_attr "cpu" "pentium") (eq_attr "type" "idiv"))
198 25 25)
199
200(define_function_unit "integer" 2 0
201 (and (eq_attr "cpu" "k6") (eq_attr "type" "idiv"))
202 17 17)
203
204;; Pentium Pro and K6 have a separate load unit.
205(define_function_unit "load" 1 0
206 (and (eq_attr "cpu" "pentiumpro") (eq_attr "memory" "load"))
207 3 0)
208
209(define_function_unit "load" 1 0
210 (and (eq_attr "cpu" "k6") (eq_attr "memory" "load"))
211 2 0)
212
213;; Pentium Pro and K6 have a separate store unit.
214(define_function_unit "store" 1 0
215 (and (eq_attr "cpu" "pentiumpro,k6") (eq_attr "memory" "store"))
216 1 0)
217
218;; lea executes in the K6 store unit with 1 cycle latency
219(define_function_unit "store" 1 0
220 (and (eq_attr "cpu" "k6") (eq_attr "type" "lea"))
221 1 0)
222
127
128;; "movl MEM,REG / testl REG,REG" is faster on a 486 than "cmpl $0,MEM".
129;; But restricting MEM here would mean that gcc could not remove a redundant
130;; test in cases like "incl MEM / je TARGET".
131;;
132;; We don't want to allow a constant operand for test insns because
133;; (set (cc0) (const_int foo)) has no mode information. Such insns will
134;; be folded while optimizing anyway.
135
136;; All test insns have expanders that save the operands away without
137;; actually generating RTL. The bCOND or sCOND (emitted immediately
138;; after the tstM or cmp) will actually emit the tstM or cmpM.
139
140;; Processor type -- this attribute must exactly match the processor_type
141;; enumeration in i386.h.
142
223
224;; "movl MEM,REG / testl REG,REG" is faster on a 486 than "cmpl $0,MEM".
225;; But restricting MEM here would mean that gcc could not remove a redundant
226;; test in cases like "incl MEM / je TARGET".
227;;
228;; We don't want to allow a constant operand for test insns because
229;; (set (cc0) (const_int foo)) has no mode information. Such insns will
230;; be folded while optimizing anyway.
231
232;; All test insns have expanders that save the operands away without
233;; actually generating RTL. The bCOND or sCOND (emitted immediately
234;; after the tstM or cmp) will actually emit the tstM or cmpM.
235
236;; Processor type -- this attribute must exactly match the processor_type
237;; enumeration in i386.h.
238
143(define_attr "cpu" "i386,i486,pentium,pentiumpro"
239(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6"
144 (const (symbol_ref "ix86_cpu")))
145
146(define_insn "tstsi_1"
147 [(set (cc0)
148 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
149 ""
150 "*
151{
152 if (REG_P (operands[0]))
153 return AS2 (test%L0,%0,%0);
154
155 operands[1] = const0_rtx;
156 return AS2 (cmp%L0,%1,%0);
240 (const (symbol_ref "ix86_cpu")))
241
242(define_insn "tstsi_1"
243 [(set (cc0)
244 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
245 ""
246 "*
247{
248 if (REG_P (operands[0]))
249 return AS2 (test%L0,%0,%0);
250
251 operands[1] = const0_rtx;
252 return AS2 (cmp%L0,%1,%0);
157}")
253}"
254 [(set_attr "type" "test")])
158
159(define_expand "tstsi"
160 [(set (cc0)
161 (match_operand:SI 0 "nonimmediate_operand" ""))]
162 ""
163 "
164{
165 i386_compare_gen = gen_tstsi_1;

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174 ""
175 "*
176{
177 if (REG_P (operands[0]))
178 return AS2 (test%W0,%0,%0);
179
180 operands[1] = const0_rtx;
181 return AS2 (cmp%W0,%1,%0);
255
256(define_expand "tstsi"
257 [(set (cc0)
258 (match_operand:SI 0 "nonimmediate_operand" ""))]
259 ""
260 "
261{
262 i386_compare_gen = gen_tstsi_1;

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271 ""
272 "*
273{
274 if (REG_P (operands[0]))
275 return AS2 (test%W0,%0,%0);
276
277 operands[1] = const0_rtx;
278 return AS2 (cmp%W0,%1,%0);
182}")
279}"
280 [(set_attr "type" "test")])
183
184(define_expand "tsthi"
185 [(set (cc0)
186 (match_operand:HI 0 "nonimmediate_operand" ""))]
187 ""
188 "
189{
190 i386_compare_gen = gen_tsthi_1;

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199 ""
200 "*
201{
202 if (REG_P (operands[0]))
203 return AS2 (test%B0,%0,%0);
204
205 operands[1] = const0_rtx;
206 return AS2 (cmp%B0,%1,%0);
281
282(define_expand "tsthi"
283 [(set (cc0)
284 (match_operand:HI 0 "nonimmediate_operand" ""))]
285 ""
286 "
287{
288 i386_compare_gen = gen_tsthi_1;

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297 ""
298 "*
299{
300 if (REG_P (operands[0]))
301 return AS2 (test%B0,%0,%0);
302
303 operands[1] = const0_rtx;
304 return AS2 (cmp%B0,%1,%0);
207}")
305}"
306 [(set_attr "type" "test")])
208
209(define_expand "tstqi"
210 [(set (cc0)
211 (match_operand:QI 0 "nonimmediate_operand" ""))]
212 ""
213 "
214{
215 i386_compare_gen = gen_tstqi_1;

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229 abort ();
230
231 output_asm_insn (\"ftst\", operands);
232
233 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
234 output_asm_insn (AS1 (fstp,%y0), operands);
235
236 return output_fp_cc0_set (insn);
307
308(define_expand "tstqi"
309 [(set (cc0)
310 (match_operand:QI 0 "nonimmediate_operand" ""))]
311 ""
312 "
313{
314 i386_compare_gen = gen_tstqi_1;

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328 abort ();
329
330 output_asm_insn (\"ftst\", operands);
331
332 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
333 output_asm_insn (AS1 (fstp,%y0), operands);
334
335 return output_fp_cc0_set (insn);
237}")
336}"
337 [(set_attr "type" "test")])
238
239;; Don't generate tstsf if generating IEEE code, since the `ftst' opcode
240;; isn't IEEE compliant.
241
242(define_expand "tstsf"
243 [(parallel [(set (cc0)
244 (match_operand:SF 0 "register_operand" ""))
245 (clobber (match_scratch:HI 1 ""))])]

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263 abort ();
264
265 output_asm_insn (\"ftst\", operands);
266
267 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
268 output_asm_insn (AS1 (fstp,%y0), operands);
269
270 return output_fp_cc0_set (insn);
338
339;; Don't generate tstsf if generating IEEE code, since the `ftst' opcode
340;; isn't IEEE compliant.
341
342(define_expand "tstsf"
343 [(parallel [(set (cc0)
344 (match_operand:SF 0 "register_operand" ""))
345 (clobber (match_scratch:HI 1 ""))])]

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363 abort ();
364
365 output_asm_insn (\"ftst\", operands);
366
367 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
368 output_asm_insn (AS1 (fstp,%y0), operands);
369
370 return output_fp_cc0_set (insn);
271}")
371}"
372 [(set_attr "type" "test")])
272
273;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode
274;; isn't IEEE compliant.
275
276(define_expand "tstdf"
277 [(parallel [(set (cc0)
278 (match_operand:DF 0 "register_operand" ""))
279 (clobber (match_scratch:HI 1 ""))])]

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297 abort ();
298
299 output_asm_insn (\"ftst\", operands);
300
301 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
302 output_asm_insn (AS1 (fstp,%y0), operands);
303
304 return output_fp_cc0_set (insn);
373
374;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode
375;; isn't IEEE compliant.
376
377(define_expand "tstdf"
378 [(parallel [(set (cc0)
379 (match_operand:DF 0 "register_operand" ""))
380 (clobber (match_scratch:HI 1 ""))])]

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398 abort ();
399
400 output_asm_insn (\"ftst\", operands);
401
402 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
403 output_asm_insn (AS1 (fstp,%y0), operands);
404
405 return output_fp_cc0_set (insn);
305}")
406}"
407 [(set_attr "type" "test")])
306
307;; Don't generate tstxf if generating IEEE code, since the `ftst' opcode
308;; isn't IEEE compliant.
309
310(define_expand "tstxf"
311 [(parallel [(set (cc0)
312 (match_operand:XF 0 "register_operand" ""))
313 (clobber (match_scratch:HI 1 ""))])]

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323;;- compare instructions. See comments above tstM patterns about
324;; expansion of these insns.
325
326(define_insn "cmpsi_1"
327 [(set (cc0)
328 (compare (match_operand:SI 0 "nonimmediate_operand" "mr,r")
329 (match_operand:SI 1 "general_operand" "ri,mr")))]
330 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
408
409;; Don't generate tstxf if generating IEEE code, since the `ftst' opcode
410;; isn't IEEE compliant.
411
412(define_expand "tstxf"
413 [(parallel [(set (cc0)
414 (match_operand:XF 0 "register_operand" ""))
415 (clobber (match_scratch:HI 1 ""))])]

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425;;- compare instructions. See comments above tstM patterns about
426;; expansion of these insns.
427
428(define_insn "cmpsi_1"
429 [(set (cc0)
430 (compare (match_operand:SI 0 "nonimmediate_operand" "mr,r")
431 (match_operand:SI 1 "general_operand" "ri,mr")))]
432 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
331 "* return AS2 (cmp%L0,%1,%0);")
433 "* return AS2 (cmp%L0,%1,%0);"
434 [(set_attr "type" "compare")])
332
333(define_expand "cmpsi"
334 [(set (cc0)
335 (compare (match_operand:SI 0 "nonimmediate_operand" "")
336 (match_operand:SI 1 "general_operand" "")))]
337 ""
338 "
339{

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346 DONE;
347}")
348
349(define_insn "cmphi_1"
350 [(set (cc0)
351 (compare (match_operand:HI 0 "nonimmediate_operand" "mr,r")
352 (match_operand:HI 1 "general_operand" "ri,mr")))]
353 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
435
436(define_expand "cmpsi"
437 [(set (cc0)
438 (compare (match_operand:SI 0 "nonimmediate_operand" "")
439 (match_operand:SI 1 "general_operand" "")))]
440 ""
441 "
442{

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449 DONE;
450}")
451
452(define_insn "cmphi_1"
453 [(set (cc0)
454 (compare (match_operand:HI 0 "nonimmediate_operand" "mr,r")
455 (match_operand:HI 1 "general_operand" "ri,mr")))]
456 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
354 "* return AS2 (cmp%W0,%1,%0);")
457 "* return AS2 (cmp%W0,%1,%0);"
458 [(set_attr "type" "compare")])
355
356(define_expand "cmphi"
357 [(set (cc0)
358 (compare (match_operand:HI 0 "nonimmediate_operand" "")
359 (match_operand:HI 1 "general_operand" "")))]
360 ""
361 "
362{

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369 DONE;
370}")
371
372(define_insn "cmpqi_1"
373 [(set (cc0)
374 (compare (match_operand:QI 0 "nonimmediate_operand" "q,mq")
375 (match_operand:QI 1 "general_operand" "qm,nq")))]
376 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
459
460(define_expand "cmphi"
461 [(set (cc0)
462 (compare (match_operand:HI 0 "nonimmediate_operand" "")
463 (match_operand:HI 1 "general_operand" "")))]
464 ""
465 "
466{

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473 DONE;
474}")
475
476(define_insn "cmpqi_1"
477 [(set (cc0)
478 (compare (match_operand:QI 0 "nonimmediate_operand" "q,mq")
479 (match_operand:QI 1 "general_operand" "qm,nq")))]
480 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
377 "* return AS2 (cmp%B0,%1,%0);")
481 "* return AS2 (cmp%B0,%1,%0);"
482 [(set_attr "type" "compare")])
378
379(define_expand "cmpqi"
380 [(set (cc0)
381 (compare (match_operand:QI 0 "nonimmediate_operand" "")
382 (match_operand:QI 1 "general_operand" "")))]
383 ""
384 "
385{

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398
399(define_insn ""
400 [(set (cc0)
401 (match_operator 2 "VOIDmode_compare_op"
402 [(match_operand:XF 0 "register_operand" "f")
403 (match_operand:XF 1 "register_operand" "f")]))
404 (clobber (match_scratch:HI 3 "=a"))]
405 "TARGET_80387"
483
484(define_expand "cmpqi"
485 [(set (cc0)
486 (compare (match_operand:QI 0 "nonimmediate_operand" "")
487 (match_operand:QI 1 "general_operand" "")))]
488 ""
489 "
490{

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503
504(define_insn ""
505 [(set (cc0)
506 (match_operator 2 "VOIDmode_compare_op"
507 [(match_operand:XF 0 "register_operand" "f")
508 (match_operand:XF 1 "register_operand" "f")]))
509 (clobber (match_scratch:HI 3 "=a"))]
510 "TARGET_80387"
406 "* return output_float_compare (insn, operands);")
511 "* return output_float_compare (insn, operands);"
512 [(set_attr "type" "fcompare")])
407
408(define_insn ""
409 [(set (cc0)
410 (match_operator 2 "VOIDmode_compare_op"
411 [(match_operand:XF 0 "register_operand" "f")
513
514(define_insn ""
515 [(set (cc0)
516 (match_operator 2 "VOIDmode_compare_op"
517 [(match_operand:XF 0 "register_operand" "f")
412 (float:XF
413 (match_operand:SI 1 "nonimmediate_operand" "rm"))]))
414 (clobber (match_scratch:HI 3 "=a"))]
415 "TARGET_80387"
416 "* return output_float_compare (insn, operands);")
417
418(define_insn ""
419 [(set (cc0)
420 (match_operator 2 "VOIDmode_compare_op"
421 [(float:XF
422 (match_operand:SI 0 "nonimmediate_operand" "rm"))
423 (match_operand:XF 1 "register_operand" "f")]))
424 (clobber (match_scratch:HI 3 "=a"))]
425 "TARGET_80387"
426 "* return output_float_compare (insn, operands);")
427
428(define_insn ""
429 [(set (cc0)
430 (match_operator 2 "VOIDmode_compare_op"
431 [(match_operand:XF 0 "register_operand" "f")
432 (float_extend:XF
433 (match_operand:DF 1 "nonimmediate_operand" "fm"))]))
434 (clobber (match_scratch:HI 3 "=a"))]
435 "TARGET_80387"
518 (float_extend:XF
519 (match_operand:DF 1 "nonimmediate_operand" "fm"))]))
520 (clobber (match_scratch:HI 3 "=a"))]
521 "TARGET_80387"
436 "* return output_float_compare (insn, operands);")
522 "* return output_float_compare (insn, operands);"
523 [(set_attr "type" "fcompare")])
437
438(define_insn ""
439 [(set (cc0)
440 (match_operator 2 "VOIDmode_compare_op"
441 [(float_extend:XF
442 (match_operand:DF 0 "nonimmediate_operand" "fm"))
443 (match_operand:XF 1 "register_operand" "f")]))
444 (clobber (match_scratch:HI 3 "=a"))]
445 "TARGET_80387"
524
525(define_insn ""
526 [(set (cc0)
527 (match_operator 2 "VOIDmode_compare_op"
528 [(float_extend:XF
529 (match_operand:DF 0 "nonimmediate_operand" "fm"))
530 (match_operand:XF 1 "register_operand" "f")]))
531 (clobber (match_scratch:HI 3 "=a"))]
532 "TARGET_80387"
446 "* return output_float_compare (insn, operands);")
533 "* return output_float_compare (insn, operands);"
534 [(set_attr "type" "fcompare")])
447
448(define_insn ""
449 [(set (cc0)
450 (match_operator 2 "VOIDmode_compare_op"
451 [(match_operand:XF 0 "register_operand" "f")
452 (float_extend:XF
453 (match_operand:SF 1 "nonimmediate_operand" "fm"))]))
454 (clobber (match_scratch:HI 3 "=a"))]
455 "TARGET_80387"
535
536(define_insn ""
537 [(set (cc0)
538 (match_operator 2 "VOIDmode_compare_op"
539 [(match_operand:XF 0 "register_operand" "f")
540 (float_extend:XF
541 (match_operand:SF 1 "nonimmediate_operand" "fm"))]))
542 (clobber (match_scratch:HI 3 "=a"))]
543 "TARGET_80387"
456 "* return output_float_compare (insn, operands);")
544 "* return output_float_compare (insn, operands);"
545 [(set_attr "type" "fcompare")])
457
458(define_insn ""
459 [(set (cc0)
460 (match_operator 2 "VOIDmode_compare_op"
461 [(float_extend:XF
462 (match_operand:SF 0 "nonimmediate_operand" "fm"))
463 (match_operand:XF 1 "register_operand" "f")]))
464 (clobber (match_scratch:HI 3 "=a"))]
465 "TARGET_80387"
546
547(define_insn ""
548 [(set (cc0)
549 (match_operator 2 "VOIDmode_compare_op"
550 [(float_extend:XF
551 (match_operand:SF 0 "nonimmediate_operand" "fm"))
552 (match_operand:XF 1 "register_operand" "f")]))
553 (clobber (match_scratch:HI 3 "=a"))]
554 "TARGET_80387"
466 "* return output_float_compare (insn, operands);")
555 "* return output_float_compare (insn, operands);"
556 [(set_attr "type" "fcompare")])
467
468(define_insn ""
469 [(set (cc0)
470 (compare:CCFPEQ (match_operand:XF 0 "register_operand" "f")
471 (match_operand:XF 1 "register_operand" "f")))
472 (clobber (match_scratch:HI 2 "=a"))]
473 "TARGET_80387"
557
558(define_insn ""
559 [(set (cc0)
560 (compare:CCFPEQ (match_operand:XF 0 "register_operand" "f")
561 (match_operand:XF 1 "register_operand" "f")))
562 (clobber (match_scratch:HI 2 "=a"))]
563 "TARGET_80387"
474 "* return output_float_compare (insn, operands);")
564 "* return output_float_compare (insn, operands);"
565 [(set_attr "type" "fcompare")])
475
476(define_insn ""
477 [(set (cc0)
478 (match_operator 2 "VOIDmode_compare_op"
479 [(match_operand:DF 0 "nonimmediate_operand" "f,fm")
480 (match_operand:DF 1 "nonimmediate_operand" "fm,f")]))
481 (clobber (match_scratch:HI 3 "=a,a"))]
482 "TARGET_80387
483 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
566
567(define_insn ""
568 [(set (cc0)
569 (match_operator 2 "VOIDmode_compare_op"
570 [(match_operand:DF 0 "nonimmediate_operand" "f,fm")
571 (match_operand:DF 1 "nonimmediate_operand" "fm,f")]))
572 (clobber (match_scratch:HI 3 "=a,a"))]
573 "TARGET_80387
574 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
484 "* return output_float_compare (insn, operands);")
575 "* return output_float_compare (insn, operands);"
576 [(set_attr "type" "fcompare")])
485
486(define_insn ""
487 [(set (cc0)
488 (match_operator 2 "VOIDmode_compare_op"
489 [(match_operand:DF 0 "register_operand" "f")
577
578(define_insn ""
579 [(set (cc0)
580 (match_operator 2 "VOIDmode_compare_op"
581 [(match_operand:DF 0 "register_operand" "f")
490 (float:DF
491 (match_operand:SI 1 "nonimmediate_operand" "rm"))]))
492 (clobber (match_scratch:HI 3 "=a"))]
493 "TARGET_80387"
494 "* return output_float_compare (insn, operands);")
495
496(define_insn ""
497 [(set (cc0)
498 (match_operator 2 "VOIDmode_compare_op"
499 [(float:DF
500 (match_operand:SI 0 "nonimmediate_operand" "rm"))
501 (match_operand:DF 1 "register_operand" "f")]))
502 (clobber (match_scratch:HI 3 "=a"))]
503 "TARGET_80387"
504 "* return output_float_compare (insn, operands);")
505
506(define_insn ""
507 [(set (cc0)
508 (match_operator 2 "VOIDmode_compare_op"
509 [(match_operand:DF 0 "register_operand" "f")
510 (float_extend:DF
511 (match_operand:SF 1 "nonimmediate_operand" "fm"))]))
512 (clobber (match_scratch:HI 3 "=a"))]
513 "TARGET_80387"
582 (float_extend:DF
583 (match_operand:SF 1 "nonimmediate_operand" "fm"))]))
584 (clobber (match_scratch:HI 3 "=a"))]
585 "TARGET_80387"
514 "* return output_float_compare (insn, operands);")
586 "* return output_float_compare (insn, operands);"
587 [(set_attr "type" "fcompare")])
515
516(define_insn ""
517 [(set (cc0)
518 (match_operator 2 "VOIDmode_compare_op"
519 [(float_extend:DF
520 (match_operand:SF 0 "nonimmediate_operand" "fm"))
521 (match_operand:DF 1 "register_operand" "f")]))
522 (clobber (match_scratch:HI 3 "=a"))]
523 "TARGET_80387"
588
589(define_insn ""
590 [(set (cc0)
591 (match_operator 2 "VOIDmode_compare_op"
592 [(float_extend:DF
593 (match_operand:SF 0 "nonimmediate_operand" "fm"))
594 (match_operand:DF 1 "register_operand" "f")]))
595 (clobber (match_scratch:HI 3 "=a"))]
596 "TARGET_80387"
524 "* return output_float_compare (insn, operands);")
597 "* return output_float_compare (insn, operands);"
598 [(set_attr "type" "fcompare")])
525
526(define_insn ""
527 [(set (cc0)
528 (match_operator 2 "VOIDmode_compare_op"
529 [(float_extend:DF
530 (match_operand:SF 0 "register_operand" "f"))
531 (match_operand:DF 1 "nonimmediate_operand" "fm")]))
532 (clobber (match_scratch:HI 3 "=a"))]
533 "TARGET_80387"
599
600(define_insn ""
601 [(set (cc0)
602 (match_operator 2 "VOIDmode_compare_op"
603 [(float_extend:DF
604 (match_operand:SF 0 "register_operand" "f"))
605 (match_operand:DF 1 "nonimmediate_operand" "fm")]))
606 (clobber (match_scratch:HI 3 "=a"))]
607 "TARGET_80387"
534 "* return output_float_compare (insn, operands);")
608 "* return output_float_compare (insn, operands);"
609 [(set_attr "type" "fcompare")])
535
536(define_insn ""
537 [(set (cc0)
538 (compare:CCFPEQ (match_operand:DF 0 "register_operand" "f")
539 (match_operand:DF 1 "register_operand" "f")))
540 (clobber (match_scratch:HI 2 "=a"))]
541 "TARGET_80387"
610
611(define_insn ""
612 [(set (cc0)
613 (compare:CCFPEQ (match_operand:DF 0 "register_operand" "f")
614 (match_operand:DF 1 "register_operand" "f")))
615 (clobber (match_scratch:HI 2 "=a"))]
616 "TARGET_80387"
542 "* return output_float_compare (insn, operands);")
617 "* return output_float_compare (insn, operands);"
618 [(set_attr "type" "fcompare")])
543
544;; These two insns will never be generated by combine due to the mode of
545;; the COMPARE.
546;(define_insn ""
547; [(set (cc0)
548; (compare:CCFPEQ (match_operand:DF 0 "register_operand" "f")
549; (float_extend:DF
550; (match_operand:SF 1 "register_operand" "f"))))

--- 5 unchanged lines hidden (view full) ---

556; [(set (cc0)
557; (compare:CCFPEQ (float_extend:DF
558; (match_operand:SF 0 "register_operand" "f"))
559; (match_operand:DF 1 "register_operand" "f")))
560; (clobber (match_scratch:HI 2 "=a"))]
561; "TARGET_80387"
562; "* return output_float_compare (insn, operands);")
563
619
620;; These two insns will never be generated by combine due to the mode of
621;; the COMPARE.
622;(define_insn ""
623; [(set (cc0)
624; (compare:CCFPEQ (match_operand:DF 0 "register_operand" "f")
625; (float_extend:DF
626; (match_operand:SF 1 "register_operand" "f"))))

--- 5 unchanged lines hidden (view full) ---

632; [(set (cc0)
633; (compare:CCFPEQ (float_extend:DF
634; (match_operand:SF 0 "register_operand" "f"))
635; (match_operand:DF 1 "register_operand" "f")))
636; (clobber (match_scratch:HI 2 "=a"))]
637; "TARGET_80387"
638; "* return output_float_compare (insn, operands);")
639
564(define_insn "cmpsf_cc_1"
640(define_insn "*cmpsf_cc_1"
565 [(set (cc0)
566 (match_operator 2 "VOIDmode_compare_op"
567 [(match_operand:SF 0 "nonimmediate_operand" "f,fm")
568 (match_operand:SF 1 "nonimmediate_operand" "fm,f")]))
569 (clobber (match_scratch:HI 3 "=a,a"))]
570 "TARGET_80387
571 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
641 [(set (cc0)
642 (match_operator 2 "VOIDmode_compare_op"
643 [(match_operand:SF 0 "nonimmediate_operand" "f,fm")
644 (match_operand:SF 1 "nonimmediate_operand" "fm,f")]))
645 (clobber (match_scratch:HI 3 "=a,a"))]
646 "TARGET_80387
647 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
572 "* return output_float_compare (insn, operands);")
648 "* return output_float_compare (insn, operands);"
649 [(set_attr "type" "fcompare")])
573
574(define_insn ""
575 [(set (cc0)
650
651(define_insn ""
652 [(set (cc0)
576 (match_operator 2 "VOIDmode_compare_op"
577 [(match_operand:SF 0 "register_operand" "f")
578 (float:SF
579 (match_operand:SI 1 "nonimmediate_operand" "rm"))]))
580 (clobber (match_scratch:HI 3 "=a"))]
581 "TARGET_80387"
582 "* return output_float_compare (insn, operands);")
583
584(define_insn ""
585 [(set (cc0)
586 (match_operator 2 "VOIDmode_compare_op"
587 [(float:SF
588 (match_operand:SI 0 "nonimmediate_operand" "rm"))
589 (match_operand:SF 1 "register_operand" "f")]))
590 (clobber (match_scratch:HI 3 "=a"))]
591 "TARGET_80387"
592 "* return output_float_compare (insn, operands);")
593
594(define_insn ""
595 [(set (cc0)
596 (compare:CCFPEQ (match_operand:SF 0 "register_operand" "f")
597 (match_operand:SF 1 "register_operand" "f")))
598 (clobber (match_scratch:HI 2 "=a"))]
599 "TARGET_80387"
653 (compare:CCFPEQ (match_operand:SF 0 "register_operand" "f")
654 (match_operand:SF 1 "register_operand" "f")))
655 (clobber (match_scratch:HI 2 "=a"))]
656 "TARGET_80387"
600 "* return output_float_compare (insn, operands);")
657 "* return output_float_compare (insn, operands);"
658 [(set_attr "type" "fcompare")])
601
602(define_expand "cmpxf"
603 [(set (cc0)
604 (compare (match_operand:XF 0 "register_operand" "")
605 (match_operand:XF 1 "register_operand" "")))]
606 "TARGET_80387"
607 "
608{

--- 97 unchanged lines hidden (view full) ---

706 (and:SI (match_operand:SI 0 "general_operand" "%ro")
707 (match_operand:SI 1 "nonmemory_operand" "ri")))]
708 ""
709 "*
710{
711 /* For small integers, we may actually use testb. */
712 if (GET_CODE (operands[1]) == CONST_INT
713 && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
659
660(define_expand "cmpxf"
661 [(set (cc0)
662 (compare (match_operand:XF 0 "register_operand" "")
663 (match_operand:XF 1 "register_operand" "")))]
664 "TARGET_80387"
665 "
666{

--- 97 unchanged lines hidden (view full) ---

764 (and:SI (match_operand:SI 0 "general_operand" "%ro")
765 (match_operand:SI 1 "nonmemory_operand" "ri")))]
766 ""
767 "*
768{
769 /* For small integers, we may actually use testb. */
770 if (GET_CODE (operands[1]) == CONST_INT
771 && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
714 && (! REG_P (operands[0]) || QI_REG_P (operands[0])))
772 && (! REG_P (operands[0]) || QI_REG_P (operands[0]))
773 /* A Pentium test is pairable only with eax. Not with ah or al. */
774 && (! REG_P (operands[0]) || REGNO (operands[0]) || !TARGET_PENTIUM
775 || optimize_size))
715 {
716 /* We may set the sign bit spuriously. */
717
718 if ((INTVAL (operands[1]) & ~0xff) == 0)
719 {
720 cc_status.flags |= CC_NOT_NEGATIVE;
721 return AS2 (test%B0,%1,%b0);
722 }

--- 29 unchanged lines hidden (view full) ---

752 return AS2 (test%B0,%1,%b0);
753 }
754 }
755
756 if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
757 return AS2 (test%L0,%1,%0);
758
759 return AS2 (test%L1,%0,%1);
776 {
777 /* We may set the sign bit spuriously. */
778
779 if ((INTVAL (operands[1]) & ~0xff) == 0)
780 {
781 cc_status.flags |= CC_NOT_NEGATIVE;
782 return AS2 (test%B0,%1,%b0);
783 }

--- 29 unchanged lines hidden (view full) ---

813 return AS2 (test%B0,%1,%b0);
814 }
815 }
816
817 if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
818 return AS2 (test%L0,%1,%0);
819
820 return AS2 (test%L1,%0,%1);
760}")
821}"
822 [(set_attr "type" "compare")])
761
762(define_insn ""
763 [(set (cc0)
764 (and:HI (match_operand:HI 0 "general_operand" "%ro")
765 (match_operand:HI 1 "nonmemory_operand" "ri")))]
766 ""
767 "*
768{

--- 31 unchanged lines hidden (view full) ---

800 && !(INTVAL (operands[1]) & ~0x7fff)
801 && i386_aligned_p (operands[0]))
802 return AS2 (test%L0,%1,%k0);
803
804 if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
805 return AS2 (test%W0,%1,%0);
806
807 return AS2 (test%W1,%0,%1);
823
824(define_insn ""
825 [(set (cc0)
826 (and:HI (match_operand:HI 0 "general_operand" "%ro")
827 (match_operand:HI 1 "nonmemory_operand" "ri")))]
828 ""
829 "*
830{

--- 31 unchanged lines hidden (view full) ---

862 && !(INTVAL (operands[1]) & ~0x7fff)
863 && i386_aligned_p (operands[0]))
864 return AS2 (test%L0,%1,%k0);
865
866 if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
867 return AS2 (test%W0,%1,%0);
868
869 return AS2 (test%W1,%0,%1);
808}")
870}"
871 [(set_attr "type" "compare")])
809
810(define_insn ""
811 [(set (cc0)
812 (and:QI (match_operand:QI 0 "nonimmediate_operand" "%qm")
813 (match_operand:QI 1 "nonmemory_operand" "qi")))]
814 ""
815 "*
816{
817 if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
818 return AS2 (test%B0,%1,%0);
819
820 return AS2 (test%B1,%0,%1);
872
873(define_insn ""
874 [(set (cc0)
875 (and:QI (match_operand:QI 0 "nonimmediate_operand" "%qm")
876 (match_operand:QI 1 "nonmemory_operand" "qi")))]
877 ""
878 "*
879{
880 if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
881 return AS2 (test%B0,%1,%0);
882
883 return AS2 (test%B1,%0,%1);
821}")
884}"
885 [(set_attr "type" "compare")])
822
823;; move instructions.
824;; There is one for each machine mode,
825;; and each is preceded by a corresponding push-insn pattern
826;; (since pushes are not general_operands on the 386).
827
828(define_insn ""
829 [(set (match_operand:SI 0 "push_operand" "=<")
830 (match_operand:SI 1 "nonmemory_operand" "rn"))]
831 "flag_pic"
886
887;; move instructions.
888;; There is one for each machine mode,
889;; and each is preceded by a corresponding push-insn pattern
890;; (since pushes are not general_operands on the 386).
891
892(define_insn ""
893 [(set (match_operand:SI 0 "push_operand" "=<")
894 (match_operand:SI 1 "nonmemory_operand" "rn"))]
895 "flag_pic"
832 "* return AS1 (push%L0,%1);")
896 "* return AS1 (push%L0,%1);"
897 [(set_attr "memory" "store")])
833
834(define_insn ""
835 [(set (match_operand:SI 0 "push_operand" "=<")
836 (match_operand:SI 1 "nonmemory_operand" "ri"))]
837 "!flag_pic"
898
899(define_insn ""
900 [(set (match_operand:SI 0 "push_operand" "=<")
901 (match_operand:SI 1 "nonmemory_operand" "ri"))]
902 "!flag_pic"
838 "* return AS1 (push%L0,%1);")
903 "* return AS1 (push%L0,%1);"
904 [(set_attr "memory" "store")])
839
840;; On a 386, it is faster to push MEM directly.
841
842(define_insn ""
843 [(set (match_operand:SI 0 "push_operand" "=<")
844 (match_operand:SI 1 "memory_operand" "m"))]
845 "TARGET_PUSH_MEMORY"
905
906;; On a 386, it is faster to push MEM directly.
907
908(define_insn ""
909 [(set (match_operand:SI 0 "push_operand" "=<")
910 (match_operand:SI 1 "memory_operand" "m"))]
911 "TARGET_PUSH_MEMORY"
846 "* return AS1 (push%L0,%1);")
912 "* return AS1 (push%L0,%1);"
913 [(set_attr "type" "memory")
914 (set_attr "memory" "load")])
847
848;; General case of fullword move.
849
850;; If generating PIC code and operands[1] is a symbolic CONST, emit a
851;; move to get the address of the symbolic object from the GOT.
852
853(define_expand "movsi"
854 [(set (match_operand:SI 0 "general_operand" "")
855 (match_operand:SI 1 "general_operand" ""))]
856 ""
857 "
858{
859 extern int flag_pic;
860
861 if (flag_pic && SYMBOLIC_CONST (operands[1]))
862 emit_pic_move (operands, SImode);
863
864 /* Don't generate memory->memory moves, go through a register */
865 else if (TARGET_MOVE
915
916;; General case of fullword move.
917
918;; If generating PIC code and operands[1] is a symbolic CONST, emit a
919;; move to get the address of the symbolic object from the GOT.
920
921(define_expand "movsi"
922 [(set (match_operand:SI 0 "general_operand" "")
923 (match_operand:SI 1 "general_operand" ""))]
924 ""
925 "
926{
927 extern int flag_pic;
928
929 if (flag_pic && SYMBOLIC_CONST (operands[1]))
930 emit_pic_move (operands, SImode);
931
932 /* Don't generate memory->memory moves, go through a register */
933 else if (TARGET_MOVE
866 && (reload_in_progress | reload_completed) == 0
934 && no_new_pseudos == 0
867 && GET_CODE (operands[0]) == MEM
868 && GET_CODE (operands[1]) == MEM)
869 {
870 operands[1] = force_reg (SImode, operands[1]);
871 }
872}")
873
874;; On i486, incl reg is faster than movl $1,reg.
875
876(define_insn ""
935 && GET_CODE (operands[0]) == MEM
936 && GET_CODE (operands[1]) == MEM)
937 {
938 operands[1] = force_reg (SImode, operands[1]);
939 }
940}")
941
942;; On i486, incl reg is faster than movl $1,reg.
943
944(define_insn ""
877 [(set (match_operand:SI 0 "general_operand" "=g,r")
878 (match_operand:SI 1 "general_operand" "rn,im"))]
945 [(set (match_operand:SI 0 "general_operand" "=g,r,r")
946 (match_operand:SI 1 "general_operand" "rn,i,m"))]
879 "((!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
880 || (GET_CODE (operands[1]) != MEM))
881 && flag_pic"
882 "*
883{
884 rtx link;
947 "((!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
948 || (GET_CODE (operands[1]) != MEM))
949 && flag_pic"
950 "*
951{
952 rtx link;
885 if (operands[1] == const0_rtx && REG_P (operands[0]))
953
954 /* K6: mov reg,0 is slightly faster than xor reg,reg but is 3 bytes
955 longer. */
956 if ((ix86_cpu != PROCESSOR_K6 || optimize_size)
957 && operands[1] == const0_rtx && REG_P (operands[0]))
886 return AS2 (xor%L0,%0,%0);
887
888 if (operands[1] == const1_rtx
958 return AS2 (xor%L0,%0,%0);
959
960 if (operands[1] == const1_rtx
961 /* PPRO and K6 prefer mov to inc to reduce dependencies. */
962 && (optimize_size || (int)ix86_cpu < (int)PROCESSOR_PENTIUMPRO)
889 && (link = find_reg_note (insn, REG_WAS_0, 0))
890 /* Make sure the insn that stored the 0 is still present. */
891 && ! INSN_DELETED_P (XEXP (link, 0))
892 && GET_CODE (XEXP (link, 0)) != NOTE
893 /* Make sure cross jumping didn't happen here. */
894 && no_labels_between_p (XEXP (link, 0), insn)
895 /* Make sure the reg hasn't been clobbered. */
896 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
897 /* Fastest way to change a 0 to a 1. */
898 return AS1 (inc%L0,%0);
899
900 if (SYMBOLIC_CONST (operands[1]))
901 return AS2 (lea%L0,%a1,%0);
902
903 return AS2 (mov%L0,%1,%0);
963 && (link = find_reg_note (insn, REG_WAS_0, 0))
964 /* Make sure the insn that stored the 0 is still present. */
965 && ! INSN_DELETED_P (XEXP (link, 0))
966 && GET_CODE (XEXP (link, 0)) != NOTE
967 /* Make sure cross jumping didn't happen here. */
968 && no_labels_between_p (XEXP (link, 0), insn)
969 /* Make sure the reg hasn't been clobbered. */
970 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
971 /* Fastest way to change a 0 to a 1. */
972 return AS1 (inc%L0,%0);
973
974 if (SYMBOLIC_CONST (operands[1]))
975 return AS2 (lea%L0,%a1,%0);
976
977 return AS2 (mov%L0,%1,%0);
904}")
978}"
979 [(set_attr "type" "integer,integer,memory")
980 (set_attr "memory" "*,*,load")])
905
906(define_insn ""
907 [(set (match_operand:SI 0 "general_operand" "=g,r")
908 (match_operand:SI 1 "general_operand" "ri,m"))]
909 "((!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
910 || (GET_CODE (operands[1]) != MEM))
911 && !flag_pic"
912 "*
913{
914 rtx link;
981
982(define_insn ""
983 [(set (match_operand:SI 0 "general_operand" "=g,r")
984 (match_operand:SI 1 "general_operand" "ri,m"))]
985 "((!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
986 || (GET_CODE (operands[1]) != MEM))
987 && !flag_pic"
988 "*
989{
990 rtx link;
991
992 /* Use of xor was disabled for AMD K6 as recommended by the Optimization
993 Manual. My test shows, that this generally hurts the performance, because
994 mov is longer and takes longer to decode and decoding is the main
995 bottleneck of K6 when executing GCC code. */
996
915 if (operands[1] == const0_rtx && REG_P (operands[0]))
916 return AS2 (xor%L0,%0,%0);
917
918 if (operands[1] == const1_rtx
997 if (operands[1] == const0_rtx && REG_P (operands[0]))
998 return AS2 (xor%L0,%0,%0);
999
1000 if (operands[1] == const1_rtx
1001 /* PPRO and K6 prefer mov to inc to reduce dependencies. */
1002 && (optimize_size || (int)ix86_cpu < (int)PROCESSOR_PENTIUMPRO)
919 && (link = find_reg_note (insn, REG_WAS_0, 0))
920 /* Make sure the insn that stored the 0 is still present. */
921 && ! INSN_DELETED_P (XEXP (link, 0))
922 && GET_CODE (XEXP (link, 0)) != NOTE
923 /* Make sure cross jumping didn't happen here. */
924 && no_labels_between_p (XEXP (link, 0), insn)
925 /* Make sure the reg hasn't been clobbered. */
926 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
927 /* Fastest way to change a 0 to a 1. */
928 return AS1 (inc%L0,%0);
929
930 return AS2 (mov%L0,%1,%0);
1003 && (link = find_reg_note (insn, REG_WAS_0, 0))
1004 /* Make sure the insn that stored the 0 is still present. */
1005 && ! INSN_DELETED_P (XEXP (link, 0))
1006 && GET_CODE (XEXP (link, 0)) != NOTE
1007 /* Make sure cross jumping didn't happen here. */
1008 && no_labels_between_p (XEXP (link, 0), insn)
1009 /* Make sure the reg hasn't been clobbered. */
1010 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
1011 /* Fastest way to change a 0 to a 1. */
1012 return AS1 (inc%L0,%0);
1013
1014 return AS2 (mov%L0,%1,%0);
931}")
1015}"
1016 [(set_attr "type" "integer,memory")
1017 (set_attr "memory" "*,load")])
932
933(define_insn ""
934 [(set (match_operand:HI 0 "push_operand" "=<")
935 (match_operand:HI 1 "nonmemory_operand" "ri"))]
936 ""
1018
1019(define_insn ""
1020 [(set (match_operand:HI 0 "push_operand" "=<")
1021 (match_operand:HI 1 "nonmemory_operand" "ri"))]
1022 ""
937 "* return AS1 (push%W0,%1);")
1023 "* return AS1 (push%W0,%1);"
1024 [(set_attr "type" "memory")
1025 (set_attr "memory" "store")])
938
939(define_insn ""
940 [(set (match_operand:HI 0 "push_operand" "=<")
941 (match_operand:HI 1 "memory_operand" "m"))]
942 "TARGET_PUSH_MEMORY"
1026
1027(define_insn ""
1028 [(set (match_operand:HI 0 "push_operand" "=<")
1029 (match_operand:HI 1 "memory_operand" "m"))]
1030 "TARGET_PUSH_MEMORY"
943 "* return AS1 (push%W0,%1);")
1031 "* return AS1 (push%W0,%1);"
1032 [(set_attr "type" "memory")
1033 (set_attr "memory" "load")])
944
945;; On i486, an incl and movl are both faster than incw and movw.
946
947(define_expand "movhi"
948 [(set (match_operand:HI 0 "general_operand" "")
949 (match_operand:HI 1 "general_operand" ""))]
950 ""
951 "
952{
953 /* Don't generate memory->memory moves, go through a register */
954 if (TARGET_MOVE
1034
1035;; On i486, an incl and movl are both faster than incw and movw.
1036
1037(define_expand "movhi"
1038 [(set (match_operand:HI 0 "general_operand" "")
1039 (match_operand:HI 1 "general_operand" ""))]
1040 ""
1041 "
1042{
1043 /* Don't generate memory->memory moves, go through a register */
1044 if (TARGET_MOVE
955 && (reload_in_progress | reload_completed) == 0
1045 && no_new_pseudos == 0
956 && GET_CODE (operands[0]) == MEM
957 && GET_CODE (operands[1]) == MEM)
958 {
959 operands[1] = force_reg (HImode, operands[1]);
960 }
961}")
962
963(define_insn ""
964 [(set (match_operand:HI 0 "general_operand" "=g,r")
965 (match_operand:HI 1 "general_operand" "ri,m"))]
966 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
967 "*
968{
969 rtx link;
970 if (REG_P (operands[0]) && operands[1] == const0_rtx)
971 return AS2 (xor%L0,%k0,%k0);
972
973 if (REG_P (operands[0]) && operands[1] == const1_rtx
1046 && GET_CODE (operands[0]) == MEM
1047 && GET_CODE (operands[1]) == MEM)
1048 {
1049 operands[1] = force_reg (HImode, operands[1]);
1050 }
1051}")
1052
1053(define_insn ""
1054 [(set (match_operand:HI 0 "general_operand" "=g,r")
1055 (match_operand:HI 1 "general_operand" "ri,m"))]
1056 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
1057 "*
1058{
1059 rtx link;
1060 if (REG_P (operands[0]) && operands[1] == const0_rtx)
1061 return AS2 (xor%L0,%k0,%k0);
1062
1063 if (REG_P (operands[0]) && operands[1] == const1_rtx
1064 /* PPRO and K6 prefer mov to inc to reduce dependencies. */
1065 && (optimize_size || (int)ix86_cpu < (int)PROCESSOR_PENTIUMPRO)
974 && (link = find_reg_note (insn, REG_WAS_0, 0))
975 /* Make sure the insn that stored the 0 is still present. */
976 && ! INSN_DELETED_P (XEXP (link, 0))
977 && GET_CODE (XEXP (link, 0)) != NOTE
978 /* Make sure cross jumping didn't happen here. */
979 && no_labels_between_p (XEXP (link, 0), insn)
980 /* Make sure the reg hasn't been clobbered. */
981 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
982 /* Fastest way to change a 0 to a 1. */
983 return AS1 (inc%L0,%k0);
984
985 if (REG_P (operands[0]))
986 {
987 if (i386_aligned_p (operands[1]))
988 {
989 operands[1] = i386_sext16_if_const (operands[1]);
990 return AS2 (mov%L0,%k1,%k0);
991 }
1066 && (link = find_reg_note (insn, REG_WAS_0, 0))
1067 /* Make sure the insn that stored the 0 is still present. */
1068 && ! INSN_DELETED_P (XEXP (link, 0))
1069 && GET_CODE (XEXP (link, 0)) != NOTE
1070 /* Make sure cross jumping didn't happen here. */
1071 && no_labels_between_p (XEXP (link, 0), insn)
1072 /* Make sure the reg hasn't been clobbered. */
1073 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
1074 /* Fastest way to change a 0 to a 1. */
1075 return AS1 (inc%L0,%k0);
1076
1077 if (REG_P (operands[0]))
1078 {
1079 if (i386_aligned_p (operands[1]))
1080 {
1081 operands[1] = i386_sext16_if_const (operands[1]);
1082 return AS2 (mov%L0,%k1,%k0);
1083 }
992 if (TARGET_PENTIUMPRO)
1084 if (! TARGET_ZERO_EXTEND_WITH_AND)
993 {
994 /* movzwl is faster than movw on the Pentium Pro,
995 * although not as fast as an aligned movl. */
996#ifdef INTEL_SYNTAX
997 return AS2 (movzx,%1,%k0);
998#else
999 return AS2 (movz%W0%L0,%1,%k0);
1000#endif
1001 }
1002 }
1003
1004 return AS2 (mov%W0,%1,%0);
1085 {
1086 /* movzwl is faster than movw on the Pentium Pro,
1087 * although not as fast as an aligned movl. */
1088#ifdef INTEL_SYNTAX
1089 return AS2 (movzx,%1,%k0);
1090#else
1091 return AS2 (movz%W0%L0,%1,%k0);
1092#endif
1093 }
1094 }
1095
1096 return AS2 (mov%W0,%1,%0);
1005}")
1097}"
1098 [(set_attr "type" "integer,memory")
1099 (set_attr "memory" "*,load")])
1006
1007(define_expand "movstricthi"
1008 [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
1009 (match_operand:HI 1 "general_operand" ""))]
1010 ""
1011 "
1012{
1013 /* Don't generate memory->memory moves, go through a register */
1014 if (TARGET_MOVE
1100
1101(define_expand "movstricthi"
1102 [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
1103 (match_operand:HI 1 "general_operand" ""))]
1104 ""
1105 "
1106{
1107 /* Don't generate memory->memory moves, go through a register */
1108 if (TARGET_MOVE
1015 && (reload_in_progress | reload_completed) == 0
1109 && no_new_pseudos == 0
1016 && GET_CODE (operands[0]) == MEM
1017 && GET_CODE (operands[1]) == MEM)
1018 {
1019 operands[1] = force_reg (HImode, operands[1]);
1020 }
1021}")
1022
1023(define_insn ""
1024 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+g,r"))
1025 (match_operand:HI 1 "general_operand" "ri,m"))]
1026 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
1027 "*
1028{
1029 rtx link;
1110 && GET_CODE (operands[0]) == MEM
1111 && GET_CODE (operands[1]) == MEM)
1112 {
1113 operands[1] = force_reg (HImode, operands[1]);
1114 }
1115}")
1116
1117(define_insn ""
1118 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+g,r"))
1119 (match_operand:HI 1 "general_operand" "ri,m"))]
1120 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
1121 "*
1122{
1123 rtx link;
1124
1125 /* Use of xor was disabled for AMD K6 as recommended by the Optimization
1126 Manual. My test shows, that this generally hurts the performance, because
1127 mov is longer and takes longer to decode and decoding is the main
1128 bottleneck of K6 when executing GCC code. */
1129
1030 if (operands[1] == const0_rtx && REG_P (operands[0]))
1031 return AS2 (xor%W0,%0,%0);
1032
1033 if (operands[1] == const1_rtx
1130 if (operands[1] == const0_rtx && REG_P (operands[0]))
1131 return AS2 (xor%W0,%0,%0);
1132
1133 if (operands[1] == const1_rtx
1134 /* PPRO and K6 prefer mov to inc to reduce dependencies. */
1135 && (optimize_size || (int)ix86_cpu < (int)PROCESSOR_PENTIUMPRO)
1034 && (link = find_reg_note (insn, REG_WAS_0, 0))
1035 /* Make sure the insn that stored the 0 is still present. */
1036 && ! INSN_DELETED_P (XEXP (link, 0))
1037 && GET_CODE (XEXP (link, 0)) != NOTE
1038 /* Make sure cross jumping didn't happen here. */
1039 && no_labels_between_p (XEXP (link, 0), insn)
1040 /* Make sure the reg hasn't been clobbered. */
1041 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
1042 /* Fastest way to change a 0 to a 1. */
1043 return AS1 (inc%W0,%0);
1044
1045 return AS2 (mov%W0,%1,%0);
1136 && (link = find_reg_note (insn, REG_WAS_0, 0))
1137 /* Make sure the insn that stored the 0 is still present. */
1138 && ! INSN_DELETED_P (XEXP (link, 0))
1139 && GET_CODE (XEXP (link, 0)) != NOTE
1140 /* Make sure cross jumping didn't happen here. */
1141 && no_labels_between_p (XEXP (link, 0), insn)
1142 /* Make sure the reg hasn't been clobbered. */
1143 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
1144 /* Fastest way to change a 0 to a 1. */
1145 return AS1 (inc%W0,%0);
1146
1147 return AS2 (mov%W0,%1,%0);
1046}")
1148}"
1149 [(set_attr "type" "integer,memory")])
1047
1048;; emit_push_insn when it calls move_by_pieces
1049;; requires an insn to "push a byte".
1050;; But actually we use pushw, which has the effect of rounding
1051;; the amount pushed up to a halfword.
1052(define_insn ""
1053 [(set (match_operand:QI 0 "push_operand" "=<")
1054 (match_operand:QI 1 "const_int_operand" "n"))]

--- 18 unchanged lines hidden (view full) ---

1073(define_expand "movqi"
1074 [(set (match_operand:QI 0 "general_operand" "")
1075 (match_operand:QI 1 "general_operand" ""))]
1076 ""
1077 "
1078{
1079 /* Don't generate memory->memory moves, go through a register */
1080 if (TARGET_MOVE
1150
1151;; emit_push_insn when it calls move_by_pieces
1152;; requires an insn to "push a byte".
1153;; But actually we use pushw, which has the effect of rounding
1154;; the amount pushed up to a halfword.
1155(define_insn ""
1156 [(set (match_operand:QI 0 "push_operand" "=<")
1157 (match_operand:QI 1 "const_int_operand" "n"))]

--- 18 unchanged lines hidden (view full) ---

1176(define_expand "movqi"
1177 [(set (match_operand:QI 0 "general_operand" "")
1178 (match_operand:QI 1 "general_operand" ""))]
1179 ""
1180 "
1181{
1182 /* Don't generate memory->memory moves, go through a register */
1183 if (TARGET_MOVE
1081 && (reload_in_progress | reload_completed) == 0
1184 && no_new_pseudos == 0
1082 && GET_CODE (operands[0]) == MEM
1083 && GET_CODE (operands[1]) == MEM)
1084 {
1085 operands[1] = force_reg (QImode, operands[1]);
1086 }
1087}")
1088
1089(define_insn ""
1090 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,*r,qm")
1091 (match_operand:QI 1 "general_operand" "*g,*rn,qn"))]
1092 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
1093 "*
1094{
1095 rtx link;
1185 && GET_CODE (operands[0]) == MEM
1186 && GET_CODE (operands[1]) == MEM)
1187 {
1188 operands[1] = force_reg (QImode, operands[1]);
1189 }
1190}")
1191
1192(define_insn ""
1193 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,*r,qm")
1194 (match_operand:QI 1 "general_operand" "*g,*rn,qn"))]
1195 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
1196 "*
1197{
1198 rtx link;
1096 if (operands[1] == const0_rtx && REG_P (operands[0]))
1097 return AS2 (xor%L0,%k0,%k0);
1098
1199
1200 /* movb $0,reg8 is 2 bytes, the same as xorl reg8,reg8.
1201 It is at least as fast as xor on any processor except a Pentium. */
1202
1099 if (operands[1] == const1_rtx
1203 if (operands[1] == const1_rtx
1204 && TARGET_PENTIUM
1100 && (link = find_reg_note (insn, REG_WAS_0, 0))
1101 /* Make sure the insn that stored the 0 is still present. */
1102 && ! INSN_DELETED_P (XEXP (link, 0))
1103 && GET_CODE (XEXP (link, 0)) != NOTE
1104 /* Make sure cross jumping didn't happen here. */
1105 && no_labels_between_p (XEXP (link, 0), insn)
1106 /* Make sure the reg hasn't been clobbered. */
1107 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))

--- 25 unchanged lines hidden (view full) ---

1133(define_expand "movstrictqi"
1134 [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
1135 (match_operand:QI 1 "general_operand" ""))]
1136 ""
1137 "
1138{
1139 /* Don't generate memory->memory moves, go through a register */
1140 if (TARGET_MOVE
1205 && (link = find_reg_note (insn, REG_WAS_0, 0))
1206 /* Make sure the insn that stored the 0 is still present. */
1207 && ! INSN_DELETED_P (XEXP (link, 0))
1208 && GET_CODE (XEXP (link, 0)) != NOTE
1209 /* Make sure cross jumping didn't happen here. */
1210 && no_labels_between_p (XEXP (link, 0), insn)
1211 /* Make sure the reg hasn't been clobbered. */
1212 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))

--- 25 unchanged lines hidden (view full) ---

1238(define_expand "movstrictqi"
1239 [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
1240 (match_operand:QI 1 "general_operand" ""))]
1241 ""
1242 "
1243{
1244 /* Don't generate memory->memory moves, go through a register */
1245 if (TARGET_MOVE
1141 && (reload_in_progress | reload_completed) == 0
1246 && no_new_pseudos == 0
1142 && GET_CODE (operands[0]) == MEM
1143 && GET_CODE (operands[1]) == MEM)
1144 {
1145 operands[1] = force_reg (QImode, operands[1]);
1146 }
1147}")
1148
1149(define_insn ""
1150 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1151 (match_operand:QI 1 "general_operand" "*qn,m"))]
1152 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
1153 "*
1154{
1155 rtx link;
1247 && GET_CODE (operands[0]) == MEM
1248 && GET_CODE (operands[1]) == MEM)
1249 {
1250 operands[1] = force_reg (QImode, operands[1]);
1251 }
1252}")
1253
1254(define_insn ""
1255 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1256 (match_operand:QI 1 "general_operand" "*qn,m"))]
1257 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
1258 "*
1259{
1260 rtx link;
1156 if (operands[1] == const0_rtx && REG_P (operands[0]))
1157 return AS2 (xor%B0,%0,%0);
1158
1261
1262 /* movb $0,reg8 is 2 bytes, the same as xorl reg8,reg8. */
1263
1159 if (operands[1] == const1_rtx
1264 if (operands[1] == const1_rtx
1265 && TARGET_PENTIUM
1160 && ! NON_QI_REG_P (operands[0])
1161 && (link = find_reg_note (insn, REG_WAS_0, 0))
1162 /* Make sure the insn that stored the 0 is still present. */
1163 && ! INSN_DELETED_P (XEXP (link, 0))
1164 && GET_CODE (XEXP (link, 0)) != NOTE
1165 /* Make sure cross jumping didn't happen here. */
1166 && no_labels_between_p (XEXP (link, 0), insn)
1167 /* Make sure the reg hasn't been clobbered. */

--- 9 unchanged lines hidden (view full) ---

1177 }
1178
1179 return AS2 (mov%B0,%1,%0);
1180}")
1181
1182(define_insn "movsf_push"
1183 [(set (match_operand:SF 0 "push_operand" "=<,<")
1184 (match_operand:SF 1 "general_operand" "*rfF,m"))]
1266 && ! NON_QI_REG_P (operands[0])
1267 && (link = find_reg_note (insn, REG_WAS_0, 0))
1268 /* Make sure the insn that stored the 0 is still present. */
1269 && ! INSN_DELETED_P (XEXP (link, 0))
1270 && GET_CODE (XEXP (link, 0)) != NOTE
1271 /* Make sure cross jumping didn't happen here. */
1272 && no_labels_between_p (XEXP (link, 0), insn)
1273 /* Make sure the reg hasn't been clobbered. */

--- 9 unchanged lines hidden (view full) ---

1283 }
1284
1285 return AS2 (mov%B0,%1,%0);
1286}")
1287
1288(define_insn "movsf_push"
1289 [(set (match_operand:SF 0 "push_operand" "=<,<")
1290 (match_operand:SF 1 "general_operand" "*rfF,m"))]
1185 "GET_CODE (operands[1]) != MEM || reload_in_progress || reload_completed"
1291 "TARGET_PUSH_MEMORY || GET_CODE (operands[1]) != MEM
1292 || reload_in_progress || reload_completed"
1186 "*
1187{
1188 if (STACK_REG_P (operands[1]))
1189 {
1190 rtx xops[3];
1191
1192 if (! STACK_TOP_P (operands[1]))
1193 abort ();

--- 10 unchanged lines hidden (view full) ---

1204 output_asm_insn (AS1 (fst%S0,%0), xops);
1205
1206 RET;
1207 }
1208
1209 return AS1 (push%L0,%1);
1210}")
1211
1293 "*
1294{
1295 if (STACK_REG_P (operands[1]))
1296 {
1297 rtx xops[3];
1298
1299 if (! STACK_TOP_P (operands[1]))
1300 abort ();

--- 10 unchanged lines hidden (view full) ---

1311 output_asm_insn (AS1 (fst%S0,%0), xops);
1312
1313 RET;
1314 }
1315
1316 return AS1 (push%L0,%1);
1317}")
1318
1212(define_insn "movsf_push_memory"
1213 [(set (match_operand:SF 0 "push_operand" "=<")
1214 (match_operand:SF 1 "memory_operand" "m"))]
1215 "TARGET_PUSH_MEMORY"
1216 "* return AS1 (push%L0,%1);")
1319(define_split
1320 [(set (match_operand:SF 0 "push_operand" "")
1321 (match_operand:SF 1 "general_operand" ""))]
1322 "reload_completed && STACK_REG_P (operands[1])"
1323 [(set (reg:SI 7)
1324 (minus:SI (reg:SI 7) (const_int 4)))
1325 (set (mem:SF (reg:SI 7))
1326 (match_dup 1))]
1327 "")
1217
1218(define_expand "movsf"
1219 [(set (match_operand:SF 0 "general_operand" "")
1220 (match_operand:SF 1 "general_operand" ""))]
1221 ""
1222 "
1223{
1224 /* Don't generate memory->memory moves, go through a register */
1225 if (TARGET_MOVE
1328
1329(define_expand "movsf"
1330 [(set (match_operand:SF 0 "general_operand" "")
1331 (match_operand:SF 1 "general_operand" ""))]
1332 ""
1333 "
1334{
1335 /* Don't generate memory->memory moves, go through a register */
1336 if (TARGET_MOVE
1226 && (reload_in_progress | reload_completed) == 0
1337 && no_new_pseudos == 0
1227 && GET_CODE (operands[0]) == MEM
1228 && GET_CODE (operands[1]) == MEM)
1229 {
1230 operands[1] = force_reg (SFmode, operands[1]);
1231 }
1232
1233 /* If we are loading a floating point constant that isn't 0 or 1
1338 && GET_CODE (operands[0]) == MEM
1339 && GET_CODE (operands[1]) == MEM)
1340 {
1341 operands[1] = force_reg (SFmode, operands[1]);
1342 }
1343
1344 /* If we are loading a floating point constant that isn't 0 or 1
1234 into a register, indicate we need the pic register loaded. This could
1235 be optimized into stores of constants if the target eventually moves
1236 to memory, but better safe than sorry. */
1345 into a register, force the value to memory now, since we'll
1346 get better code out the back end. */
1237 else if ((reload_in_progress | reload_completed) == 0
1347 else if ((reload_in_progress | reload_completed) == 0
1238 && GET_CODE (operands[0]) != MEM
1239 && GET_CODE (operands[1]) == CONST_DOUBLE
1240 && !standard_80387_constant_p (operands[1]))
1348 && GET_CODE (operands[0]) != MEM
1349 && GET_CODE (operands[1]) == CONST_DOUBLE
1350 && !standard_80387_constant_p (operands[1]))
1241 {
1351 {
1242 rtx insn, note, fp_const;
1243
1244 fp_const = force_const_mem (SFmode, operands[1]);
1245 if (flag_pic)
1246 current_function_uses_pic_offset_table = 1;
1247
1248 insn = emit_insn (gen_rtx_SET (SFmode, operands[0], fp_const));
1249 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
1250
1251 if (note)
1252 XEXP (note, 0) = operands[1];
1253 else
1254 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1], REG_NOTES (insn));
1352 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
1255 }
1256}")
1257
1258;; For the purposes of regclass, prefer FLOAT_REGS.
1259(define_insn ""
1353 }
1354}")
1355
1356;; For the purposes of regclass, prefer FLOAT_REGS.
1357(define_insn ""
1260 [(set (match_operand:SF 0 "nonimmediate_operand" "=*rfm,*rf,f,!*rm")
1261 (match_operand:SF 1 "general_operand" "*rf,*rfm,fG,fF"))]
1358 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,m,!*r,!m")
1359 (match_operand:SF 1 "general_operand" "fmG,f,*rmF,*rF"))]
1262 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
1263 "*
1264{
1265 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
1266
1267 /* First handle a `pop' insn or a `fld %st(0)' */
1268
1269 if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1]))
1270 {
1271 if (stack_top_dies)
1272 return AS1 (fstp,%y0);
1273 else
1274 return AS1 (fld,%y0);
1275 }
1276
1360 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
1361 "*
1362{
1363 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
1364
1365 /* First handle a `pop' insn or a `fld %st(0)' */
1366
1367 if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1]))
1368 {
1369 if (stack_top_dies)
1370 return AS1 (fstp,%y0);
1371 else
1372 return AS1 (fld,%y0);
1373 }
1374
1277 /* Handle a transfer between the 387 and a 386 register */
1278
1279 if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1]))
1280 {
1281 output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
1282 RET;
1283 }
1284
1285 if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0]))
1286 {
1287 output_to_reg (operands[0], stack_top_dies, 0);
1288 RET;
1289 }
1290
1291 /* Handle other kinds of writes from the 387 */
1292
1293 if (STACK_TOP_P (operands[1]))
1294 {
1295 if (stack_top_dies)
1296 return AS1 (fstp%z0,%y0);
1297 else
1298 return AS1 (fst%z0,%y0);

--- 23 unchanged lines hidden (view full) ---

1322 "*
1323{
1324 if (STACK_TOP_P (operands[0]))
1325 return AS1 (fxch,%1);
1326 else
1327 return AS1 (fxch,%0);
1328}")
1329
1375 /* Handle other kinds of writes from the 387 */
1376
1377 if (STACK_TOP_P (operands[1]))
1378 {
1379 if (stack_top_dies)
1380 return AS1 (fstp%z0,%y0);
1381 else
1382 return AS1 (fst%z0,%y0);

--- 23 unchanged lines hidden (view full) ---

1406 "*
1407{
1408 if (STACK_TOP_P (operands[0]))
1409 return AS1 (fxch,%1);
1410 else
1411 return AS1 (fxch,%0);
1412}")
1413
1414
1330(define_insn "movdf_push"
1331 [(set (match_operand:DF 0 "push_operand" "=<,<")
1332 (match_operand:DF 1 "general_operand" "*rfF,o"))]
1415(define_insn "movdf_push"
1416 [(set (match_operand:DF 0 "push_operand" "=<,<")
1417 (match_operand:DF 1 "general_operand" "*rfF,o"))]
1333 "GET_CODE (operands[1]) != MEM || reload_in_progress || reload_completed"
1418 "TARGET_PUSH_MEMORY || GET_CODE (operands[1]) != MEM
1419 || reload_in_progress || reload_completed"
1334 "*
1335{
1336 if (STACK_REG_P (operands[1]))
1337 {
1338 rtx xops[3];
1339
1340 xops[0] = AT_SP (DFmode);
1341 xops[1] = GEN_INT (8);

--- 10 unchanged lines hidden (view full) ---

1352 }
1353
1354 if (which_alternative == 1)
1355 return output_move_pushmem (operands, insn, GET_MODE_SIZE (DFmode), 0, 0);
1356
1357 return output_move_double (operands);
1358}")
1359
1420 "*
1421{
1422 if (STACK_REG_P (operands[1]))
1423 {
1424 rtx xops[3];
1425
1426 xops[0] = AT_SP (DFmode);
1427 xops[1] = GEN_INT (8);

--- 10 unchanged lines hidden (view full) ---

1438 }
1439
1440 if (which_alternative == 1)
1441 return output_move_pushmem (operands, insn, GET_MODE_SIZE (DFmode), 0, 0);
1442
1443 return output_move_double (operands);
1444}")
1445
1360(define_insn "movdf_push_memory"
1361 [(set (match_operand:DF 0 "push_operand" "=<")
1362 (match_operand:DF 1 "memory_operand" "o"))]
1363 "TARGET_PUSH_MEMORY"
1364 "* return output_move_pushmem (operands, insn, GET_MODE_SIZE (DFmode),0,0);")
1446(define_split
1447 [(set (match_operand:DF 0 "push_operand" "")
1448 (match_operand:DF 1 "register_operand" ""))]
1449 "reload_completed && STACK_REG_P (operands[1])"
1450 [(set (reg:SI 7)
1451 (minus:SI (reg:SI 7) (const_int 8)))
1452 (set (mem:DF (reg:SI 7))
1453 (match_dup 1))]
1454 "")
1365
1366(define_expand "movdf"
1367 [(set (match_operand:DF 0 "general_operand" "")
1368 (match_operand:DF 1 "general_operand" ""))]
1369 ""
1370 "
1371{
1372 /* Don't generate memory->memory moves, go through a register */
1373 if (TARGET_MOVE
1455
1456(define_expand "movdf"
1457 [(set (match_operand:DF 0 "general_operand" "")
1458 (match_operand:DF 1 "general_operand" ""))]
1459 ""
1460 "
1461{
1462 /* Don't generate memory->memory moves, go through a register */
1463 if (TARGET_MOVE
1374 && (reload_in_progress | reload_completed) == 0
1464 && no_new_pseudos == 0
1375 && GET_CODE (operands[0]) == MEM
1376 && GET_CODE (operands[1]) == MEM)
1377 {
1378 operands[1] = force_reg (DFmode, operands[1]);
1379 }
1380
1381 /* If we are loading a floating point constant that isn't 0 or 1 into a
1382 register, indicate we need the pic register loaded. This could be
1383 optimized into stores of constants if the target eventually moves to
1384 memory, but better safe than sorry. */
1385 else if ((reload_in_progress | reload_completed) == 0
1465 && GET_CODE (operands[0]) == MEM
1466 && GET_CODE (operands[1]) == MEM)
1467 {
1468 operands[1] = force_reg (DFmode, operands[1]);
1469 }
1470
1471 /* If we are loading a floating point constant that isn't 0 or 1 into a
1472 register, indicate we need the pic register loaded. This could be
1473 optimized into stores of constants if the target eventually moves to
1474 memory, but better safe than sorry. */
1475 else if ((reload_in_progress | reload_completed) == 0
1386 && GET_CODE (operands[0]) != MEM
1387 && GET_CODE (operands[1]) == CONST_DOUBLE
1388 && !standard_80387_constant_p (operands[1]))
1476 && GET_CODE (operands[0]) != MEM
1477 && GET_CODE (operands[1]) == CONST_DOUBLE
1478 && !standard_80387_constant_p (operands[1]))
1389 {
1479 {
1390 rtx insn, note, fp_const;
1391
1392 fp_const = force_const_mem (DFmode, operands[1]);
1393 if (flag_pic)
1394 current_function_uses_pic_offset_table = 1;
1395
1396 insn = emit_insn (gen_rtx_SET (DFmode, operands[0], fp_const));
1397 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
1398
1399 if (note)
1400 XEXP (note, 0) = operands[1];
1401 else
1402 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1], REG_NOTES (insn));
1480 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
1403 }
1404}")
1405
1406;; For the purposes of regclass, prefer FLOAT_REGS.
1407(define_insn ""
1481 }
1482}")
1483
1484;; For the purposes of regclass, prefer FLOAT_REGS.
1485(define_insn ""
1408 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,fm,!*rf,!*rm")
1409 (match_operand:DF 1 "general_operand" "fmG,f,*rfm,*rfF"))]
1486 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m,!*r,!o")
1487 (match_operand:DF 1 "general_operand" "fmG,f,*roF,*rF"))]
1410 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
1411 || (GET_CODE (operands[1]) != MEM)"
1412 "*
1413{
1414 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
1415
1416 /* First handle a `pop' insn or a `fld %st(0)' */
1417
1418 if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1]))
1419 {
1420 if (stack_top_dies)
1421 return AS1 (fstp,%y0);
1422 else
1423 return AS1 (fld,%y0);
1424 }
1425
1488 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
1489 || (GET_CODE (operands[1]) != MEM)"
1490 "*
1491{
1492 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
1493
1494 /* First handle a `pop' insn or a `fld %st(0)' */
1495
1496 if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1]))
1497 {
1498 if (stack_top_dies)
1499 return AS1 (fstp,%y0);
1500 else
1501 return AS1 (fld,%y0);
1502 }
1503
1426 /* Handle a transfer between the 387 and a 386 register */
1427
1428 if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1]))
1429 {
1430 output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
1431 RET;
1432 }
1433
1434 if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0]))
1435 {
1436 output_to_reg (operands[0], stack_top_dies, 0);
1437 RET;
1438 }
1439
1440 /* Handle other kinds of writes from the 387 */
1441
1442 if (STACK_TOP_P (operands[1]))
1443 {
1444 if (stack_top_dies)
1445 return AS1 (fstp%z0,%y0);
1446 else
1447 return AS1 (fst%z0,%y0);

--- 27 unchanged lines hidden (view full) ---

1475 return AS1 (fxch,%1);
1476 else
1477 return AS1 (fxch,%0);
1478}")
1479
1480(define_insn "movxf_push"
1481 [(set (match_operand:XF 0 "push_operand" "=<,<")
1482 (match_operand:XF 1 "general_operand" "*rfF,o"))]
1504 /* Handle other kinds of writes from the 387 */
1505
1506 if (STACK_TOP_P (operands[1]))
1507 {
1508 if (stack_top_dies)
1509 return AS1 (fstp%z0,%y0);
1510 else
1511 return AS1 (fst%z0,%y0);

--- 27 unchanged lines hidden (view full) ---

1539 return AS1 (fxch,%1);
1540 else
1541 return AS1 (fxch,%0);
1542}")
1543
1544(define_insn "movxf_push"
1545 [(set (match_operand:XF 0 "push_operand" "=<,<")
1546 (match_operand:XF 1 "general_operand" "*rfF,o"))]
1483 "GET_CODE (operands[1]) != MEM || reload_in_progress || reload_completed"
1547 "TARGET_PUSH_MEMORY || GET_CODE (operands[1]) != MEM
1548 || reload_in_progress || reload_completed"
1484 "*
1485{
1486 if (STACK_REG_P (operands[1]))
1487 {
1488 rtx xops[3];
1489
1490 xops[0] = AT_SP (XFmode);
1491 xops[1] = GEN_INT (12);

--- 9 unchanged lines hidden (view full) ---

1501 }
1502
1503 if (which_alternative == 1)
1504 return output_move_pushmem (operands, insn, GET_MODE_SIZE (XFmode), 0, 0);
1505
1506 return output_move_double (operands);
1507 }")
1508
1549 "*
1550{
1551 if (STACK_REG_P (operands[1]))
1552 {
1553 rtx xops[3];
1554
1555 xops[0] = AT_SP (XFmode);
1556 xops[1] = GEN_INT (12);

--- 9 unchanged lines hidden (view full) ---

1566 }
1567
1568 if (which_alternative == 1)
1569 return output_move_pushmem (operands, insn, GET_MODE_SIZE (XFmode), 0, 0);
1570
1571 return output_move_double (operands);
1572 }")
1573
1509(define_insn "movxf_push_memory"
1510 [(set (match_operand:XF 0 "push_operand" "=<")
1511 (match_operand:XF 1 "memory_operand" "o"))]
1512 "TARGET_PUSH_MEMORY"
1513 "* return output_move_pushmem (operands, insn, GET_MODE_SIZE (XFmode),0,0);")
1574(define_split
1575 [(set (match_operand:XF 0 "push_operand" "")
1576 (match_operand:XF 1 "register_operand" ""))]
1577 "reload_completed && STACK_REG_P (operands[1])"
1578 [(set (reg:SI 7)
1579 (minus:SI (reg:SI 7) (const_int 12)))
1580 (set (mem:XF (reg:SI 7))
1581 (match_dup 1))]
1582 "")
1514
1515(define_expand "movxf"
1516 [(set (match_operand:XF 0 "general_operand" "")
1517 (match_operand:XF 1 "general_operand" ""))]
1518 ""
1519 "
1520{
1521 /* Don't generate memory->memory moves, go through a register */
1522 if (TARGET_MOVE
1583
1584(define_expand "movxf"
1585 [(set (match_operand:XF 0 "general_operand" "")
1586 (match_operand:XF 1 "general_operand" ""))]
1587 ""
1588 "
1589{
1590 /* Don't generate memory->memory moves, go through a register */
1591 if (TARGET_MOVE
1523 && (reload_in_progress | reload_completed) == 0
1592 && no_new_pseudos == 0
1524 && GET_CODE (operands[0]) == MEM
1525 && GET_CODE (operands[1]) == MEM)
1526 {
1527 operands[1] = force_reg (XFmode, operands[1]);
1528 }
1529
1530 /* If we are loading a floating point constant that isn't 0 or 1
1531 into a register, indicate we need the pic register loaded. This could
1532 be optimized into stores of constants if the target eventually moves
1533 to memory, but better safe than sorry. */
1534 else if ((reload_in_progress | reload_completed) == 0
1593 && GET_CODE (operands[0]) == MEM
1594 && GET_CODE (operands[1]) == MEM)
1595 {
1596 operands[1] = force_reg (XFmode, operands[1]);
1597 }
1598
1599 /* If we are loading a floating point constant that isn't 0 or 1
1600 into a register, indicate we need the pic register loaded. This could
1601 be optimized into stores of constants if the target eventually moves
1602 to memory, but better safe than sorry. */
1603 else if ((reload_in_progress | reload_completed) == 0
1535 && GET_CODE (operands[0]) != MEM
1536 && GET_CODE (operands[1]) == CONST_DOUBLE
1537 && !standard_80387_constant_p (operands[1]))
1604 && GET_CODE (operands[0]) != MEM
1605 && GET_CODE (operands[1]) == CONST_DOUBLE
1606 && !standard_80387_constant_p (operands[1]))
1538 {
1607 {
1539 rtx insn, note, fp_const;
1540
1541 fp_const = force_const_mem (XFmode, operands[1]);
1542 if (flag_pic)
1543 current_function_uses_pic_offset_table = 1;
1544
1545 insn = emit_insn (gen_rtx_SET (XFmode, operands[0], fp_const));
1546 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
1547
1548 if (note)
1549 XEXP (note, 0) = operands[1];
1550 else
1551 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1], REG_NOTES (insn));
1608 operands[1] = validize_mem (force_const_mem (XFmode, operands[1]));
1552 }
1553}")
1554
1555
1556(define_insn ""
1609 }
1610}")
1611
1612
1613(define_insn ""
1557 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,fm,!*rf,!*rm")
1558 (match_operand:XF 1 "general_operand" "fmG,f,*rfm,*rfF"))]
1614 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,!*r,!o")
1615 (match_operand:XF 1 "general_operand" "fmG,f,*roF,*rF"))]
1559 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
1560 || (GET_CODE (operands[1]) != MEM)"
1561 "*
1562{
1563 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
1564
1565 /* First handle a `pop' insn or a `fld %st(0)' */
1566
1567 if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1]))
1568 {
1569 if (stack_top_dies)
1570 return AS1 (fstp,%y0);
1571 else
1572 return AS1 (fld,%y0);
1573 }
1574
1616 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
1617 || (GET_CODE (operands[1]) != MEM)"
1618 "*
1619{
1620 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
1621
1622 /* First handle a `pop' insn or a `fld %st(0)' */
1623
1624 if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1]))
1625 {
1626 if (stack_top_dies)
1627 return AS1 (fstp,%y0);
1628 else
1629 return AS1 (fld,%y0);
1630 }
1631
1575 /* Handle a transfer between the 387 and a 386 register */
1576
1577 if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1]))
1578 {
1579 output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
1580 RET;
1581 }
1582
1583 if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0]))
1584 {
1585 output_to_reg (operands[0], stack_top_dies, 0);
1586 RET;
1587 }
1588
1589 /* Handle other kinds of writes from the 387 */
1590
1591 if (STACK_TOP_P (operands[1]))
1592 {
1593 output_asm_insn (AS1 (fstp%z0,%y0), operands);
1594 if (! stack_top_dies)
1595 return AS1 (fld%z0,%y0);
1596

--- 42 unchanged lines hidden (view full) ---

1639(define_expand "movdi"
1640 [(set (match_operand:DI 0 "general_operand" "")
1641 (match_operand:DI 1 "general_operand" ""))]
1642 ""
1643 "
1644{
1645 /* Don't generate memory->memory moves, go through a register */
1646 if (TARGET_MOVE
1632 /* Handle other kinds of writes from the 387 */
1633
1634 if (STACK_TOP_P (operands[1]))
1635 {
1636 output_asm_insn (AS1 (fstp%z0,%y0), operands);
1637 if (! stack_top_dies)
1638 return AS1 (fld%z0,%y0);
1639

--- 42 unchanged lines hidden (view full) ---

1682(define_expand "movdi"
1683 [(set (match_operand:DI 0 "general_operand" "")
1684 (match_operand:DI 1 "general_operand" ""))]
1685 ""
1686 "
1687{
1688 /* Don't generate memory->memory moves, go through a register */
1689 if (TARGET_MOVE
1647 && (reload_in_progress | reload_completed) == 0
1690 && no_new_pseudos == 0
1648 && GET_CODE (operands[0]) == MEM
1649 && GET_CODE (operands[1]) == MEM)
1650 {
1651 operands[1] = force_reg (DImode, operands[1]);
1652 }
1653}")
1654
1655(define_insn ""
1656 [(set (match_operand:DI 0 "general_operand" "=g,r")
1657 (match_operand:DI 1 "general_operand" "riF,m"))]
1658 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
1659 || (GET_CODE (operands[1]) != MEM)"
1691 && GET_CODE (operands[0]) == MEM
1692 && GET_CODE (operands[1]) == MEM)
1693 {
1694 operands[1] = force_reg (DImode, operands[1]);
1695 }
1696}")
1697
1698(define_insn ""
1699 [(set (match_operand:DI 0 "general_operand" "=g,r")
1700 (match_operand:DI 1 "general_operand" "riF,m"))]
1701 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
1702 || (GET_CODE (operands[1]) != MEM)"
1660 "* return output_move_double (operands);")
1703 "* return output_move_double (operands);"
1704 [(set_attr "type" "integer,memory")
1705 (set_attr "memory" "*,load")])
1661
1706
1707(define_split
1708 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1709 (match_operand:DI 1 "general_operand" ""))]
1710 "reload_completed
1711 && (offsettable_memref_p (operands[0])
1712 || nonmemory_operand (operands[0], DImode))
1713 && (offsettable_memref_p (operands[1])
1714 || nonmemory_operand (operands[1], DImode))
1715 && (! reg_overlap_mentioned_p (gen_lowpart (SImode, operands[0]),
1716 operands[1])
1717 || ! reg_overlap_mentioned_p (gen_highpart (SImode, operands[0]),
1718 operands[1]))"
1719 [(set (match_dup 2)
1720 (match_dup 4))
1721 (set (match_dup 3)
1722 (match_dup 5))]
1723 "
1724{
1725 split_di (&operands[0], 1, &operands[2], &operands[3]);
1726 split_di (&operands[1], 1, &operands[4], &operands[5]);
1727
1728 if (reg_overlap_mentioned_p (operands[2], operands[1]))
1729 {
1730 rtx tmp;
1731
1732 tmp = operands[2];
1733 operands[2] = operands[3];
1734 operands[3] = tmp;
1735
1736 tmp = operands[4];
1737 operands[4] = operands[5];
1738 operands[5] = tmp;
1739 }
1740}")
1662
1663;;- conversion instructions
1664;;- NONE
1665
1666;;- zero extension instructions
1667;; See comments by `andsi' for when andl is faster than movzx.
1668
1741
1742;;- conversion instructions
1743;;- NONE
1744
1745;;- zero extension instructions
1746;; See comments by `andsi' for when andl is faster than movzx.
1747
1669(define_insn "zero_extendhisi2"
1748(define_expand "zero_extendhisi2"
1749 [(set (match_operand:SI 0 "register_operand" "")
1750 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1751 ""
1752 "")
1753
1754;; When optimizing for the PPro/PII or code size, always use movzwl.
1755;; We want to use a different pattern so we can use different constraints
1756;; than the generic pattern.
1757(define_insn ""
1758 [(set (match_operand:SI 0 "register_operand" "=r")
1759 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
1760 "(optimize_size || (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO)"
1761 "* return AS2 (movz%W0%L0,%1,%0);")
1762
1763(define_insn ""
1670 [(set (match_operand:SI 0 "register_operand" "=r,&r,?r")
1671 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,rm,rm")))]
1764 [(set (match_operand:SI 0 "register_operand" "=r,&r,?r")
1765 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,rm,rm")))]
1672 ""
1766 "! (optimize_size || (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO)"
1673 "*
1674 {
1675 rtx xops[2];
1676
1677 if ((TARGET_ZERO_EXTEND_WITH_AND || REGNO (operands[0]) == 0)
1678 && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1]))
1679 {
1680 xops[0] = operands[0];

--- 44 unchanged lines hidden (view full) ---

1725 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && reg_overlap_mentioned_p (operands[0], operands[1])"
1726 [(set (strict_low_part (match_dup 2))
1727 (match_dup 1))
1728 (set (match_dup 0)
1729 (and:SI (match_dup 0)
1730 (const_int 65535)))]
1731 "operands[2] = gen_rtx_REG (HImode, true_regnum (operands[0]));")
1732
1767 "*
1768 {
1769 rtx xops[2];
1770
1771 if ((TARGET_ZERO_EXTEND_WITH_AND || REGNO (operands[0]) == 0)
1772 && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1]))
1773 {
1774 xops[0] = operands[0];

--- 44 unchanged lines hidden (view full) ---

1819 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && reg_overlap_mentioned_p (operands[0], operands[1])"
1820 [(set (strict_low_part (match_dup 2))
1821 (match_dup 1))
1822 (set (match_dup 0)
1823 (and:SI (match_dup 0)
1824 (const_int 65535)))]
1825 "operands[2] = gen_rtx_REG (HImode, true_regnum (operands[0]));")
1826
1733(define_insn "zero_extendqihi2"
1827(define_expand "zero_extendqihi2"
1828 [(set (match_operand:HI 0 "register_operand" "")
1829 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1830 ""
1831 "")
1832
1833(define_insn ""
1834 [(set (match_operand:HI 0 "register_operand" "=r")
1835 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
1836 "optimize_size || (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO"
1837
1838 "* return AS2 (movz%B0%W0,%1,%0);")
1839
1840(define_insn ""
1734 [(set (match_operand:HI 0 "register_operand" "=q,&q,?r")
1735 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm,qm")))]
1841 [(set (match_operand:HI 0 "register_operand" "=q,&q,?r")
1842 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm,qm")))]
1736 ""
1843 "! (optimize_size || (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO)"
1737 "*
1738 {
1739 rtx xops[2];
1740
1741 if ((TARGET_ZERO_EXTEND_WITH_AND || REGNO (operands[0]) == 0)
1742 && REG_P (operands[1])
1743 && REGNO (operands[0]) == REGNO (operands[1]))
1744 {

--- 61 unchanged lines hidden (view full) ---

1806 (const_int 255)))]
1807 "if (GET_CODE (operands[1]) == SUBREG && SUBREG_WORD (operands[1]) == 0)
1808 operands[1] = SUBREG_REG (operands[1]);
1809 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG
1810 || REGNO (operands[0]) == REGNO (operands[1]))
1811 FAIL;
1812 operands[2] = gen_rtx_REG (HImode, REGNO (operands[1]));")
1813
1844 "*
1845 {
1846 rtx xops[2];
1847
1848 if ((TARGET_ZERO_EXTEND_WITH_AND || REGNO (operands[0]) == 0)
1849 && REG_P (operands[1])
1850 && REGNO (operands[0]) == REGNO (operands[1]))
1851 {

--- 61 unchanged lines hidden (view full) ---

1913 (const_int 255)))]
1914 "if (GET_CODE (operands[1]) == SUBREG && SUBREG_WORD (operands[1]) == 0)
1915 operands[1] = SUBREG_REG (operands[1]);
1916 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG
1917 || REGNO (operands[0]) == REGNO (operands[1]))
1918 FAIL;
1919 operands[2] = gen_rtx_REG (HImode, REGNO (operands[1]));")
1920
1814(define_insn "zero_extendqisi2"
1921(define_expand "zero_extendqisi2"
1922 [(set (match_operand:SI 0 "register_operand" "")
1923 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1924 ""
1925 "")
1926
1927(define_insn ""
1928 [(set (match_operand:SI 0 "register_operand" "=r")
1929 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
1930 "optimize_size || (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO"
1931 "* return AS2 (movz%B0%L0,%1,%0);")
1932
1933(define_insn ""
1815 [(set (match_operand:SI 0 "register_operand" "=q,&q,?r")
1816 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm,qm")))]
1934 [(set (match_operand:SI 0 "register_operand" "=q,&q,?r")
1935 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm,qm")))]
1817 ""
1936 "! (optimize_size || (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO)"
1818 "*
1819 {
1820 rtx xops[2];
1821
1822 if ((TARGET_ZERO_EXTEND_WITH_AND || REGNO (operands[0]) == 0)
1823 && REG_P (operands[1])
1824 && REGNO (operands[0]) == REGNO (operands[1]))
1825 {

--- 68 unchanged lines hidden (view full) ---

1894 [(set (match_dup 0)
1895 (match_dup 2))
1896 (set (match_dup 0)
1897 (and:SI (match_dup 0)
1898 (const_int 255)))]
1899 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
1900
1901(define_insn "zero_extendsidi2"
1937 "*
1938 {
1939 rtx xops[2];
1940
1941 if ((TARGET_ZERO_EXTEND_WITH_AND || REGNO (operands[0]) == 0)
1942 && REG_P (operands[1])
1943 && REGNO (operands[0]) == REGNO (operands[1]))
1944 {

--- 68 unchanged lines hidden (view full) ---

2013 [(set (match_dup 0)
2014 (match_dup 2))
2015 (set (match_dup 0)
2016 (and:SI (match_dup 0)
2017 (const_int 255)))]
2018 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
2019
2020(define_insn "zero_extendsidi2"
1902 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?m")
1903 (zero_extend:DI (match_operand:SI 1 "register_operand" "0,rm,r")))]
2021 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
2022 (zero_extend:DI (match_operand:SI 1 "general_operand" "0,rm,r")))]
1904 ""
2023 ""
1905 "*
1906 {
1907 rtx high[2], low[2], xops[4];
2024 "#")
1908
2025
1909 if (REG_P (operands[0]) && REG_P (operands[1])
1910 && REGNO (operands[0]) == REGNO (operands[1]))
1911 {
1912 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1913 return AS2 (xor%L0,%0,%0);
1914 }
2026(define_split
2027 [(set (match_operand:DI 0 "register_operand" "")
2028 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))]
2029 "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])"
2030 [(set (match_dup 4) (const_int 0))]
2031 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
1915
2032
1916 split_di (operands, 1, low, high);
1917 xops[0] = low[0];
1918 xops[1] = operands[1];
1919 xops[2] = high[0];
1920 xops[3] = const0_rtx;
1921
1922 output_asm_insn (AS2 (mov%L0,%1,%0), xops);
1923 if (GET_CODE (low[0]) == MEM)
1924 output_asm_insn (AS2 (mov%L2,%3,%2), xops);
1925 else
1926 output_asm_insn (AS2 (xor%L2,%2,%2), xops);
1927
1928 RET;
1929}")
2033(define_split
2034 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2035 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))]
2036 "reload_completed"
2037 [(set (match_dup 3) (match_dup 1))
2038 (set (match_dup 4) (const_int 0))]
2039 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
1930
1931;;- sign extension instructions
1932
1933(define_insn "extendsidi2"
2040
2041;;- sign extension instructions
2042
2043(define_insn "extendsidi2"
1934 [(set (match_operand:DI 0 "register_operand" "=r")
1935 (sign_extend:DI (match_operand:SI 1 "register_operand" "0")))]
2044 [(set (match_operand:DI 0 "nonimmediate_operand" "=A,?r,?Ar,*o")
2045 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,*r")))
2046 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
1936 ""
2047 ""
1937 "*
2048 "#")
2049
2050;; Extend to memory case when source register does die.
2051(define_split
2052 [(set (match_operand:DI 0 "memory_operand" "")
2053 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
2054 (clobber (match_operand:SI 2 "register_operand" ""))]
2055 "(flow2_completed
2056 && dead_or_set_p (insn, operands[1])
2057 && !reg_mentioned_p (operands[1], operands[0]))"
2058 [(set (match_dup 3) (match_dup 1))
2059 (set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
2060 (set (match_dup 4) (match_dup 1))]
2061 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
2062
2063;; Extend to memory case when source register does not die.
2064(define_split
2065 [(set (match_operand:DI 0 "memory_operand" "")
2066 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
2067 (clobber (match_operand:SI 2 "register_operand" ""))]
2068 "flow2_completed"
2069 [(const_int 0)]
2070 "
1938{
2071{
1939 if (REGNO (operands[0]) == 0)
2072 split_di (&operands[0], 1, &operands[3], &operands[4]);
2073
2074 emit_move_insn (operands[3], operands[1]);
2075
2076 /* Generate a cltd if possible and doing so it profitable. */
2077 if (true_regnum (operands[1]) == 0
2078 && true_regnum (operands[2]) == 1
2079 && (optimize_size || !TARGET_PENTIUM))
1940 {
2080 {
1941 /* This used to be cwtl, but that extends HI to SI somehow. */
1942#ifdef INTEL_SYNTAX
1943 return \"cdq\";
1944#else
1945 return \"cltd\";
1946#endif
2081 emit_insn (gen_ashrsi3_31 (operands[2], operands[1]));
1947 }
2082 }
2083 else
2084 {
2085 emit_move_insn (operands[2], operands[1]);
2086 emit_insn (gen_ashrsi3_31 (operands[2], operands[2]));
2087 }
2088 emit_move_insn (operands[4], operands[2]);
2089 DONE;
2090}")
1948
2091
1949 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1950 output_asm_insn (AS2 (mov%L0,%0,%1), operands);
2092;; Extend to register case. Optimize case where source and destination
2093;; registers match and cases where we can use cltd.
2094(define_split
2095 [(set (match_operand:DI 0 "register_operand" "")
2096 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
2097 (clobber (match_scratch:SI 2 ""))]
2098 "reload_completed"
2099 [(const_int 0)]
2100 "
2101{
2102 split_di (&operands[0], 1, &operands[3], &operands[4]);
1951
2103
1952 operands[0] = GEN_INT (31);
1953 return AS2 (sar%L1,%0,%1);
2104 if (true_regnum (operands[3]) != true_regnum (operands[1]))
2105 emit_move_insn (operands[3], operands[1]);
2106
2107 /* Generate a cltd if possible and doing so it profitable. */
2108 if (true_regnum (operands[3]) == 0
2109 && (optimize_size || !TARGET_PENTIUM))
2110 {
2111 emit_insn (gen_ashrsi3_31 (operands[4], operands[3]));
2112 DONE;
2113 }
2114
2115 if (true_regnum (operands[4]) != true_regnum (operands[1]))
2116 emit_move_insn (operands[4], operands[1]);
2117
2118 emit_insn (gen_ashrsi3_31 (operands[4], operands[4]));
2119 DONE;
1954}")
1955
1956;; Note that the i386 programmers' manual says that the opcodes
1957;; are named movsx..., but the assembler on Unix does not accept that.
1958;; We use what the Unix assembler expects.
1959
1960(define_insn "extendhisi2"
1961 [(set (match_operand:SI 0 "register_operand" "=r")
1962 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
1963 ""
1964 "*
1965{
1966 if (REGNO (operands[0]) == 0
2120}")
2121
2122;; Note that the i386 programmers' manual says that the opcodes
2123;; are named movsx..., but the assembler on Unix does not accept that.
2124;; We use what the Unix assembler expects.
2125
2126(define_insn "extendhisi2"
2127 [(set (match_operand:SI 0 "register_operand" "=r")
2128 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
2129 ""
2130 "*
2131{
2132 if (REGNO (operands[0]) == 0
1967 && REG_P (operands[1]) && REGNO (operands[1]) == 0)
2133 && REG_P (operands[1]) && REGNO (operands[1]) == 0
2134 && (optimize_size || ix86_cpu != PROCESSOR_K6))
1968#ifdef INTEL_SYNTAX
1969 return \"cwde\";
1970#else
1971 return \"cwtl\";
1972#endif
1973
1974#ifdef INTEL_SYNTAX
1975 return AS2 (movsx,%1,%0);

--- 4 unchanged lines hidden (view full) ---

1980
1981(define_insn "extendqihi2"
1982 [(set (match_operand:HI 0 "register_operand" "=r")
1983 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
1984 ""
1985 "*
1986{
1987 if (REGNO (operands[0]) == 0
2135#ifdef INTEL_SYNTAX
2136 return \"cwde\";
2137#else
2138 return \"cwtl\";
2139#endif
2140
2141#ifdef INTEL_SYNTAX
2142 return AS2 (movsx,%1,%0);

--- 4 unchanged lines hidden (view full) ---

2147
2148(define_insn "extendqihi2"
2149 [(set (match_operand:HI 0 "register_operand" "=r")
2150 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
2151 ""
2152 "*
2153{
2154 if (REGNO (operands[0]) == 0
1988 && REG_P (operands[1]) && REGNO (operands[1]) == 0)
2155 && REG_P (operands[1]) && REGNO (operands[1]) == 0
2156 && (optimize_size || ix86_cpu != PROCESSOR_K6))
1989 return \"cbtw\";
1990
1991#ifdef INTEL_SYNTAX
1992 return AS2 (movsx,%1,%0);
1993#else
1994 return AS2 (movs%B0%W0,%1,%0);
1995#endif
1996}")

--- 67 unchanged lines hidden (view full) ---

2064
2065 RET;
2066}")
2067
2068
2069
2070;; Conversions between float and double.
2071
2157 return \"cbtw\";
2158
2159#ifdef INTEL_SYNTAX
2160 return AS2 (movsx,%1,%0);
2161#else
2162 return AS2 (movs%B0%W0,%1,%0);
2163#endif
2164}")

--- 67 unchanged lines hidden (view full) ---

2232
2233 RET;
2234}")
2235
2236
2237
2238;; Conversions between float and double.
2239
2072(define_insn "extendsfdf2"
2073 [(set (match_operand:DF 0 "nonimmediate_operand" "=fm,f")
2074 (float_extend:DF
2075 (match_operand:SF 1 "nonimmediate_operand" "f,fm")))]
2240(define_expand "extendsfdf2"
2241 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
2242 (float_extend:DF
2243 (match_operand:SF 1 "nonimmediate_operand" "")))
2244 (clobber (match_dup 2))
2245 (clobber (match_dup 3))])]
2076 "TARGET_80387"
2246 "TARGET_80387"
2247 "
2248{
2249 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
2250 operands[1] = force_reg (SFmode, operands[1]);
2251
2252 operands[2] = assign_386_stack_local (SFmode, 0);
2253 operands[3] = assign_386_stack_local (DFmode, 0);
2254}")
2255
2256(define_insn ""
2257 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m,!f,!*r")
2258 (float_extend:DF
2259 (match_operand:SF 1 "nonimmediate_operand" "fm,f,*r,f")))
2260 (clobber (match_operand:SF 2 "memory_operand" "m,m,m,m"))
2261 (clobber (match_operand:DF 3 "memory_operand" "m,m,m,o"))]
2262 "TARGET_80387 && (GET_CODE (operands[0]) != MEM
2263 || GET_CODE (operands[1]) != MEM)"
2077 "*
2078{
2264 "*
2265{
2079 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
2266 output_float_extend (insn, operands);
2267 return \"\";
2268}"
2269 [(set_attr "type" "fld,fpop,fld,fpop")])
2080
2270
2081 if (NON_STACK_REG_P (operands[1]))
2082 {
2083 output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
2084 RET;
2085 }
2271(define_split
2272 [(set (match_operand:DF 0 "register_operand" "")
2273 (float_extend:DF (match_operand:SF 1 "register_operand" "")))
2274 (clobber (match_operand:SF 2 "memory_operand" ""))
2275 (clobber (match_operand:DF 3 "memory_operand" ""))]
2276 "TARGET_80387 && reload_completed && NON_STACK_REG_P (operands[1])"
2277 [(set (match_dup 2)
2278 (match_dup 1))
2279 (set (match_dup 0)
2280 (float_extend:DF (match_dup 2)))]
2281 "")
2086
2282
2087 if (NON_STACK_REG_P (operands[0]))
2088 {
2089 output_to_reg (operands[0], stack_top_dies, 0);
2090 RET;
2091 }
2283(define_split
2284 [(set (match_operand:DF 0 "register_operand" "")
2285 (float_extend:DF (match_operand:SF 1 "register_operand" "")))
2286 (clobber (match_operand:SF 2 "memory_operand" ""))
2287 (clobber (match_operand:DF 3 "memory_operand" ""))]
2288 "TARGET_80387 && reload_completed && NON_STACK_REG_P (operands[0])"
2289 [(set (match_dup 3)
2290 (float_extend:DF (match_dup 1)))
2291 (set (match_dup 0)
2292 (match_dup 3))]
2293 "")
2092
2294
2093 if (STACK_TOP_P (operands[0]))
2094 return AS1 (fld%z1,%y1);
2295(define_split
2296 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2297 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))
2298 (clobber (match_operand:SF 2 "memory_operand" ""))
2299 (clobber (match_operand:DF 3 "memory_operand" ""))]
2300 "TARGET_80387 && reload_completed"
2301 [(set (match_dup 0)
2302 (float_extend:DF (match_dup 1)))]
2303 "")
2095
2304
2096 if (GET_CODE (operands[0]) == MEM)
2097 {
2098 if (stack_top_dies)
2099 return AS1 (fstp%z0,%y0);
2100 else
2101 return AS1 (fst%z0,%y0);
2102 }
2305(define_insn ""
2306 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m")
2307 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
2308 "TARGET_80387 && (GET_CODE (operands[0]) != MEM
2309 || GET_CODE (operands[1]) != MEM)"
2310 "*
2311{
2312 output_float_extend (insn, operands);
2313 return \"\";
2314}"
2315 [(set_attr "type" "fld,fpop")])
2103
2316
2104 abort ();
2317(define_expand "extenddfxf2"
2318 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
2319 (float_extend:XF
2320 (match_operand:DF 1 "nonimmediate_operand" "")))
2321 (clobber (match_dup 2))
2322 (clobber (match_dup 3))])]
2323 "TARGET_80387"
2324 "
2325{
2326 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
2327 operands[1] = force_reg (DFmode, operands[1]);
2328
2329 operands[2] = assign_386_stack_local (DFmode, 0);
2330 operands[3] = assign_386_stack_local (XFmode, 0);
2105}")
2106
2331}")
2332
2107(define_insn "extenddfxf2"
2108 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f,f,!*r")
2333(define_insn ""
2334 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,!f,!*r")
2109 (float_extend:XF
2335 (float_extend:XF
2110 (match_operand:DF 1 "nonimmediate_operand" "f,fm,!*r,f")))]
2111 "TARGET_80387"
2336 (match_operand:DF 1 "nonimmediate_operand" "fm,f,*r,f")))
2337 (clobber (match_operand:DF 2 "memory_operand" "m,m,o,m"))
2338 (clobber (match_operand:XF 3 "memory_operand" "m,m,m,o"))]
2339 "TARGET_80387 && (GET_CODE (operands[0]) != MEM
2340 || GET_CODE (operands[1]) != MEM)"
2112 "*
2113{
2341 "*
2342{
2114 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
2343 output_float_extend (insn, operands);
2344 return \"\";
2345}"
2346 [(set_attr "type" "fld,fpop,fld,fpop")])
2115
2347
2116 if (NON_STACK_REG_P (operands[1]))
2117 {
2118 output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
2119 RET;
2120 }
2348(define_split
2349 [(set (match_operand:XF 0 "register_operand" "")
2350 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
2351 (clobber (match_operand:DF 2 "memory_operand" ""))
2352 (clobber (match_operand:XF 3 "memory_operand" ""))]
2353 "TARGET_80387 && reload_completed && NON_STACK_REG_P (operands[1])"
2354 [(set (match_dup 2)
2355 (match_dup 1))
2356 (set (match_dup 0)
2357 (float_extend:XF (match_dup 2)))]
2358 "")
2121
2359
2122 if (NON_STACK_REG_P (operands[0]))
2123 {
2124 output_to_reg (operands[0], stack_top_dies, 0);
2125 RET;
2126 }
2360(define_split
2361 [(set (match_operand:XF 0 "register_operand" "")
2362 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
2363 (clobber (match_operand:DF 2 "memory_operand" ""))
2364 (clobber (match_operand:XF 3 "memory_operand" ""))]
2365 "TARGET_80387 && reload_completed && NON_STACK_REG_P (operands[0])"
2366 [(set (match_dup 3)
2367 (float_extend:XF (match_dup 1)))
2368 (set (match_dup 0)
2369 (match_dup 3))]
2370 "")
2127
2371
2128 if (STACK_TOP_P (operands[0]))
2129 return AS1 (fld%z1,%y1);
2372(define_split
2373 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2374 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "")))
2375 (clobber (match_operand:DF 2 "memory_operand" ""))
2376 (clobber (match_operand:XF 3 "memory_operand" ""))]
2377 "TARGET_80387 && reload_completed"
2378 [(set (match_dup 0)
2379 (float_extend:XF (match_dup 1)))]
2380 "")
2130
2381
2131 if (GET_CODE (operands[0]) == MEM)
2132 {
2133 output_asm_insn (AS1 (fstp%z0,%y0), operands);
2134 if (! stack_top_dies)
2135 return AS1 (fld%z0,%y0);
2136 RET;
2137 }
2382(define_insn ""
2383 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
2384 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
2385 "TARGET_80387 && (GET_CODE (operands[0]) != MEM
2386 || GET_CODE (operands[1]) != MEM)"
2387 "*
2388{
2389 output_float_extend (insn, operands);
2390 return \"\";
2391}"
2392 [(set_attr "type" "fld,fpop")])
2138
2393
2139 abort ();
2394(define_expand "extendsfxf2"
2395 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
2396 (float_extend:XF
2397 (match_operand:SF 1 "nonimmediate_operand" "")))
2398 (clobber (match_dup 2))
2399 (clobber (match_dup 3))])]
2400 "TARGET_80387"
2401 "
2402{
2403 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
2404 operands[1] = force_reg (SFmode, operands[1]);
2405
2406 operands[2] = assign_386_stack_local (SFmode, 0);
2407 operands[3] = assign_386_stack_local (XFmode, 0);
2140}")
2141
2408}")
2409
2142(define_insn "extendsfxf2"
2143 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f,f,!*r")
2410(define_insn ""
2411 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,!f,!*r")
2144 (float_extend:XF
2412 (float_extend:XF
2145 (match_operand:SF 1 "nonimmediate_operand" "f,fm,!*r,f")))]
2146 "TARGET_80387"
2413 (match_operand:SF 1 "nonimmediate_operand" "fm,f,*r,f")))
2414 (clobber (match_operand:SF 2 "memory_operand" "m,m,m,m"))
2415 (clobber (match_operand:XF 3 "memory_operand" "m,m,m,o"))]
2416 "TARGET_80387 && (GET_CODE (operands[0]) != MEM
2417 || GET_CODE (operands[1]) != MEM)"
2147 "*
2148{
2418 "*
2419{
2149 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
2420 output_float_extend (insn, operands);
2421 return \"\";
2422}"
2423 [(set_attr "type" "fld,fpop,fld,fpop")])
2150
2424
2151 if (NON_STACK_REG_P (operands[1]))
2152 {
2153 output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
2154 RET;
2155 }
2425(define_split
2426 [(set (match_operand:XF 0 "register_operand" "")
2427 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
2428 (clobber (match_operand:SF 2 "memory_operand" ""))
2429 (clobber (match_operand:XF 3 "memory_operand" ""))]
2430 "TARGET_80387 && reload_completed && NON_STACK_REG_P (operands[1])"
2431 [(set (match_dup 2)
2432 (match_dup 1))
2433 (set (match_dup 0)
2434 (float_extend:XF (match_dup 2)))]
2435 "")
2156
2436
2157 if (NON_STACK_REG_P (operands[0]))
2158 {
2159 output_to_reg (operands[0], stack_top_dies, 0);
2160 RET;
2161 }
2437(define_split
2438 [(set (match_operand:XF 0 "register_operand" "")
2439 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
2440 (clobber (match_operand:SF 2 "memory_operand" ""))
2441 (clobber (match_operand:XF 3 "memory_operand" ""))]
2442 "TARGET_80387 && reload_completed && NON_STACK_REG_P (operands[0])"
2443 [(set (match_dup 3)
2444 (float_extend:XF (match_dup 1)))
2445 (set (match_dup 0)
2446 (match_dup 3))]
2447 "")
2162
2448
2163 if (STACK_TOP_P (operands[0]))
2164 return AS1 (fld%z1,%y1);
2449(define_split
2450 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2451 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "")))
2452 (clobber (match_operand:SF 2 "memory_operand" ""))
2453 (clobber (match_operand:XF 3 "memory_operand" ""))]
2454 "TARGET_80387 && reload_completed"
2455 [(set (match_dup 0)
2456 (float_extend:XF (match_dup 1)))]
2457 "")
2165
2458
2166 if (GET_CODE (operands[0]) == MEM)
2167 {
2168 output_asm_insn (AS1 (fstp%z0,%y0), operands);
2169 if (! stack_top_dies)
2170 return AS1 (fld%z0,%y0);
2171 RET;
2172 }
2459(define_insn ""
2460 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
2461 (float_extend:XF
2462 (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
2463 "TARGET_80387 && (GET_CODE (operands[0]) != MEM
2464 || GET_CODE (operands[1]) != MEM)"
2465 "*
2466{
2467 output_float_extend (insn, operands);
2468 return \"\";
2469}"
2470 [(set_attr "type" "fld,fpop")])
2173
2471
2174 abort ();
2175}")
2176
2177(define_expand "truncdfsf2"
2178 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
2179 (float_truncate:SF
2180 (match_operand:DF 1 "register_operand" "")))
2181 (clobber (match_dup 2))])]
2182 "TARGET_80387"
2183 "
2184{
2185 operands[2] = (rtx) assign_386_stack_local (SFmode, 0);
2186}")
2187
2472(define_expand "truncdfsf2"
2473 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
2474 (float_truncate:SF
2475 (match_operand:DF 1 "register_operand" "")))
2476 (clobber (match_dup 2))])]
2477 "TARGET_80387"
2478 "
2479{
2480 operands[2] = (rtx) assign_386_stack_local (SFmode, 0);
2481}")
2482
2188;; This cannot output into an f-reg because there is no way to be sure
2189;; of truncating in that case. Otherwise this is just like a simple move
2190;; insn. So we pretend we can output to a reg in order to get better
2191;; register preferencing, but we really use a stack slot.
2192
2193(define_insn ""
2483(define_insn ""
2194 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,m")
2484 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,m,!*r")
2195 (float_truncate:SF
2485 (float_truncate:SF
2196 (match_operand:DF 1 "register_operand" "0,f")))
2197 (clobber (match_operand:SF 2 "memory_operand" "m,m"))]
2486 (match_operand:DF 1 "register_operand" "0,f,f")))
2487 (clobber (match_operand:SF 2 "memory_operand" "m,m,m"))]
2198 "TARGET_80387"
2199 "*
2200{
2201 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
2488 "TARGET_80387"
2489 "*
2490{
2491 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
2492 rtx xops[1];
2202
2493
2203 if (GET_CODE (operands[0]) == MEM)
2204 {
2205 if (stack_top_dies)
2206 return AS1 (fstp%z0,%0);
2207 else
2208 return AS1 (fst%z0,%0);
2209 }
2210 else if (STACK_TOP_P (operands[0]))
2211 {
2212 output_asm_insn (AS1 (fstp%z2,%y2), operands);
2213 return AS1 (fld%z2,%y2);
2214 }
2494 xops[0] = GET_CODE (operands[0]) == MEM ? operands[0] : operands[2];
2495
2496 if (stack_top_dies || STACK_REG_P (operands[0]))
2497 output_asm_insn (AS1 (fstp%z0,%0), xops);
2215 else
2498 else
2216 abort ();
2217}")
2499 output_asm_insn (AS1 (fst%z0,%0), xops);
2218
2500
2219(define_insn "truncxfsf2"
2220 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,!*r")
2221 (float_truncate:SF
2222 (match_operand:XF 1 "register_operand" "f,f")))]
2501 if (STACK_REG_P (operands[0]))
2502 return AS1 (fld%z2,%2);
2503 else if (NON_STACK_REG_P (operands[0]))
2504 return AS2 (mov%L0,%2,%0);
2505
2506 return \"\";
2507}"
2508 [(set_attr "type" "fpop")])
2509
2510(define_split
2511 [(set (match_operand:SF 0 "register_operand" "")
2512 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))
2513 (clobber (match_operand:SF 2 "memory_operand" ""))]
2514 "TARGET_80387 && reload_completed"
2515 [(set (match_dup 2)
2516 (float_truncate:SF (match_dup 1)))
2517 (set (match_dup 0)
2518 (match_dup 2))]
2519 "")
2520
2521(define_split
2522 [(set (match_operand:SF 0 "memory_operand" "")
2523 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))
2524 (clobber (match_operand:SF 2 "memory_operand" ""))]
2525 "TARGET_80387 && reload_completed"
2526 [(set (match_dup 0)
2527 (float_truncate:SF (match_dup 1)))]
2528 "")
2529
2530;; This cannot output into an f-reg because there is no way to be sure
2531;; of truncating in that case.
2532
2533(define_insn ""
2534 [(set (match_operand:SF 0 "memory_operand" "=m")
2535 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2223 "TARGET_80387"
2224 "*
2225{
2226 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
2227
2536 "TARGET_80387"
2537 "*
2538{
2539 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
2540
2228 if (NON_STACK_REG_P (operands[0]))
2229 {
2230 if (stack_top_dies == 0)
2231 {
2232 output_asm_insn (AS1 (fld,%y1), operands);
2233 stack_top_dies = 1;
2234 }
2235 output_to_reg (operands[0], stack_top_dies, 0);
2236 RET;
2237 }
2238 else if (GET_CODE (operands[0]) == MEM)
2239 {
2240 if (stack_top_dies)
2241 return AS1 (fstp%z0,%0);
2242 else
2243 {
2244 output_asm_insn (AS1 (fld,%y1), operands);
2245 return AS1 (fstp%z0,%0);
2246 }
2247 }
2541 if (stack_top_dies)
2542 return AS1 (fstp%z0,%0);
2248 else
2543 else
2249 abort ();
2544 return AS1 (fst%z0,%0);
2545}"
2546 [(set_attr "type" "fpop")])
2547
2548(define_expand "truncxfsf2"
2549 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
2550 (float_truncate:SF
2551 (match_operand:XF 1 "register_operand" "")))
2552 (clobber (match_dup 2))])]
2553 "TARGET_80387"
2554 "
2555{
2556 operands[2] = (rtx) assign_386_stack_local (SFmode, 0);
2250}")
2251
2557}")
2558
2252(define_insn "truncxfdf2"
2253 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!*r")
2254 (float_truncate:DF
2255 (match_operand:XF 1 "register_operand" "f,f")))]
2559(define_insn ""
2560 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,m,!*r")
2561 (float_truncate:SF
2562 (match_operand:XF 1 "register_operand" "0,f,f")))
2563 (clobber (match_operand:SF 2 "memory_operand" "m,m,m"))]
2256 "TARGET_80387"
2257 "*
2258{
2259 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
2564 "TARGET_80387"
2565 "*
2566{
2567 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
2568 rtx xops[1];
2260
2569
2261 if (NON_STACK_REG_P (operands[0]))
2262 {
2263 if (stack_top_dies == 0)
2264 {
2265 output_asm_insn (AS1 (fld,%y1), operands);
2266 stack_top_dies = 1;
2267 }
2268 output_to_reg (operands[0], stack_top_dies, 0);
2269 RET;
2270 }
2271 else if (GET_CODE (operands[0]) == MEM)
2272 {
2273 if (stack_top_dies)
2274 return AS1 (fstp%z0,%0);
2275 else
2276 {
2277 output_asm_insn (AS1 (fld,%y1), operands);
2278 return AS1 (fstp%z0,%0);
2279 }
2280 }
2570 xops[0] = GET_CODE (operands[0]) == MEM ? operands[0] : operands[2];
2571
2572 if (stack_top_dies || STACK_REG_P (operands[0]))
2573 output_asm_insn (AS1 (fstp%z0,%0), xops);
2281 else
2574 else
2282 abort ();
2283}")
2575 output_asm_insn (AS1 (fst%z0,%0), xops);
2284
2576
2285
2286;; The 387 requires that the stack top dies after converting to DImode.
2577 if (STACK_REG_P (operands[0]))
2578 return AS1 (fld%z2,%2);
2579 else if (NON_STACK_REG_P (operands[0]))
2580 return AS2 (mov%L0,%2,%0);
2287
2581
2288;; Represent an unsigned conversion from SImode to MODE_FLOAT by first
2289;; doing a signed conversion to DImode, and then taking just the low
2290;; part.
2582 return \"\";
2583}"
2584 [(set_attr "type" "fpop")])
2291
2585
2292(define_expand "fixuns_truncxfsi2"
2293 [(set (match_dup 4)
2294 (match_operand:XF 1 "register_operand" ""))
2295 (parallel [(set (match_dup 2)
2296 (fix:DI (fix:XF (match_dup 4))))
2297 (clobber (match_dup 4))
2298 (clobber (match_dup 5))
2299 (clobber (match_dup 6))
2300 (clobber (match_scratch:SI 7 ""))])
2301 (set (match_operand:SI 0 "general_operand" "")
2302 (match_dup 3))]
2586(define_split
2587 [(set (match_operand:SF 0 "register_operand" "")
2588 (float_truncate:SF (match_operand:XF 1 "register_operand" "")))
2589 (clobber (match_operand:SF 2 "memory_operand" ""))]
2590 "TARGET_80387 && reload_completed"
2591 [(set (match_dup 2)
2592 (float_truncate:SF (match_dup 1)))
2593 (set (match_dup 0)
2594 (match_dup 2))]
2595 "")
2596
2597(define_split
2598 [(set (match_operand:SF 0 "memory_operand" "")
2599 (float_truncate:SF (match_operand:XF 1 "register_operand" "")))
2600 (clobber (match_operand:SF 2 "memory_operand" ""))]
2601 "TARGET_80387 && reload_completed"
2602 [(set (match_dup 0)
2603 (float_truncate:SF (match_dup 1)))]
2604 "")
2605
2606(define_insn ""
2607 [(set (match_operand:SF 0 "memory_operand" "=m")
2608 (float_truncate:SF (match_operand:XF 1 "register_operand" "f")))]
2303 "TARGET_80387"
2609 "TARGET_80387"
2304 "
2610 "*
2305{
2611{
2306 operands[2] = gen_reg_rtx (DImode);
2307 operands[3] = gen_lowpart (SImode, operands[2]);
2308 operands[4] = gen_reg_rtx (XFmode);
2309 operands[5] = (rtx) assign_386_stack_local (SImode, 0);
2310 operands[6] = (rtx) assign_386_stack_local (DImode, 1);
2311}")
2612 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
2312
2613
2313(define_expand "fixuns_truncdfsi2"
2314 [(set (match_dup 4)
2315 (match_operand:DF 1 "register_operand" ""))
2316 (parallel [(set (match_dup 2)
2317 (fix:DI (fix:DF (match_dup 4))))
2318 (clobber (match_dup 4))
2319 (clobber (match_dup 5))
2320 (clobber (match_dup 6))
2321 (clobber (match_scratch:SI 7 ""))])
2322 (set (match_operand:SI 0 "general_operand" "")
2323 (match_dup 3))]
2614 if (stack_top_dies)
2615 return AS1 (fstp%z0,%0);
2616 else
2617 return AS1 (fst%z0,%0);
2618}"
2619 [(set_attr "type" "fpop")])
2620
2621(define_expand "truncxfdf2"
2622 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
2623 (float_truncate:DF
2624 (match_operand:XF 1 "register_operand" "")))
2625 (clobber (match_dup 2))])]
2324 "TARGET_80387"
2325 "
2326{
2626 "TARGET_80387"
2627 "
2628{
2327 operands[2] = gen_reg_rtx (DImode);
2328 operands[3] = gen_lowpart (SImode, operands[2]);
2329 operands[4] = gen_reg_rtx (DFmode);
2330 operands[5] = (rtx) assign_386_stack_local (SImode, 0);
2331 operands[6] = (rtx) assign_386_stack_local (DImode, 1);
2629 operands[2] = (rtx) assign_386_stack_local (DFmode, 0);
2332}")
2333
2630}")
2631
2334(define_expand "fixuns_truncsfsi2"
2335 [(set (match_dup 4)
2336 (match_operand:SF 1 "register_operand" ""))
2337 (parallel [(set (match_dup 2)
2338 (fix:DI (fix:SF (match_dup 4))))
2339 (clobber (match_dup 4))
2340 (clobber (match_dup 5))
2341 (clobber (match_dup 6))
2342 (clobber (match_scratch:SI 7 ""))])
2343 (set (match_operand:SI 0 "general_operand" "")
2344 (match_dup 3))]
2632(define_insn ""
2633 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m,!*r")
2634 (float_truncate:DF
2635 (match_operand:XF 1 "register_operand" "0,f,f")))
2636 (clobber (match_operand:DF 2 "memory_operand" "m,m,o"))]
2345 "TARGET_80387"
2637 "TARGET_80387"
2346 "
2638 "*
2347{
2639{
2348 operands[2] = gen_reg_rtx (DImode);
2349 operands[3] = gen_lowpart (SImode, operands[2]);
2350 operands[4] = gen_reg_rtx (SFmode);
2351 operands[5] = (rtx) assign_386_stack_local (SImode, 0);
2352 operands[6] = (rtx) assign_386_stack_local (DImode, 1);
2353}")
2640 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
2641 rtx xops[2];
2354
2642
2355;; Signed conversion to DImode.
2643 xops[0] = GET_CODE (operands[0]) == MEM ? operands[0] : operands[2];
2356
2644
2357(define_expand "fix_truncxfdi2"
2645 if (stack_top_dies || STACK_REG_P (operands[0]))
2646 output_asm_insn (AS1 (fstp%z0,%0), xops);
2647 else
2648 output_asm_insn (AS1 (fst%z0,%0), xops);
2649
2650 if (STACK_REG_P (operands[0]))
2651 return AS1 (fld%z2,%2);
2652 else if (NON_STACK_REG_P (operands[0]))
2653 {
2654 xops[0] = operands[0];
2655 xops[1] = operands[2];
2656 output_asm_insn (output_move_double (xops), xops);
2657 }
2658
2659 return \"\";
2660}"
2661 [(set_attr "type" "fpop")])
2662
2663(define_split
2664 [(set (match_operand:DF 0 "register_operand" "")
2665 (float_truncate:DF (match_operand:XF 1 "register_operand" "")))
2666 (clobber (match_operand:DF 2 "memory_operand" ""))]
2667 "TARGET_80387 && reload_completed"
2358 [(set (match_dup 2)
2668 [(set (match_dup 2)
2359 (match_operand:XF 1 "register_operand" ""))
2360 (parallel [(set (match_operand:DI 0 "general_operand" "")
2361 (fix:DI (fix:XF (match_dup 2))))
2362 (clobber (match_dup 2))
2363 (clobber (match_dup 3))
2364 (clobber (match_dup 4))
2365 (clobber (match_scratch:SI 5 ""))])]
2669 (float_truncate:DF (match_dup 1)))
2670 (set (match_dup 0)
2671 (match_dup 2))]
2672 "")
2673
2674(define_split
2675 [(set (match_operand:DF 0 "memory_operand" "")
2676 (float_truncate:DF (match_operand:XF 1 "register_operand" "")))
2677 (clobber (match_operand:DF 2 "memory_operand" ""))]
2678 "TARGET_80387 && reload_completed"
2679 [(set (match_dup 0)
2680 (float_truncate:DF (match_dup 1)))]
2681 "")
2682
2683(define_insn ""
2684 [(set (match_operand:DF 0 "memory_operand" "=m")
2685 (float_truncate:DF (match_operand:XF 1 "register_operand" "f")))]
2366 "TARGET_80387"
2686 "TARGET_80387"
2367 "
2687 "*
2368{
2688{
2369 operands[1] = copy_to_mode_reg (XFmode, operands[1]);
2370 operands[2] = gen_reg_rtx (XFmode);
2371 operands[3] = (rtx) assign_386_stack_local (SImode, 0);
2372 operands[4] = (rtx) assign_386_stack_local (DImode, 1);
2373}")
2689 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
2374
2690
2375(define_expand "fix_truncdfdi2"
2376 [(set (match_dup 2)
2377 (match_operand:DF 1 "register_operand" ""))
2378 (parallel [(set (match_operand:DI 0 "general_operand" "")
2379 (fix:DI (fix:DF (match_dup 2))))
2691 if (stack_top_dies)
2692 return AS1 (fstp%z0,%0);
2693 else
2694 return AS1 (fst%z0,%0);
2695}"
2696 [(set_attr "type" "fpop")])
2697
2698;; Conversions between floating point and fix point.
2699
2700(define_expand "fix_truncsfsi2"
2701 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
2702 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" ""))))
2380 (clobber (match_dup 2))
2381 (clobber (match_dup 3))
2382 (clobber (match_dup 4))
2703 (clobber (match_dup 2))
2704 (clobber (match_dup 3))
2705 (clobber (match_dup 4))
2383 (clobber (match_scratch:SI 5 ""))])]
2706 (clobber (match_scratch:HI 5 ""))])]
2384 "TARGET_80387"
2385 "
2386{
2707 "TARGET_80387"
2708 "
2709{
2387 operands[1] = copy_to_mode_reg (DFmode, operands[1]);
2388 operands[2] = gen_reg_rtx (DFmode);
2389 operands[3] = (rtx) assign_386_stack_local (SImode, 0);
2390 operands[4] = (rtx) assign_386_stack_local (DImode, 1);
2710 operands[2] = (rtx) assign_386_stack_local (HImode, 0);
2711 operands[3] = (rtx) assign_386_stack_local (HImode, 1);
2712 operands[4] = (rtx) assign_386_stack_local (SImode, 0);
2391}")
2392
2713}")
2714
2715(define_insn ""
2716 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,!r")
2717 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f,f"))))
2718 (clobber (match_operand:HI 2 "memory_operand" "m,m"))
2719 (clobber (match_operand:HI 3 "memory_operand" "m,m"))
2720 (clobber (match_operand:SI 4 "memory_operand" "m,m"))
2721 (clobber (match_scratch:HI 5 "=&r,&r"))]
2722 "TARGET_80387"
2723 "* return output_fix_trunc (insn, operands);"
2724 [(set_attr "type" "fpop")])
2725
2393(define_expand "fix_truncsfdi2"
2726(define_expand "fix_truncsfdi2"
2394 [(set (match_dup 2)
2395 (match_operand:SF 1 "register_operand" ""))
2396 (parallel [(set (match_operand:DI 0 "general_operand" "")
2397 (fix:DI (fix:SF (match_dup 2))))
2727 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
2728 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" ""))))
2729 (clobber (match_dup 1))
2398 (clobber (match_dup 2))
2399 (clobber (match_dup 3))
2400 (clobber (match_dup 4))
2730 (clobber (match_dup 2))
2731 (clobber (match_dup 3))
2732 (clobber (match_dup 4))
2401 (clobber (match_scratch:SI 5 ""))])]
2733 (clobber (match_scratch:HI 5 ""))])]
2402 "TARGET_80387"
2403 "
2404{
2405 operands[1] = copy_to_mode_reg (SFmode, operands[1]);
2734 "TARGET_80387"
2735 "
2736{
2737 operands[1] = copy_to_mode_reg (SFmode, operands[1]);
2406 operands[2] = gen_reg_rtx (SFmode);
2407 operands[3] = (rtx) assign_386_stack_local (SImode, 0);
2408 operands[4] = (rtx) assign_386_stack_local (DImode, 1);
2738 operands[2] = (rtx) assign_386_stack_local (HImode, 0);
2739 operands[3] = (rtx) assign_386_stack_local (HImode, 1);
2740 operands[4] = (rtx) assign_386_stack_local (DImode, 0);
2409}")
2410
2741}")
2742
2411;; These match a signed conversion of either DFmode or SFmode to DImode.
2412
2413(define_insn ""
2743(define_insn ""
2414 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
2415 (fix:DI (fix:XF (match_operand:XF 1 "register_operand" "+f"))))
2744 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,!r")
2745 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f,f"))))
2416 (clobber (match_dup 1))
2746 (clobber (match_dup 1))
2417 (clobber (match_operand:SI 2 "memory_operand" "m"))
2418 (clobber (match_operand:DI 3 "memory_operand" "m"))
2419 (clobber (match_scratch:SI 4 "=&q"))]
2747 (clobber (match_operand:HI 2 "memory_operand" "m,m"))
2748 (clobber (match_operand:HI 3 "memory_operand" "m,m"))
2749 (clobber (match_operand:DI 4 "memory_operand" "m,o"))
2750 (clobber (match_scratch:HI 5 "=&r,&r"))]
2420 "TARGET_80387"
2751 "TARGET_80387"
2421 "* return output_fix_trunc (insn, operands);")
2752 "* return output_fix_trunc (insn, operands);"
2753 [(set_attr "type" "fpop")])
2422
2754
2423(define_insn ""
2424 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
2425 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "+f"))))
2426 (clobber (match_dup 1))
2427 (clobber (match_operand:SI 2 "memory_operand" "m"))
2428 (clobber (match_operand:DI 3 "memory_operand" "m"))
2429 (clobber (match_scratch:SI 4 "=&q"))]
2755(define_expand "fix_truncdfsi2"
2756 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
2757 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" ""))))
2758 (clobber (match_dup 2))
2759 (clobber (match_dup 3))
2760 (clobber (match_dup 4))
2761 (clobber (match_scratch:HI 5 ""))])]
2430 "TARGET_80387"
2762 "TARGET_80387"
2431 "* return output_fix_trunc (insn, operands);")
2763 "
2764{
2765 operands[2] = (rtx) assign_386_stack_local (HImode, 0);
2766 operands[3] = (rtx) assign_386_stack_local (HImode, 1);
2767 operands[4] = (rtx) assign_386_stack_local (SImode, 0);
2768}")
2432
2433(define_insn ""
2769
2770(define_insn ""
2434 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
2435 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "+f"))))
2436 (clobber (match_dup 1))
2437 (clobber (match_operand:SI 2 "memory_operand" "m"))
2438 (clobber (match_operand:DI 3 "memory_operand" "m"))
2439 (clobber (match_scratch:SI 4 "=&q"))]
2771 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,!r")
2772 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f,f"))))
2773 (clobber (match_operand:HI 2 "memory_operand" "m,m"))
2774 (clobber (match_operand:HI 3 "memory_operand" "m,m"))
2775 (clobber (match_operand:SI 4 "memory_operand" "m,m"))
2776 (clobber (match_scratch:HI 5 "=&r,&r"))]
2440 "TARGET_80387"
2777 "TARGET_80387"
2441 "* return output_fix_trunc (insn, operands);")
2778 "* return output_fix_trunc (insn, operands);"
2779 [(set_attr "type" "fpop")])
2442
2780
2443;; Signed MODE_FLOAT conversion to SImode.
2444
2445(define_expand "fix_truncxfsi2"
2446 [(parallel [(set (match_operand:SI 0 "general_operand" "")
2447 (fix:SI
2448 (fix:XF (match_operand:XF 1 "register_operand" ""))))
2781(define_expand "fix_truncdfdi2"
2782 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
2783 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" ""))))
2784 (clobber (match_dup 1))
2449 (clobber (match_dup 2))
2450 (clobber (match_dup 3))
2785 (clobber (match_dup 2))
2786 (clobber (match_dup 3))
2451 (clobber (match_scratch:SI 4 ""))])]
2787 (clobber (match_dup 4))
2788 (clobber (match_scratch:HI 5 ""))])]
2452 "TARGET_80387"
2453 "
2454{
2789 "TARGET_80387"
2790 "
2791{
2455 operands[2] = (rtx) assign_386_stack_local (SImode, 0);
2456 operands[3] = (rtx) assign_386_stack_local (DImode, 1);
2792 operands[1] = copy_to_mode_reg (DFmode, operands[1]);
2793 operands[2] = (rtx) assign_386_stack_local (HImode, 0);
2794 operands[3] = (rtx) assign_386_stack_local (HImode, 1);
2795 operands[4] = (rtx) assign_386_stack_local (DImode, 0);
2457}")
2458
2796}")
2797
2459(define_expand "fix_truncdfsi2"
2460 [(parallel [(set (match_operand:SI 0 "general_operand" "")
2461 (fix:SI
2462 (fix:DF (match_operand:DF 1 "register_operand" ""))))
2798(define_insn ""
2799 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,!r")
2800 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f,f"))))
2801 (clobber (match_dup 1))
2802 (clobber (match_operand:HI 2 "memory_operand" "m,m"))
2803 (clobber (match_operand:HI 3 "memory_operand" "m,m"))
2804 (clobber (match_operand:DI 4 "memory_operand" "m,o"))
2805 (clobber (match_scratch:HI 5 "=&r,&r"))]
2806 "TARGET_80387"
2807 "* return output_fix_trunc (insn, operands);"
2808 [(set_attr "type" "fpop")])
2809
2810(define_expand "fix_truncxfsi2"
2811 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
2812 (fix:SI (fix:XF (match_operand:XF 1 "register_operand" ""))))
2463 (clobber (match_dup 2))
2464 (clobber (match_dup 3))
2813 (clobber (match_dup 2))
2814 (clobber (match_dup 3))
2465 (clobber (match_scratch:SI 4 ""))])]
2815 (clobber (match_dup 4))
2816 (clobber (match_scratch:HI 5 ""))])]
2466 "TARGET_80387"
2467 "
2468{
2817 "TARGET_80387"
2818 "
2819{
2469 operands[2] = (rtx) assign_386_stack_local (SImode, 0);
2470 operands[3] = (rtx) assign_386_stack_local (DImode, 1);
2820 operands[2] = (rtx) assign_386_stack_local (HImode, 0);
2821 operands[3] = (rtx) assign_386_stack_local (HImode, 1);
2822 operands[4] = (rtx) assign_386_stack_local (SImode, 0);
2471}")
2472
2823}")
2824
2473(define_expand "fix_truncsfsi2"
2474 [(parallel [(set (match_operand:SI 0 "general_operand" "")
2475 (fix:SI
2476 (fix:SF (match_operand:SF 1 "register_operand" ""))))
2825(define_insn ""
2826 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,!r")
2827 (fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f,f"))))
2828 (clobber (match_operand:HI 2 "memory_operand" "m,m"))
2829 (clobber (match_operand:HI 3 "memory_operand" "m,m"))
2830 (clobber (match_operand:SI 4 "memory_operand" "m,m"))
2831 (clobber (match_scratch:HI 5 "=&r,&r"))]
2832 "TARGET_80387"
2833 "* return output_fix_trunc (insn, operands);"
2834 [(set_attr "type" "fpop")])
2835
2836(define_expand "fix_truncxfdi2"
2837 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
2838 (fix:DI (fix:XF (match_operand:XF 1 "register_operand" ""))))
2839 (clobber (match_dup 1))
2477 (clobber (match_dup 2))
2478 (clobber (match_dup 3))
2840 (clobber (match_dup 2))
2841 (clobber (match_dup 3))
2479 (clobber (match_scratch:SI 4 ""))])]
2842 (clobber (match_dup 4))
2843 (clobber (match_scratch:HI 5 ""))])]
2480 "TARGET_80387"
2481 "
2482{
2844 "TARGET_80387"
2845 "
2846{
2483 operands[2] = (rtx) assign_386_stack_local (SImode, 0);
2484 operands[3] = (rtx) assign_386_stack_local (DImode, 1);
2847 operands[1] = copy_to_mode_reg (XFmode, operands[1]);
2848 operands[2] = (rtx) assign_386_stack_local (HImode, 0);
2849 operands[3] = (rtx) assign_386_stack_local (HImode, 1);
2850 operands[4] = (rtx) assign_386_stack_local (DImode, 0);
2485}")
2486
2487(define_insn ""
2851}")
2852
2853(define_insn ""
2488 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
2489 (fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))
2490 (clobber (match_operand:SI 2 "memory_operand" "m"))
2491 (clobber (match_operand:DI 3 "memory_operand" "m"))
2492 (clobber (match_scratch:SI 4 "=&q"))]
2854 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,!r")
2855 (fix:DI (fix:XF (match_operand:XF 1 "register_operand" "f,f"))))
2856 (clobber (match_dup 1))
2857 (clobber (match_operand:HI 2 "memory_operand" "m,m"))
2858 (clobber (match_operand:HI 3 "memory_operand" "m,m"))
2859 (clobber (match_operand:DI 4 "memory_operand" "m,o"))
2860 (clobber (match_scratch:HI 5 "=&r,&r"))]
2493 "TARGET_80387"
2861 "TARGET_80387"
2494 "* return output_fix_trunc (insn, operands);")
2862 "* return output_fix_trunc (insn, operands);"
2863 [(set_attr "type" "fpop")])
2864
2865;; Conversion between fixed point and floating point.
2495
2866
2496(define_insn ""
2497 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
2498 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
2499 (clobber (match_operand:SI 2 "memory_operand" "m"))
2500 (clobber (match_operand:DI 3 "memory_operand" "m"))
2501 (clobber (match_scratch:SI 4 "=&q"))]
2867;; ??? Possibly represent floatunssidf2 here in gcc2.
2868
2869(define_expand "floatsisf2"
2870 [(parallel [(set (match_operand:SF 0 "register_operand" "")
2871 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))
2872 (clobber (match_dup 2))])]
2502 "TARGET_80387"
2873 "TARGET_80387"
2503 "* return output_fix_trunc (insn, operands);")
2874 "operands[2] = assign_386_stack_local (SImode, 0);")
2504
2505(define_insn ""
2875
2876(define_insn ""
2506 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
2507 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))
2508 (clobber (match_operand:SI 2 "memory_operand" "m"))
2509 (clobber (match_operand:DI 3 "memory_operand" "m"))
2510 (clobber (match_scratch:SI 4 "=&q"))]
2877 [(set (match_operand:SF 0 "register_operand" "=f,f")
2878 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,!r")))
2879 (clobber (match_operand:SI 2 "memory_operand" "m,m"))]
2511 "TARGET_80387"
2880 "TARGET_80387"
2512 "* return output_fix_trunc (insn, operands);")
2513
2514;; Conversion between fixed point and floating point.
2515;; The actual pattern that matches these is at the end of this file.
2881 "#")
2516
2882
2517;; ??? Possibly represent floatunssidf2 here in gcc2.
2883(define_split
2884 [(set (match_operand:SF 0 "register_operand" "")
2885 (float:SF (match_operand:SI 1 "memory_operand" "")))
2886 (clobber (match_operand:SI 2 "memory_operand" ""))]
2887 "TARGET_80387 && reload_completed"
2888 [(set (match_dup 0)
2889 (float:SF (match_dup 1)))]
2890 "")
2518
2891
2519(define_expand "floatsisf2"
2892(define_split
2520 [(set (match_operand:SF 0 "register_operand" "")
2893 [(set (match_operand:SF 0 "register_operand" "")
2521 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
2894 (float:SF (match_operand:SI 1 "register_operand" "")))
2895 (clobber (match_operand:SI 2 "memory_operand" ""))]
2896 "TARGET_80387 && reload_completed"
2897 [(set (match_dup 2)
2898 (match_dup 1))
2899 (set (match_dup 0)
2900 (float:SF (match_dup 2)))]
2901 "")
2902
2903(define_insn ""
2904 [(set (match_operand:SF 0 "register_operand" "=f")
2905 (float:SF (match_operand:SI 1 "memory_operand" "m")))]
2522 "TARGET_80387"
2906 "TARGET_80387"
2907 "* return AS1 (fild%z1,%1);"
2908 [(set_attr "type" "fpop")])
2909
2910(define_expand "floathisf2"
2911 [(parallel [(set (match_operand:SF 0 "register_operand" "")
2912 (float:SF (match_operand:HI 1 "nonimmediate_operand" "")))
2913 (clobber (match_dup 2))])]
2914 "TARGET_80387"
2915 "operands[2] = assign_386_stack_local (HImode, 0);")
2916
2917(define_insn ""
2918 [(set (match_operand:SF 0 "register_operand" "=f,f")
2919 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,!r")))
2920 (clobber (match_operand:HI 2 "memory_operand" "m,m"))]
2921 "TARGET_80387"
2922 "#")
2923
2924(define_split
2925 [(set (match_operand:SF 0 "register_operand" "")
2926 (float:SF (match_operand:HI 1 "memory_operand" "")))
2927 (clobber (match_operand:HI 2 "memory_operand" ""))]
2928 "TARGET_80387 && reload_completed"
2929 [(set (match_dup 0)
2930 (float:SF (match_dup 1)))]
2523 "")
2524
2931 "")
2932
2525(define_expand "floatdisf2"
2933(define_split
2526 [(set (match_operand:SF 0 "register_operand" "")
2934 [(set (match_operand:SF 0 "register_operand" "")
2527 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
2935 (float:SF (match_operand:HI 1 "register_operand" "")))
2936 (clobber (match_operand:HI 2 "memory_operand" ""))]
2937 "TARGET_80387 && reload_completed"
2938 [(set (match_dup 2)
2939 (match_dup 1))
2940 (set (match_dup 0)
2941 (float:SF (match_dup 2)))]
2942 "")
2943
2944(define_insn ""
2945 [(set (match_operand:SF 0 "register_operand" "=f")
2946 (float:SF (match_operand:HI 1 "memory_operand" "m")))]
2528 "TARGET_80387"
2947 "TARGET_80387"
2948 "* return AS1 (fild%z1,%1);"
2949 [(set_attr "type" "fpop")])
2950
2951(define_expand "floatdisf2"
2952 [(parallel [(set (match_operand:SF 0 "register_operand" "")
2953 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))
2954 (clobber (match_dup 2))])]
2955 "TARGET_80387"
2956 "operands[2] = assign_386_stack_local (DImode, 0);")
2957
2958(define_insn ""
2959 [(set (match_operand:SF 0 "register_operand" "=f,f")
2960 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,!r")))
2961 (clobber (match_operand:DI 2 "memory_operand" "m,o"))]
2962 "TARGET_80387"
2963 "#")
2964
2965(define_split
2966 [(set (match_operand:SF 0 "register_operand" "")
2967 (float:SF (match_operand:DI 1 "memory_operand" "")))
2968 (clobber (match_operand:DI 2 "memory_operand" ""))]
2969 "TARGET_80387 && reload_completed"
2970 [(set (match_dup 0)
2971 (float:SF (match_dup 1)))]
2529 "")
2530
2972 "")
2973
2974(define_split
2975 [(set (match_operand:SF 0 "register_operand" "")
2976 (float:SF (match_operand:DI 1 "register_operand" "")))
2977 (clobber (match_operand:DI 2 "memory_operand" ""))]
2978 "TARGET_80387 && reload_completed"
2979 [(set (match_dup 2)
2980 (match_dup 1))
2981 (set (match_dup 0)
2982 (float:SF (match_dup 2)))]
2983 "")
2984
2985(define_insn ""
2986 [(set (match_operand:SF 0 "register_operand" "=f")
2987 (float:SF (match_operand:DI 1 "memory_operand" "m")))]
2988 "TARGET_80387"
2989 "* return AS1 (fild%z1,%1);"
2990 [(set_attr "type" "fpop")])
2991
2531(define_expand "floatsidf2"
2992(define_expand "floatsidf2"
2993 [(parallel [(set (match_operand:DF 0 "register_operand" "")
2994 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
2995 (clobber (match_dup 2))])]
2996 "TARGET_80387"
2997 "operands[2] = assign_386_stack_local (SImode, 0);")
2998
2999(define_insn ""
3000 [(set (match_operand:DF 0 "register_operand" "=f,f")
3001 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,!r")))
3002 (clobber (match_operand:SI 2 "memory_operand" "m,m"))]
3003 "TARGET_80387"
3004 "#")
3005
3006(define_split
2532 [(set (match_operand:DF 0 "register_operand" "")
3007 [(set (match_operand:DF 0 "register_operand" "")
2533 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
3008 (float:DF (match_operand:SI 1 "memory_operand" "")))
3009 (clobber (match_operand:SI 2 "memory_operand" ""))]
3010 "TARGET_80387 && reload_completed"
3011 [(set (match_dup 0)
3012 (float:DF (match_dup 1)))]
3013 "")
3014
3015(define_split
3016 [(set (match_operand:DF 0 "register_operand" "")
3017 (float:DF (match_operand:SI 1 "register_operand" "")))
3018 (clobber (match_operand:SI 2 "memory_operand" ""))]
3019 "TARGET_80387 && reload_completed"
3020 [(set (match_dup 2)
3021 (match_dup 1))
3022 (set (match_dup 0)
3023 (float:DF (match_dup 2)))]
3024 "")
3025
3026(define_insn ""
3027 [(set (match_operand:DF 0 "register_operand" "=f")
3028 (float:DF (match_operand:SI 1 "memory_operand" "m")))]
2534 "TARGET_80387"
3029 "TARGET_80387"
3030 "* return AS1 (fild%z1,%1);"
3031 [(set_attr "type" "fpop")])
3032
3033(define_expand "floathidf2"
3034 [(parallel [(set (match_operand:DF 0 "register_operand" "")
3035 (float:DF (match_operand:HI 1 "nonimmediate_operand" "")))
3036 (clobber (match_dup 2))])]
3037 "TARGET_80387"
3038 "operands[2] = assign_386_stack_local (HImode, 0);")
3039
3040(define_insn ""
3041 [(set (match_operand:DF 0 "register_operand" "=f,f")
3042 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,!r")))
3043 (clobber (match_operand:HI 2 "memory_operand" "m,m"))]
3044 "TARGET_80387"
3045 "#")
3046
3047(define_split
3048 [(set (match_operand:DF 0 "register_operand" "")
3049 (float:DF (match_operand:HI 1 "memory_operand" "")))
3050 (clobber (match_operand:HI 2 "memory_operand" ""))]
3051 "TARGET_80387 && reload_completed"
3052 [(set (match_dup 0)
3053 (float:DF (match_dup 1)))]
2535 "")
2536
3054 "")
3055
2537(define_expand "floatdidf2"
3056(define_split
2538 [(set (match_operand:DF 0 "register_operand" "")
3057 [(set (match_operand:DF 0 "register_operand" "")
2539 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
3058 (float:DF (match_operand:HI 1 "register_operand" "")))
3059 (clobber (match_operand:HI 2 "memory_operand" ""))]
3060 "TARGET_80387 && reload_completed"
3061 [(set (match_dup 2)
3062 (match_dup 1))
3063 (set (match_dup 0)
3064 (float:DF (match_dup 2)))]
3065 "")
3066
3067(define_insn ""
3068 [(set (match_operand:DF 0 "register_operand" "=f")
3069 (float:DF (match_operand:HI 1 "memory_operand" "m")))]
2540 "TARGET_80387"
3070 "TARGET_80387"
3071 "* return AS1 (fild%z1,%1);"
3072 [(set_attr "type" "fpop")])
3073
3074(define_expand "floatdidf2"
3075 [(parallel [(set (match_operand:DF 0 "register_operand" "")
3076 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))
3077 (clobber (match_dup 2))])]
3078 "TARGET_80387"
3079 "operands[2] = assign_386_stack_local (DImode, 0);")
3080
3081(define_insn ""
3082 [(set (match_operand:DF 0 "register_operand" "=f,f")
3083 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,!r")))
3084 (clobber (match_operand:DI 2 "memory_operand" "m,o"))]
3085 "TARGET_80387"
3086 "#")
3087
3088(define_split
3089 [(set (match_operand:DF 0 "register_operand" "")
3090 (float:DF (match_operand:DI 1 "memory_operand" "")))
3091 (clobber (match_operand:DI 2 "memory_operand" ""))]
3092 "TARGET_80387 && reload_completed"
3093 [(set (match_dup 0)
3094 (float:DF (match_dup 1)))]
2541 "")
2542
3095 "")
3096
3097(define_split
3098 [(set (match_operand:DF 0 "register_operand" "")
3099 (float:DF (match_operand:DI 1 "register_operand" "")))
3100 (clobber (match_operand:DI 2 "memory_operand" ""))]
3101 "TARGET_80387 && reload_completed"
3102 [(set (match_dup 2)
3103 (match_dup 1))
3104 (set (match_dup 0)
3105 (float:DF (match_dup 2)))]
3106 "")
3107
3108(define_insn ""
3109 [(set (match_operand:DF 0 "register_operand" "=f")
3110 (float:DF (match_operand:DI 1 "memory_operand" "m")))]
3111 "TARGET_80387"
3112 "* return AS1 (fild%z1,%1);"
3113 [(set_attr "type" "fpop")])
3114
2543(define_expand "floatsixf2"
3115(define_expand "floatsixf2"
2544 [(set (match_operand:XF 0 "register_operand" "")
2545 (float:XF (match_operand:SI 1 "nonimmediate_operand" "")))]
3116 [(parallel [(set (match_operand:XF 0 "register_operand" "")
3117 (float:XF (match_operand:SI 1 "nonimmediate_operand" "")))
3118 (clobber (match_dup 2))])]
2546 "TARGET_80387"
3119 "TARGET_80387"
3120 "operands[2] = assign_386_stack_local (SImode, 0);")
3121
3122(define_insn ""
3123 [(set (match_operand:XF 0 "register_operand" "=f,f")
3124 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,!r")))
3125 (clobber (match_operand:SI 2 "memory_operand" "m,m"))]
3126 "TARGET_80387"
3127 "#")
3128
3129(define_split
3130 [(set (match_operand:XF 0 "register_operand" "")
3131 (float:XF (match_operand:SI 1 "memory_operand" "")))
3132 (clobber (match_operand:SI 2 "memory_operand" ""))]
3133 "TARGET_80387 && reload_completed"
3134 [(set (match_dup 0)
3135 (float:XF (match_dup 1)))]
2547 "")
2548
3136 "")
3137
2549(define_expand "floatdixf2"
3138(define_split
2550 [(set (match_operand:XF 0 "register_operand" "")
3139 [(set (match_operand:XF 0 "register_operand" "")
2551 (float:XF (match_operand:DI 1 "nonimmediate_operand" "")))]
2552 "TARGET_80387 && LONG_DOUBLE_TYPE_SIZE == 96"
3140 (float:XF (match_operand:SI 1 "register_operand" "")))
3141 (clobber (match_operand:SI 2 "memory_operand" ""))]
3142 "TARGET_80387 && reload_completed"
3143 [(set (match_dup 2)
3144 (match_dup 1))
3145 (set (match_dup 0)
3146 (float:XF (match_dup 2)))]
2553 "")
2554
3147 "")
3148
2555;; This will convert from SImode or DImode to MODE_FLOAT.
2556
2557(define_insn ""
2558 [(set (match_operand:XF 0 "register_operand" "=f")
3149(define_insn ""
3150 [(set (match_operand:XF 0 "register_operand" "=f")
2559 (float:XF (match_operand:DI 1 "nonimmediate_operand" "rm")))]
3151 (float:XF (match_operand:SI 1 "memory_operand" "m")))]
2560 "TARGET_80387"
3152 "TARGET_80387"
2561 "*
2562{
2563 if (NON_STACK_REG_P (operands[1]))
2564 {
2565 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
2566 RET;
2567 }
2568 else if (GET_CODE (operands[1]) == MEM)
2569 return AS1 (fild%z1,%1);
2570 else
2571 abort ();
2572}")
3153 "* return AS1 (fild%z1,%1);"
3154 [(set_attr "type" "fpop")])
2573
3155
2574(define_insn ""
2575 [(set (match_operand:DF 0 "register_operand" "=f")
2576 (float:DF (match_operand:DI 1 "nonimmediate_operand" "rm")))]
3156(define_expand "floathixf2"
3157 [(parallel [(set (match_operand:XF 0 "register_operand" "")
3158 (float:XF (match_operand:HI 1 "nonimmediate_operand" "")))
3159 (clobber (match_dup 2))])]
2577 "TARGET_80387"
3160 "TARGET_80387"
2578 "*
2579{
2580 if (NON_STACK_REG_P (operands[1]))
2581 {
2582 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
2583 RET;
2584 }
2585 else if (GET_CODE (operands[1]) == MEM)
2586 return AS1 (fild%z1,%1);
2587 else
2588 abort ();
2589}")
3161 "operands[2] = assign_386_stack_local (HImode, 0);")
2590
2591(define_insn ""
3162
3163(define_insn ""
2592 [(set (match_operand:SF 0 "register_operand" "=f")
2593 (float:SF (match_operand:DI 1 "nonimmediate_operand" "rm")))]
3164 [(set (match_operand:XF 0 "register_operand" "=f,f")
3165 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,!r")))
3166 (clobber (match_operand:HI 2 "memory_operand" "m,m"))]
2594 "TARGET_80387"
3167 "TARGET_80387"
2595 "*
2596{
2597 if (NON_STACK_REG_P (operands[1]))
2598 {
2599 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
2600 RET;
2601 }
2602 else if (GET_CODE (operands[1]) == MEM)
2603 return AS1 (fild%z1,%1);
2604 else
2605 abort ();
2606}")
3168 "#")
2607
3169
3170(define_split
3171 [(set (match_operand:XF 0 "register_operand" "")
3172 (float:XF (match_operand:HI 1 "memory_operand" "")))
3173 (clobber (match_operand:HI 2 "memory_operand" ""))]
3174 "TARGET_80387 && reload_completed"
3175 [(set (match_dup 0)
3176 (float:XF (match_dup 1)))]
3177 "")
3178
3179(define_split
3180 [(set (match_operand:XF 0 "register_operand" "")
3181 (float:XF (match_operand:HI 1 "register_operand" "")))
3182 (clobber (match_operand:HI 2 "memory_operand" ""))]
3183 "TARGET_80387 && reload_completed"
3184 [(set (match_dup 2)
3185 (match_dup 1))
3186 (set (match_dup 0)
3187 (float:XF (match_dup 2)))]
3188 "")
3189
2608(define_insn ""
3190(define_insn ""
2609 [(set (match_operand:DF 0 "register_operand" "=f")
2610 (float:DF (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3191 [(set (match_operand:XF 0 "register_operand" "=f")
3192 (float:XF (match_operand:HI 1 "memory_operand" "m")))]
2611 "TARGET_80387"
3193 "TARGET_80387"
2612 "*
2613{
2614 if (NON_STACK_REG_P (operands[1]))
2615 {
2616 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
2617 RET;
2618 }
2619 else if (GET_CODE (operands[1]) == MEM)
2620 return AS1 (fild%z1,%1);
2621 else
2622 abort ();
2623}")
3194 "* return AS1 (fild%z1,%1);"
3195 [(set_attr "type" "fpop")])
2624
3196
3197(define_expand "floatdixf2"
3198 [(parallel [(set (match_operand:XF 0 "register_operand" "")
3199 (float:XF (match_operand:DI 1 "nonimmediate_operand" "")))
3200 (clobber (match_dup 2))])]
3201 "TARGET_80387"
3202 "operands[2] = assign_386_stack_local (DImode, 0);")
3203
2625(define_insn ""
2626 [(set (match_operand:XF 0 "register_operand" "=f,f")
3204(define_insn ""
3205 [(set (match_operand:XF 0 "register_operand" "=f,f")
2627 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,!*r")))]
3206 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,!r")))
3207 (clobber (match_operand:DI 2 "memory_operand" "m,o"))]
2628 "TARGET_80387"
3208 "TARGET_80387"
2629 "*
2630{
2631 if (NON_STACK_REG_P (operands[1]))
2632 {
2633 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
2634 RET;
2635 }
2636 else if (GET_CODE (operands[1]) == MEM)
2637 return AS1 (fild%z1,%1);
2638 else
2639 abort ();
2640}")
3209 "#")
2641
3210
3211(define_split
3212 [(set (match_operand:XF 0 "register_operand" "")
3213 (float:XF (match_operand:DI 1 "memory_operand" "")))
3214 (clobber (match_operand:DI 2 "memory_operand" ""))]
3215 "TARGET_80387 && reload_completed"
3216 [(set (match_dup 0)
3217 (float:XF (match_dup 1)))]
3218 "")
3219
3220(define_split
3221 [(set (match_operand:XF 0 "register_operand" "")
3222 (float:XF (match_operand:DI 1 "register_operand" "")))
3223 (clobber (match_operand:DI 2 "memory_operand" ""))]
3224 "TARGET_80387 && reload_completed"
3225 [(set (match_dup 2)
3226 (match_dup 1))
3227 (set (match_dup 0)
3228 (float:XF (match_dup 2)))]
3229 "")
3230
2642(define_insn ""
3231(define_insn ""
2643 [(set (match_operand:SF 0 "register_operand" "=f")
2644 (float:SF (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3232 [(set (match_operand:XF 0 "register_operand" "=f")
3233 (float:XF (match_operand:DI 1 "memory_operand" "m")))]
2645 "TARGET_80387"
3234 "TARGET_80387"
2646 "*
2647{
2648 if (NON_STACK_REG_P (operands[1]))
2649 {
2650 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
2651 RET;
2652 }
2653 else if (GET_CODE (operands[1]) == MEM)
2654 return AS1 (fild%z1,%1);
2655 else
2656 abort ();
2657}")
3235 "* return AS1 (fild%z1,%1);"
3236 [(set_attr "type" "fpop")])
2658
2659;;- add instructions
2660
3237
3238;;- add instructions
3239
2661(define_insn "addsidi3_1"
3240(define_insn "*addsidi3_1"
2662 [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r,o,!&r,!r,o,!o")
2663 (plus:DI (match_operand:DI 1 "general_operand" "0,0,0,o,riF,riF,o")
2664 (zero_extend:DI (match_operand:SI 2 "general_operand" "o,ri,ri,roi,roi,ri,ri"))))
2665 (clobber (match_scratch:SI 3 "=X,X,X,X,X,X,&r"))]
2666 ""
2667 "*
2668{
3241 [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r,o,!&r,!r,o,!o")
3242 (plus:DI (match_operand:DI 1 "general_operand" "0,0,0,o,riF,riF,o")
3243 (zero_extend:DI (match_operand:SI 2 "general_operand" "o,ri,ri,roi,roi,ri,ri"))))
3244 (clobber (match_scratch:SI 3 "=X,X,X,X,X,X,&r"))]
3245 ""
3246 "*
3247{
2669 rtx low[3], high[3], xops[7], temp;
3248 rtx low[3], high[3], xops[7];
2670
2671 CC_STATUS_INIT;
2672
2673 split_di (operands, 2, low, high);
2674 high[2] = const0_rtx;
2675 low[2] = operands[2];
2676
2677 if (!rtx_equal_p (operands[0], operands[1]))

--- 20 unchanged lines hidden (view full) ---

2698 output_asm_insn (AS2 (adc%L6,%4,%6), xops);
2699 output_asm_insn (AS2 (mov%L0,%6,%0), xops);
2700 RET;
2701 }
2702 }
2703
2704 output_asm_insn (AS2 (add%L0,%2,%0), low);
2705 output_asm_insn (AS2 (adc%L0,%2,%0), high);
3249
3250 CC_STATUS_INIT;
3251
3252 split_di (operands, 2, low, high);
3253 high[2] = const0_rtx;
3254 low[2] = operands[2];
3255
3256 if (!rtx_equal_p (operands[0], operands[1]))

--- 20 unchanged lines hidden (view full) ---

3277 output_asm_insn (AS2 (adc%L6,%4,%6), xops);
3278 output_asm_insn (AS2 (mov%L0,%6,%0), xops);
3279 RET;
3280 }
3281 }
3282
3283 output_asm_insn (AS2 (add%L0,%2,%0), low);
3284 output_asm_insn (AS2 (adc%L0,%2,%0), high);
3285 cc_status.value1 = high[0];
3286 cc_status.flags = CC_NO_OVERFLOW;
2706 RET;
3287 RET;
2707}")
3288}"
3289 [(set_attr "type" "binary")])
2708
2709(define_insn "addsidi3_2"
2710 [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r,o,&r,!&r,&r,o,o,!o")
2711 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "o,ri,ri,o,o,ri,ri,i,r"))
2712 (match_operand:DI 1 "general_operand" "0,0,0,iF,ro,roiF,riF,o,o")))
2713 (clobber (match_scratch:SI 3 "=X,X,X,X,X,X,X,&r,&r"))]
2714 ""
2715 "*
2716{
3290
3291(define_insn "addsidi3_2"
3292 [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r,o,&r,!&r,&r,o,o,!o")
3293 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "o,ri,ri,o,o,ri,ri,i,r"))
3294 (match_operand:DI 1 "general_operand" "0,0,0,iF,ro,roiF,riF,o,o")))
3295 (clobber (match_scratch:SI 3 "=X,X,X,X,X,X,X,&r,&r"))]
3296 ""
3297 "*
3298{
2717 rtx low[3], high[3], xops[7], temp;
3299 rtx low[3], high[3], xops[7];
2718
2719 CC_STATUS_INIT;
2720
2721 split_di (operands, 2, low, high);
2722 high[2] = const0_rtx;
2723 low[2] = operands[2];
2724
2725 if (!rtx_equal_p (operands[0], operands[1]))

--- 50 unchanged lines hidden (view full) ---

2776 output_asm_insn (AS2 (adc%L6,%4,%6), xops);
2777 output_asm_insn (AS2 (mov%L0,%6,%0), xops);
2778 RET;
2779 }
2780 }
2781
2782 output_asm_insn (AS2 (add%L0,%2,%0), low);
2783 output_asm_insn (AS2 (adc%L0,%2,%0), high);
3300
3301 CC_STATUS_INIT;
3302
3303 split_di (operands, 2, low, high);
3304 high[2] = const0_rtx;
3305 low[2] = operands[2];
3306
3307 if (!rtx_equal_p (operands[0], operands[1]))

--- 50 unchanged lines hidden (view full) ---

3358 output_asm_insn (AS2 (adc%L6,%4,%6), xops);
3359 output_asm_insn (AS2 (mov%L0,%6,%0), xops);
3360 RET;
3361 }
3362 }
3363
3364 output_asm_insn (AS2 (add%L0,%2,%0), low);
3365 output_asm_insn (AS2 (adc%L0,%2,%0), high);
3366 cc_status.value1 = high[0];
3367 cc_status.flags = CC_NO_OVERFLOW;
2784 RET;
3368 RET;
2785}")
3369}"
3370 [(set_attr "type" "binary")])
2786
2787(define_insn "adddi3"
2788 [(set (match_operand:DI 0 "general_operand" "=&r,&ro,!r,o,!&r,!o,!o")
2789 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0iF,or,riF,o")
2790 (match_operand:DI 2 "general_operand" "o,riF,0,or,or,oriF,o")))
2791 (clobber (match_scratch:SI 3 "=X,X,X,&r,X,&r,&r"))]
2792 ""
2793 "*

--- 32 unchanged lines hidden (view full) ---

2826 output_asm_insn (AS2 (mov%L1,%6,%1), xops);
2827 output_asm_insn (AS2 (mov%L6,%2,%6), xops);
2828 output_asm_insn (AS2 (adc%L6,%4,%6), xops);
2829 output_asm_insn (AS2 (mov%L0,%6,%0), xops);
2830 RET;
2831 }
2832 }
2833
3371
3372(define_insn "adddi3"
3373 [(set (match_operand:DI 0 "general_operand" "=&r,&ro,!r,o,!&r,!o,!o")
3374 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0iF,or,riF,o")
3375 (match_operand:DI 2 "general_operand" "o,riF,0,or,or,oriF,o")))
3376 (clobber (match_scratch:SI 3 "=X,X,X,&r,X,&r,&r"))]
3377 ""
3378 "*

--- 32 unchanged lines hidden (view full) ---

3411 output_asm_insn (AS2 (mov%L1,%6,%1), xops);
3412 output_asm_insn (AS2 (mov%L6,%2,%6), xops);
3413 output_asm_insn (AS2 (adc%L6,%4,%6), xops);
3414 output_asm_insn (AS2 (mov%L0,%6,%0), xops);
3415 RET;
3416 }
3417 }
3418
3419 cc_status.value1 = high[0];
3420 cc_status.flags = CC_NO_OVERFLOW;
3421
2834 if (GET_CODE (operands[3]) == REG && GET_CODE (operands[2]) != REG)
2835 {
2836 xops[0] = high[0];
2837 xops[1] = low[0];
2838 xops[2] = high[2];
2839 xops[3] = low[2];
2840 xops[4] = operands[3];
2841

--- 8 unchanged lines hidden (view full) ---

2850 output_asm_insn (AS2 (add%L0,%2,%0), low);
2851 output_asm_insn (AS2 (adc%L0,%2,%0), high);
2852 }
2853
2854 else
2855 output_asm_insn (AS2 (add%L0,%2,%0), high);
2856
2857 RET;
3422 if (GET_CODE (operands[3]) == REG && GET_CODE (operands[2]) != REG)
3423 {
3424 xops[0] = high[0];
3425 xops[1] = low[0];
3426 xops[2] = high[2];
3427 xops[3] = low[2];
3428 xops[4] = operands[3];
3429

--- 8 unchanged lines hidden (view full) ---

3438 output_asm_insn (AS2 (add%L0,%2,%0), low);
3439 output_asm_insn (AS2 (adc%L0,%2,%0), high);
3440 }
3441
3442 else
3443 output_asm_insn (AS2 (add%L0,%2,%0), high);
3444
3445 RET;
2858}")
3446}"
3447 [(set_attr "type" "binary")])
2859
2860;; On a 486, it is faster to do movl/addl than to do a single leal if
2861;; operands[1] and operands[2] are both registers.
2862
2863(define_expand "addsi3"
2864 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2865 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
2866 (match_operand:SI 2 "general_operand" "")))]
2867 ""
2868 "IX86_EXPAND_BINARY_OPERATOR (PLUS, SImode, operands);")
2869
2870(define_insn ""
2871 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
2872 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
2873 (match_operand:SI 2 "general_operand" "rmi,ri,ri")))]
2874 "ix86_binary_operator_ok (PLUS, SImode, operands)"
2875 "*
2876{
2877 if (REG_P (operands[0]) && REG_P (operands[1])
3448
3449;; On a 486, it is faster to do movl/addl than to do a single leal if
3450;; operands[1] and operands[2] are both registers.
3451
3452(define_expand "addsi3"
3453 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3454 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
3455 (match_operand:SI 2 "general_operand" "")))]
3456 ""
3457 "IX86_EXPAND_BINARY_OPERATOR (PLUS, SImode, operands);")
3458
3459(define_insn ""
3460 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
3461 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
3462 (match_operand:SI 2 "general_operand" "rmi,ri,ri")))]
3463 "ix86_binary_operator_ok (PLUS, SImode, operands)"
3464 "*
3465{
3466 if (REG_P (operands[0]) && REG_P (operands[1])
2878 && (REG_P (operands[2]) || GET_CODE (operands[2]) == CONST_INT)
3467 && (REG_P (operands[2]) || CONSTANT_P (operands[2]))
2879 && REGNO (operands[0]) != REGNO (operands[1]))
2880 {
2881 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
2882 return AS2 (add%L0,%1,%0);
2883
2884 if (operands[2] == stack_pointer_rtx)
2885 {
2886 rtx temp;

--- 28 unchanged lines hidden (view full) ---

2915 * as add%L0, but we use inc and dec above and they
2916 * don't set the carry bit at all. If inc/dec don't need
2917 * a CC_STATUS_INIT, this doesn't either... */
2918 operands[2] = GEN_INT (-128);
2919 return AS2 (sub%L0,%2,%0);
2920 }
2921
2922 return AS2 (add%L0,%2,%0);
3468 && REGNO (operands[0]) != REGNO (operands[1]))
3469 {
3470 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
3471 return AS2 (add%L0,%1,%0);
3472
3473 if (operands[2] == stack_pointer_rtx)
3474 {
3475 rtx temp;

--- 28 unchanged lines hidden (view full) ---

3504 * as add%L0, but we use inc and dec above and they
3505 * don't set the carry bit at all. If inc/dec don't need
3506 * a CC_STATUS_INIT, this doesn't either... */
3507 operands[2] = GEN_INT (-128);
3508 return AS2 (sub%L0,%2,%0);
3509 }
3510
3511 return AS2 (add%L0,%2,%0);
2923}")
3512}"
3513 [(set_attr "type" "binary")])
2924
2925;; addsi3 is faster, so put this after.
2926
2927(define_insn "movsi_lea"
2928 [(set (match_operand:SI 0 "register_operand" "=r")
2929 (match_operand:QI 1 "address_operand" "p"))]
2930 ""
2931 "*

--- 12 unchanged lines hidden (view full) ---

2944 if (operands[1] == constm1_rtx)
2945 return AS1 (dec%L0,%0);
2946
2947 return AS2 (add%L0,%1,%0);
2948 }
2949
2950 CC_STATUS_INIT;
2951 return AS2 (lea%L0,%a1,%0);
3514
3515;; addsi3 is faster, so put this after.
3516
3517(define_insn "movsi_lea"
3518 [(set (match_operand:SI 0 "register_operand" "=r")
3519 (match_operand:QI 1 "address_operand" "p"))]
3520 ""
3521 "*

--- 12 unchanged lines hidden (view full) ---

3534 if (operands[1] == constm1_rtx)
3535 return AS1 (dec%L0,%0);
3536
3537 return AS2 (add%L0,%1,%0);
3538 }
3539
3540 CC_STATUS_INIT;
3541 return AS2 (lea%L0,%a1,%0);
2952}")
3542}"
3543 [(set_attr "type" "lea")])
2953
2954;; ??? `lea' here, for three operand add? If leaw is used, only %bx,
2955;; %si and %di can appear in SET_SRC, and output_asm_insn might not be
2956;; able to handle the operand. But leal always works?
2957
2958(define_expand "addhi3"
2959 [(set (match_operand:HI 0 "general_operand" "")
2960 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
2961 (match_operand:HI 2 "general_operand" "")))]
2962 ""
2963 "IX86_EXPAND_BINARY_OPERATOR (PLUS, HImode, operands);")
2964
2965(define_insn ""
3544
3545;; ??? `lea' here, for three operand add? If leaw is used, only %bx,
3546;; %si and %di can appear in SET_SRC, and output_asm_insn might not be
3547;; able to handle the operand. But leal always works?
3548
3549(define_expand "addhi3"
3550 [(set (match_operand:HI 0 "general_operand" "")
3551 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
3552 (match_operand:HI 2 "general_operand" "")))]
3553 ""
3554 "IX86_EXPAND_BINARY_OPERATOR (PLUS, HImode, operands);")
3555
3556(define_insn ""
2966 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
2967 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
2968 (match_operand:HI 2 "general_operand" "ri,rm")))]
3557 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,?r")
3558 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
3559 (match_operand:HI 2 "general_operand" "ri,rm,ri")))]
2969 "ix86_binary_operator_ok (PLUS, HImode, operands)"
2970 "*
2971{
3560 "ix86_binary_operator_ok (PLUS, HImode, operands)"
3561 "*
3562{
3563 if (REG_P (operands[0]) && REG_P (operands[1])
3564 && (REG_P (operands[2]) || CONSTANT_P (operands[2]))
3565 && REGNO (operands[0]) != REGNO (operands[1]))
3566 {
3567 if (operands[2] == stack_pointer_rtx)
3568 abort ();
3569
3570 CC_STATUS_INIT;
3571 operands[1]
3572 = gen_rtx_PLUS (SImode,
3573 gen_rtx_REG (SImode, REGNO (operands[1])),
3574 (! REG_P (operands[2])
3575 ? operands[2]
3576 : gen_rtx_REG (SImode, REGNO (operands[2]))));
3577 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
3578 return AS2 (lea%L0,%a1,%0);
3579 }
3580
2972 /* ??? what about offsettable memory references? */
2973 if (!TARGET_PENTIUMPRO /* partial stalls are just too painful to risk. */
2974 && QI_REG_P (operands[0])
2975 && GET_CODE (operands[2]) == CONST_INT
2976 && (INTVAL (operands[2]) & 0xff) == 0
2977 && i386_cc_probably_useless_p (insn))
2978 {
2979 int byteval = (INTVAL (operands[2]) >> 8) & 0xff;

--- 34 unchanged lines hidden (view full) ---

3014 return AS1 (inc%W0,%0);
3015
3016 if (operands[2] == constm1_rtx
3017 || (GET_CODE (operands[2]) == CONST_INT
3018 && INTVAL (operands[2]) == 65535))
3019 return AS1 (dec%W0,%0);
3020
3021 return AS2 (add%W0,%2,%0);
3581 /* ??? what about offsettable memory references? */
3582 if (!TARGET_PENTIUMPRO /* partial stalls are just too painful to risk. */
3583 && QI_REG_P (operands[0])
3584 && GET_CODE (operands[2]) == CONST_INT
3585 && (INTVAL (operands[2]) & 0xff) == 0
3586 && i386_cc_probably_useless_p (insn))
3587 {
3588 int byteval = (INTVAL (operands[2]) >> 8) & 0xff;

--- 34 unchanged lines hidden (view full) ---

3623 return AS1 (inc%W0,%0);
3624
3625 if (operands[2] == constm1_rtx
3626 || (GET_CODE (operands[2]) == CONST_INT
3627 && INTVAL (operands[2]) == 65535))
3628 return AS1 (dec%W0,%0);
3629
3630 return AS2 (add%W0,%2,%0);
3022}")
3631}"
3632 [(set_attr "type" "binary")])
3023
3024(define_expand "addqi3"
3025 [(set (match_operand:QI 0 "general_operand" "")
3026 (plus:QI (match_operand:QI 1 "general_operand" "")
3027 (match_operand:QI 2 "general_operand" "")))]
3028 ""
3029 "IX86_EXPAND_BINARY_OPERATOR (PLUS, QImode, operands);")
3030
3031(define_insn ""
3633
3634(define_expand "addqi3"
3635 [(set (match_operand:QI 0 "general_operand" "")
3636 (plus:QI (match_operand:QI 1 "general_operand" "")
3637 (match_operand:QI 2 "general_operand" "")))]
3638 ""
3639 "IX86_EXPAND_BINARY_OPERATOR (PLUS, QImode, operands);")
3640
3641(define_insn ""
3032 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
3033 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
3034 (match_operand:QI 2 "general_operand" "qn,qmn")))]
3642 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,?q")
3643 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,q")
3644 (match_operand:QI 2 "general_operand" "qn,qmn,qn")))]
3035 "ix86_binary_operator_ok (PLUS, QImode, operands)"
3036 "*
3037{
3645 "ix86_binary_operator_ok (PLUS, QImode, operands)"
3646 "*
3647{
3648 if (REG_P (operands[0]) && REG_P (operands[1])
3649 && (REG_P (operands[2]) || CONSTANT_P (operands[2]))
3650 && (REGNO (operands[0]) != REGNO (operands[1])
3651 || NON_QI_REG_P (operands[1])
3652 || (REG_P (operands[2]) && NON_QI_REG_P (operands[2]))))
3653 {
3654 if (operands[2] == stack_pointer_rtx)
3655 abort ();
3656
3657 CC_STATUS_INIT;
3658 operands[1]
3659 = gen_rtx_PLUS (SImode,
3660 gen_rtx_REG (SImode, REGNO (operands[1])),
3661 (! REG_P (operands[2])
3662 ? operands[2]
3663 : gen_rtx_REG (SImode, REGNO (operands[2]))));
3664 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
3665 return AS2 (lea%L0,%a1,%0);
3666 }
3038 if (operands[2] == const1_rtx)
3039 return AS1 (inc%B0,%0);
3040
3041 if (operands[2] == constm1_rtx
3042 || (GET_CODE (operands[2]) == CONST_INT
3043 && INTVAL (operands[2]) == 255))
3044 return AS1 (dec%B0,%0);
3045
3046 return AS2 (add%B0,%2,%0);
3667 if (operands[2] == const1_rtx)
3668 return AS1 (inc%B0,%0);
3669
3670 if (operands[2] == constm1_rtx
3671 || (GET_CODE (operands[2]) == CONST_INT
3672 && INTVAL (operands[2]) == 255))
3673 return AS1 (dec%B0,%0);
3674
3675 return AS2 (add%B0,%2,%0);
3047}")
3676}"
3677 [(set_attr "type" "binary")])
3048
3049;Lennart Augustsson <augustss@cs.chalmers.se>
3050;says this pattern just makes slower code:
3051; pushl %ebp
3052; addl $-80,(%esp)
3053;instead of
3054; leal -80(%ebp),%eax
3055; pushl %eax

--- 80 unchanged lines hidden (view full) ---

3136 output_asm_insn (AS2 (sbb%L6,%4,%6), xops);
3137 output_asm_insn (AS2 (mov%L0,%6,%0), xops);
3138 RET;
3139 }
3140 }
3141
3142 output_asm_insn (AS2 (sub%L0,%2,%0), low);
3143 output_asm_insn (AS2 (sbb%L0,%2,%0), high);
3678
3679;Lennart Augustsson <augustss@cs.chalmers.se>
3680;says this pattern just makes slower code:
3681; pushl %ebp
3682; addl $-80,(%esp)
3683;instead of
3684; leal -80(%ebp),%eax
3685; pushl %eax

--- 80 unchanged lines hidden (view full) ---

3766 output_asm_insn (AS2 (sbb%L6,%4,%6), xops);
3767 output_asm_insn (AS2 (mov%L0,%6,%0), xops);
3768 RET;
3769 }
3770 }
3771
3772 output_asm_insn (AS2 (sub%L0,%2,%0), low);
3773 output_asm_insn (AS2 (sbb%L0,%2,%0), high);
3774 cc_status.value1 = high[0];
3775 cc_status.flags = CC_NO_OVERFLOW;
3776
3144 RET;
3777 RET;
3145}")
3778}"
3779 [(set_attr "type" "binary")])
3146
3147(define_insn "subdi3"
3148 [(set (match_operand:DI 0 "general_operand" "=&r,&ro,o,o,!&r,!o")
3149 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0iF,or,roiF,roiF")
3150 (match_operand:DI 2 "general_operand" "or,riF,or,iF,roiF,roiF")))
3151 (clobber (match_scratch:SI 3 "=X,X,&r,&r,X,&r"))]
3152 ""
3153 "*

--- 26 unchanged lines hidden (view full) ---

3180 output_asm_insn (AS2 (mov%L1,%6,%1), xops);
3181 output_asm_insn (AS2 (mov%L6,%2,%6), xops);
3182 output_asm_insn (AS2 (sbb%L6,%4,%6), xops);
3183 output_asm_insn (AS2 (mov%L0,%6,%0), xops);
3184 RET;
3185 }
3186 }
3187
3780
3781(define_insn "subdi3"
3782 [(set (match_operand:DI 0 "general_operand" "=&r,&ro,o,o,!&r,!o")
3783 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0iF,or,roiF,roiF")
3784 (match_operand:DI 2 "general_operand" "or,riF,or,iF,roiF,roiF")))
3785 (clobber (match_scratch:SI 3 "=X,X,&r,&r,X,&r"))]
3786 ""
3787 "*

--- 26 unchanged lines hidden (view full) ---

3814 output_asm_insn (AS2 (mov%L1,%6,%1), xops);
3815 output_asm_insn (AS2 (mov%L6,%2,%6), xops);
3816 output_asm_insn (AS2 (sbb%L6,%4,%6), xops);
3817 output_asm_insn (AS2 (mov%L0,%6,%0), xops);
3818 RET;
3819 }
3820 }
3821
3822 cc_status.value1 = high[0];
3823 cc_status.flags = CC_NO_OVERFLOW;
3824
3188 if (GET_CODE (operands[3]) == REG)
3189 {
3190 xops[0] = high[0];
3191 xops[1] = low[0];
3192 xops[2] = high[2];
3193 xops[3] = low[2];
3194 xops[4] = operands[3];
3195

--- 5 unchanged lines hidden (view full) ---

3201
3202 else if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0)
3203 {
3204 output_asm_insn (AS2 (sub%L0,%2,%0), low);
3205 output_asm_insn (AS2 (sbb%L0,%2,%0), high);
3206 }
3207
3208 else
3825 if (GET_CODE (operands[3]) == REG)
3826 {
3827 xops[0] = high[0];
3828 xops[1] = low[0];
3829 xops[2] = high[2];
3830 xops[3] = low[2];
3831 xops[4] = operands[3];
3832

--- 5 unchanged lines hidden (view full) ---

3838
3839 else if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0)
3840 {
3841 output_asm_insn (AS2 (sub%L0,%2,%0), low);
3842 output_asm_insn (AS2 (sbb%L0,%2,%0), high);
3843 }
3844
3845 else
3209 output_asm_insn (AS2 (sub%L0,%2,%0), high);
3846 output_asm_insn (AS2 (sub%L0,%2,%0), high);
3210
3847
3848
3211 RET;
3849 RET;
3212}")
3850}"
3851 [(set_attr "type" "binary")])
3213
3214(define_expand "subsi3"
3215 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3216 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
3217 (match_operand:SI 2 "general_operand" "")))]
3218 ""
3219 "IX86_EXPAND_BINARY_OPERATOR (MINUS, SImode, operands);")
3220
3221(define_insn ""
3222 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
3223 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
3224 (match_operand:SI 2 "general_operand" "ri,rm")))]
3225 "ix86_binary_operator_ok (MINUS, SImode, operands)"
3852
3853(define_expand "subsi3"
3854 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3855 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
3856 (match_operand:SI 2 "general_operand" "")))]
3857 ""
3858 "IX86_EXPAND_BINARY_OPERATOR (MINUS, SImode, operands);")
3859
3860(define_insn ""
3861 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
3862 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
3863 (match_operand:SI 2 "general_operand" "ri,rm")))]
3864 "ix86_binary_operator_ok (MINUS, SImode, operands)"
3226 "* return AS2 (sub%L0,%2,%0);")
3865 "* return AS2 (sub%L0,%2,%0);"
3866 [(set_attr "type" "binary")])
3227
3228(define_expand "subhi3"
3229 [(set (match_operand:HI 0 "general_operand" "")
3230 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
3231 (match_operand:HI 2 "general_operand" "")))]
3232 ""
3233 "IX86_EXPAND_BINARY_OPERATOR (MINUS, HImode, operands);")
3234

--- 8 unchanged lines hidden (view full) ---

3243 && i386_aligned_p (operands[2])
3244 && i386_cc_probably_useless_p (insn))
3245 {
3246 CC_STATUS_INIT;
3247 operands[2] = i386_sext16_if_const (operands[2]);
3248 return AS2 (sub%L0,%k2,%k0);
3249 }
3250 return AS2 (sub%W0,%2,%0);
3867
3868(define_expand "subhi3"
3869 [(set (match_operand:HI 0 "general_operand" "")
3870 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
3871 (match_operand:HI 2 "general_operand" "")))]
3872 ""
3873 "IX86_EXPAND_BINARY_OPERATOR (MINUS, HImode, operands);")
3874

--- 8 unchanged lines hidden (view full) ---

3883 && i386_aligned_p (operands[2])
3884 && i386_cc_probably_useless_p (insn))
3885 {
3886 CC_STATUS_INIT;
3887 operands[2] = i386_sext16_if_const (operands[2]);
3888 return AS2 (sub%L0,%k2,%k0);
3889 }
3890 return AS2 (sub%W0,%2,%0);
3251}")
3891}"
3892 [(set_attr "type" "binary")])
3252
3253(define_expand "subqi3"
3254 [(set (match_operand:QI 0 "general_operand" "")
3255 (minus:QI (match_operand:QI 1 "general_operand" "")
3256 (match_operand:QI 2 "general_operand" "")))]
3257 ""
3258 "IX86_EXPAND_BINARY_OPERATOR (MINUS, QImode, operands);")
3259
3260(define_insn ""
3261 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
3262 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
3263 (match_operand:QI 2 "general_operand" "qn,qmn")))]
3264 "ix86_binary_operator_ok (MINUS, QImode, operands)"
3893
3894(define_expand "subqi3"
3895 [(set (match_operand:QI 0 "general_operand" "")
3896 (minus:QI (match_operand:QI 1 "general_operand" "")
3897 (match_operand:QI 2 "general_operand" "")))]
3898 ""
3899 "IX86_EXPAND_BINARY_OPERATOR (MINUS, QImode, operands);")
3900
3901(define_insn ""
3902 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
3903 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
3904 (match_operand:QI 2 "general_operand" "qn,qmn")))]
3905 "ix86_binary_operator_ok (MINUS, QImode, operands)"
3265 "* return AS2 (sub%B0,%2,%0);")
3906 "* return AS2 (sub%B0,%2,%0);"
3907 [(set_attr "type" "binary")])
3266
3267;; The patterns that match these are at the end of this file.
3268
3269(define_expand "subxf3"
3270 [(set (match_operand:XF 0 "register_operand" "")
3271 (minus:XF (match_operand:XF 1 "register_operand" "")
3272 (match_operand:XF 2 "register_operand" "")))]
3273 "TARGET_80387"

--- 409 unchanged lines hidden (view full) ---

3683 goto word_zero_and_operation;
3684 }
3685
3686 default:
3687 break;
3688 }
3689
3690 return AS2 (and%L0,%2,%0);
3908
3909;; The patterns that match these are at the end of this file.
3910
3911(define_expand "subxf3"
3912 [(set (match_operand:XF 0 "register_operand" "")
3913 (minus:XF (match_operand:XF 1 "register_operand" "")
3914 (match_operand:XF 2 "register_operand" "")))]
3915 "TARGET_80387"

--- 409 unchanged lines hidden (view full) ---

4325 goto word_zero_and_operation;
4326 }
4327
4328 default:
4329 break;
4330 }
4331
4332 return AS2 (and%L0,%2,%0);
3691}")
4333}"
4334 [(set_attr "type" "binary")])
3692
3693(define_insn "andhi3"
3694 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
3695 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
3696 (match_operand:HI 2 "general_operand" "ri,rm")))]
3697 ""
3698 "*
3699{

--- 61 unchanged lines hidden (view full) ---

3761 CC_STATUS_INIT;
3762 val |= ~0xffff;
3763 if (val != INTVAL (operands[2]))
3764 operands[2] = GEN_INT (val);
3765 return AS2 (and%L0,%k2,%k0);
3766 }
3767
3768 return AS2 (and%W0,%2,%0);
4335
4336(define_insn "andhi3"
4337 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
4338 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
4339 (match_operand:HI 2 "general_operand" "ri,rm")))]
4340 ""
4341 "*
4342{

--- 61 unchanged lines hidden (view full) ---

4404 CC_STATUS_INIT;
4405 val |= ~0xffff;
4406 if (val != INTVAL (operands[2]))
4407 operands[2] = GEN_INT (val);
4408 return AS2 (and%L0,%k2,%k0);
4409 }
4410
4411 return AS2 (and%W0,%2,%0);
3769}")
4412}"
4413 [(set_attr "type" "binary")])
3770
3771(define_insn "andqi3"
3772 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
3773 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
3774 (match_operand:QI 2 "general_operand" "qn,qmn")))]
3775 ""
4414
4415(define_insn "andqi3"
4416 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
4417 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
4418 (match_operand:QI 2 "general_operand" "qn,qmn")))]
4419 ""
3776 "* return AS2 (and%B0,%2,%0);")
4420 "* return AS2 (and%B0,%2,%0);"
4421 [(set_attr "type" "binary")])
3777
3778/* I am nervous about these two.. add them later..
3779;I presume this means that we have something in say op0= eax which is small
3780;and we want to and it with memory so we can do this by just an
3781;andb m,%al and have success.
3782(define_insn ""
3783 [(set (match_operand:SI 0 "general_operand" "=r")
3784 (and:SI (zero_extend:SI

--- 99 unchanged lines hidden (view full) ---

3884 goto byte_or_operation;
3885 }
3886
3887 default:
3888 break;
3889 }
3890
3891 return AS2 (or%L0,%2,%0);
4422
4423/* I am nervous about these two.. add them later..
4424;I presume this means that we have something in say op0= eax which is small
4425;and we want to and it with memory so we can do this by just an
4426;andb m,%al and have success.
4427(define_insn ""
4428 [(set (match_operand:SI 0 "general_operand" "=r")
4429 (and:SI (zero_extend:SI

--- 99 unchanged lines hidden (view full) ---

4529 goto byte_or_operation;
4530 }
4531
4532 default:
4533 break;
4534 }
4535
4536 return AS2 (or%L0,%2,%0);
3892}")
4537}"
4538 [(set_attr "type" "binary")])
3893
3894(define_insn "iorhi3"
3895 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
3896 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
3897 (match_operand:HI 2 "general_operand" "ri,rm")))]
3898 ""
3899 "*
3900{

--- 67 unchanged lines hidden (view full) ---

3968 CC_STATUS_INIT;
3969 intval = 0xffff & INTVAL (operands[2]);
3970 if (intval != INTVAL (operands[2]))
3971 operands[2] = GEN_INT (intval);
3972 return AS2 (or%L0,%2,%k0);
3973 }
3974
3975 return AS2 (or%W0,%2,%0);
4539
4540(define_insn "iorhi3"
4541 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
4542 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
4543 (match_operand:HI 2 "general_operand" "ri,rm")))]
4544 ""
4545 "*
4546{

--- 67 unchanged lines hidden (view full) ---

4614 CC_STATUS_INIT;
4615 intval = 0xffff & INTVAL (operands[2]);
4616 if (intval != INTVAL (operands[2]))
4617 operands[2] = GEN_INT (intval);
4618 return AS2 (or%L0,%2,%k0);
4619 }
4620
4621 return AS2 (or%W0,%2,%0);
3976}")
4622}"
4623 [(set_attr "type" "binary")])
3977
3978(define_insn "iorqi3"
3979 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
3980 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
3981 (match_operand:QI 2 "general_operand" "qn,qmn")))]
3982 ""
4624
4625(define_insn "iorqi3"
4626 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
4627 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
4628 (match_operand:QI 2 "general_operand" "qn,qmn")))]
4629 ""
3983 "* return AS2 (or%B0,%2,%0);")
4630 "* return AS2 (or%B0,%2,%0);"
4631 [(set_attr "type" "binary")])
3984
3985;;- xor instructions
3986
3987(define_insn "xorsi3"
3988 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
3989 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3990 (match_operand:SI 2 "general_operand" "ri,rm")))]
3991 ""

--- 19 unchanged lines hidden (view full) ---

4011 /* Do low byte access only for %eax or when high bit is set */
4012 if (REGNO (operands[0]) != 0 && !(intval & 0x80))
4013 break;
4014 }
4015
4016byte_xor_operation:
4017 CC_STATUS_INIT;
4018
4632
4633;;- xor instructions
4634
4635(define_insn "xorsi3"
4636 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
4637 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4638 (match_operand:SI 2 "general_operand" "ri,rm")))]
4639 ""

--- 19 unchanged lines hidden (view full) ---

4659 /* Do low byte access only for %eax or when high bit is set */
4660 if (REGNO (operands[0]) != 0 && !(intval & 0x80))
4661 break;
4662 }
4663
4664byte_xor_operation:
4665 CC_STATUS_INIT;
4666
4019 if (intval == 0xff)
4667 if (intval == 0xff
4668 && (!TARGET_PENTIUM || optimize_size
4669 || (GET_CODE (operands[0]) == MEM
4670 && memory_address_info (XEXP (operands[0], 0), 1))))
4020 return AS1 (not%B0,%b0);
4021
4022 if (intval != INTVAL (operands[2]))
4023 operands[2] = GEN_INT (intval);
4024 return AS2 (xor%B0,%2,%b0);
4025 }
4026
4027 /* second byte? */
4028 if ((intval & ~0xff00) == 0)
4029 {
4030 intval >>= 8;
4031
4032 if (REG_P (operands[0]))
4033 {
4034 CC_STATUS_INIT;
4671 return AS1 (not%B0,%b0);
4672
4673 if (intval != INTVAL (operands[2]))
4674 operands[2] = GEN_INT (intval);
4675 return AS2 (xor%B0,%2,%b0);
4676 }
4677
4678 /* second byte? */
4679 if ((intval & ~0xff00) == 0)
4680 {
4681 intval >>= 8;
4682
4683 if (REG_P (operands[0]))
4684 {
4685 CC_STATUS_INIT;
4035 if (intval == 0xff)
4686 if (intval == 0xff
4687 && (!TARGET_PENTIUM || optimize_size
4688 || (GET_CODE (operands[0]) == MEM
4689 && memory_address_info (XEXP (operands[0], 0), 1))))
4036 return AS1 (not%B0,%h0);
4037
4038 operands[2] = GEN_INT (intval);
4039 return AS2 (xor%B0,%2,%h0);
4040 }
4041
4042 operands[0] = adj_offsettable_operand (operands[0], 1);
4043

--- 19 unchanged lines hidden (view full) ---

4063 goto byte_xor_operation;
4064 }
4065
4066 default:
4067 break;
4068 }
4069
4070 return AS2 (xor%L0,%2,%0);
4690 return AS1 (not%B0,%h0);
4691
4692 operands[2] = GEN_INT (intval);
4693 return AS2 (xor%B0,%2,%h0);
4694 }
4695
4696 operands[0] = adj_offsettable_operand (operands[0], 1);
4697

--- 19 unchanged lines hidden (view full) ---

4717 goto byte_xor_operation;
4718 }
4719
4720 default:
4721 break;
4722 }
4723
4724 return AS2 (xor%L0,%2,%0);
4071}")
4725}"
4726 [(set_attr "type" "binary")])
4072
4073(define_insn "xorhi3"
4074 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
4075 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
4076 (match_operand:HI 2 "general_operand" "ri,rm")))]
4077 ""
4078 "*
4079{
4080 if (GET_CODE (operands[2]) == CONST_INT
4081 && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
4082 {
4083 /* Can we ignore the upper byte? */
4084 if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
4085 && (INTVAL (operands[2]) & 0xff00) == 0)
4086 {
4087 CC_STATUS_INIT;
4088 if (INTVAL (operands[2]) & 0xffff0000)
4089 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
4090
4727
4728(define_insn "xorhi3"
4729 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
4730 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
4731 (match_operand:HI 2 "general_operand" "ri,rm")))]
4732 ""
4733 "*
4734{
4735 if (GET_CODE (operands[2]) == CONST_INT
4736 && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
4737 {
4738 /* Can we ignore the upper byte? */
4739 if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
4740 && (INTVAL (operands[2]) & 0xff00) == 0)
4741 {
4742 CC_STATUS_INIT;
4743 if (INTVAL (operands[2]) & 0xffff0000)
4744 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
4745
4091 if (INTVAL (operands[2]) == 0xff)
4746 if (INTVAL (operands[2]) == 0xff
4747 && (!TARGET_PENTIUM || optimize_size
4748 || (GET_CODE (operands[0]) == MEM
4749 && memory_address_info (XEXP (operands[0], 0), 1))))
4092 return AS1 (not%B0,%b0);
4093
4094 return AS2 (xor%B0,%2,%b0);
4095 }
4096
4097 /* Can we ignore the lower byte? */
4098 /* ??? what about offsettable memory references? */
4099 if (QI_REG_P (operands[0])
4100 && (INTVAL (operands[2]) & 0xff) == 0)
4101 {
4102 CC_STATUS_INIT;
4103 operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
4104
4750 return AS1 (not%B0,%b0);
4751
4752 return AS2 (xor%B0,%2,%b0);
4753 }
4754
4755 /* Can we ignore the lower byte? */
4756 /* ??? what about offsettable memory references? */
4757 if (QI_REG_P (operands[0])
4758 && (INTVAL (operands[2]) & 0xff) == 0)
4759 {
4760 CC_STATUS_INIT;
4761 operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
4762
4105 if (INTVAL (operands[2]) == 0xff)
4763 if (INTVAL (operands[2]) == 0xff
4764 && (!TARGET_PENTIUM || optimize_size
4765 || (GET_CODE (operands[0]) == MEM
4766 && memory_address_info (XEXP (operands[0], 0), 1))))
4106 return AS1 (not%B0,%h0);
4107
4108 return AS2 (xor%B0,%2,%h0);
4109 }
4110 }
4111
4112 if (REG_P (operands[0])
4113 && i386_aligned_p (operands[2]))

--- 10 unchanged lines hidden (view full) ---

4124 CC_STATUS_INIT;
4125 intval = 0xffff & INTVAL (operands[2]);
4126 if (intval != INTVAL (operands[2]))
4127 operands[2] = GEN_INT (intval);
4128 return AS2 (xor%L0,%2,%k0);
4129 }
4130
4131 return AS2 (xor%W0,%2,%0);
4767 return AS1 (not%B0,%h0);
4768
4769 return AS2 (xor%B0,%2,%h0);
4770 }
4771 }
4772
4773 if (REG_P (operands[0])
4774 && i386_aligned_p (operands[2]))

--- 10 unchanged lines hidden (view full) ---

4785 CC_STATUS_INIT;
4786 intval = 0xffff & INTVAL (operands[2]);
4787 if (intval != INTVAL (operands[2]))
4788 operands[2] = GEN_INT (intval);
4789 return AS2 (xor%L0,%2,%k0);
4790 }
4791
4792 return AS2 (xor%W0,%2,%0);
4132}")
4793}"
4794 [(set_attr "type" "binary")])
4133
4134(define_insn "xorqi3"
4135 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
4136 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
4137 (match_operand:QI 2 "general_operand" "qn,qm")))]
4138 ""
4795
4796(define_insn "xorqi3"
4797 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
4798 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
4799 (match_operand:QI 2 "general_operand" "qn,qm")))]
4800 ""
4139 "* return AS2 (xor%B0,%2,%0);")
4801 "* return AS2 (xor%B0,%2,%0);"
4802 [(set_attr "type" "binary")])
4140
4141;; logical operations for DImode
4142
4803
4804;; logical operations for DImode
4805
4143
4144(define_insn "anddi3"
4806(define_insn "anddi3"
4145 [(set (match_operand:DI 0 "general_operand" "=&r,&ro,!r,o,!&r,!o,!o")
4146 (and:DI (match_operand:DI 1 "general_operand" "%0,0,0,0iF,or,riF,o")
4147 (match_operand:DI 2 "general_operand" "o,riF,0,or,or,oriF,o")))
4148 (clobber (match_scratch:SI 3 "=X,X,X,&r,X,&r,&r"))]
4807 [(set (match_operand:DI 0 "general_operand" "=&r,&ro")
4808 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
4809 (match_operand:DI 2 "general_operand" "oriF,riF")))]
4149 ""
4810 ""
4150 "#")
4811 "#"
4812 [(set_attr "type" "binary")])
4151
4813
4814
4152(define_insn "iordi3"
4815(define_insn "iordi3"
4153 [(set (match_operand:DI 0 "general_operand" "=&r,&ro,!r,o,!&r,!o,!o")
4154 (ior:DI (match_operand:DI 1 "general_operand" "%0,0,0,0iF,or,riF,o")
4155 (match_operand:DI 2 "general_operand" "o,riF,0,or,or,oriF,o")))
4156 (clobber (match_scratch:SI 3 "=X,X,X,&r,X,&r,&r"))]
4816 [(set (match_operand:DI 0 "general_operand" "=&r,&ro")
4817 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
4818 (match_operand:DI 2 "general_operand" "oriF,riF")))]
4157 ""
4819 ""
4158 "#")
4159
4820 "#"
4821 [(set_attr "type" "binary")])
4822
4160(define_insn "xordi3"
4823(define_insn "xordi3"
4161 [(set (match_operand:DI 0 "general_operand" "=&r,&ro,!r,o,!&r,!o,!o")
4162 (xor:DI (match_operand:DI 1 "general_operand" "%0,0,0,0iF,or,riF,o")
4163 (match_operand:DI 2 "general_operand" "o,riF,0,or,or,oriF,o")))
4164 (clobber (match_scratch:SI 3 "=X,X,X,&r,X,&r,&r"))]
4824 [(set (match_operand:DI 0 "general_operand" "=&r,&ro")
4825 (xor:DI (match_operand:DI 1 "general_operand" "%0,0")
4826 (match_operand:DI 2 "general_operand" "oriF,riF")))]
4165 ""
4827 ""
4166 "#")
4828 "#"
4829 [(set_attr "type" "binary")])
4167
4168(define_split
4830
4831(define_split
4169 [(set (match_operand:DI 0 "general_operand" "=&r,&ro,!r,o,!&r,!o,!o")
4170 (match_operator:DI 4 "ix86_logical_operator"
4171 [(match_operand:DI 1 "general_operand" "%0,0,0,0iF,or,riF,o")
4172 (match_operand:DI 2 "general_operand" "o,riF,0,or,or,oriF,o")]))
4173 (clobber (match_scratch:SI 3 "=X,X,X,&r,X,&r,&r"))]
4174 "reload_completed"
4175 [(const_int 0)]
4176 "
4177{
4178 rtx low[3], high[3], xops[7], temp;
4179 rtx (*genfunc)() = (GET_CODE (operands[4]) == AND ? gen_andsi3
4180 : GET_CODE (operands[4]) == IOR ? gen_iorsi3
4181 : GET_CODE (operands[4]) == XOR ? gen_xorsi3
4182 : 0);
4832 [(set (match_operand:DI 0 "general_operand" "")
4833 (match_operator:DI 3 "ix86_logical_operator"
4834 [(match_operand:DI 1 "general_operand" "")
4835 (match_operand:DI 2 "general_operand" "")]))]
4836 ""
4837 [(set (match_dup 4) (match_op_dup:SI 3 [(match_dup 6) (match_dup 8)]))
4838 (set (match_dup 5) (match_op_dup:SI 3 [(match_dup 7) (match_dup 9)]))]
4839 "split_di (&operands[0], 1, &operands[4], &operands[5]);
4840 split_di (&operands[1], 1, &operands[6], &operands[7]);
4841 split_di (&operands[2], 1, &operands[8], &operands[9]);")
4183
4842
4184 if (rtx_equal_p (operands[0], operands[2]))
4185 {
4186 temp = operands[1];
4187 operands[1] = operands[2];
4188 operands[2] = temp;
4189 }
4190
4191 split_di (operands, 3, low, high);
4192 if (!rtx_equal_p (operands[0], operands[1]))
4193 {
4194 xops[0] = high[0];
4195 xops[1] = low[0];
4196 xops[2] = high[1];
4197 xops[3] = low[1];
4198
4199 if (GET_CODE (operands[0]) != MEM)
4200 {
4201 emit_insn (gen_movsi (xops[1], xops[3]));
4202 emit_insn (gen_movsi (xops[0], xops[2]));
4203 }
4204 else
4205 {
4206 xops[4] = high[2];
4207 xops[5] = low[2];
4208 xops[6] = operands[3];
4209 emit_insn (gen_movsi (xops[6], xops[3]));
4210 emit_insn ((*genfunc) (xops[6], xops[6], xops[5]));
4211 emit_insn (gen_movsi (xops[1], xops[6]));
4212 emit_insn (gen_movsi (xops[6], xops[2]));
4213 emit_insn ((*genfunc) (xops[6], xops[6], xops[4]));
4214 emit_insn (gen_movsi (xops[0], xops[6]));
4215 DONE;
4216 }
4217 }
4218
4219 if (GET_CODE (operands[3]) == REG && GET_CODE (operands[2]) != REG)
4220 {
4221 xops[0] = high[0];
4222 xops[1] = low[0];
4223 xops[2] = high[2];
4224 xops[3] = low[2];
4225 xops[4] = operands[3];
4226
4227 emit_insn (gen_movsi (xops[4], xops[3]));
4228 emit_insn ((*genfunc) (xops[1], xops[1], xops[4]));
4229 emit_insn (gen_movsi (xops[4], xops[2]));
4230 emit_insn ((*genfunc) (xops[0], xops[0], xops[4]));
4231 }
4232
4233 else
4234 {
4235 emit_insn ((*genfunc) (low[0], low[0], low[2]));
4236 emit_insn ((*genfunc) (high[0], high[0], high[2]));
4237 }
4238
4239 DONE;
4240}")
4241
4242;;- negation instructions
4243
4244(define_insn "negdi2"
4245 [(set (match_operand:DI 0 "general_operand" "=&ro")
4246 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4247 ""
4248 "*
4249{

--- 16 unchanged lines hidden (view full) ---

4266 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
4267 ""
4268 "neg%L0 %0")
4269
4270(define_insn "neghi2"
4271 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
4272 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
4273 ""
4843;;- negation instructions
4844
4845(define_insn "negdi2"
4846 [(set (match_operand:DI 0 "general_operand" "=&ro")
4847 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4848 ""
4849 "*
4850{

--- 16 unchanged lines hidden (view full) ---

4867 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
4868 ""
4869 "neg%L0 %0")
4870
4871(define_insn "neghi2"
4872 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
4873 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
4874 ""
4274 "neg%W0 %0")
4875 "*
4876 if (REG_P (operands[0]) && i386_cc_probably_useless_p (insn))
4877 {
4878 CC_STATUS_INIT;
4879 return AS1(neg%L0,%k0);
4880 }
4881 return AS1(neg%W0,%0);")
4275
4276(define_insn "negqi2"
4277 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
4278 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))]
4279 ""
4280 "neg%B0 %0")
4281
4282(define_insn "negsf2"
4283 [(set (match_operand:SF 0 "register_operand" "=f")
4284 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
4285 "TARGET_80387"
4882
4883(define_insn "negqi2"
4884 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
4885 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))]
4886 ""
4887 "neg%B0 %0")
4888
4889(define_insn "negsf2"
4890 [(set (match_operand:SF 0 "register_operand" "=f")
4891 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
4892 "TARGET_80387"
4286 "fchs")
4893 "fchs"
4894 [(set_attr "type" "fpop")])
4287
4288(define_insn "negdf2"
4289 [(set (match_operand:DF 0 "register_operand" "=f")
4290 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
4291 "TARGET_80387"
4895
4896(define_insn "negdf2"
4897 [(set (match_operand:DF 0 "register_operand" "=f")
4898 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
4899 "TARGET_80387"
4292 "fchs")
4900 "fchs"
4901 [(set_attr "type" "fpop")])
4293
4294(define_insn ""
4295 [(set (match_operand:DF 0 "register_operand" "=f")
4296 (neg:DF (float_extend:DF (match_operand:SF 1 "register_operand" "0"))))]
4297 "TARGET_80387"
4902
4903(define_insn ""
4904 [(set (match_operand:DF 0 "register_operand" "=f")
4905 (neg:DF (float_extend:DF (match_operand:SF 1 "register_operand" "0"))))]
4906 "TARGET_80387"
4298 "fchs")
4907 "fchs"
4908 [(set_attr "type" "fpop")])
4299
4300(define_insn "negxf2"
4301 [(set (match_operand:XF 0 "register_operand" "=f")
4302 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
4303 "TARGET_80387"
4909
4910(define_insn "negxf2"
4911 [(set (match_operand:XF 0 "register_operand" "=f")
4912 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
4913 "TARGET_80387"
4304 "fchs")
4914 "fchs"
4915 [(set_attr "type" "fpop")])
4305
4306(define_insn ""
4307 [(set (match_operand:XF 0 "register_operand" "=f")
4308 (neg:XF (float_extend:XF (match_operand:DF 1 "register_operand" "0"))))]
4309 "TARGET_80387"
4916
4917(define_insn ""
4918 [(set (match_operand:XF 0 "register_operand" "=f")
4919 (neg:XF (float_extend:XF (match_operand:DF 1 "register_operand" "0"))))]
4920 "TARGET_80387"
4310 "fchs")
4921 "fchs"
4922 [(set_attr "type" "fpop")])
4311
4312;; Absolute value instructions
4313
4314(define_insn "abssf2"
4315 [(set (match_operand:SF 0 "register_operand" "=f")
4316 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
4317 "TARGET_80387"
4318 "fabs"

--- 119 unchanged lines hidden (view full) ---

4438 "fcos")
4439
4440;;- one complement instructions
4441
4442(define_insn "one_cmplsi2"
4443 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4444 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
4445 ""
4923
4924;; Absolute value instructions
4925
4926(define_insn "abssf2"
4927 [(set (match_operand:SF 0 "register_operand" "=f")
4928 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
4929 "TARGET_80387"
4930 "fabs"

--- 119 unchanged lines hidden (view full) ---

5050 "fcos")
5051
5052;;- one complement instructions
5053
5054(define_insn "one_cmplsi2"
5055 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5056 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
5057 ""
4446 "not%L0 %0")
5058 "*
5059{
5060 /* A Pentium NOT is not pariable. Output it only in case of complex
5061 memory address, because XOR will be inpariable anyway because
5062 of immediate/displacement rule. */
4447
5063
5064 if (TARGET_PENTIUM && !optimize_size
5065 && (GET_CODE (operands[0]) != MEM
5066 || memory_address_info (XEXP (operands[0], 0), 1) == 0))
5067 {
5068 rtx xops[2];
5069 xops[0] = operands[0];
5070 xops[1] = GEN_INT (0xffffffff);
5071 output_asm_insn (AS2 (xor%L0,%1,%0), xops);
5072 RET;
5073 }
5074 else
5075 return AS1 (not%L0,%0);
5076}")
5077
4448(define_insn "one_cmplhi2"
4449 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
4450 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
4451 ""
5078(define_insn "one_cmplhi2"
5079 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
5080 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
5081 ""
4452 "not%W0 %0")
5082 "*
5083{
5084 /* A Pentium NOT is not pariable. Output it only in case of complex
5085 memory address, because XOR will be inpariable anyway because
5086 of immediate/displacement rule. */
4453
5087
5088 if (TARGET_PENTIUM && !optimize_size
5089 && (GET_CODE (operands[0]) != MEM
5090 || memory_address_info (XEXP (operands[0], 0), 1) == 0))
5091 {
5092 rtx xops[2];
5093 xops[0] = operands[0];
5094 xops[1] = GEN_INT (0xffff);
5095 if (REG_P (operands[0])
5096 && i386_cc_probably_useless_p (insn))
5097 {
5098 CC_STATUS_INIT;
5099 output_asm_insn (AS2 (xor%L0,%1,%k0), xops);
5100 }
5101 else
5102 output_asm_insn (AS2 (xor%W0,%1,%0), xops);
5103 RET;
5104 }
5105 else
5106 {
5107 if (REG_P (operands[0])
5108 && i386_cc_probably_useless_p (insn))
5109 {
5110 CC_STATUS_INIT;
5111 return AS1 (not%L0,%k0);
5112 }
5113 return AS1 (not%W0,%0);
5114 }
5115}")
5116
4454(define_insn "one_cmplqi2"
4455 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
4456 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0")))]
4457 ""
5117(define_insn "one_cmplqi2"
5118 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
5119 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0")))]
5120 ""
4458 "not%B0 %0")
5121 "*
5122{
5123 /* A Pentium NOT is not pariable. Output it only in case of complex
5124 memory address, because XOR will be inpariable anyway because
5125 of immediate/displacement rule. */
5126
5127 if (TARGET_PENTIUM && !optimize_size
5128 && (GET_CODE (operands[0]) != MEM
5129 || memory_address_info (XEXP (operands[0], 0), 1) == 0))
5130 {
5131 rtx xops[2];
5132 xops[0] = operands[0];
5133 xops[1] = GEN_INT (0xff);
5134 output_asm_insn (AS2 (xor%B0,%1,%0), xops);
5135 RET;
5136 }
5137 else
5138 return AS1 (not%B0,%0);
5139}")
4459
4460;;- arithmetic shift instructions
4461
4462;; DImode shifts are implemented using the i386 "shift double" opcode,
4463;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
4464;; is variable, then the count is in %cl and the "imm" operand is dropped
4465;; from the assembler input.
4466

--- 94 unchanged lines hidden (view full) ---

4561 output_asm_insn (AS1 (je,%X4), xops);
4562 output_asm_insn (AS2 (mov%L3,%2,%3), xops); /* Fast shift by 32 */
4563 output_asm_insn (AS2 (xor%L2,%2,%2), xops);
4564 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
4565 CODE_LABEL_NUMBER (xops[4]));
4566 RET;
4567}")
4568
5140
5141;;- arithmetic shift instructions
5142
5143;; DImode shifts are implemented using the i386 "shift double" opcode,
5144;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
5145;; is variable, then the count is in %cl and the "imm" operand is dropped
5146;; from the assembler input.
5147

--- 94 unchanged lines hidden (view full) ---

5242 output_asm_insn (AS1 (je,%X4), xops);
5243 output_asm_insn (AS2 (mov%L3,%2,%3), xops); /* Fast shift by 32 */
5244 output_asm_insn (AS2 (xor%L2,%2,%2), xops);
5245 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5246 CODE_LABEL_NUMBER (xops[4]));
5247 RET;
5248}")
5249
4569;; On i386 and i486, "addl reg,reg" is faster than "sall $1,reg"
4570;; On i486, movl/sall appears slightly faster than leal, but the leal
4571;; is smaller - use leal for now unless the shift count is 1.
5250(define_expand "ashlsi3"
5251 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5252 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
5253 (match_operand:SI 2 "nonmemory_operand" "")))]
5254 ""
5255 "")
4572
5256
4573(define_insn "ashlsi3"
4574 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
4575 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "r,0")
4576 (match_operand:SI 2 "nonmemory_operand" "M,cI")))]
5257(define_expand "ashlhi3"
5258 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5259 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
5260 (match_operand:HI 2 "nonmemory_operand" "")))]
4577 ""
5261 ""
4578 "*
4579{
4580 if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1]))
4581 {
4582 if (TARGET_DOUBLE_WITH_ADD && INTVAL (operands[2]) == 1)
4583 {
4584 output_asm_insn (AS2 (mov%L0,%1,%0), operands);
4585 return AS2 (add%L0,%1,%0);
4586 }
4587 else
4588 {
4589 CC_STATUS_INIT;
5262 "")
4590
5263
4591 if (operands[1] == stack_pointer_rtx)
4592 {
4593 output_asm_insn (AS2 (mov%L0,%1,%0), operands);
4594 operands[1] = operands[0];
4595 }
4596 operands[1] = gen_rtx_MULT (SImode, operands[1],
4597 GEN_INT (1 << INTVAL (operands[2])));
4598 return AS2 (lea%L0,%a1,%0);
4599 }
4600 }
5264(define_expand "ashlqi3"
5265 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5266 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
5267 (match_operand:QI 2 "nonmemory_operand" "")))]
5268 ""
5269 "")
4601
5270
4602 if (REG_P (operands[2]))
4603 return AS2 (sal%L0,%b2,%0);
5271;; Pattern for shifts which can be encoded into an lea instruction.
5272;; This is kept as a separate pattern so that regmove can optimize cases
5273;; where we know the source and destination must match.
5274;;
5275;; Do not expose this pattern when optimizing for size since we never want
5276;; to use lea when optimizing for size since mov+sal is smaller than lea.
4604
5277
4605 if (REG_P (operands[0]) && operands[2] == const1_rtx)
4606 return AS2 (add%L0,%0,%0);
5278(define_insn ""
5279 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r")
5280 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
5281 (match_operand:SI 2 "small_shift_operand" "M,M")))]
5282 "! optimize_size"
5283 "* return output_ashl (insn, operands);")
4607
5284
4608 return AS2 (sal%L0,%2,%0);
4609}")
5285;; Generic left shift pattern to catch all cases not handled by the
5286;; shift pattern above.
5287(define_insn ""
5288 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5289 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
5290 (match_operand:SI 2 "nonmemory_operand" "cI")))]
5291 ""
5292 "* return output_ashl (insn, operands);")
4610
5293
4611(define_insn "ashlhi3"
5294(define_insn ""
5295 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r")
5296 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
5297 (match_operand:HI 2 "small_shift_operand" "M,M")))]
5298 "! optimize_size"
5299 "* return output_ashl (insn, operands);")
5300
5301(define_insn ""
4612 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
4613 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
4614 (match_operand:HI 2 "nonmemory_operand" "cI")))]
4615 ""
5302 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
5303 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
5304 (match_operand:HI 2 "nonmemory_operand" "cI")))]
5305 ""
4616 "*
4617{
4618 if (REG_P (operands[2]))
4619 return AS2 (sal%W0,%b2,%0);
5306 "* return output_ashl (insn, operands);")
4620
5307
4621 if (REG_P (operands[0]) && operands[2] == const1_rtx)
4622 return AS2 (add%W0,%0,%0);
5308(define_insn ""
5309 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q")
5310 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,q")
5311 (match_operand:QI 2 "small_shift_operand" "M,M")))]
5312 "! optimize_size"
5313 "* return output_ashl (insn, operands);")
4623
5314
4624 return AS2 (sal%W0,%2,%0);
4625}")
4626
4627(define_insn "ashlqi3"
5315;; Generic left shift pattern to catch all cases not handled by the
5316;; shift pattern above.
5317(define_insn ""
4628 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
4629 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
4630 (match_operand:QI 2 "nonmemory_operand" "cI")))]
4631 ""
5318 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
5319 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
5320 (match_operand:QI 2 "nonmemory_operand" "cI")))]
5321 ""
4632 "*
4633{
4634 if (REG_P (operands[2]))
4635 return AS2 (sal%B0,%b2,%0);
5322 "* return output_ashl (insn, operands);")
4636
5323
4637 if (REG_P (operands[0]) && operands[2] == const1_rtx)
4638 return AS2 (add%B0,%0,%0);
4639
4640 return AS2 (sal%B0,%2,%0);
4641}")
4642
4643;; See comment above `ashldi3' about how this works.
4644
4645(define_expand "ashrdi3"
4646 [(set (match_operand:DI 0 "register_operand" "")
4647 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4648 (match_operand:QI 2 "nonmemory_operand" "")))]
4649 ""
4650 "

--- 99 unchanged lines hidden (view full) ---

4750 xops[1] = GEN_INT (31);
4751 output_asm_insn (AS2 (mov%L2,%3,%2), xops);
4752 output_asm_insn (AS2 (sar%L3,%1,%3), xops); /* shift by 32 */
4753 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
4754 CODE_LABEL_NUMBER (xops[4]));
4755 RET;
4756}")
4757
5324;; See comment above `ashldi3' about how this works.
5325
5326(define_expand "ashrdi3"
5327 [(set (match_operand:DI 0 "register_operand" "")
5328 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5329 (match_operand:QI 2 "nonmemory_operand" "")))]
5330 ""
5331 "

--- 99 unchanged lines hidden (view full) ---

5431 xops[1] = GEN_INT (31);
5432 output_asm_insn (AS2 (mov%L2,%3,%2), xops);
5433 output_asm_insn (AS2 (sar%L3,%1,%3), xops); /* shift by 32 */
5434 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5435 CODE_LABEL_NUMBER (xops[4]));
5436 RET;
5437}")
5438
5439(define_insn "ashrsi3_31"
5440 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,d")
5441 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,a")
5442 (const_int 31)))]
5443 "!TARGET_PENTIUM || optimize_size"
5444 "@
5445 sar%L0 $31,%0
5446 cltd")
5447
4758(define_insn "ashrsi3"
4759 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4760 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
4761 (match_operand:SI 2 "nonmemory_operand" "cI")))]
4762 ""
4763 "*
4764{
4765 if (REG_P (operands[2]))

--- 406 unchanged lines hidden (view full) ---

5172 ""
5173 "*
5174{
5175 unsigned int mask;
5176
5177 mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]);
5178 operands[1] = GEN_INT (mask);
5179
5448(define_insn "ashrsi3"
5449 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5450 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
5451 (match_operand:SI 2 "nonmemory_operand" "cI")))]
5452 ""
5453 "*
5454{
5455 if (REG_P (operands[2]))

--- 406 unchanged lines hidden (view full) ---

5862 ""
5863 "*
5864{
5865 unsigned int mask;
5866
5867 mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]);
5868 operands[1] = GEN_INT (mask);
5869
5180 if (QI_REG_P (operands[0]))
5870 if (QI_REG_P (operands[0])
5871 /* A Pentium test is pairable only with eax. Not with ah or al. */
5872 && (! REG_P (operands[0]) || REGNO (operands[0]) || !TARGET_PENTIUM
5873 || optimize_size))
5181 {
5182 if ((mask & ~0xff) == 0)
5183 {
5184 cc_status.flags |= CC_NOT_NEGATIVE;
5185 return AS2 (test%B0,%1,%b0);
5186 }
5187
5188 if ((mask & ~0xff00) == 0)

--- 17 unchanged lines hidden (view full) ---

5206 "GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0])"
5207 "*
5208{
5209 unsigned int mask;
5210
5211 mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]);
5212 operands[1] = GEN_INT (mask);
5213
5874 {
5875 if ((mask & ~0xff) == 0)
5876 {
5877 cc_status.flags |= CC_NOT_NEGATIVE;
5878 return AS2 (test%B0,%1,%b0);
5879 }
5880
5881 if ((mask & ~0xff00) == 0)

--- 17 unchanged lines hidden (view full) ---

5899 "GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0])"
5900 "*
5901{
5902 unsigned int mask;
5903
5904 mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]);
5905 operands[1] = GEN_INT (mask);
5906
5214 if (! REG_P (operands[0]) || QI_REG_P (operands[0]))
5907 if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
5908 /* A Pentium test is pairable only with eax. Not with ah or al. */
5909 && (! REG_P (operands[0]) || REGNO (operands[0]) || !TARGET_PENTIUM
5910 || optimize_size))
5215 {
5216 if ((mask & ~0xff) == 0)
5217 {
5218 cc_status.flags |= CC_NOT_NEGATIVE;
5219 return AS2 (test%B0,%1,%b0);
5220 }
5221
5222 if ((mask & ~0xff00) == 0)

--- 33 unchanged lines hidden (view full) ---

5256 return AS2 (test%L1,%0,%1);
5257}")
5258
5259;; Store-flag instructions.
5260
5261;; For all sCOND expanders, also expand the compare or test insn that
5262;; generates cc0. Generate an equality comparison if `seq' or `sne'.
5263
5911 {
5912 if ((mask & ~0xff) == 0)
5913 {
5914 cc_status.flags |= CC_NOT_NEGATIVE;
5915 return AS2 (test%B0,%1,%b0);
5916 }
5917
5918 if ((mask & ~0xff00) == 0)

--- 33 unchanged lines hidden (view full) ---

5952 return AS2 (test%L1,%0,%1);
5953}")
5954
5955;; Store-flag instructions.
5956
5957;; For all sCOND expanders, also expand the compare or test insn that
5958;; generates cc0. Generate an equality comparison if `seq' or `sne'.
5959
5264;; The 386 sCOND opcodes can write to memory. But a gcc sCOND insn may
5265;; not have any input reloads. A MEM write might need an input reload
5266;; for the address of the MEM. So don't allow MEM as the SET_DEST.
5267
5268(define_expand "seq"
5269 [(match_dup 1)
5270 (set (match_operand:QI 0 "register_operand" "")
5271 (eq:QI (cc0) (const_int 0)))]
5272 ""
5273 "
5274{
5275 if (TARGET_IEEE_FP
5276 && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT)
5277 operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1);
5278 else
5279 operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);
5280}")
5281
5960(define_expand "seq"
5961 [(match_dup 1)
5962 (set (match_operand:QI 0 "register_operand" "")
5963 (eq:QI (cc0) (const_int 0)))]
5964 ""
5965 "
5966{
5967 if (TARGET_IEEE_FP
5968 && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT)
5969 operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1);
5970 else
5971 operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);
5972}")
5973
5282(define_insn ""
5283 [(set (match_operand:QI 0 "register_operand" "=q")
5284 (eq:QI (cc0) (const_int 0)))]
5285 ""
5286 "*
5287{
5288 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
5289 return AS1 (setnb,%0);
5290 else
5291 return AS1 (sete,%0);
5292}")
5293
5294(define_expand "sne"
5295 [(match_dup 1)
5296 (set (match_operand:QI 0 "register_operand" "")
5297 (ne:QI (cc0) (const_int 0)))]
5298 ""
5299 "
5300{
5301 if (TARGET_IEEE_FP
5302 && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT)
5303 operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1);
5304 else
5305 operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);
5306}")
5307
5974(define_expand "sne"
5975 [(match_dup 1)
5976 (set (match_operand:QI 0 "register_operand" "")
5977 (ne:QI (cc0) (const_int 0)))]
5978 ""
5979 "
5980{
5981 if (TARGET_IEEE_FP
5982 && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT)
5983 operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1);
5984 else
5985 operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);
5986}")
5987
5308(define_insn ""
5309 [(set (match_operand:QI 0 "register_operand" "=q")
5310 (ne:QI (cc0) (const_int 0)))]
5311 ""
5312 "*
5313{
5314 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
5315 return AS1 (setb,%0);
5316 else
5317 return AS1 (setne,%0);
5318}
5319")
5320
5321(define_expand "sgt"
5322 [(match_dup 1)
5323 (set (match_operand:QI 0 "register_operand" "")
5324 (gt:QI (cc0) (const_int 0)))]
5325 ""
5326 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5327
5988(define_expand "sgt"
5989 [(match_dup 1)
5990 (set (match_operand:QI 0 "register_operand" "")
5991 (gt:QI (cc0) (const_int 0)))]
5992 ""
5993 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5994
5328(define_insn ""
5329 [(set (match_operand:QI 0 "register_operand" "=q")
5330 (gt:QI (cc0) (const_int 0)))]
5331 ""
5332 "*
5333{
5334 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
5335 && ! (cc_prev_status.flags & CC_FCOMI))
5336 return AS1 (sete,%0);
5337
5338 OUTPUT_JUMP (\"setg %0\", \"seta %0\", NULL_PTR);
5339}")
5340
5341(define_expand "sgtu"
5342 [(match_dup 1)
5343 (set (match_operand:QI 0 "register_operand" "")
5344 (gtu:QI (cc0) (const_int 0)))]
5345 ""
5346 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5347
5995(define_expand "sgtu"
5996 [(match_dup 1)
5997 (set (match_operand:QI 0 "register_operand" "")
5998 (gtu:QI (cc0) (const_int 0)))]
5999 ""
6000 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
6001
5348(define_insn ""
5349 [(set (match_operand:QI 0 "register_operand" "=q")
5350 (gtu:QI (cc0) (const_int 0)))]
5351 ""
5352 "* return \"seta %0\"; ")
5353
5354(define_expand "slt"
5355 [(match_dup 1)
5356 (set (match_operand:QI 0 "register_operand" "")
5357 (lt:QI (cc0) (const_int 0)))]
5358 ""
5359 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5360
6002(define_expand "slt"
6003 [(match_dup 1)
6004 (set (match_operand:QI 0 "register_operand" "")
6005 (lt:QI (cc0) (const_int 0)))]
6006 ""
6007 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
6008
5361(define_insn ""
5362 [(set (match_operand:QI 0 "register_operand" "=q")
5363 (lt:QI (cc0) (const_int 0)))]
5364 ""
5365 "*
5366{
5367 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
5368 && ! (cc_prev_status.flags & CC_FCOMI))
5369 return AS1 (sete,%0);
5370
5371 OUTPUT_JUMP (\"setl %0\", \"setb %0\", \"sets %0\");
5372}")
5373
5374(define_expand "sltu"
5375 [(match_dup 1)
5376 (set (match_operand:QI 0 "register_operand" "")
5377 (ltu:QI (cc0) (const_int 0)))]
5378 ""
5379 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5380
6009(define_expand "sltu"
6010 [(match_dup 1)
6011 (set (match_operand:QI 0 "register_operand" "")
6012 (ltu:QI (cc0) (const_int 0)))]
6013 ""
6014 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
6015
5381(define_insn ""
5382 [(set (match_operand:QI 0 "register_operand" "=q")
5383 (ltu:QI (cc0) (const_int 0)))]
5384 ""
5385 "* return \"setb %0\"; ")
5386
5387(define_expand "sge"
5388 [(match_dup 1)
5389 (set (match_operand:QI 0 "register_operand" "")
5390 (ge:QI (cc0) (const_int 0)))]
5391 ""
5392 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5393
6016(define_expand "sge"
6017 [(match_dup 1)
6018 (set (match_operand:QI 0 "register_operand" "")
6019 (ge:QI (cc0) (const_int 0)))]
6020 ""
6021 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
6022
5394(define_insn ""
5395 [(set (match_operand:QI 0 "register_operand" "=q")
5396 (ge:QI (cc0) (const_int 0)))]
5397 ""
5398 "*
5399{
5400 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
5401 && ! (cc_prev_status.flags & CC_FCOMI))
5402 return AS1 (sete,%0);
5403
5404 OUTPUT_JUMP (\"setge %0\", \"setae %0\", \"setns %0\");
5405}")
5406
5407(define_expand "sgeu"
5408 [(match_dup 1)
5409 (set (match_operand:QI 0 "register_operand" "")
5410 (geu:QI (cc0) (const_int 0)))]
5411 ""
5412 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5413
6023(define_expand "sgeu"
6024 [(match_dup 1)
6025 (set (match_operand:QI 0 "register_operand" "")
6026 (geu:QI (cc0) (const_int 0)))]
6027 ""
6028 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
6029
5414(define_insn ""
5415 [(set (match_operand:QI 0 "register_operand" "=q")
5416 (geu:QI (cc0) (const_int 0)))]
5417 ""
5418 "* return \"setae %0\"; ")
5419
5420(define_expand "sle"
5421 [(match_dup 1)
5422 (set (match_operand:QI 0 "register_operand" "")
5423 (le:QI (cc0) (const_int 0)))]
5424 ""
5425 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5426
6030(define_expand "sle"
6031 [(match_dup 1)
6032 (set (match_operand:QI 0 "register_operand" "")
6033 (le:QI (cc0) (const_int 0)))]
6034 ""
6035 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
6036
5427(define_insn ""
5428 [(set (match_operand:QI 0 "register_operand" "=q")
5429 (le:QI (cc0) (const_int 0)))]
5430 ""
5431 "*
5432{
5433 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
5434 && ! (cc_prev_status.flags & CC_FCOMI))
5435 return AS1 (setb,%0);
5436
5437 OUTPUT_JUMP (\"setle %0\", \"setbe %0\", NULL_PTR);
5438}")
5439
5440(define_expand "sleu"
5441 [(match_dup 1)
5442 (set (match_operand:QI 0 "register_operand" "")
5443 (leu:QI (cc0) (const_int 0)))]
5444 ""
5445 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5446
6037(define_expand "sleu"
6038 [(match_dup 1)
6039 (set (match_operand:QI 0 "register_operand" "")
6040 (leu:QI (cc0) (const_int 0)))]
6041 ""
6042 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
6043
5447(define_insn ""
5448 [(set (match_operand:QI 0 "register_operand" "=q")
5449 (leu:QI (cc0) (const_int 0)))]
5450 ""
5451 "* return \"setbe %0\"; ")
6044;; The 386 sCOND opcodes can write to memory. But a gcc sCOND insn may
6045;; not have any input reloads. A MEM write might need an input reload
6046;; for the address of the MEM. So don't allow MEM as the SET_DEST.
6047
6048(define_insn "*setcc"
6049 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
6050 (match_operator:QI 1 "comparison_operator" [(cc0) (const_int 0)]))]
6051 "reload_completed || register_operand (operands[0], QImode)"
6052 "*
6053{
6054 enum rtx_code code = GET_CODE (operands[1]);
6055 if (cc_prev_status.flags & CC_TEST_AX)
6056 {
6057 int eq;
6058 HOST_WIDE_INT c;
6059 operands[2] = gen_rtx_REG (SImode, 0);
6060 switch (code)
6061 {
6062 case EQ:
6063 c = 0x4000;
6064 eq = 0;
6065 break;
6066 case NE:
6067 c = 0x4000;
6068 eq = 1;
6069 break;
6070 case GT:
6071 c = 0x4100;
6072 eq = 1;
6073 break;
6074 case LT:
6075 c = 0x100;
6076 eq = 0;
6077 break;
6078 case GE:
6079 c = 0x100;
6080 eq = 1;
6081 break;
6082 case LE:
6083 c = 0x4100;
6084 eq = 0;
6085 break;
6086 default:
6087 abort ();
6088 }
6089 if (!TARGET_PENTIUM || optimize_size)
6090 {
6091 operands[3] = GEN_INT (c >> 8);
6092 output_asm_insn (AS2 (test%B0,%3,%h2), operands);
6093 }
6094 else
6095 {
6096 operands[3] = GEN_INT (c);
6097 output_asm_insn (AS2 (test%L0,%3,%2), operands);
6098 }
6099 return eq ? AS1 (sete,%0) : AS1 (setne, %0);
6100 }
6101
6102 if ((cc_status.flags & CC_NO_OVERFLOW) && (code == LE || code == GT))
6103 return (char *)0;
6104 return AS1(set%D1,%0);
6105}")
6106
5452
5453;; Basic conditional jump instructions.
5454;; We ignore the overflow flag for signed branch instructions.
5455
5456;; For all bCOND expanders, also expand the compare or test insn that
5457;; generates cc0. Generate an equality comparison if `beq' or `bne'.
5458
5459(define_expand "beq"

--- 8 unchanged lines hidden (view full) ---

5468{
5469 if (TARGET_IEEE_FP
5470 && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT)
5471 operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1);
5472 else
5473 operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);
5474}")
5475
6107
6108;; Basic conditional jump instructions.
6109;; We ignore the overflow flag for signed branch instructions.
6110
6111;; For all bCOND expanders, also expand the compare or test insn that
6112;; generates cc0. Generate an equality comparison if `beq' or `bne'.
6113
6114(define_expand "beq"

--- 8 unchanged lines hidden (view full) ---

6123{
6124 if (TARGET_IEEE_FP
6125 && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT)
6126 operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1);
6127 else
6128 operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);
6129}")
6130
5476(define_insn ""
5477 [(set (pc)
5478 (if_then_else (eq (cc0)
5479 (const_int 0))
5480 (label_ref (match_operand 0 "" ""))
5481 (pc)))]
5482 ""
5483 "*
5484{
5485 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
5486 return \"jnc %l0\";
5487 else
5488 if (cc_prev_status.flags & CC_TEST_AX)
5489 {
5490 operands[1] = gen_rtx_REG (SImode, 0);
5491 operands[2] = GEN_INT (0x4000);
5492 output_asm_insn (AS2 (testl,%2,%1), operands);
5493 return AS1 (jne,%l0);
5494 }
5495
5496 return \"je %l0\";
5497}")
5498
5499(define_expand "bne"
5500 [(match_dup 1)
5501 (set (pc)
5502 (if_then_else (ne (cc0)
5503 (const_int 0))
5504 (label_ref (match_operand 0 "" ""))
5505 (pc)))]
5506 ""
5507 "
5508{
5509 if (TARGET_IEEE_FP
5510 && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT)
5511 operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1);
5512 else
5513 operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);
5514}")
5515
6131(define_expand "bne"
6132 [(match_dup 1)
6133 (set (pc)
6134 (if_then_else (ne (cc0)
6135 (const_int 0))
6136 (label_ref (match_operand 0 "" ""))
6137 (pc)))]
6138 ""
6139 "
6140{
6141 if (TARGET_IEEE_FP
6142 && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT)
6143 operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1);
6144 else
6145 operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);
6146}")
6147
5516(define_insn ""
5517 [(set (pc)
5518 (if_then_else (ne (cc0)
5519 (const_int 0))
5520 (label_ref (match_operand 0 "" ""))
5521 (pc)))]
5522 ""
5523 "*
5524{
5525 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
5526 return \"jc %l0\";
5527 else
5528 if (cc_prev_status.flags & CC_TEST_AX)
5529 {
5530 operands[1] = gen_rtx_REG (SImode, 0);
5531 operands[2] = GEN_INT (0x4000);
5532 output_asm_insn (AS2 (testl,%2,%1), operands);
5533 return AS1 (je,%l0);
5534 }
5535
6148
5536 return \"jne %l0\";
5537}")
5538
5539(define_expand "bgt"
5540 [(match_dup 1)
5541 (set (pc)
5542 (if_then_else (gt (cc0)
5543 (const_int 0))
5544 (label_ref (match_operand 0 "" ""))
5545 (pc)))]
5546 ""
5547 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5548
6149(define_expand "bgt"
6150 [(match_dup 1)
6151 (set (pc)
6152 (if_then_else (gt (cc0)
6153 (const_int 0))
6154 (label_ref (match_operand 0 "" ""))
6155 (pc)))]
6156 ""
6157 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
6158
5549(define_insn ""
5550 [(set (pc)
5551 (if_then_else (gt (cc0)
5552 (const_int 0))
5553 (label_ref (match_operand 0 "" ""))
5554 (pc)))]
5555 ""
5556 "*
5557{
5558 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
5559 && ! (cc_prev_status.flags & CC_FCOMI))
5560 return AS1 (je,%l0);
5561
5562 if (cc_prev_status.flags & CC_TEST_AX)
5563 {
5564 operands[1] = gen_rtx_REG (SImode, 0);
5565 operands[2] = GEN_INT (0x4100);
5566 output_asm_insn (AS2 (testl,%2,%1), operands);
5567 return AS1 (je,%l0);
5568 }
5569 OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR);
5570}")
5571
5572(define_expand "bgtu"
5573 [(match_dup 1)
5574 (set (pc)
5575 (if_then_else (gtu (cc0)
5576 (const_int 0))
5577 (label_ref (match_operand 0 "" ""))
5578 (pc)))]
5579 ""
5580 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5581
6159(define_expand "bgtu"
6160 [(match_dup 1)
6161 (set (pc)
6162 (if_then_else (gtu (cc0)
6163 (const_int 0))
6164 (label_ref (match_operand 0 "" ""))
6165 (pc)))]
6166 ""
6167 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
6168
5582(define_insn ""
5583 [(set (pc)
5584 (if_then_else (gtu (cc0)
5585 (const_int 0))
5586 (label_ref (match_operand 0 "" ""))
5587 (pc)))]
5588 ""
5589 "ja %l0")
5590
5591(define_expand "blt"
5592 [(match_dup 1)
5593 (set (pc)
5594 (if_then_else (lt (cc0)
5595 (const_int 0))
5596 (label_ref (match_operand 0 "" ""))
5597 (pc)))]
5598 ""
5599 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5600
6169(define_expand "blt"
6170 [(match_dup 1)
6171 (set (pc)
6172 (if_then_else (lt (cc0)
6173 (const_int 0))
6174 (label_ref (match_operand 0 "" ""))
6175 (pc)))]
6176 ""
6177 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
6178
5601(define_insn ""
5602 [(set (pc)
5603 (if_then_else (lt (cc0)
5604 (const_int 0))
5605 (label_ref (match_operand 0 "" ""))
5606 (pc)))]
5607 ""
5608 "*
5609{
5610 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
5611 && ! (cc_prev_status.flags & CC_FCOMI))
5612 return AS1 (je,%l0);
5613
6179
5614 if (cc_prev_status.flags & CC_TEST_AX)
5615 {
5616 operands[1] = gen_rtx_REG (SImode, 0);
5617 operands[2] = GEN_INT (0x100);
5618 output_asm_insn (AS2 (testl,%2,%1), operands);
5619 return AS1 (jne,%l0);
5620 }
5621 OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\");
5622}")
5623
5624(define_expand "bltu"
5625 [(match_dup 1)
5626 (set (pc)
5627 (if_then_else (ltu (cc0)
5628 (const_int 0))
5629 (label_ref (match_operand 0 "" ""))
5630 (pc)))]
5631 ""
5632 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5633
6180(define_expand "bltu"
6181 [(match_dup 1)
6182 (set (pc)
6183 (if_then_else (ltu (cc0)
6184 (const_int 0))
6185 (label_ref (match_operand 0 "" ""))
6186 (pc)))]
6187 ""
6188 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
6189
5634(define_insn ""
5635 [(set (pc)
5636 (if_then_else (ltu (cc0)
5637 (const_int 0))
5638 (label_ref (match_operand 0 "" ""))
5639 (pc)))]
5640 ""
5641 "jb %l0")
5642
5643(define_expand "bge"
5644 [(match_dup 1)
5645 (set (pc)
5646 (if_then_else (ge (cc0)
5647 (const_int 0))
5648 (label_ref (match_operand 0 "" ""))
5649 (pc)))]
5650 ""
5651 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5652
6190(define_expand "bge"
6191 [(match_dup 1)
6192 (set (pc)
6193 (if_then_else (ge (cc0)
6194 (const_int 0))
6195 (label_ref (match_operand 0 "" ""))
6196 (pc)))]
6197 ""
6198 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
6199
5653(define_insn ""
5654 [(set (pc)
5655 (if_then_else (ge (cc0)
5656 (const_int 0))
5657 (label_ref (match_operand 0 "" ""))
5658 (pc)))]
5659 ""
5660 "*
5661{
5662 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
5663 && ! (cc_prev_status.flags & CC_FCOMI))
5664 return AS1 (je,%l0);
5665 if (cc_prev_status.flags & CC_TEST_AX)
5666 {
5667 operands[1] = gen_rtx_REG (SImode, 0);
5668 operands[2] = GEN_INT (0x100);
5669 output_asm_insn (AS2 (testl,%2,%1), operands);
5670 return AS1 (je,%l0);
5671 }
5672 OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\");
5673}")
5674
5675(define_expand "bgeu"
5676 [(match_dup 1)
5677 (set (pc)
5678 (if_then_else (geu (cc0)
5679 (const_int 0))
5680 (label_ref (match_operand 0 "" ""))
5681 (pc)))]
5682 ""
5683 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5684
6200(define_expand "bgeu"
6201 [(match_dup 1)
6202 (set (pc)
6203 (if_then_else (geu (cc0)
6204 (const_int 0))
6205 (label_ref (match_operand 0 "" ""))
6206 (pc)))]
6207 ""
6208 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
6209
5685(define_insn ""
5686 [(set (pc)
5687 (if_then_else (geu (cc0)
5688 (const_int 0))
5689 (label_ref (match_operand 0 "" ""))
5690 (pc)))]
5691 ""
5692 "jae %l0")
5693
5694(define_expand "ble"
5695 [(match_dup 1)
5696 (set (pc)
5697 (if_then_else (le (cc0)
5698 (const_int 0))
5699 (label_ref (match_operand 0 "" ""))
5700 (pc)))]
5701 ""
5702 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5703
6210(define_expand "ble"
6211 [(match_dup 1)
6212 (set (pc)
6213 (if_then_else (le (cc0)
6214 (const_int 0))
6215 (label_ref (match_operand 0 "" ""))
6216 (pc)))]
6217 ""
6218 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
6219
5704(define_insn ""
5705 [(set (pc)
5706 (if_then_else (le (cc0)
5707 (const_int 0))
5708 (label_ref (match_operand 0 "" ""))
5709 (pc)))]
5710 ""
5711 "*
5712{
5713 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
5714 && ! (cc_prev_status.flags & CC_FCOMI))
5715 return AS1 (jb,%l0);
5716 if (cc_prev_status.flags & CC_TEST_AX)
5717 {
5718 operands[1] = gen_rtx_REG (SImode, 0);
5719 operands[2] = GEN_INT (0x4100);
5720 output_asm_insn (AS2 (testl,%2,%1), operands);
5721 return AS1 (jne,%l0);
5722 }
5723
5724 OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR);
5725}")
5726
5727(define_expand "bleu"
5728 [(match_dup 1)
5729 (set (pc)
5730 (if_then_else (leu (cc0)
5731 (const_int 0))
5732 (label_ref (match_operand 0 "" ""))
5733 (pc)))]
5734 ""
5735 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
5736
5737(define_insn ""
5738 [(set (pc)
6220(define_expand "bleu"
6221 [(match_dup 1)
6222 (set (pc)
6223 (if_then_else (leu (cc0)
6224 (const_int 0))
6225 (label_ref (match_operand 0 "" ""))
6226 (pc)))]
6227 ""
6228 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
6229
6230(define_insn ""
6231 [(set (pc)
5739 (if_then_else (leu (cc0)
5740 (const_int 0))
5741 (label_ref (match_operand 0 "" ""))
6232 (if_then_else (match_operator 0 "comparison_operator"
6233 [(cc0) (const_int 0)])
6234 (label_ref (match_operand 1 "" ""))
5742 (pc)))]
5743 ""
6235 (pc)))]
6236 ""
5744 "jbe %l0")
5745
5746;; Negated conditional jump instructions.
5747
5748(define_insn ""
5749 [(set (pc)
5750 (if_then_else (eq (cc0)
5751 (const_int 0))
5752 (pc)
5753 (label_ref (match_operand 0 "" ""))))]
5754 ""
5755 "*
5756{
6237 "*
6238{
5757 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
5758 return \"jc %l0\";
5759 else
6239 enum rtx_code code = GET_CODE (operands[0]);
5760 if (cc_prev_status.flags & CC_TEST_AX)
5761 {
6240 if (cc_prev_status.flags & CC_TEST_AX)
6241 {
5762 operands[1] = gen_rtx_REG (SImode, 0);
5763 operands[2] = GEN_INT (0x4000);
5764 output_asm_insn (AS2 (testl,%2,%1), operands);
5765 return AS1 (je,%l0);
6242 int eq;
6243 HOST_WIDE_INT c;
6244 operands[2] = gen_rtx_REG (SImode, 0);
6245 switch (code)
6246 {
6247 case EQ:
6248 c = 0x4000;
6249 eq = 0;
6250 break;
6251 case NE:
6252 c = 0x4000;
6253 eq = 1;
6254 break;
6255 case GT:
6256 c = 0x4100;
6257 eq = 1;
6258 break;
6259 case LT:
6260 c = 0x100;
6261 eq = 0;
6262 break;
6263 case GE:
6264 c = 0x100;
6265 eq = 1;
6266 break;
6267 case LE:
6268 c = 0x4100;
6269 eq = 0;
6270 break;
6271 default:
6272 abort ();
6273 }
6274 if (!TARGET_PENTIUM || optimize_size)
6275 {
6276 operands[3] = GEN_INT (c >> 8);
6277 output_asm_insn (AS2 (test%B0,%3,%h2), operands);
6278 }
6279 else
6280 {
6281 operands[3] = GEN_INT (c);
6282 output_asm_insn (AS2 (test%L0,%3,%2), operands);
6283 }
6284 return eq ? AS1 (je,%l1) : AS1 (jne, %l1);
5766 }
6285 }
5767 return \"jne %l0\";
5768}")
6286 if ((cc_status.flags & CC_NO_OVERFLOW) && (code == LE || code == GT))
6287 return (char *)0;
5769
6288
5770(define_insn ""
5771 [(set (pc)
5772 (if_then_else (ne (cc0)
5773 (const_int 0))
5774 (pc)
5775 (label_ref (match_operand 0 "" ""))))]
5776 ""
5777 "*
5778{
5779 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
5780 return \"jnc %l0\";
5781 else
5782 if (cc_prev_status.flags & CC_TEST_AX)
5783 {
5784 operands[1] = gen_rtx_REG (SImode, 0);
5785 operands[2] = GEN_INT (0x4000);
5786 output_asm_insn (AS2 (testl,%2,%1), operands);
5787 return AS1 (jne,%l0);
5788 }
5789 return \"je %l0\";
6289 return AS1(j%D0,%l1);
5790}")
5791
5792(define_insn ""
5793 [(set (pc)
6290}")
6291
6292(define_insn ""
6293 [(set (pc)
5794 (if_then_else (gt (cc0)
5795 (const_int 0))
6294 (if_then_else (match_operator 0 "comparison_operator"
6295 [(cc0) (const_int 0)])
5796 (pc)
6296 (pc)
5797 (label_ref (match_operand 0 "" ""))))]
6297 (label_ref (match_operand 1 "" ""))))]
5798 ""
5799 "*
5800{
6298 ""
6299 "*
6300{
5801 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
5802 && ! (cc_prev_status.flags & CC_FCOMI))
5803 return AS1 (jne,%l0);
6301 enum rtx_code code = GET_CODE (operands[0]);
5804 if (cc_prev_status.flags & CC_TEST_AX)
5805 {
6302 if (cc_prev_status.flags & CC_TEST_AX)
6303 {
5806 operands[1] = gen_rtx_REG (SImode, 0);
5807 operands[2] = GEN_INT (0x4100);
5808 output_asm_insn (AS2 (testl,%2,%1), operands);
5809 return AS1 (jne,%l0);
6304 int eq;
6305 HOST_WIDE_INT c;
6306 operands[2] = gen_rtx_REG (SImode, 0);
6307 switch (code)
6308 {
6309 case EQ:
6310 c = 0x4000;
6311 eq = 1;
6312 break;
6313 case NE:
6314 c = 0x4000;
6315 eq = 0;
6316 break;
6317 case GT:
6318 c = 0x4100;
6319 eq = 0;
6320 break;
6321 case LT:
6322 c = 0x100;
6323 eq = 1;
6324 break;
6325 case GE:
6326 c = 0x100;
6327 eq = 0;
6328 break;
6329 case LE:
6330 c = 0x4100;
6331 eq = 1;
6332 break;
6333 default:
6334 abort ();
6335 }
6336 if (!TARGET_PENTIUM || optimize_size)
6337 {
6338 operands[3] = GEN_INT (c >> 8);
6339 output_asm_insn (AS2 (test%B0,%3,%h2), operands);
6340 }
6341 else
6342 {
6343 operands[3] = GEN_INT (c);
6344 output_asm_insn (AS2 (test%L0,%3,%2), operands);
6345 }
6346 return eq ? AS1 (je,%l1) : AS1 (jne, %l1);
5810 }
6347 }
5811 OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR);
5812}")
6348 if ((cc_status.flags & CC_NO_OVERFLOW) && (code == LE || code == GT))
6349 return (char *)0;
5813
6350
5814(define_insn ""
5815 [(set (pc)
5816 (if_then_else (gtu (cc0)
5817 (const_int 0))
5818 (pc)
5819 (label_ref (match_operand 0 "" ""))))]
5820 ""
5821 "jbe %l0")
5822
5823(define_insn ""
5824 [(set (pc)
5825 (if_then_else (lt (cc0)
5826 (const_int 0))
5827 (pc)
5828 (label_ref (match_operand 0 "" ""))))]
5829 ""
5830 "*
5831{
5832 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
5833 && ! (cc_prev_status.flags & CC_FCOMI))
5834 return AS1 (jne,%l0);
5835 if (cc_prev_status.flags & CC_TEST_AX)
5836 {
5837 operands[1] = gen_rtx_REG (SImode, 0);
5838 operands[2] = GEN_INT (0x100);
5839 output_asm_insn (AS2 (testl,%2,%1), operands);
5840 return AS1 (je,%l0);
5841 }
5842
5843 OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\");
6351 return AS1(j%d0,%l1);
5844}")
6352}")
5845
5846(define_insn ""
5847 [(set (pc)
5848 (if_then_else (ltu (cc0)
5849 (const_int 0))
5850 (pc)
5851 (label_ref (match_operand 0 "" ""))))]
5852 ""
5853 "jae %l0")
5854
5855(define_insn ""
5856 [(set (pc)
5857 (if_then_else (ge (cc0)
5858 (const_int 0))
5859 (pc)
5860 (label_ref (match_operand 0 "" ""))))]
5861 ""
5862 "*
5863{
5864 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
5865 && ! (cc_prev_status.flags & CC_FCOMI))
5866 return AS1 (jne,%l0);
5867 if (cc_prev_status.flags & CC_TEST_AX)
5868 {
5869 operands[1] = gen_rtx_REG (SImode, 0);
5870 operands[2] = GEN_INT (0x100);
5871 output_asm_insn (AS2 (testl,%2,%1), operands);
5872 return AS1 (jne,%l0);
5873 }
5874 OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\");
5875}")
5876
5877(define_insn ""
5878 [(set (pc)
5879 (if_then_else (geu (cc0)
5880 (const_int 0))
5881 (pc)
5882 (label_ref (match_operand 0 "" ""))))]
5883 ""
5884 "jb %l0")
5885
5886(define_insn ""
5887 [(set (pc)
5888 (if_then_else (le (cc0)
5889 (const_int 0))
5890 (pc)
5891 (label_ref (match_operand 0 "" ""))))]
5892 ""
5893 "*
5894{
5895 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
5896 && ! (cc_prev_status.flags & CC_FCOMI))
5897 return AS1 (jae,%l0);
5898
5899 if (cc_prev_status.flags & CC_TEST_AX)
5900 {
5901 operands[1] = gen_rtx_REG (SImode, 0);
5902 operands[2] = GEN_INT (0x4100);
5903 output_asm_insn (AS2 (testl,%2,%1), operands);
5904 return AS1 (je,%l0);
5905 }
5906 OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR);
5907}")
5908
5909(define_insn ""
5910 [(set (pc)
5911 (if_then_else (leu (cc0)
5912 (const_int 0))
5913 (pc)
5914 (label_ref (match_operand 0 "" ""))))]
5915 ""
5916 "ja %l0")
5917
5918;; Unconditional and other jump instructions
5919
5920(define_insn "jump"
5921 [(set (pc)
5922 (label_ref (match_operand 0 "" "")))]
5923 ""
6353
6354;; Unconditional and other jump instructions
6355
6356(define_insn "jump"
6357 [(set (pc)
6358 (label_ref (match_operand 0 "" "")))]
6359 ""
5924 "jmp %l0")
6360 "jmp %l0"
6361 [(set_attr "memory" "none")])
5925
5926(define_insn "indirect_jump"
5927 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
5928 ""
5929 "*
5930{
5931 CC_STATUS_INIT;
5932
5933 return AS1 (jmp,%*%0);
6362
6363(define_insn "indirect_jump"
6364 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
6365 ""
6366 "*
6367{
6368 CC_STATUS_INIT;
6369
6370 return AS1 (jmp,%*%0);
5934}")
6371}"
6372 [(set_attr "memory" "none")])
5935
5936;; ??? could transform while(--i > 0) S; to if (--i > 0) do S; while(--i);
5937;; if S does not change i
5938
5939(define_expand "decrement_and_branch_until_zero"
5940 [(parallel [(set (pc)
5941 (if_then_else (ge (plus:SI (match_operand:SI 0 "general_operand" "")
5942 (const_int -1))

--- 4 unchanged lines hidden (view full) ---

5947 (plus:SI (match_dup 0)
5948 (const_int -1)))])]
5949 ""
5950 "")
5951
5952(define_insn ""
5953 [(set (pc)
5954 (if_then_else (match_operator 0 "arithmetic_comparison_operator"
6373
6374;; ??? could transform while(--i > 0) S; to if (--i > 0) do S; while(--i);
6375;; if S does not change i
6376
6377(define_expand "decrement_and_branch_until_zero"
6378 [(parallel [(set (pc)
6379 (if_then_else (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6380 (const_int -1))

--- 4 unchanged lines hidden (view full) ---

6385 (plus:SI (match_dup 0)
6386 (const_int -1)))])]
6387 ""
6388 "")
6389
6390(define_insn ""
6391 [(set (pc)
6392 (if_then_else (match_operator 0 "arithmetic_comparison_operator"
5955 [(plus:SI (match_operand:SI 1 "nonimmediate_operand" "+r,m")
6393 [(plus:SI (match_operand:SI 1 "nonimmediate_operand" "+c*r,m")
5956 (match_operand:SI 2 "general_operand" "rmi,ri"))
5957 (const_int 0)])
5958 (label_ref (match_operand 3 "" ""))
5959 (pc)))
5960 (set (match_dup 1)
5961 (plus:SI (match_dup 1)
5962 (match_dup 2)))]
5963 ""
5964 "*
5965{
5966 CC_STATUS_INIT;
6394 (match_operand:SI 2 "general_operand" "rmi,ri"))
6395 (const_int 0)])
6396 (label_ref (match_operand 3 "" ""))
6397 (pc)))
6398 (set (match_dup 1)
6399 (plus:SI (match_dup 1)
6400 (match_dup 2)))]
6401 ""
6402 "*
6403{
6404 CC_STATUS_INIT;
6405
6406 if (GET_CODE (operands[1]) == REG && REGNO (operands[2]) == 2 &&
6407 operands[2] == constm1_rtx && ix86_cpu == PROCESSOR_K6)
6408 return \"loop %l3\";
6409
5967 if (operands[2] == constm1_rtx)
5968 output_asm_insn (AS1 (dec%L1,%1), operands);
5969
5970 else if (operands[2] == const1_rtx)
5971 output_asm_insn (AS1 (inc%L1,%1), operands);
5972
5973 else
5974 output_asm_insn (AS2 (add%L1,%2,%1), operands);

--- 248 unchanged lines hidden (view full) ---

6223 (set (reg:SI 7)
6224 (plus:SI (reg:SI 7)
6225 (match_operand:SI 3 "immediate_operand" "")))])]
6226 ""
6227 "
6228{
6229 rtx addr;
6230
6410 if (operands[2] == constm1_rtx)
6411 output_asm_insn (AS1 (dec%L1,%1), operands);
6412
6413 else if (operands[2] == const1_rtx)
6414 output_asm_insn (AS1 (inc%L1,%1), operands);
6415
6416 else
6417 output_asm_insn (AS2 (add%L1,%2,%1), operands);

--- 248 unchanged lines hidden (view full) ---

6666 (set (reg:SI 7)
6667 (plus:SI (reg:SI 7)
6668 (match_operand:SI 3 "immediate_operand" "")))])]
6669 ""
6670 "
6671{
6672 rtx addr;
6673
6674 if (operands[3] == const0_rtx)
6675 {
6676 emit_insn (gen_call (operands[0], operands[1]));
6677 DONE;
6678 }
6679
6231 if (flag_pic)
6232 current_function_uses_pic_offset_table = 1;
6233
6234 /* With half-pic, force the address into a register. */
6235 addr = XEXP (operands[0], 0);
6236 if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr))
6237 XEXP (operands[0], 0) = force_reg (Pmode, addr);
6238

--- 86 unchanged lines hidden (view full) ---

6325 (set (reg:SI 7)
6326 (plus:SI (reg:SI 7)
6327 (match_operand:SI 4 "immediate_operand" "")))])]
6328 ""
6329 "
6330{
6331 rtx addr;
6332
6680 if (flag_pic)
6681 current_function_uses_pic_offset_table = 1;
6682
6683 /* With half-pic, force the address into a register. */
6684 addr = XEXP (operands[0], 0);
6685 if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr))
6686 XEXP (operands[0], 0) = force_reg (Pmode, addr);
6687

--- 86 unchanged lines hidden (view full) ---

6774 (set (reg:SI 7)
6775 (plus:SI (reg:SI 7)
6776 (match_operand:SI 4 "immediate_operand" "")))])]
6777 ""
6778 "
6779{
6780 rtx addr;
6781
6782 if (operands[4] == const0_rtx)
6783 {
6784 emit_insn (gen_call_value (operands[0], operands[1], operands[2]));
6785 DONE;
6786 }
6787
6333 if (flag_pic)
6334 current_function_uses_pic_offset_table = 1;
6335
6336 /* With half-pic, force the address into a register. */
6337 addr = XEXP (operands[1], 0);
6338 if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr))
6339 XEXP (operands[1], 0) = force_reg (Pmode, addr);
6340

--- 123 unchanged lines hidden (view full) ---

6464}")
6465
6466;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6467;; all of memory. This blocks insns from being moved across this point.
6468
6469(define_insn "blockage"
6470 [(unspec_volatile [(const_int 0)] 0)]
6471 ""
6788 if (flag_pic)
6789 current_function_uses_pic_offset_table = 1;
6790
6791 /* With half-pic, force the address into a register. */
6792 addr = XEXP (operands[1], 0);
6793 if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr))
6794 XEXP (operands[1], 0) = force_reg (Pmode, addr);
6795

--- 123 unchanged lines hidden (view full) ---

6919}")
6920
6921;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6922;; all of memory. This blocks insns from being moved across this point.
6923
6924(define_insn "blockage"
6925 [(unspec_volatile [(const_int 0)] 0)]
6926 ""
6472 "")
6927 ""
6928 [(set_attr "memory" "none")])
6473
6474;; Insn emitted into the body of a function to return from a function.
6475;; This is only done if the function's epilogue is known to be simple.
6476;; See comments for simple_386_epilogue in i386.c.
6477
6478(define_expand "return"
6479 [(return)]
6480 "ix86_can_use_return_insn_p ()"
6481 "")
6482
6483(define_insn "return_internal"
6484 [(return)]
6485 "reload_completed"
6929
6930;; Insn emitted into the body of a function to return from a function.
6931;; This is only done if the function's epilogue is known to be simple.
6932;; See comments for simple_386_epilogue in i386.c.
6933
6934(define_expand "return"
6935 [(return)]
6936 "ix86_can_use_return_insn_p ()"
6937 "")
6938
6939(define_insn "return_internal"
6940 [(return)]
6941 "reload_completed"
6486 "ret")
6942 "ret"
6943 [(set_attr "memory" "none")])
6487
6488(define_insn "return_pop_internal"
6489 [(return)
6490 (use (match_operand:SI 0 "const_int_operand" ""))]
6491 "reload_completed"
6944
6945(define_insn "return_pop_internal"
6946 [(return)
6947 (use (match_operand:SI 0 "const_int_operand" ""))]
6948 "reload_completed"
6492 "ret %0")
6949 "ret %0"
6950 [(set_attr "memory" "none")])
6493
6494(define_insn "nop"
6495 [(const_int 0)]
6496 ""
6951
6952(define_insn "nop"
6953 [(const_int 0)]
6954 ""
6497 "nop")
6955 "nop"
6956 [(set_attr "memory" "none")])
6498
6499(define_expand "prologue"
6500 [(const_int 1)]
6501 ""
6502 "
6503{
6504 ix86_expand_prologue ();
6505 DONE;

--- 10 unchanged lines hidden (view full) ---

6516 "*
6517{
6518 rtx xops [2];
6519
6520 xops[0] = operands[0];
6521 xops[1] = stack_pointer_rtx;
6522 output_asm_insn (AS2 (sub%L1,%0,%1), xops);
6523 RET;
6957
6958(define_expand "prologue"
6959 [(const_int 1)]
6960 ""
6961 "
6962{
6963 ix86_expand_prologue ();
6964 DONE;

--- 10 unchanged lines hidden (view full) ---

6975 "*
6976{
6977 rtx xops [2];
6978
6979 xops[0] = operands[0];
6980 xops[1] = stack_pointer_rtx;
6981 output_asm_insn (AS2 (sub%L1,%0,%1), xops);
6982 RET;
6524}")
6983}"
6984 [(set_attr "memory" "none")])
6525
6526(define_insn "prologue_set_got"
6527 [(set (match_operand:SI 0 "" "")
6528 (unspec_volatile
6529 [(plus:SI (match_dup 0)
6530 (plus:SI (match_operand:SI 1 "symbolic_operand" "")
6531 (minus:SI (pc) (match_operand 2 "" ""))))] 1))]
6532 ""

--- 15 unchanged lines hidden (view full) ---

6548}")
6549
6550(define_insn "prologue_get_pc"
6551 [(set (match_operand:SI 0 "" "")
6552 (unspec_volatile [(plus:SI (pc) (match_operand 1 "" ""))] 2))]
6553 ""
6554 "*
6555{
6985
6986(define_insn "prologue_set_got"
6987 [(set (match_operand:SI 0 "" "")
6988 (unspec_volatile
6989 [(plus:SI (match_dup 0)
6990 (plus:SI (match_operand:SI 1 "symbolic_operand" "")
6991 (minus:SI (pc) (match_operand 2 "" ""))))] 1))]
6992 ""

--- 15 unchanged lines hidden (view full) ---

7008}")
7009
7010(define_insn "prologue_get_pc"
7011 [(set (match_operand:SI 0 "" "")
7012 (unspec_volatile [(plus:SI (pc) (match_operand 1 "" ""))] 2))]
7013 ""
7014 "*
7015{
6556 char buffer[64];
6557
6558 output_asm_insn (AS1 (call,%X1), operands);
6559 if (! TARGET_DEEP_BRANCH_PREDICTION)
6560 {
6561 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (operands[1]));
6562 }
6563 RET;
7016 output_asm_insn (AS1 (call,%X1), operands);
7017 if (! TARGET_DEEP_BRANCH_PREDICTION)
7018 {
7019 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (operands[1]));
7020 }
7021 RET;
6564}")
7022}"
7023 [(set_attr "memory" "none")])
6565
6566(define_insn "prologue_get_pc_and_set_got"
6567 [(unspec_volatile [(match_operand:SI 0 "" "")] 3)]
6568 ""
6569 "*
6570{
6571 operands[1] = gen_label_rtx ();
6572 output_asm_insn (AS1 (call,%X1), operands);
6573 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
6574 CODE_LABEL_NUMBER (operands[1]));
6575 output_asm_insn (AS1 (pop%L0,%0), operands);
7024
7025(define_insn "prologue_get_pc_and_set_got"
7026 [(unspec_volatile [(match_operand:SI 0 "" "")] 3)]
7027 ""
7028 "*
7029{
7030 operands[1] = gen_label_rtx ();
7031 output_asm_insn (AS1 (call,%X1), operands);
7032 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
7033 CODE_LABEL_NUMBER (operands[1]));
7034 output_asm_insn (AS1 (pop%L0,%0), operands);
6576 output_asm_insn (\"addl $_GLOBAL_OFFSET_TABLE_+[.-%X1],%0\", operands);
7035 output_asm_insn (\"addl $%__GLOBAL_OFFSET_TABLE_+[.-%X1],%0\", operands);
6577 RET;
7036 RET;
6578}")
7037}"
7038 [(set_attr "memory" "none")])
6579
6580(define_expand "epilogue"
6581 [(const_int 1)]
6582 ""
6583 "
6584{
6585 ix86_expand_epilogue ();
6586 DONE;

--- 6 unchanged lines hidden (view full) ---

6593 "*
6594{
6595 rtx xops [2];
6596
6597 xops[0] = frame_pointer_rtx;
6598 xops[1] = stack_pointer_rtx;
6599 output_asm_insn (AS2 (mov%L0,%0,%1), xops);
6600 RET;
7039
7040(define_expand "epilogue"
7041 [(const_int 1)]
7042 ""
7043 "
7044{
7045 ix86_expand_epilogue ();
7046 DONE;

--- 6 unchanged lines hidden (view full) ---

7053 "*
7054{
7055 rtx xops [2];
7056
7057 xops[0] = frame_pointer_rtx;
7058 xops[1] = stack_pointer_rtx;
7059 output_asm_insn (AS2 (mov%L0,%0,%1), xops);
7060 RET;
6601}")
7061}"
7062 [(set_attr "memory" "none")])
6602
6603(define_insn "leave"
6604 [(const_int 2)
6605 (clobber (reg:SI 6))
6606 (clobber (reg:SI 7))]
6607 ""
7063
7064(define_insn "leave"
7065 [(const_int 2)
7066 (clobber (reg:SI 6))
7067 (clobber (reg:SI 7))]
7068 ""
6608 "leave")
7069 "leave"
7070 [(set_attr "memory" "none")])
6609
6610(define_insn "pop"
6611 [(set (match_operand:SI 0 "register_operand" "r")
6612 (mem:SI (reg:SI 7)))
6613 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))]
6614 ""
6615 "*
6616{
6617 output_asm_insn (AS1 (pop%L0,%P0), operands);
6618 RET;
7071
7072(define_insn "pop"
7073 [(set (match_operand:SI 0 "register_operand" "r")
7074 (mem:SI (reg:SI 7)))
7075 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))]
7076 ""
7077 "*
7078{
7079 output_asm_insn (AS1 (pop%L0,%P0), operands);
7080 RET;
6619}")
7081}"
7082 [(set_attr "memory" "load")])
6620
6621(define_expand "movstrsi"
6622 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6623 (match_operand:BLK 1 "memory_operand" ""))
6624 (use (match_operand:SI 2 "const_int_operand" ""))
6625 (use (match_operand:SI 3 "const_int_operand" ""))
6626 (clobber (match_scratch:SI 4 ""))
6627 (clobber (match_dup 5))

--- 65 unchanged lines hidden (view full) ---

6693 (use (match_operand:SI 1 "const_int_operand" ""))
6694 (use (match_operand:SI 2 "const_int_operand" ""))
6695 (use (match_dup 3))
6696 (clobber (match_scratch:SI 4 ""))
6697 (clobber (match_dup 5))])]
6698 ""
6699 "
6700{
7083
7084(define_expand "movstrsi"
7085 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
7086 (match_operand:BLK 1 "memory_operand" ""))
7087 (use (match_operand:SI 2 "const_int_operand" ""))
7088 (use (match_operand:SI 3 "const_int_operand" ""))
7089 (clobber (match_scratch:SI 4 ""))
7090 (clobber (match_dup 5))

--- 65 unchanged lines hidden (view full) ---

7156 (use (match_operand:SI 1 "const_int_operand" ""))
7157 (use (match_operand:SI 2 "const_int_operand" ""))
7158 (use (match_dup 3))
7159 (clobber (match_scratch:SI 4 ""))
7160 (clobber (match_dup 5))])]
7161 ""
7162 "
7163{
6701 rtx addr0, addr1;
7164 rtx addr0;
6702
6703 if (GET_CODE (operands[1]) != CONST_INT)
6704 FAIL;
6705
6706 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
6707
6708 operands[3] = gen_reg_rtx (SImode);
6709 operands[5] = addr0;
6710
6711 operands[0] = gen_rtx_MEM (BLKmode, addr0);
6712}")
6713
6714;; It might seem that operand 0 could use predicate register_operand.
6715;; But strength reduction might offset the MEM expression. So we let
6716;; reload put the address into %edi.
6717
7165
7166 if (GET_CODE (operands[1]) != CONST_INT)
7167 FAIL;
7168
7169 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
7170
7171 operands[3] = gen_reg_rtx (SImode);
7172 operands[5] = addr0;
7173
7174 operands[0] = gen_rtx_MEM (BLKmode, addr0);
7175}")
7176
7177;; It might seem that operand 0 could use predicate register_operand.
7178;; But strength reduction might offset the MEM expression. So we let
7179;; reload put the address into %edi.
7180
6718(define_insn ""
7181(define_insn "*bzero"
6719 [(set (mem:BLK (match_operand:SI 0 "address_operand" "D"))
6720 (const_int 0))
6721 (use (match_operand:SI 1 "const_int_operand" "n"))
6722 (use (match_operand:SI 2 "immediate_operand" "i"))
6723 (use (match_operand:SI 3 "register_operand" "a"))
6724 (clobber (match_scratch:SI 4 "=&c"))
6725 (clobber (match_dup 0))]
6726 ""
6727 "*
6728{
6729 rtx xops[2];
6730
6731 output_asm_insn (\"cld\", operands);
6732 if (GET_CODE (operands[1]) == CONST_INT)
6733 {
7182 [(set (mem:BLK (match_operand:SI 0 "address_operand" "D"))
7183 (const_int 0))
7184 (use (match_operand:SI 1 "const_int_operand" "n"))
7185 (use (match_operand:SI 2 "immediate_operand" "i"))
7186 (use (match_operand:SI 3 "register_operand" "a"))
7187 (clobber (match_scratch:SI 4 "=&c"))
7188 (clobber (match_dup 0))]
7189 ""
7190 "*
7191{
7192 rtx xops[2];
7193
7194 output_asm_insn (\"cld\", operands);
7195 if (GET_CODE (operands[1]) == CONST_INT)
7196 {
6734 if (INTVAL (operands[1]) & ~0x03)
7197 unsigned int count = INTVAL (operands[1]) & 0xffffffff;
7198 if (count & ~0x03)
6735 {
7199 {
6736 xops[0] = GEN_INT ((INTVAL (operands[1]) >> 2) & 0x3fffffff);
7200 xops[0] = GEN_INT (count / 4);
6737 xops[1] = operands[4];
6738
7201 xops[1] = operands[4];
7202
6739 output_asm_insn (AS2 (mov%L1,%0,%1), xops);
7203 /* K6: stos takes 1 cycle, rep stos takes 8 + %ecx cycles.
7204 80386: 4/5+5n (+2 for set of ecx)
7205 80486: 5/7+5n (+1 for set of ecx)
7206 */
7207 if (count / 4 < ((int) ix86_cpu < (int)PROCESSOR_PENTIUM ? 4 : 6))
7208 {
7209 do
6740#ifdef INTEL_SYNTAX
7210#ifdef INTEL_SYNTAX
6741 output_asm_insn (\"rep stosd\", xops);
7211 output_asm_insn (\"stosd\", xops);
6742#else
7212#else
6743 output_asm_insn (\"rep\;stosl\", xops);
7213 output_asm_insn (\"stosl\", xops);
6744#endif
7214#endif
7215 while ((count -= 4) > 3);
7216 }
7217 else
7218 {
7219 output_asm_insn (AS2 (mov%L1,%0,%1), xops);
7220#ifdef INTEL_SYNTAX
7221 output_asm_insn (\"rep stosd\", xops);
7222#else
7223 output_asm_insn (\"rep\;stosl\", xops);
7224#endif
7225 }
6745 }
6746 if (INTVAL (operands[1]) & 0x02)
6747 output_asm_insn (\"stosw\", operands);
6748 if (INTVAL (operands[1]) & 0x01)
6749 output_asm_insn (\"stosb\", operands);
6750 }
6751 else
6752 abort ();

--- 152 unchanged lines hidden (view full) ---

6905 (unspec:HI [(match_operand:SI 1 "nonimmediate_operand" "rm")] 5))]
6906 ""
6907 "* return AS2 (bsf%W0,%1,%0);")
6908
6909;; These patterns match the binary 387 instructions for addM3, subM3,
6910;; mulM3 and divM3. There are three patterns for each of DFmode and
6911;; SFmode. The first is the normal insn, the second the same insn but
6912;; with one operand a conversion, and the third the same insn but with
7226 }
7227 if (INTVAL (operands[1]) & 0x02)
7228 output_asm_insn (\"stosw\", operands);
7229 if (INTVAL (operands[1]) & 0x01)
7230 output_asm_insn (\"stosb\", operands);
7231 }
7232 else
7233 abort ();

--- 152 unchanged lines hidden (view full) ---

7386 (unspec:HI [(match_operand:SI 1 "nonimmediate_operand" "rm")] 5))]
7387 ""
7388 "* return AS2 (bsf%W0,%1,%0);")
7389
7390;; These patterns match the binary 387 instructions for addM3, subM3,
7391;; mulM3 and divM3. There are three patterns for each of DFmode and
7392;; SFmode. The first is the normal insn, the second the same insn but
7393;; with one operand a conversion, and the third the same insn but with
6913;; the other operand a conversion. The conversion may be SFmode or
6914;; SImode if the target mode DFmode, but only SImode if the target mode
6915;; is SFmode.
7394;; the other operand a conversion.
6916
6917(define_insn ""
6918 [(set (match_operand:DF 0 "register_operand" "=f,f")
6919 (match_operator:DF 3 "binary_387_op"
6920 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
6921 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
6922 "TARGET_80387"
6923 "* return output_387_binary_op (insn, operands);"
6924 [(set (attr "type")
6925 (cond [(match_operand:DF 3 "is_mul" "")
6926 (const_string "fpmul")
6927 (match_operand:DF 3 "is_div" "")
6928 (const_string "fpdiv")
6929 ]
6930 (const_string "fpop")
6931 )
6932 )])
6933
6934(define_insn ""
7395
7396(define_insn ""
7397 [(set (match_operand:DF 0 "register_operand" "=f,f")
7398 (match_operator:DF 3 "binary_387_op"
7399 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
7400 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
7401 "TARGET_80387"
7402 "* return output_387_binary_op (insn, operands);"
7403 [(set (attr "type")
7404 (cond [(match_operand:DF 3 "is_mul" "")
7405 (const_string "fpmul")
7406 (match_operand:DF 3 "is_div" "")
7407 (const_string "fpdiv")
7408 ]
7409 (const_string "fpop")
7410 )
7411 )])
7412
7413(define_insn ""
6935 [(set (match_operand:DF 0 "register_operand" "=f")
6936 (match_operator:DF 3 "binary_387_op"
6937 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "rm"))
6938 (match_operand:DF 2 "register_operand" "0")]))]
6939 "TARGET_80387"
6940 "* return output_387_binary_op (insn, operands);"
6941 [(set (attr "type")
6942 (cond [(match_operand:DF 3 "is_mul" "")
6943 (const_string "fpmul")
6944 (match_operand:DF 3 "is_div" "")
6945 (const_string "fpdiv")
6946 ]
6947 (const_string "fpop")
6948 )
6949 )])
6950
6951(define_insn ""
6952 [(set (match_operand:XF 0 "register_operand" "=f,f")
6953 (match_operator:XF 3 "binary_387_op"
6954 [(match_operand:XF 1 "register_operand" "0,f")
6955 (match_operand:XF 2 "register_operand" "f,0")]))]
6956 "TARGET_80387"
6957 "* return output_387_binary_op (insn, operands);"
6958 [(set (attr "type")
6959 (cond [(match_operand:DF 3 "is_mul" "")
6960 (const_string "fpmul")
6961 (match_operand:DF 3 "is_div" "")
6962 (const_string "fpdiv")
6963 ]
6964 (const_string "fpop")
6965 )
6966 )])
6967
6968(define_insn ""
7414 [(set (match_operand:XF 0 "register_operand" "=f,f")
7415 (match_operator:XF 3 "binary_387_op"
7416 [(match_operand:XF 1 "register_operand" "0,f")
7417 (match_operand:XF 2 "register_operand" "f,0")]))]
7418 "TARGET_80387"
7419 "* return output_387_binary_op (insn, operands);"
7420 [(set (attr "type")
7421 (cond [(match_operand:DF 3 "is_mul" "")
7422 (const_string "fpmul")
7423 (match_operand:DF 3 "is_div" "")
7424 (const_string "fpdiv")
7425 ]
7426 (const_string "fpop")
7427 )
7428 )])
7429
7430(define_insn ""
6969 [(set (match_operand:XF 0 "register_operand" "=f")
6970 (match_operator:XF 3 "binary_387_op"
6971 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "rm"))
6972 (match_operand:XF 2 "register_operand" "0")]))]
6973 "TARGET_80387"
6974 "* return output_387_binary_op (insn, operands);"
6975 [(set (attr "type")
6976 (cond [(match_operand:DF 3 "is_mul" "")
6977 (const_string "fpmul")
6978 (match_operand:DF 3 "is_div" "")
6979 (const_string "fpdiv")
6980 ]
6981 (const_string "fpop")
6982 )
6983 )])
6984
6985(define_insn ""
6986 [(set (match_operand:XF 0 "register_operand" "=f,f")
6987 (match_operator:XF 3 "binary_387_op"
6988 [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
6989 (match_operand:XF 2 "register_operand" "0,f")]))]
6990 "TARGET_80387"
6991 "* return output_387_binary_op (insn, operands);"
6992 [(set (attr "type")
6993 (cond [(match_operand:DF 3 "is_mul" "")
6994 (const_string "fpmul")
6995 (match_operand:DF 3 "is_div" "")
6996 (const_string "fpdiv")
6997 ]
6998 (const_string "fpop")
6999 )
7000 )])
7001
7002(define_insn ""
7431 [(set (match_operand:XF 0 "register_operand" "=f,f")
7432 (match_operator:XF 3 "binary_387_op"
7433 [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
7434 (match_operand:XF 2 "register_operand" "0,f")]))]
7435 "TARGET_80387"
7436 "* return output_387_binary_op (insn, operands);"
7437 [(set (attr "type")
7438 (cond [(match_operand:DF 3 "is_mul" "")
7439 (const_string "fpmul")
7440 (match_operand:DF 3 "is_div" "")
7441 (const_string "fpdiv")
7442 ]
7443 (const_string "fpop")
7444 )
7445 )])
7446
7447(define_insn ""
7003 [(set (match_operand:XF 0 "register_operand" "=f")
7004 (match_operator:XF 3 "binary_387_op"
7005 [(match_operand:XF 1 "register_operand" "0")
7006 (float:XF (match_operand:SI 2 "nonimmediate_operand" "rm"))]))]
7007 "TARGET_80387"
7008 "* return output_387_binary_op (insn, operands);"
7009 [(set (attr "type")
7010 (cond [(match_operand:DF 3 "is_mul" "")
7011 (const_string "fpmul")
7012 (match_operand:DF 3 "is_div" "")
7013 (const_string "fpdiv")
7014 ]
7015 (const_string "fpop")
7016 )
7017 )])
7018
7019(define_insn ""
7020 [(set (match_operand:XF 0 "register_operand" "=f,f")
7021 (match_operator:XF 3 "binary_387_op"
7022 [(match_operand:XF 1 "register_operand" "0,f")
7023 (float_extend:XF
7024 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
7025 "TARGET_80387"
7026 "* return output_387_binary_op (insn, operands);"
7027 [(set (attr "type")

--- 19 unchanged lines hidden (view full) ---

7047 (match_operand:DF 3 "is_div" "")
7048 (const_string "fpdiv")
7049 ]
7050 (const_string "fpop")
7051 )
7052 )])
7053
7054(define_insn ""
7448 [(set (match_operand:XF 0 "register_operand" "=f,f")
7449 (match_operator:XF 3 "binary_387_op"
7450 [(match_operand:XF 1 "register_operand" "0,f")
7451 (float_extend:XF
7452 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
7453 "TARGET_80387"
7454 "* return output_387_binary_op (insn, operands);"
7455 [(set (attr "type")

--- 19 unchanged lines hidden (view full) ---

7475 (match_operand:DF 3 "is_div" "")
7476 (const_string "fpdiv")
7477 ]
7478 (const_string "fpop")
7479 )
7480 )])
7481
7482(define_insn ""
7055 [(set (match_operand:DF 0 "register_operand" "=f")
7056 (match_operator:DF 3 "binary_387_op"
7057 [(match_operand:DF 1 "register_operand" "0")
7058 (float:DF (match_operand:SI 2 "nonimmediate_operand" "rm"))]))]
7059 "TARGET_80387"
7060 "* return output_387_binary_op (insn, operands);"
7061 [(set (attr "type")
7062 (cond [(match_operand:DF 3 "is_mul" "")
7063 (const_string "fpmul")
7064 (match_operand:DF 3 "is_div" "")
7065 (const_string "fpdiv")
7066 ]
7067 (const_string "fpop")
7068 )
7069 )])
7070
7071(define_insn ""
7072 [(set (match_operand:DF 0 "register_operand" "=f,f")
7073 (match_operator:DF 3 "binary_387_op"
7074 [(match_operand:DF 1 "register_operand" "0,f")
7075 (float_extend:DF
7076 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
7077 "TARGET_80387"
7078 "* return output_387_binary_op (insn, operands);"
7079 [(set (attr "type")

--- 17 unchanged lines hidden (view full) ---

7097 (cond [(match_operand:DF 3 "is_mul" "")
7098 (const_string "fpmul")
7099 (match_operand:DF 3 "is_div" "")
7100 (const_string "fpdiv")
7101 ]
7102 (const_string "fpop")
7103 )
7104 )])
7483 [(set (match_operand:DF 0 "register_operand" "=f,f")
7484 (match_operator:DF 3 "binary_387_op"
7485 [(match_operand:DF 1 "register_operand" "0,f")
7486 (float_extend:DF
7487 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
7488 "TARGET_80387"
7489 "* return output_387_binary_op (insn, operands);"
7490 [(set (attr "type")

--- 17 unchanged lines hidden (view full) ---

7508 (cond [(match_operand:DF 3 "is_mul" "")
7509 (const_string "fpmul")
7510 (match_operand:DF 3 "is_div" "")
7511 (const_string "fpdiv")
7512 ]
7513 (const_string "fpop")
7514 )
7515 )])
7105
7106(define_insn ""
7107 [(set (match_operand:SF 0 "register_operand" "=f")
7108 (match_operator:SF 3 "binary_387_op"
7109 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "rm"))
7110 (match_operand:SF 2 "register_operand" "0")]))]
7111 "TARGET_80387"
7112 "* return output_387_binary_op (insn, operands);"
7113 [(set (attr "type")
7114 (cond [(match_operand:DF 3 "is_mul" "")
7115 (const_string "fpmul")
7116 (match_operand:DF 3 "is_div" "")
7117 (const_string "fpdiv")
7118 ]
7119 (const_string "fpop")
7120 )
7121 )])
7122
7123(define_insn ""
7124 [(set (match_operand:SF 0 "register_operand" "=f")
7125 (match_operator:SF 3 "binary_387_op"
7126 [(match_operand:SF 1 "register_operand" "0")
7127 (float:SF (match_operand:SI 2 "nonimmediate_operand" "rm"))]))]
7128 "TARGET_80387"
7129 "* return output_387_binary_op (insn, operands);"
7130 [(set (attr "type")
7131 (cond [(match_operand:DF 3 "is_mul" "")
7132 (const_string "fpmul")
7133 (match_operand:DF 3 "is_div" "")
7134 (const_string "fpdiv")
7135 ]
7136 (const_string "fpop")
7137 )
7138 )])
7139
7140(define_expand "strlensi"
7141 [(parallel [(set (match_dup 4)
7142 (unspec:SI [(mem:BLK (match_operand:BLK 1 "general_operand" ""))
7143 (match_operand:QI 2 "immediate_operand" "")
7144 (match_operand:SI 3 "immediate_operand" "")] 0))
7145 (clobber (match_dup 1))])
7146 (set (match_dup 5)

--- 106 unchanged lines hidden (view full) ---

7253 [(match_operand 2 "nonimmediate_operand" "r,m,r,m")
7254 (match_operand 3 "general_operand" "rmi,ri,rmi,ri")])
7255 (match_operand:SI 4 "nonimmediate_operand" "rm,rm,0,0")
7256 (match_operand:SI 5 "nonimmediate_operand" "0,0,rm,rm")))]
7257 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT"
7258 "#")
7259
7260(define_split
7516
7517(define_expand "strlensi"
7518 [(parallel [(set (match_dup 4)
7519 (unspec:SI [(mem:BLK (match_operand:BLK 1 "general_operand" ""))
7520 (match_operand:QI 2 "immediate_operand" "")
7521 (match_operand:SI 3 "immediate_operand" "")] 0))
7522 (clobber (match_dup 1))])
7523 (set (match_dup 5)

--- 106 unchanged lines hidden (view full) ---

7630 [(match_operand 2 "nonimmediate_operand" "r,m,r,m")
7631 (match_operand 3 "general_operand" "rmi,ri,rmi,ri")])
7632 (match_operand:SI 4 "nonimmediate_operand" "rm,rm,0,0")
7633 (match_operand:SI 5 "nonimmediate_operand" "0,0,rm,rm")))]
7634 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT"
7635 "#")
7636
7637(define_split
7261 [(set (match_operand:SI 0 "register_operand" "=r,r")
7638 [(set (match_operand:SI 0 "register_operand" "")
7262 (if_then_else:SI (match_operator 1 "comparison_operator"
7263 [(match_operand 2 "nonimmediate_operand" "")
7264 (const_int 0)])
7639 (if_then_else:SI (match_operator 1 "comparison_operator"
7640 [(match_operand 2 "nonimmediate_operand" "")
7641 (const_int 0)])
7265 (match_operand:SI 3 "nonimmediate_operand" "rm,0")
7266 (match_operand:SI 4 "nonimmediate_operand" "0,rm")))]
7642 (match_operand:SI 3 "nonimmediate_operand" "")
7643 (match_operand:SI 4 "nonimmediate_operand" "")))]
7267 "TARGET_CMOVE && reload_completed"
7268 [(set (cc0)
7269 (match_dup 2))
7270 (set (match_dup 0)
7271 (if_then_else:SI (match_op_dup 1 [(cc0) (const_int 0)])
7272 (match_dup 3) (match_dup 4)))]
7273 "")
7274
7275(define_split
7644 "TARGET_CMOVE && reload_completed"
7645 [(set (cc0)
7646 (match_dup 2))
7647 (set (match_dup 0)
7648 (if_then_else:SI (match_op_dup 1 [(cc0) (const_int 0)])
7649 (match_dup 3) (match_dup 4)))]
7650 "")
7651
7652(define_split
7276 [(set (match_operand:SI 0 "register_operand" "=r,r")
7653 [(set (match_operand:SI 0 "register_operand" "")
7277 (if_then_else:SI (match_operator 1 "comparison_operator"
7278 [(match_operand 2 "nonimmediate_operand" "")
7279 (match_operand 3 "general_operand" "")])
7654 (if_then_else:SI (match_operator 1 "comparison_operator"
7655 [(match_operand 2 "nonimmediate_operand" "")
7656 (match_operand 3 "general_operand" "")])
7280 (match_operand:SI 4 "nonimmediate_operand" "rm,0")
7281 (match_operand:SI 5 "nonimmediate_operand" "0,rm")))]
7657 (match_operand:SI 4 "nonimmediate_operand" "")
7658 (match_operand:SI 5 "nonimmediate_operand" "")))]
7282 "TARGET_CMOVE && reload_completed"
7283 [(set (cc0) (compare (match_dup 2) (match_dup 3)))
7284 (set (match_dup 0)
7285 (if_then_else:SI (match_op_dup 1 [(cc0) (const_int 0)])
7286 (match_dup 4) (match_dup 5)))]
7287 "")
7288
7289(define_insn ""

--- 37 unchanged lines hidden (view full) ---

7327 [(match_operand 2 "nonimmediate_operand" "r,m,r,m")
7328 (match_operand 3 "general_operand" "rmi,ri,rmi,ri")])
7329 (match_operand:HI 4 "nonimmediate_operand" "rm,rm,0,0")
7330 (match_operand:HI 5 "nonimmediate_operand" "0,0,rm,rm")))]
7331 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT"
7332 "#")
7333
7334(define_split
7659 "TARGET_CMOVE && reload_completed"
7660 [(set (cc0) (compare (match_dup 2) (match_dup 3)))
7661 (set (match_dup 0)
7662 (if_then_else:SI (match_op_dup 1 [(cc0) (const_int 0)])
7663 (match_dup 4) (match_dup 5)))]
7664 "")
7665
7666(define_insn ""

--- 37 unchanged lines hidden (view full) ---

7704 [(match_operand 2 "nonimmediate_operand" "r,m,r,m")
7705 (match_operand 3 "general_operand" "rmi,ri,rmi,ri")])
7706 (match_operand:HI 4 "nonimmediate_operand" "rm,rm,0,0")
7707 (match_operand:HI 5 "nonimmediate_operand" "0,0,rm,rm")))]
7708 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT"
7709 "#")
7710
7711(define_split
7335 [(set (match_operand:HI 0 "register_operand" "=r,r")
7712 [(set (match_operand:HI 0 "register_operand" "")
7336 (if_then_else:HI (match_operator 1 "comparison_operator"
7337 [(match_operand 2 "nonimmediate_operand" "")
7338 (const_int 0)])
7713 (if_then_else:HI (match_operator 1 "comparison_operator"
7714 [(match_operand 2 "nonimmediate_operand" "")
7715 (const_int 0)])
7339 (match_operand:HI 3 "nonimmediate_operand" "rm,0")
7340 (match_operand:HI 4 "nonimmediate_operand" "0,rm")))]
7716 (match_operand:HI 3 "nonimmediate_operand" "")
7717 (match_operand:HI 4 "nonimmediate_operand" "")))]
7341 "TARGET_CMOVE && reload_completed"
7342 [(set (cc0)
7343 (match_dup 2))
7344 (set (match_dup 0)
7345 (if_then_else:HI (match_op_dup 1 [(cc0) (const_int 0)])
7346 (match_dup 3) (match_dup 4)))]
7347 "")
7348
7349(define_split
7718 "TARGET_CMOVE && reload_completed"
7719 [(set (cc0)
7720 (match_dup 2))
7721 (set (match_dup 0)
7722 (if_then_else:HI (match_op_dup 1 [(cc0) (const_int 0)])
7723 (match_dup 3) (match_dup 4)))]
7724 "")
7725
7726(define_split
7350 [(set (match_operand:HI 0 "register_operand" "=r,r")
7727 [(set (match_operand:HI 0 "register_operand" "")
7351 (if_then_else:HI (match_operator 1 "comparison_operator"
7352 [(match_operand 2 "nonimmediate_operand" "")
7353 (match_operand 3 "general_operand" "")])
7728 (if_then_else:HI (match_operator 1 "comparison_operator"
7729 [(match_operand 2 "nonimmediate_operand" "")
7730 (match_operand 3 "general_operand" "")])
7354 (match_operand:HI 4 "nonimmediate_operand" "rm,0")
7355 (match_operand:HI 5 "nonimmediate_operand" "0,rm")))]
7731 (match_operand:HI 4 "nonimmediate_operand" "")
7732 (match_operand:HI 5 "nonimmediate_operand" "")))]
7356 "TARGET_CMOVE && reload_completed"
7357 [(set (cc0)
7358 (compare (match_dup 2) (match_dup 3)))
7359 (set (match_dup 0)
7360 (if_then_else:HI (match_op_dup 1 [(cc0) (const_int 0)])
7361 (match_dup 4) (match_dup 5)))]
7362 "")
7363

--- 66 unchanged lines hidden (view full) ---

7430 (match_operand:SF 4 "register_operand" "f,f,0,0")
7431 (match_operand:SF 5 "register_operand" "0,0,f,f")))]
7432 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT
7433 && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE
7434 && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT"
7435 "#")
7436
7437(define_split
7733 "TARGET_CMOVE && reload_completed"
7734 [(set (cc0)
7735 (compare (match_dup 2) (match_dup 3)))
7736 (set (match_dup 0)
7737 (if_then_else:HI (match_op_dup 1 [(cc0) (const_int 0)])
7738 (match_dup 4) (match_dup 5)))]
7739 "")
7740

--- 66 unchanged lines hidden (view full) ---

7807 (match_operand:SF 4 "register_operand" "f,f,0,0")
7808 (match_operand:SF 5 "register_operand" "0,0,f,f")))]
7809 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT
7810 && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE
7811 && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT"
7812 "#")
7813
7814(define_split
7438 [(set (match_operand:SF 0 "register_operand" "=f,f")
7815 [(set (match_operand:SF 0 "register_operand" "")
7439 (if_then_else:SF (match_operator 1 "comparison_operator"
7440 [(match_operand 2 "nonimmediate_operand" "")
7441 (const_int 0)])
7816 (if_then_else:SF (match_operator 1 "comparison_operator"
7817 [(match_operand 2 "nonimmediate_operand" "")
7818 (const_int 0)])
7442 (match_operand:SF 3 "register_operand" "f,0")
7443 (match_operand:SF 4 "register_operand" "0,f")))]
7819 (match_operand:SF 3 "register_operand" "")
7820 (match_operand:SF 4 "register_operand" "")))]
7444 "TARGET_CMOVE && reload_completed"
7445 [(set (cc0)
7446 (match_dup 2))
7447 (set (match_dup 0)
7448 (if_then_else:SF (match_op_dup 1 [(cc0) (const_int 0)])
7449 (match_dup 3) (match_dup 4)))]
7450 "")
7451
7452(define_split
7821 "TARGET_CMOVE && reload_completed"
7822 [(set (cc0)
7823 (match_dup 2))
7824 (set (match_dup 0)
7825 (if_then_else:SF (match_op_dup 1 [(cc0) (const_int 0)])
7826 (match_dup 3) (match_dup 4)))]
7827 "")
7828
7829(define_split
7453 [(set (match_operand:SF 0 "register_operand" "=f,f")
7830 [(set (match_operand:SF 0 "register_operand" "")
7454 (if_then_else:SF (match_operator 1 "comparison_operator"
7455 [(match_operand 2 "nonimmediate_operand" "")
7456 (match_operand 3 "general_operand" "")])
7831 (if_then_else:SF (match_operator 1 "comparison_operator"
7832 [(match_operand 2 "nonimmediate_operand" "")
7833 (match_operand 3 "general_operand" "")])
7457 (match_operand:SF 4 "register_operand" "f,0")
7458 (match_operand:SF 5 "register_operand" "0,f")))]
7834 (match_operand:SF 4 "register_operand" "")
7835 (match_operand:SF 5 "register_operand" "")))]
7459 "TARGET_CMOVE && reload_completed"
7460 [(set (cc0) (compare (match_dup 2) (match_dup 3)))
7461 (set (match_dup 0)
7462 (if_then_else:SF (match_op_dup 1 [(cc0) (const_int 0)])
7463 (match_dup 4) (match_dup 5)))]
7464 "")
7465
7466(define_insn ""

--- 65 unchanged lines hidden (view full) ---

7532 (match_operand:DF 4 "register_operand" "f,f,0,0")
7533 (match_operand:DF 5 "register_operand" "0,0,f,f")))]
7534 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT
7535 && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE
7536 && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT"
7537 "#")
7538
7539(define_split
7836 "TARGET_CMOVE && reload_completed"
7837 [(set (cc0) (compare (match_dup 2) (match_dup 3)))
7838 (set (match_dup 0)
7839 (if_then_else:SF (match_op_dup 1 [(cc0) (const_int 0)])
7840 (match_dup 4) (match_dup 5)))]
7841 "")
7842
7843(define_insn ""

--- 65 unchanged lines hidden (view full) ---

7909 (match_operand:DF 4 "register_operand" "f,f,0,0")
7910 (match_operand:DF 5 "register_operand" "0,0,f,f")))]
7911 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT
7912 && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE
7913 && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT"
7914 "#")
7915
7916(define_split
7540 [(set (match_operand:DF 0 "register_operand" "=f,f")
7917 [(set (match_operand:DF 0 "register_operand" "")
7541 (if_then_else:DF (match_operator 1 "comparison_operator"
7542 [(match_operand 2 "nonimmediate_operand" "")
7543 (const_int 0)])
7918 (if_then_else:DF (match_operator 1 "comparison_operator"
7919 [(match_operand 2 "nonimmediate_operand" "")
7920 (const_int 0)])
7544 (match_operand:DF 3 "register_operand" "f,0")
7545 (match_operand:DF 4 "register_operand" "0,f")))]
7921 (match_operand:DF 3 "register_operand" "")
7922 (match_operand:DF 4 "register_operand" "")))]
7546 "TARGET_CMOVE && reload_completed"
7547 [(set (cc0)
7548 (match_dup 2))
7549 (set (match_dup 0)
7550 (if_then_else:DF (match_op_dup 1 [(cc0) (const_int 0)])
7551 (match_dup 3) (match_dup 4)))]
7552 "")
7553
7554(define_split
7923 "TARGET_CMOVE && reload_completed"
7924 [(set (cc0)
7925 (match_dup 2))
7926 (set (match_dup 0)
7927 (if_then_else:DF (match_op_dup 1 [(cc0) (const_int 0)])
7928 (match_dup 3) (match_dup 4)))]
7929 "")
7930
7931(define_split
7555 [(set (match_operand:DF 0 "register_operand" "=f,f")
7932 [(set (match_operand:DF 0 "register_operand" "")
7556 (if_then_else:DF (match_operator 1 "comparison_operator"
7557 [(match_operand 2 "nonimmediate_operand" "")
7558 (match_operand 3 "general_operand" "")])
7933 (if_then_else:DF (match_operator 1 "comparison_operator"
7934 [(match_operand 2 "nonimmediate_operand" "")
7935 (match_operand 3 "general_operand" "")])
7559 (match_operand:DF 4 "register_operand" "f,0")
7560 (match_operand:DF 5 "register_operand" "0,f")))]
7936 (match_operand:DF 4 "register_operand" "")
7937 (match_operand:DF 5 "register_operand" "")))]
7561 "TARGET_CMOVE && reload_completed"
7562 [(set (cc0) (compare (match_dup 2) (match_dup 3)))
7563 (set (match_dup 0)
7564 (if_then_else:DF (match_op_dup 1 [(cc0) (const_int 0)])
7565 (match_dup 4) (match_dup 5)))]
7566 "")
7567
7568(define_insn ""

--- 65 unchanged lines hidden (view full) ---

7634 (match_operand:XF 4 "register_operand" "f,f,0,0")
7635 (match_operand:XF 5 "register_operand" "0,0,f,f")))]
7636 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT
7637 && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE
7638 && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT"
7639 "#")
7640
7641(define_split
7938 "TARGET_CMOVE && reload_completed"
7939 [(set (cc0) (compare (match_dup 2) (match_dup 3)))
7940 (set (match_dup 0)
7941 (if_then_else:DF (match_op_dup 1 [(cc0) (const_int 0)])
7942 (match_dup 4) (match_dup 5)))]
7943 "")
7944
7945(define_insn ""

--- 65 unchanged lines hidden (view full) ---

8011 (match_operand:XF 4 "register_operand" "f,f,0,0")
8012 (match_operand:XF 5 "register_operand" "0,0,f,f")))]
8013 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT
8014 && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE
8015 && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT"
8016 "#")
8017
8018(define_split
7642 [(set (match_operand:XF 0 "register_operand" "=f,f")
8019 [(set (match_operand:XF 0 "register_operand" "")
7643 (if_then_else:XF (match_operator 1 "comparison_operator"
7644 [(match_operand 2 "nonimmediate_operand" "")
7645 (const_int 0)])
8020 (if_then_else:XF (match_operator 1 "comparison_operator"
8021 [(match_operand 2 "nonimmediate_operand" "")
8022 (const_int 0)])
7646 (match_operand:XF 3 "register_operand" "f,0")
7647 (match_operand:XF 4 "register_operand" "0,f")))]
8023 (match_operand:XF 3 "register_operand" "")
8024 (match_operand:XF 4 "register_operand" "")))]
7648 "TARGET_CMOVE && reload_completed"
7649 [(set (cc0)
7650 (match_dup 2))
7651 (set (match_dup 0)
7652 (if_then_else:XF (match_op_dup 1 [(cc0) (const_int 0)])
7653 (match_dup 3) (match_dup 4)))]
7654 "")
7655
7656(define_split
8025 "TARGET_CMOVE && reload_completed"
8026 [(set (cc0)
8027 (match_dup 2))
8028 (set (match_dup 0)
8029 (if_then_else:XF (match_op_dup 1 [(cc0) (const_int 0)])
8030 (match_dup 3) (match_dup 4)))]
8031 "")
8032
8033(define_split
7657 [(set (match_operand:XF 0 "register_operand" "=f,f")
8034 [(set (match_operand:XF 0 "register_operand" "")
7658 (if_then_else:XF (match_operator 1 "comparison_operator"
7659 [(match_operand 2 "nonimmediate_operand" "")
7660 (match_operand 3 "general_operand" "")])
8035 (if_then_else:XF (match_operator 1 "comparison_operator"
8036 [(match_operand 2 "nonimmediate_operand" "")
8037 (match_operand 3 "general_operand" "")])
7661 (match_operand:XF 4 "register_operand" "f,0")
7662 (match_operand:XF 5 "register_operand" "0,f")))]
8038 (match_operand:XF 4 "register_operand" "")
8039 (match_operand:XF 5 "register_operand" "")))]
7663 "TARGET_CMOVE && reload_completed"
7664 [(set (cc0) (compare (match_dup 2) (match_dup 3)))
7665 (set (match_dup 0)
7666 (if_then_else:XF (match_op_dup 1 [(cc0) (const_int 0)])
7667 (match_dup 4) (match_dup 5)))]
7668 "")
7669
7670(define_insn ""

--- 37 unchanged lines hidden (view full) ---

7708 [(match_operand 2 "nonimmediate_operand" "r,m,r,m")
7709 (match_operand 3 "general_operand" "rmi,ri,rmi,ri")])
7710 (match_operand:DI 4 "nonimmediate_operand" "ro,ro,0,0")
7711 (match_operand:DI 5 "nonimmediate_operand" "0,0,ro,ro")))]
7712 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT"
7713 "#")
7714
7715(define_split
8040 "TARGET_CMOVE && reload_completed"
8041 [(set (cc0) (compare (match_dup 2) (match_dup 3)))
8042 (set (match_dup 0)
8043 (if_then_else:XF (match_op_dup 1 [(cc0) (const_int 0)])
8044 (match_dup 4) (match_dup 5)))]
8045 "")
8046
8047(define_insn ""

--- 37 unchanged lines hidden (view full) ---

8085 [(match_operand 2 "nonimmediate_operand" "r,m,r,m")
8086 (match_operand 3 "general_operand" "rmi,ri,rmi,ri")])
8087 (match_operand:DI 4 "nonimmediate_operand" "ro,ro,0,0")
8088 (match_operand:DI 5 "nonimmediate_operand" "0,0,ro,ro")))]
8089 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT"
8090 "#")
8091
8092(define_split
7716 [(set (match_operand:DI 0 "register_operand" "=&r,&r")
8093 [(set (match_operand:DI 0 "register_operand" "")
7717 (if_then_else:DI (match_operator 1 "comparison_operator"
7718 [(match_operand 2 "nonimmediate_operand" "")
7719 (const_int 0)])
8094 (if_then_else:DI (match_operator 1 "comparison_operator"
8095 [(match_operand 2 "nonimmediate_operand" "")
8096 (const_int 0)])
7720 (match_operand:DI 3 "nonimmediate_operand" "ro,0")
7721 (match_operand:DI 4 "nonimmediate_operand" "0,ro")))]
8097 (match_operand:DI 3 "nonimmediate_operand" "")
8098 (match_operand:DI 4 "nonimmediate_operand" "")))]
7722 "TARGET_CMOVE && reload_completed"
7723 [(set (cc0)
7724 (match_dup 2))
8099 "TARGET_CMOVE && reload_completed"
8100 [(set (cc0)
8101 (match_dup 2))
7725 (set (match_dup 0)
7726 (if_then_else:DI (match_op_dup 1 [(cc0) (const_int 0)])
7727 (match_dup 3) (match_dup 4)))]
7728 "")
8102 (set (match_dup 5)
8103 (if_then_else:SI (match_op_dup 1 [(cc0) (const_int 0)])
8104 (match_dup 7) (match_dup 9)))
8105 (set (match_dup 6)
8106 (if_then_else:SI (match_op_dup 1 [(cc0) (const_int 0)])
8107 (match_dup 8) (match_dup 10)))]
8108 "split_di (&operands[0], 1, &operands[5], &operands[6]);
8109 split_di (&operands[3], 1, &operands[7], &operands[8]);
8110 split_di (&operands[4], 1, &operands[9], &operands[10]);")
7729
7730(define_split
8111
8112(define_split
7731 [(set (match_operand:DI 0 "register_operand" "=&r,&r")
8113 [(set (match_operand:DI 0 "register_operand" "")
7732 (if_then_else:DI (match_operator 1 "comparison_operator"
7733 [(match_operand 2 "nonimmediate_operand" "")
7734 (match_operand 3 "general_operand" "")])
8114 (if_then_else:DI (match_operator 1 "comparison_operator"
8115 [(match_operand 2 "nonimmediate_operand" "")
8116 (match_operand 3 "general_operand" "")])
7735 (match_operand:DI 4 "nonimmediate_operand" "ro,0")
7736 (match_operand:DI 5 "nonimmediate_operand" "0,ro")))]
8117 (match_operand:DI 4 "nonimmediate_operand" "")
8118 (match_operand:DI 5 "nonimmediate_operand" "")))]
7737 "TARGET_CMOVE && reload_completed"
7738 [(set (cc0) (compare (match_dup 2) (match_dup 3)))
8119 "TARGET_CMOVE && reload_completed"
8120 [(set (cc0) (compare (match_dup 2) (match_dup 3)))
7739 (set (match_dup 0)
7740 (if_then_else:DI (match_op_dup 1 [(cc0) (const_int 0)])
7741 (match_dup 4) (match_dup 5)))]
7742 "")
8121 (set (match_dup 6)
8122 (if_then_else:SI (match_op_dup 1 [(cc0) (const_int 0)])
8123 (match_dup 8) (match_dup 10)))
8124 (set (match_dup 7)
8125 (if_then_else:SI (match_op_dup 1 [(cc0) (const_int 0)])
8126 (match_dup 9) (match_dup 11)))]
8127 "split_di (&operands[0], 1, &operands[6], &operands[7]);
8128 split_di (&operands[4], 1, &operands[8], &operands[9]);
8129 split_di (&operands[5], 1, &operands[10], &operands[11]);")
7743
8130
7744(define_insn ""
7745 [(set (match_operand:DI 0 "register_operand" "=&r,&r")
7746 (if_then_else:DI (match_operator 1 "comparison_operator"
7747 [(cc0) (const_int 0)])
7748 (match_operand:DI 2 "nonimmediate_operand" "ro,0")
7749 (match_operand:DI 3 "nonimmediate_operand" "0,ro")))]
7750 "TARGET_CMOVE && reload_completed"
7751 "* return output_int_conditional_move (which_alternative, operands);")
7752
7753(define_insn "strlensi_unroll"
7754 [(set (match_operand:SI 0 "register_operand" "=&r,&r")
7755 (unspec:SI [(mem:BLK (match_operand:SI 1 "address_operand" "r,r"))
7756 (match_operand:SI 2 "immediate_operand" "i,i")] 0))
7757 (clobber (match_scratch:SI 3 "=&q,&r"))]
7758 "optimize > 1"
7759 "* return output_strlen_unroll (operands);")
7760

--- 19 unchanged lines hidden (view full) ---

7780 "* return output_strlen_unroll (operands);"
7781)
7782
7783(define_insn "allocate_stack_worker"
7784 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
7785 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
7786 (clobber (match_dup 0))]
7787 "TARGET_STACK_PROBE"
8131(define_insn "strlensi_unroll"
8132 [(set (match_operand:SI 0 "register_operand" "=&r,&r")
8133 (unspec:SI [(mem:BLK (match_operand:SI 1 "address_operand" "r,r"))
8134 (match_operand:SI 2 "immediate_operand" "i,i")] 0))
8135 (clobber (match_scratch:SI 3 "=&q,&r"))]
8136 "optimize > 1"
8137 "* return output_strlen_unroll (operands);")
8138

--- 19 unchanged lines hidden (view full) ---

8158 "* return output_strlen_unroll (operands);"
8159)
8160
8161(define_insn "allocate_stack_worker"
8162 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
8163 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
8164 (clobber (match_dup 0))]
8165 "TARGET_STACK_PROBE"
7788 "* return AS1(call,__alloca);")
8166 "* return AS1(call,__alloca);"
8167 [(set_attr "memory" "none")])
7789
7790(define_expand "allocate_stack"
7791 [(set (match_operand:SI 0 "register_operand" "=r")
7792 (minus:SI (reg:SI 7) (match_operand:SI 1 "general_operand" "")))
7793 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 1)))]
7794 "TARGET_STACK_PROBE"
7795 "
7796{

--- 22 unchanged lines hidden --- 		8168
8169(define_expand "allocate_stack"
8170 [(set (match_operand:SI 0 "register_operand" "=r")
8171 (minus:SI (reg:SI 7) (match_operand:SI 1 "general_operand" "")))
8172 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 1)))]
8173 "TARGET_STACK_PROBE"
8174 "
8175{

--- 22 unchanged lines hidden ---