i386.md (19194) | i386.md (50650) |
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1;; GCC machine description for Intel X86. 2;; Copyright (C) 1988, 1994, 1995 Free Software Foundation, Inc. | 1; GCC machine description for Intel X86. 2;; Copyright (C) 1988, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc. |
3;; Mostly by William Schelter. 4 5;; This file is part of GNU CC. 6 7;; GNU CC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 2, or (at your option) 10;; any later version. 11 12;; GNU CC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GNU CC; see the file COPYING. If not, write to 19;; the Free Software Foundation, 59 Temple Place - Suite 330, | 3;; Mostly by William Schelter. 4 5;; This file is part of GNU CC. 6 7;; GNU CC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 2, or (at your option) 10;; any later version. 11 12;; GNU CC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GNU CC; see the file COPYING. If not, write to 19;; the Free Software Foundation, 59 Temple Place - Suite 330, |
20;; Boston, MA 02111-1307, USA. | 20;; Boston, MA 02111-1307, USA. */ |
21 | 21 |
22 | |
23;; The original PO technology requires these to be ordered by speed, 24;; so that assigner will pick the fastest. 25 26;; See file "rtl.def" for documentation on define_insn, match_*, et. al. 27 28;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code 29;; updates for most instructions. 30 31;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register 32;; constraint letters. 33 34;; the special asm out single letter directives following a '%' are: 35;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of 36;; operands[1]. 37;; 'L' Print the opcode suffix for a 32-bit integer opcode. 38;; 'W' Print the opcode suffix for a 16-bit integer opcode. 39;; 'B' Print the opcode suffix for an 8-bit integer opcode. | 22;; The original PO technology requires these to be ordered by speed, 23;; so that assigner will pick the fastest. 24 25;; See file "rtl.def" for documentation on define_insn, match_*, et. al. 26 27;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code 28;; updates for most instructions. 29 30;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register 31;; constraint letters. 32 33;; the special asm out single letter directives following a '%' are: 34;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of 35;; operands[1]. 36;; 'L' Print the opcode suffix for a 32-bit integer opcode. 37;; 'W' Print the opcode suffix for a 16-bit integer opcode. 38;; 'B' Print the opcode suffix for an 8-bit integer opcode. |
40;; 'S' Print the opcode suffix for a 32-bit float opcode. | |
41;; 'Q' Print the opcode suffix for a 64-bit float opcode. | 39;; 'Q' Print the opcode suffix for a 64-bit float opcode. |
40;; 'S' Print the opcode suffix for a 32-bit float opcode. |
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42;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode. 43;; 'J' Print the appropriate jump operand. 44 45;; 'b' Print the QImode name of the register for the indicated operand. 46;; %b0 would print %al if operands[0] is reg 0. 47;; 'w' Likewise, print the HImode name of the register. 48;; 'k' Likewise, print the SImode name of the register. 49;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh. --- 4 unchanged lines hidden (view full) --- 54;; operand 0 is the memory address to scan. 55;; operand 1 is a register containing the value to scan for. The mode 56;; of the scas opcode will be the same as the mode of this operand. 57;; operand 2 is the known alignment of operand 0. 58;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT. 59;; operand 0 is the argument for `sin'. 60;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT. 61;; operand 0 is the argument for `cos'. | 41;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode. 42;; 'J' Print the appropriate jump operand. 43 44;; 'b' Print the QImode name of the register for the indicated operand. 45;; %b0 would print %al if operands[0] is reg 0. 46;; 'w' Likewise, print the HImode name of the register. 47;; 'k' Likewise, print the SImode name of the register. 48;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh. --- 4 unchanged lines hidden (view full) --- 53;; operand 0 is the memory address to scan. 54;; operand 1 is a register containing the value to scan for. The mode 55;; of the scas opcode will be the same as the mode of this operand. 56;; operand 2 is the known alignment of operand 0. 57;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT. 58;; operand 0 is the argument for `sin'. 59;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT. 60;; operand 0 is the argument for `cos'. |
61;; 3 This is part of a `stack probe' operation. The mode of the UNSPEC is 62;; always SImode. operand 0 is the size of the stack allocation. 63;; 4 This is the source of a fake SET of the frame pointer which is used to 64;; prevent insns referencing it being scheduled across the initial 65;; decrement of the stack pointer. 66;; 5 This is a `bsf' operation. |
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62 | 67 |
68;; This shadows the processor_type enumeration, so changes must be made 69;; to i386.h at the same time. 70 71(define_attr "type" "integer,idiv,imul,fld,fpop,fpdiv,fpmul" 72 (const_string "integer")) 73 74;; Functional units 75 76; (define_function_unit NAME MULTIPLICITY SIMULTANEITY 77; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) 78 79; pentiumpro has a reservation station with 5 ports 80; port 0 has integer, float add, integer divide, float divide, float 81; multiply, and shifter units. 82; port 1 has integer, and jump units. 83; port 2 has the load address generation unit 84; ports 3 and 4 have the store address generation units 85 86; pentium has two integer pipelines, the main u pipe and the secondary v pipe. 87; and a float pipeline 88 89;; Floating point 90 91(define_function_unit "fp" 1 0 92 (and (eq_attr "type" "fpop") (eq_attr "cpu" "i386,i486")) 93 5 5) 94 95(define_function_unit "fp" 1 0 96 (and (eq_attr "type" "fpop") (eq_attr "cpu" "pentium,pentiumpro")) 97 3 0) 98 99(define_function_unit "fp" 1 0 100 (and (eq_attr "type" "fpmul") (eq_attr "cpu" "pentium")) 101 7 0) 102 103(define_function_unit "fp" 1 0 104 (and (eq_attr "type" "fpmul") (eq_attr "cpu" "pentiumpro")) 105 5 0) 106 107(define_function_unit "fp" 1 0 108 (and (eq_attr "type" "idiv") (eq_attr "cpu" "pentiumpro")) 109 10 10) 110 111(define_function_unit "fp" 1 0 112 (and (eq_attr "type" "imul") (eq_attr "cpu" "pentiumpro")) 113 6 0) 114 115(define_function_unit "fp" 1 0 116 (eq_attr "type" "fpdiv") 117 10 10) 118 119(define_function_unit "fp" 1 0 120 (eq_attr "type" "fld") 121 1 0) 122 123(define_function_unit "integer" 1 0 124 (and (eq_attr "type" "integer") (eq_attr "cpu" "!i386")) 125 2 0) 126 127 |
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63;; "movl MEM,REG / testl REG,REG" is faster on a 486 than "cmpl $0,MEM". 64;; But restricting MEM here would mean that gcc could not remove a redundant 65;; test in cases like "incl MEM / je TARGET". 66;; 67;; We don't want to allow a constant operand for test insns because 68;; (set (cc0) (const_int foo)) has no mode information. Such insns will 69;; be folded while optimizing anyway. 70 71;; All test insns have expanders that save the operands away without 72;; actually generating RTL. The bCOND or sCOND (emitted immediately 73;; after the tstM or cmp) will actually emit the tstM or cmpM. 74 | 128;; "movl MEM,REG / testl REG,REG" is faster on a 486 than "cmpl $0,MEM". 129;; But restricting MEM here would mean that gcc could not remove a redundant 130;; test in cases like "incl MEM / je TARGET". 131;; 132;; We don't want to allow a constant operand for test insns because 133;; (set (cc0) (const_int foo)) has no mode information. Such insns will 134;; be folded while optimizing anyway. 135 136;; All test insns have expanders that save the operands away without 137;; actually generating RTL. The bCOND or sCOND (emitted immediately 138;; after the tstM or cmp) will actually emit the tstM or cmpM. 139 |
140;; Processor type -- this attribute must exactly match the processor_type 141;; enumeration in i386.h. 142 143(define_attr "cpu" "i386,i486,pentium,pentiumpro" 144 (const (symbol_ref "ix86_cpu"))) 145 |
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75(define_insn "tstsi_1" 76 [(set (cc0) 77 (match_operand:SI 0 "nonimmediate_operand" "rm"))] 78 "" 79 "* 80{ 81 if (REG_P (operands[0])) 82 return AS2 (test%L0,%0,%0); --- 5 unchanged lines hidden (view full) --- 88(define_expand "tstsi" 89 [(set (cc0) 90 (match_operand:SI 0 "nonimmediate_operand" ""))] 91 "" 92 " 93{ 94 i386_compare_gen = gen_tstsi_1; 95 i386_compare_op0 = operands[0]; | 146(define_insn "tstsi_1" 147 [(set (cc0) 148 (match_operand:SI 0 "nonimmediate_operand" "rm"))] 149 "" 150 "* 151{ 152 if (REG_P (operands[0])) 153 return AS2 (test%L0,%0,%0); --- 5 unchanged lines hidden (view full) --- 159(define_expand "tstsi" 160 [(set (cc0) 161 (match_operand:SI 0 "nonimmediate_operand" ""))] 162 "" 163 " 164{ 165 i386_compare_gen = gen_tstsi_1; 166 i386_compare_op0 = operands[0]; |
167 i386_compare_op1 = const0_rtx; |
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96 DONE; 97}") 98 99(define_insn "tsthi_1" 100 [(set (cc0) 101 (match_operand:HI 0 "nonimmediate_operand" "rm"))] 102 "" 103 "* --- 8 unchanged lines hidden (view full) --- 112(define_expand "tsthi" 113 [(set (cc0) 114 (match_operand:HI 0 "nonimmediate_operand" ""))] 115 "" 116 " 117{ 118 i386_compare_gen = gen_tsthi_1; 119 i386_compare_op0 = operands[0]; | 168 DONE; 169}") 170 171(define_insn "tsthi_1" 172 [(set (cc0) 173 (match_operand:HI 0 "nonimmediate_operand" "rm"))] 174 "" 175 "* --- 8 unchanged lines hidden (view full) --- 184(define_expand "tsthi" 185 [(set (cc0) 186 (match_operand:HI 0 "nonimmediate_operand" ""))] 187 "" 188 " 189{ 190 i386_compare_gen = gen_tsthi_1; 191 i386_compare_op0 = operands[0]; |
192 i386_compare_op1 = const0_rtx; |
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120 DONE; 121}") 122 123(define_insn "tstqi_1" 124 [(set (cc0) 125 (match_operand:QI 0 "nonimmediate_operand" "qm"))] 126 "" 127 "* --- 8 unchanged lines hidden (view full) --- 136(define_expand "tstqi" 137 [(set (cc0) 138 (match_operand:QI 0 "nonimmediate_operand" ""))] 139 "" 140 " 141{ 142 i386_compare_gen = gen_tstqi_1; 143 i386_compare_op0 = operands[0]; | 193 DONE; 194}") 195 196(define_insn "tstqi_1" 197 [(set (cc0) 198 (match_operand:QI 0 "nonimmediate_operand" "qm"))] 199 "" 200 "* --- 8 unchanged lines hidden (view full) --- 209(define_expand "tstqi" 210 [(set (cc0) 211 (match_operand:QI 0 "nonimmediate_operand" ""))] 212 "" 213 " 214{ 215 i386_compare_gen = gen_tstqi_1; 216 i386_compare_op0 = operands[0]; |
217 i386_compare_op1 = const0_rtx; |
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144 DONE; 145}") 146 147(define_insn "tstsf_cc" 148 [(set (cc0) 149 (match_operand:SF 0 "register_operand" "f")) 150 (clobber (match_scratch:HI 1 "=a"))] 151 "TARGET_80387 && ! TARGET_IEEE_FP" --- 17 unchanged lines hidden (view full) --- 169 [(parallel [(set (cc0) 170 (match_operand:SF 0 "register_operand" "")) 171 (clobber (match_scratch:HI 1 ""))])] 172 "TARGET_80387 && ! TARGET_IEEE_FP" 173 " 174{ 175 i386_compare_gen = gen_tstsf_cc; 176 i386_compare_op0 = operands[0]; | 218 DONE; 219}") 220 221(define_insn "tstsf_cc" 222 [(set (cc0) 223 (match_operand:SF 0 "register_operand" "f")) 224 (clobber (match_scratch:HI 1 "=a"))] 225 "TARGET_80387 && ! TARGET_IEEE_FP" --- 17 unchanged lines hidden (view full) --- 243 [(parallel [(set (cc0) 244 (match_operand:SF 0 "register_operand" "")) 245 (clobber (match_scratch:HI 1 ""))])] 246 "TARGET_80387 && ! TARGET_IEEE_FP" 247 " 248{ 249 i386_compare_gen = gen_tstsf_cc; 250 i386_compare_op0 = operands[0]; |
251 i386_compare_op1 = const0_rtx; |
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177 DONE; 178}") 179 180(define_insn "tstdf_cc" 181 [(set (cc0) 182 (match_operand:DF 0 "register_operand" "f")) 183 (clobber (match_scratch:HI 1 "=a"))] 184 "TARGET_80387 && ! TARGET_IEEE_FP" --- 17 unchanged lines hidden (view full) --- 202 [(parallel [(set (cc0) 203 (match_operand:DF 0 "register_operand" "")) 204 (clobber (match_scratch:HI 1 ""))])] 205 "TARGET_80387 && ! TARGET_IEEE_FP" 206 " 207{ 208 i386_compare_gen = gen_tstdf_cc; 209 i386_compare_op0 = operands[0]; | 252 DONE; 253}") 254 255(define_insn "tstdf_cc" 256 [(set (cc0) 257 (match_operand:DF 0 "register_operand" "f")) 258 (clobber (match_scratch:HI 1 "=a"))] 259 "TARGET_80387 && ! TARGET_IEEE_FP" --- 17 unchanged lines hidden (view full) --- 277 [(parallel [(set (cc0) 278 (match_operand:DF 0 "register_operand" "")) 279 (clobber (match_scratch:HI 1 ""))])] 280 "TARGET_80387 && ! TARGET_IEEE_FP" 281 " 282{ 283 i386_compare_gen = gen_tstdf_cc; 284 i386_compare_op0 = operands[0]; |
285 i386_compare_op1 = const0_rtx; |
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210 DONE; 211}") 212 213(define_insn "tstxf_cc" 214 [(set (cc0) 215 (match_operand:XF 0 "register_operand" "f")) 216 (clobber (match_scratch:HI 1 "=a"))] 217 "TARGET_80387 && ! TARGET_IEEE_FP" --- 5 unchanged lines hidden (view full) --- 223 output_asm_insn (\"ftst\", operands); 224 225 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) 226 output_asm_insn (AS1 (fstp,%y0), operands); 227 228 return output_fp_cc0_set (insn); 229}") 230 | 286 DONE; 287}") 288 289(define_insn "tstxf_cc" 290 [(set (cc0) 291 (match_operand:XF 0 "register_operand" "f")) 292 (clobber (match_scratch:HI 1 "=a"))] 293 "TARGET_80387 && ! TARGET_IEEE_FP" --- 5 unchanged lines hidden (view full) --- 299 output_asm_insn (\"ftst\", operands); 300 301 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) 302 output_asm_insn (AS1 (fstp,%y0), operands); 303 304 return output_fp_cc0_set (insn); 305}") 306 |
231;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode | 307;; Don't generate tstxf if generating IEEE code, since the `ftst' opcode |
232;; isn't IEEE compliant. 233 234(define_expand "tstxf" 235 [(parallel [(set (cc0) 236 (match_operand:XF 0 "register_operand" "")) 237 (clobber (match_scratch:HI 1 ""))])] 238 "TARGET_80387 && ! TARGET_IEEE_FP" 239 " 240{ 241 i386_compare_gen = gen_tstxf_cc; 242 i386_compare_op0 = operands[0]; | 308;; isn't IEEE compliant. 309 310(define_expand "tstxf" 311 [(parallel [(set (cc0) 312 (match_operand:XF 0 "register_operand" "")) 313 (clobber (match_scratch:HI 1 ""))])] 314 "TARGET_80387 && ! TARGET_IEEE_FP" 315 " 316{ 317 i386_compare_gen = gen_tstxf_cc; 318 i386_compare_op0 = operands[0]; |
319 i386_compare_op1 = const0_rtx; |
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243 DONE; 244}") 245 246;;- compare instructions. See comments above tstM patterns about 247;; expansion of these insns. 248 249(define_insn "cmpsi_1" 250 [(set (cc0) 251 (compare (match_operand:SI 0 "nonimmediate_operand" "mr,r") 252 (match_operand:SI 1 "general_operand" "ri,mr")))] 253 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" | 320 DONE; 321}") 322 323;;- compare instructions. See comments above tstM patterns about 324;; expansion of these insns. 325 326(define_insn "cmpsi_1" 327 [(set (cc0) 328 (compare (match_operand:SI 0 "nonimmediate_operand" "mr,r") 329 (match_operand:SI 1 "general_operand" "ri,mr")))] 330 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" |
254 "* 255{ 256 if (CONSTANT_P (operands[0]) || GET_CODE (operands[1]) == MEM) 257 { 258 cc_status.flags |= CC_REVERSED; 259 return AS2 (cmp%L0,%0,%1); 260 } 261 return AS2 (cmp%L0,%1,%0); 262}") | 331 "* return AS2 (cmp%L0,%1,%0);") |
263 264(define_expand "cmpsi" 265 [(set (cc0) 266 (compare (match_operand:SI 0 "nonimmediate_operand" "") 267 (match_operand:SI 1 "general_operand" "")))] 268 "" 269 " 270{ --- 6 unchanged lines hidden (view full) --- 277 DONE; 278}") 279 280(define_insn "cmphi_1" 281 [(set (cc0) 282 (compare (match_operand:HI 0 "nonimmediate_operand" "mr,r") 283 (match_operand:HI 1 "general_operand" "ri,mr")))] 284 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" | 332 333(define_expand "cmpsi" 334 [(set (cc0) 335 (compare (match_operand:SI 0 "nonimmediate_operand" "") 336 (match_operand:SI 1 "general_operand" "")))] 337 "" 338 " 339{ --- 6 unchanged lines hidden (view full) --- 346 DONE; 347}") 348 349(define_insn "cmphi_1" 350 [(set (cc0) 351 (compare (match_operand:HI 0 "nonimmediate_operand" "mr,r") 352 (match_operand:HI 1 "general_operand" "ri,mr")))] 353 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" |
285 "* 286{ 287 if (CONSTANT_P (operands[0]) || GET_CODE (operands[1]) == MEM) 288 { 289 cc_status.flags |= CC_REVERSED; 290 return AS2 (cmp%W0,%0,%1); 291 } 292 return AS2 (cmp%W0,%1,%0); 293}") | 354 "* return AS2 (cmp%W0,%1,%0);") |
294 295(define_expand "cmphi" 296 [(set (cc0) 297 (compare (match_operand:HI 0 "nonimmediate_operand" "") 298 (match_operand:HI 1 "general_operand" "")))] 299 "" 300 " 301{ --- 6 unchanged lines hidden (view full) --- 308 DONE; 309}") 310 311(define_insn "cmpqi_1" 312 [(set (cc0) 313 (compare (match_operand:QI 0 "nonimmediate_operand" "q,mq") 314 (match_operand:QI 1 "general_operand" "qm,nq")))] 315 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" | 355 356(define_expand "cmphi" 357 [(set (cc0) 358 (compare (match_operand:HI 0 "nonimmediate_operand" "") 359 (match_operand:HI 1 "general_operand" "")))] 360 "" 361 " 362{ --- 6 unchanged lines hidden (view full) --- 369 DONE; 370}") 371 372(define_insn "cmpqi_1" 373 [(set (cc0) 374 (compare (match_operand:QI 0 "nonimmediate_operand" "q,mq") 375 (match_operand:QI 1 "general_operand" "qm,nq")))] 376 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" |
316 "* 317{ 318 if (CONSTANT_P (operands[0]) || GET_CODE (operands[1]) == MEM) 319 { 320 cc_status.flags |= CC_REVERSED; 321 return AS2 (cmp%B0,%0,%1); 322 } 323 return AS2 (cmp%B0,%1,%0); 324}") | 377 "* return AS2 (cmp%B0,%1,%0);") |
325 326(define_expand "cmpqi" 327 [(set (cc0) 328 (compare (match_operand:QI 0 "nonimmediate_operand" "") 329 (match_operand:QI 1 "general_operand" "")))] 330 "" 331 " 332{ --- 8 unchanged lines hidden (view full) --- 341 342;; These implement float point compares. For each of DFmode and 343;; SFmode, there is the normal insn, and an insn where the second operand 344;; is converted to the desired mode. 345 346(define_insn "" 347 [(set (cc0) 348 (match_operator 2 "VOIDmode_compare_op" | 378 379(define_expand "cmpqi" 380 [(set (cc0) 381 (compare (match_operand:QI 0 "nonimmediate_operand" "") 382 (match_operand:QI 1 "general_operand" "")))] 383 "" 384 " 385{ --- 8 unchanged lines hidden (view full) --- 394 395;; These implement float point compares. For each of DFmode and 396;; SFmode, there is the normal insn, and an insn where the second operand 397;; is converted to the desired mode. 398 399(define_insn "" 400 [(set (cc0) 401 (match_operator 2 "VOIDmode_compare_op" |
349 [(match_operand:XF 0 "nonimmediate_operand" "f") 350 (match_operand:XF 1 "nonimmediate_operand" "f")])) | 402 [(match_operand:XF 0 "register_operand" "f") 403 (match_operand:XF 1 "register_operand" "f")])) |
351 (clobber (match_scratch:HI 3 "=a"))] | 404 (clobber (match_scratch:HI 3 "=a"))] |
352 "TARGET_80387 353 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | 405 "TARGET_80387" |
354 "* return output_float_compare (insn, operands);") 355 356(define_insn "" 357 [(set (cc0) 358 (match_operator 2 "VOIDmode_compare_op" 359 [(match_operand:XF 0 "register_operand" "f") 360 (float:XF 361 (match_operand:SI 1 "nonimmediate_operand" "rm"))])) --- 19 unchanged lines hidden (view full) --- 381 (match_operand:DF 1 "nonimmediate_operand" "fm"))])) 382 (clobber (match_scratch:HI 3 "=a"))] 383 "TARGET_80387" 384 "* return output_float_compare (insn, operands);") 385 386(define_insn "" 387 [(set (cc0) 388 (match_operator 2 "VOIDmode_compare_op" | 406 "* return output_float_compare (insn, operands);") 407 408(define_insn "" 409 [(set (cc0) 410 (match_operator 2 "VOIDmode_compare_op" 411 [(match_operand:XF 0 "register_operand" "f") 412 (float:XF 413 (match_operand:SI 1 "nonimmediate_operand" "rm"))])) --- 19 unchanged lines hidden (view full) --- 433 (match_operand:DF 1 "nonimmediate_operand" "fm"))])) 434 (clobber (match_scratch:HI 3 "=a"))] 435 "TARGET_80387" 436 "* return output_float_compare (insn, operands);") 437 438(define_insn "" 439 [(set (cc0) 440 (match_operator 2 "VOIDmode_compare_op" |
441 [(float_extend:XF 442 (match_operand:DF 0 "nonimmediate_operand" "fm")) 443 (match_operand:XF 1 "register_operand" "f")])) 444 (clobber (match_scratch:HI 3 "=a"))] 445 "TARGET_80387" 446 "* return output_float_compare (insn, operands);") 447 448(define_insn "" 449 [(set (cc0) 450 (match_operator 2 "VOIDmode_compare_op" |
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389 [(match_operand:XF 0 "register_operand" "f") 390 (float_extend:XF 391 (match_operand:SF 1 "nonimmediate_operand" "fm"))])) 392 (clobber (match_scratch:HI 3 "=a"))] 393 "TARGET_80387" 394 "* return output_float_compare (insn, operands);") 395 396(define_insn "" 397 [(set (cc0) | 451 [(match_operand:XF 0 "register_operand" "f") 452 (float_extend:XF 453 (match_operand:SF 1 "nonimmediate_operand" "fm"))])) 454 (clobber (match_scratch:HI 3 "=a"))] 455 "TARGET_80387" 456 "* return output_float_compare (insn, operands);") 457 458(define_insn "" 459 [(set (cc0) |
460 (match_operator 2 "VOIDmode_compare_op" 461 [(float_extend:XF 462 (match_operand:SF 0 "nonimmediate_operand" "fm")) 463 (match_operand:XF 1 "register_operand" "f")])) 464 (clobber (match_scratch:HI 3 "=a"))] 465 "TARGET_80387" 466 "* return output_float_compare (insn, operands);") 467 468(define_insn "" 469 [(set (cc0) |
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398 (compare:CCFPEQ (match_operand:XF 0 "register_operand" "f") 399 (match_operand:XF 1 "register_operand" "f"))) 400 (clobber (match_scratch:HI 2 "=a"))] 401 "TARGET_80387" 402 "* return output_float_compare (insn, operands);") 403 404(define_insn "" 405 [(set (cc0) --- 42 unchanged lines hidden (view full) --- 448 (match_operand:SF 0 "nonimmediate_operand" "fm")) 449 (match_operand:DF 1 "register_operand" "f")])) 450 (clobber (match_scratch:HI 3 "=a"))] 451 "TARGET_80387" 452 "* return output_float_compare (insn, operands);") 453 454(define_insn "" 455 [(set (cc0) | 470 (compare:CCFPEQ (match_operand:XF 0 "register_operand" "f") 471 (match_operand:XF 1 "register_operand" "f"))) 472 (clobber (match_scratch:HI 2 "=a"))] 473 "TARGET_80387" 474 "* return output_float_compare (insn, operands);") 475 476(define_insn "" 477 [(set (cc0) --- 42 unchanged lines hidden (view full) --- 520 (match_operand:SF 0 "nonimmediate_operand" "fm")) 521 (match_operand:DF 1 "register_operand" "f")])) 522 (clobber (match_scratch:HI 3 "=a"))] 523 "TARGET_80387" 524 "* return output_float_compare (insn, operands);") 525 526(define_insn "" 527 [(set (cc0) |
528 (match_operator 2 "VOIDmode_compare_op" 529 [(float_extend:DF 530 (match_operand:SF 0 "register_operand" "f")) 531 (match_operand:DF 1 "nonimmediate_operand" "fm")])) 532 (clobber (match_scratch:HI 3 "=a"))] 533 "TARGET_80387" 534 "* return output_float_compare (insn, operands);") 535 536(define_insn "" 537 [(set (cc0) |
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456 (compare:CCFPEQ (match_operand:DF 0 "register_operand" "f") 457 (match_operand:DF 1 "register_operand" "f"))) 458 (clobber (match_scratch:HI 2 "=a"))] 459 "TARGET_80387" 460 "* return output_float_compare (insn, operands);") 461 462;; These two insns will never be generated by combine due to the mode of 463;; the COMPARE. --- 51 unchanged lines hidden (view full) --- 515 (match_operand:SF 1 "register_operand" "f"))) 516 (clobber (match_scratch:HI 2 "=a"))] 517 "TARGET_80387" 518 "* return output_float_compare (insn, operands);") 519 520(define_expand "cmpxf" 521 [(set (cc0) 522 (compare (match_operand:XF 0 "register_operand" "") | 538 (compare:CCFPEQ (match_operand:DF 0 "register_operand" "f") 539 (match_operand:DF 1 "register_operand" "f"))) 540 (clobber (match_scratch:HI 2 "=a"))] 541 "TARGET_80387" 542 "* return output_float_compare (insn, operands);") 543 544;; These two insns will never be generated by combine due to the mode of 545;; the COMPARE. --- 51 unchanged lines hidden (view full) --- 597 (match_operand:SF 1 "register_operand" "f"))) 598 (clobber (match_scratch:HI 2 "=a"))] 599 "TARGET_80387" 600 "* return output_float_compare (insn, operands);") 601 602(define_expand "cmpxf" 603 [(set (cc0) 604 (compare (match_operand:XF 0 "register_operand" "") |
523 (match_operand:XF 1 "nonimmediate_operand" "")))] | 605 (match_operand:XF 1 "register_operand" "")))] |
524 "TARGET_80387" 525 " 526{ 527 i386_compare_gen = gen_cmpxf_cc; 528 i386_compare_gen_eq = gen_cmpxf_ccfpeq; 529 i386_compare_op0 = operands[0]; 530 i386_compare_op1 = operands[1]; 531 DONE; 532}") 533 534(define_expand "cmpdf" 535 [(set (cc0) 536 (compare (match_operand:DF 0 "register_operand" "") | 606 "TARGET_80387" 607 " 608{ 609 i386_compare_gen = gen_cmpxf_cc; 610 i386_compare_gen_eq = gen_cmpxf_ccfpeq; 611 i386_compare_op0 = operands[0]; 612 i386_compare_op1 = operands[1]; 613 DONE; 614}") 615 616(define_expand "cmpdf" 617 [(set (cc0) 618 (compare (match_operand:DF 0 "register_operand" "") |
537 (match_operand:DF 1 "nonimmediate_operand" "")))] | 619 (match_operand:DF 1 "general_operand" "")))] |
538 "TARGET_80387" 539 " 540{ 541 i386_compare_gen = gen_cmpdf_cc; 542 i386_compare_gen_eq = gen_cmpdf_ccfpeq; 543 i386_compare_op0 = operands[0]; | 620 "TARGET_80387" 621 " 622{ 623 i386_compare_gen = gen_cmpdf_cc; 624 i386_compare_gen_eq = gen_cmpdf_ccfpeq; 625 i386_compare_op0 = operands[0]; |
544 i386_compare_op1 = operands[1]; | 626 i386_compare_op1 = (immediate_operand (operands[1], DFmode)) 627 ? copy_to_mode_reg (DFmode, operands[1]) : operands[1]; |
545 DONE; 546}") 547 548(define_expand "cmpsf" 549 [(set (cc0) 550 (compare (match_operand:SF 0 "register_operand" "") | 628 DONE; 629}") 630 631(define_expand "cmpsf" 632 [(set (cc0) 633 (compare (match_operand:SF 0 "register_operand" "") |
551 (match_operand:SF 1 "nonimmediate_operand" "")))] | 634 (match_operand:SF 1 "general_operand" "")))] |
552 "TARGET_80387" 553 " 554{ 555 i386_compare_gen = gen_cmpsf_cc; 556 i386_compare_gen_eq = gen_cmpsf_ccfpeq; 557 i386_compare_op0 = operands[0]; | 635 "TARGET_80387" 636 " 637{ 638 i386_compare_gen = gen_cmpsf_cc; 639 i386_compare_gen_eq = gen_cmpsf_ccfpeq; 640 i386_compare_op0 = operands[0]; |
558 i386_compare_op1 = operands[1]; | 641 i386_compare_op1 = (immediate_operand (operands[1], SFmode)) 642 ? copy_to_mode_reg (SFmode, operands[1]) : operands[1]; |
559 DONE; 560}") 561 562(define_expand "cmpxf_cc" 563 [(parallel [(set (cc0) 564 (compare (match_operand:XF 0 "register_operand" "") 565 (match_operand:XF 1 "register_operand" ""))) 566 (clobber (match_scratch:HI 2 ""))])] 567 "TARGET_80387" 568 "") 569 570(define_expand "cmpxf_ccfpeq" 571 [(parallel [(set (cc0) 572 (compare:CCFPEQ (match_operand:XF 0 "register_operand" "") 573 (match_operand:XF 1 "register_operand" ""))) 574 (clobber (match_scratch:HI 2 ""))])] 575 "TARGET_80387" | 643 DONE; 644}") 645 646(define_expand "cmpxf_cc" 647 [(parallel [(set (cc0) 648 (compare (match_operand:XF 0 "register_operand" "") 649 (match_operand:XF 1 "register_operand" ""))) 650 (clobber (match_scratch:HI 2 ""))])] 651 "TARGET_80387" 652 "") 653 654(define_expand "cmpxf_ccfpeq" 655 [(parallel [(set (cc0) 656 (compare:CCFPEQ (match_operand:XF 0 "register_operand" "") 657 (match_operand:XF 1 "register_operand" ""))) 658 (clobber (match_scratch:HI 2 ""))])] 659 "TARGET_80387" |
576 " 577{ 578 if (! register_operand (operands[1], XFmode)) 579 operands[1] = copy_to_mode_reg (XFmode, operands[1]); 580}") | 660 "") |
581 582(define_expand "cmpdf_cc" 583 [(parallel [(set (cc0) 584 (compare (match_operand:DF 0 "register_operand" "") 585 (match_operand:DF 1 "register_operand" ""))) 586 (clobber (match_scratch:HI 2 ""))])] 587 "TARGET_80387" 588 "") --- 30 unchanged lines hidden (view full) --- 619 operands[1] = copy_to_mode_reg (SFmode, operands[1]); 620}") 621 622;; logical compare 623 624(define_insn "" 625 [(set (cc0) 626 (and:SI (match_operand:SI 0 "general_operand" "%ro") | 661 662(define_expand "cmpdf_cc" 663 [(parallel [(set (cc0) 664 (compare (match_operand:DF 0 "register_operand" "") 665 (match_operand:DF 1 "register_operand" ""))) 666 (clobber (match_scratch:HI 2 ""))])] 667 "TARGET_80387" 668 "") --- 30 unchanged lines hidden (view full) --- 699 operands[1] = copy_to_mode_reg (SFmode, operands[1]); 700}") 701 702;; logical compare 703 704(define_insn "" 705 [(set (cc0) 706 (and:SI (match_operand:SI 0 "general_operand" "%ro") |
627 (match_operand:SI 1 "general_operand" "ri")))] | 707 (match_operand:SI 1 "nonmemory_operand" "ri")))] |
628 "" 629 "* 630{ 631 /* For small integers, we may actually use testb. */ 632 if (GET_CODE (operands[1]) == CONST_INT 633 && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) 634 && (! REG_P (operands[0]) || QI_REG_P (operands[0]))) 635 { --- 41 unchanged lines hidden (view full) --- 677 return AS2 (test%L0,%1,%0); 678 679 return AS2 (test%L1,%0,%1); 680}") 681 682(define_insn "" 683 [(set (cc0) 684 (and:HI (match_operand:HI 0 "general_operand" "%ro") | 708 "" 709 "* 710{ 711 /* For small integers, we may actually use testb. */ 712 if (GET_CODE (operands[1]) == CONST_INT 713 && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) 714 && (! REG_P (operands[0]) || QI_REG_P (operands[0]))) 715 { --- 41 unchanged lines hidden (view full) --- 757 return AS2 (test%L0,%1,%0); 758 759 return AS2 (test%L1,%0,%1); 760}") 761 762(define_insn "" 763 [(set (cc0) 764 (and:HI (match_operand:HI 0 "general_operand" "%ro") |
685 (match_operand:HI 1 "general_operand" "ri")))] | 765 (match_operand:HI 1 "nonmemory_operand" "ri")))] |
686 "" 687 "* 688{ 689 if (GET_CODE (operands[1]) == CONST_INT 690 && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) 691 && (! REG_P (operands[0]) || QI_REG_P (operands[0]))) 692 { 693 if ((INTVAL (operands[1]) & 0xff00) == 0) --- 16 unchanged lines hidden (view full) --- 710 else 711 { 712 operands[0] = adj_offsettable_operand (operands[0], 1); 713 return AS2 (test%B0,%1,%b0); 714 } 715 } 716 } 717 | 766 "" 767 "* 768{ 769 if (GET_CODE (operands[1]) == CONST_INT 770 && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) 771 && (! REG_P (operands[0]) || QI_REG_P (operands[0]))) 772 { 773 if ((INTVAL (operands[1]) & 0xff00) == 0) --- 16 unchanged lines hidden (view full) --- 790 else 791 { 792 operands[0] = adj_offsettable_operand (operands[0], 1); 793 return AS2 (test%B0,%1,%b0); 794 } 795 } 796 } 797 |
798 /* use 32-bit test instruction if there are no sign issues */ 799 if (GET_CODE (operands[1]) == CONST_INT 800 && !(INTVAL (operands[1]) & ~0x7fff) 801 && i386_aligned_p (operands[0])) 802 return AS2 (test%L0,%1,%k0); 803 |
|
718 if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) 719 return AS2 (test%W0,%1,%0); 720 721 return AS2 (test%W1,%0,%1); 722}") 723 724(define_insn "" 725 [(set (cc0) | 804 if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) 805 return AS2 (test%W0,%1,%0); 806 807 return AS2 (test%W1,%0,%1); 808}") 809 810(define_insn "" 811 [(set (cc0) |
726 (and:QI (match_operand:QI 0 "general_operand" "%qm") 727 (match_operand:QI 1 "general_operand" "qi")))] | 812 (and:QI (match_operand:QI 0 "nonimmediate_operand" "%qm") 813 (match_operand:QI 1 "nonmemory_operand" "qi")))] |
728 "" 729 "* 730{ 731 if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) 732 return AS2 (test%B0,%1,%0); 733 734 return AS2 (test%B1,%0,%1); 735}") 736 737;; move instructions. 738;; There is one for each machine mode, 739;; and each is preceded by a corresponding push-insn pattern 740;; (since pushes are not general_operands on the 386). 741 742(define_insn "" 743 [(set (match_operand:SI 0 "push_operand" "=<") | 814 "" 815 "* 816{ 817 if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) 818 return AS2 (test%B0,%1,%0); 819 820 return AS2 (test%B1,%0,%1); 821}") 822 823;; move instructions. 824;; There is one for each machine mode, 825;; and each is preceded by a corresponding push-insn pattern 826;; (since pushes are not general_operands on the 386). 827 828(define_insn "" 829 [(set (match_operand:SI 0 "push_operand" "=<") |
744 (match_operand:SI 1 "general_operand" "g"))] 745 "TARGET_386" 746 "push%L0 %1") | 830 (match_operand:SI 1 "nonmemory_operand" "rn"))] 831 "flag_pic" 832 "* return AS1 (push%L0,%1);") |
747 | 833 |
748;; On a 486, it is faster to move MEM to a REG and then push, rather than 749;; push MEM directly. 750 | |
751(define_insn "" 752 [(set (match_operand:SI 0 "push_operand" "=<") 753 (match_operand:SI 1 "nonmemory_operand" "ri"))] | 834(define_insn "" 835 [(set (match_operand:SI 0 "push_operand" "=<") 836 (match_operand:SI 1 "nonmemory_operand" "ri"))] |
754 "!TARGET_386 && TARGET_MOVE" 755 "push%L0 %1") | 837 "!flag_pic" 838 "* return AS1 (push%L0,%1);") |
756 | 839 |
840;; On a 386, it is faster to push MEM directly. 841 |
|
757(define_insn "" 758 [(set (match_operand:SI 0 "push_operand" "=<") | 842(define_insn "" 843 [(set (match_operand:SI 0 "push_operand" "=<") |
759 (match_operand:SI 1 "general_operand" "ri"))] 760 "!TARGET_386 && !TARGET_MOVE" 761 "push%L0 %1") | 844 (match_operand:SI 1 "memory_operand" "m"))] 845 "TARGET_PUSH_MEMORY" 846 "* return AS1 (push%L0,%1);") |
762 763;; General case of fullword move. 764 765;; If generating PIC code and operands[1] is a symbolic CONST, emit a 766;; move to get the address of the symbolic object from the GOT. 767 768(define_expand "movsi" 769 [(set (match_operand:SI 0 "general_operand" "") --- 15 unchanged lines hidden (view full) --- 785 operands[1] = force_reg (SImode, operands[1]); 786 } 787}") 788 789;; On i486, incl reg is faster than movl $1,reg. 790 791(define_insn "" 792 [(set (match_operand:SI 0 "general_operand" "=g,r") | 847 848;; General case of fullword move. 849 850;; If generating PIC code and operands[1] is a symbolic CONST, emit a 851;; move to get the address of the symbolic object from the GOT. 852 853(define_expand "movsi" 854 [(set (match_operand:SI 0 "general_operand" "") --- 15 unchanged lines hidden (view full) --- 870 operands[1] = force_reg (SImode, operands[1]); 871 } 872}") 873 874;; On i486, incl reg is faster than movl $1,reg. 875 876(define_insn "" 877 [(set (match_operand:SI 0 "general_operand" "=g,r") |
793 (match_operand:SI 1 "general_operand" "ri,m"))] 794 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" | 878 (match_operand:SI 1 "general_operand" "rn,im"))] 879 "((!TARGET_MOVE || GET_CODE (operands[0]) != MEM) 880 || (GET_CODE (operands[1]) != MEM)) 881 && flag_pic" |
795 "* 796{ 797 rtx link; 798 if (operands[1] == const0_rtx && REG_P (operands[0])) 799 return AS2 (xor%L0,%0,%0); 800 801 if (operands[1] == const1_rtx 802 && (link = find_reg_note (insn, REG_WAS_0, 0)) 803 /* Make sure the insn that stored the 0 is still present. */ 804 && ! INSN_DELETED_P (XEXP (link, 0)) 805 && GET_CODE (XEXP (link, 0)) != NOTE 806 /* Make sure cross jumping didn't happen here. */ 807 && no_labels_between_p (XEXP (link, 0), insn) 808 /* Make sure the reg hasn't been clobbered. */ 809 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) 810 /* Fastest way to change a 0 to a 1. */ 811 return AS1 (inc%L0,%0); 812 | 882 "* 883{ 884 rtx link; 885 if (operands[1] == const0_rtx && REG_P (operands[0])) 886 return AS2 (xor%L0,%0,%0); 887 888 if (operands[1] == const1_rtx 889 && (link = find_reg_note (insn, REG_WAS_0, 0)) 890 /* Make sure the insn that stored the 0 is still present. */ 891 && ! INSN_DELETED_P (XEXP (link, 0)) 892 && GET_CODE (XEXP (link, 0)) != NOTE 893 /* Make sure cross jumping didn't happen here. */ 894 && no_labels_between_p (XEXP (link, 0), insn) 895 /* Make sure the reg hasn't been clobbered. */ 896 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) 897 /* Fastest way to change a 0 to a 1. */ 898 return AS1 (inc%L0,%0); 899 |
813 if (flag_pic && SYMBOLIC_CONST (operands[1])) | 900 if (SYMBOLIC_CONST (operands[1])) |
814 return AS2 (lea%L0,%a1,%0); 815 816 return AS2 (mov%L0,%1,%0); 817}") 818 819(define_insn "" | 901 return AS2 (lea%L0,%a1,%0); 902 903 return AS2 (mov%L0,%1,%0); 904}") 905 906(define_insn "" |
820 [(set (match_operand:HI 0 "push_operand" "=<") 821 (match_operand:HI 1 "general_operand" "g"))] 822 "TARGET_386" 823 "push%W0 %1") | 907 [(set (match_operand:SI 0 "general_operand" "=g,r") 908 (match_operand:SI 1 "general_operand" "ri,m"))] 909 "((!TARGET_MOVE || GET_CODE (operands[0]) != MEM) 910 || (GET_CODE (operands[1]) != MEM)) 911 && !flag_pic" 912 "* 913{ 914 rtx link; 915 if (operands[1] == const0_rtx && REG_P (operands[0])) 916 return AS2 (xor%L0,%0,%0); |
824 | 917 |
918 if (operands[1] == const1_rtx 919 && (link = find_reg_note (insn, REG_WAS_0, 0)) 920 /* Make sure the insn that stored the 0 is still present. */ 921 && ! INSN_DELETED_P (XEXP (link, 0)) 922 && GET_CODE (XEXP (link, 0)) != NOTE 923 /* Make sure cross jumping didn't happen here. */ 924 && no_labels_between_p (XEXP (link, 0), insn) 925 /* Make sure the reg hasn't been clobbered. */ 926 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) 927 /* Fastest way to change a 0 to a 1. */ 928 return AS1 (inc%L0,%0); 929 930 return AS2 (mov%L0,%1,%0); 931}") 932 |
|
825(define_insn "" 826 [(set (match_operand:HI 0 "push_operand" "=<") 827 (match_operand:HI 1 "nonmemory_operand" "ri"))] | 933(define_insn "" 934 [(set (match_operand:HI 0 "push_operand" "=<") 935 (match_operand:HI 1 "nonmemory_operand" "ri"))] |
828 "!TARGET_386 && TARGET_MOVE" 829 "push%W0 %1") | 936 "" 937 "* return AS1 (push%W0,%1);") |
830 831(define_insn "" 832 [(set (match_operand:HI 0 "push_operand" "=<") | 938 939(define_insn "" 940 [(set (match_operand:HI 0 "push_operand" "=<") |
833 (match_operand:HI 1 "general_operand" "ri"))] 834 "!TARGET_386 && !TARGET_MOVE" 835 "push%W0 %1") | 941 (match_operand:HI 1 "memory_operand" "m"))] 942 "TARGET_PUSH_MEMORY" 943 "* return AS1 (push%W0,%1);") |
836 837;; On i486, an incl and movl are both faster than incw and movw. 838 839(define_expand "movhi" 840 [(set (match_operand:HI 0 "general_operand" "") 841 (match_operand:HI 1 "general_operand" ""))] 842 "" 843 " --- 27 unchanged lines hidden (view full) --- 871 && no_labels_between_p (XEXP (link, 0), insn) 872 /* Make sure the reg hasn't been clobbered. */ 873 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) 874 /* Fastest way to change a 0 to a 1. */ 875 return AS1 (inc%L0,%k0); 876 877 if (REG_P (operands[0])) 878 { | 944 945;; On i486, an incl and movl are both faster than incw and movw. 946 947(define_expand "movhi" 948 [(set (match_operand:HI 0 "general_operand" "") 949 (match_operand:HI 1 "general_operand" ""))] 950 "" 951 " --- 27 unchanged lines hidden (view full) --- 979 && no_labels_between_p (XEXP (link, 0), insn) 980 /* Make sure the reg hasn't been clobbered. */ 981 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) 982 /* Fastest way to change a 0 to a 1. */ 983 return AS1 (inc%L0,%k0); 984 985 if (REG_P (operands[0])) 986 { |
879 if (REG_P (operands[1])) 880 return AS2 (mov%L0,%k1,%k0); 881 else if (CONSTANT_P (operands[1])) 882 return AS2 (mov%L0,%1,%k0); | 987 if (i386_aligned_p (operands[1])) 988 { 989 operands[1] = i386_sext16_if_const (operands[1]); 990 return AS2 (mov%L0,%k1,%k0); 991 } 992 if (TARGET_PENTIUMPRO) 993 { 994 /* movzwl is faster than movw on the Pentium Pro, 995 * although not as fast as an aligned movl. */ 996#ifdef INTEL_SYNTAX 997 return AS2 (movzx,%1,%k0); 998#else 999 return AS2 (movz%W0%L0,%1,%k0); 1000#endif 1001 } |
883 } 884 885 return AS2 (mov%W0,%1,%0); 886}") 887 888(define_expand "movstricthi" 889 [(set (strict_low_part (match_operand:HI 0 "general_operand" "")) 890 (match_operand:HI 1 "general_operand" ""))] --- 36 unchanged lines hidden (view full) --- 927}") 928 929;; emit_push_insn when it calls move_by_pieces 930;; requires an insn to "push a byte". 931;; But actually we use pushw, which has the effect of rounding 932;; the amount pushed up to a halfword. 933(define_insn "" 934 [(set (match_operand:QI 0 "push_operand" "=<") | 1002 } 1003 1004 return AS2 (mov%W0,%1,%0); 1005}") 1006 1007(define_expand "movstricthi" 1008 [(set (strict_low_part (match_operand:HI 0 "general_operand" "")) 1009 (match_operand:HI 1 "general_operand" ""))] --- 36 unchanged lines hidden (view full) --- 1046}") 1047 1048;; emit_push_insn when it calls move_by_pieces 1049;; requires an insn to "push a byte". 1050;; But actually we use pushw, which has the effect of rounding 1051;; the amount pushed up to a halfword. 1052(define_insn "" 1053 [(set (match_operand:QI 0 "push_operand" "=<") |
935 (match_operand:QI 1 "immediate_operand" "n"))] | 1054 (match_operand:QI 1 "const_int_operand" "n"))] |
936 "" | 1055 "" |
937 "* return AS1 (push%W0,%1);") | 1056 "* return AS1(push%W0,%1);") |
938 939(define_insn "" 940 [(set (match_operand:QI 0 "push_operand" "=<") | 1057 1058(define_insn "" 1059 [(set (match_operand:QI 0 "push_operand" "=<") |
941 (match_operand:QI 1 "nonimmediate_operand" "q"))] 942 "!TARGET_MOVE" 943 "* 944{ 945 operands[1] = gen_rtx (REG, HImode, REGNO (operands[1])); 946 return AS1 (push%W0,%1); 947}") 948 949(define_insn "" 950 [(set (match_operand:QI 0 "push_operand" "=<") | |
951 (match_operand:QI 1 "register_operand" "q"))] | 1060 (match_operand:QI 1 "register_operand" "q"))] |
952 "TARGET_MOVE" | 1061 "" |
953 "* 954{ | 1062 "* 1063{ |
955 operands[1] = gen_rtx (REG, HImode, REGNO (operands[1])); | 1064 operands[1] = gen_rtx_REG (HImode, REGNO (operands[1])); |
956 return AS1 (push%W0,%1); 957}") 958 959;; On i486, incb reg is faster than movb $1,reg. 960 961;; ??? Do a recognizer for zero_extract that looks just like this, but reads 962;; or writes %ah, %bh, %ch, %dh. 963 --- 9 unchanged lines hidden (view full) --- 973 && GET_CODE (operands[0]) == MEM 974 && GET_CODE (operands[1]) == MEM) 975 { 976 operands[1] = force_reg (QImode, operands[1]); 977 } 978}") 979 980(define_insn "" | 1065 return AS1 (push%W0,%1); 1066}") 1067 1068;; On i486, incb reg is faster than movb $1,reg. 1069 1070;; ??? Do a recognizer for zero_extract that looks just like this, but reads 1071;; or writes %ah, %bh, %ch, %dh. 1072 --- 9 unchanged lines hidden (view full) --- 1082 && GET_CODE (operands[0]) == MEM 1083 && GET_CODE (operands[1]) == MEM) 1084 { 1085 operands[1] = force_reg (QImode, operands[1]); 1086 } 1087}") 1088 1089(define_insn "" |
981 [(set (match_operand:QI 0 "general_operand" "=q,*r,qm") 982 (match_operand:QI 1 "general_operand" "*g,q,qn"))] | 1090 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,*r,qm") 1091 (match_operand:QI 1 "general_operand" "*g,*rn,qn"))] |
983 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" 984 "* 985{ 986 rtx link; 987 if (operands[1] == const0_rtx && REG_P (operands[0])) | 1092 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" 1093 "* 1094{ 1095 rtx link; 1096 if (operands[1] == const0_rtx && REG_P (operands[0])) |
988 return AS2 (xor%B0,%0,%0); | 1097 return AS2 (xor%L0,%k0,%k0); |
989 990 if (operands[1] == const1_rtx 991 && (link = find_reg_note (insn, REG_WAS_0, 0)) 992 /* Make sure the insn that stored the 0 is still present. */ 993 && ! INSN_DELETED_P (XEXP (link, 0)) 994 && GET_CODE (XEXP (link, 0)) != NOTE 995 /* Make sure cross jumping didn't happen here. */ 996 && no_labels_between_p (XEXP (link, 0), insn) 997 /* Make sure the reg hasn't been clobbered. */ 998 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) | 1098 1099 if (operands[1] == const1_rtx 1100 && (link = find_reg_note (insn, REG_WAS_0, 0)) 1101 /* Make sure the insn that stored the 0 is still present. */ 1102 && ! INSN_DELETED_P (XEXP (link, 0)) 1103 && GET_CODE (XEXP (link, 0)) != NOTE 1104 /* Make sure cross jumping didn't happen here. */ 1105 && no_labels_between_p (XEXP (link, 0), insn) 1106 /* Make sure the reg hasn't been clobbered. */ 1107 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) |
999 /* Fastest way to change a 0 to a 1. */ 1000 return AS1 (inc%B0,%0); | 1108 { 1109 /* Fastest way to change a 0 to a 1. 1110 If inc%B0 isn't allowed, use inc%L0. */ 1111 if (NON_QI_REG_P (operands[0])) 1112 return AS1 (inc%L0,%k0); 1113 else 1114 return AS1 (inc%B0,%0); 1115 } |
1001 1002 /* If mov%B0 isn't allowed for one of these regs, use mov%L0. */ 1003 if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1])) 1004 return (AS2 (mov%L0,%k1,%k0)); 1005 1006 return (AS2 (mov%B0,%1,%0)); 1007}") 1008 --- 18 unchanged lines hidden (view full) --- 1027 && GET_CODE (operands[0]) == MEM 1028 && GET_CODE (operands[1]) == MEM) 1029 { 1030 operands[1] = force_reg (QImode, operands[1]); 1031 } 1032}") 1033 1034(define_insn "" | 1116 1117 /* If mov%B0 isn't allowed for one of these regs, use mov%L0. */ 1118 if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1])) 1119 return (AS2 (mov%L0,%k1,%k0)); 1120 1121 return (AS2 (mov%B0,%1,%0)); 1122}") 1123 --- 18 unchanged lines hidden (view full) --- 1142 && GET_CODE (operands[0]) == MEM 1143 && GET_CODE (operands[1]) == MEM) 1144 { 1145 operands[1] = force_reg (QImode, operands[1]); 1146 } 1147}") 1148 1149(define_insn "" |
1035 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+qm,q")) | 1150 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) |
1036 (match_operand:QI 1 "general_operand" "*qn,m"))] 1037 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" 1038 "* 1039{ 1040 rtx link; 1041 if (operands[1] == const0_rtx && REG_P (operands[0])) 1042 return AS2 (xor%B0,%0,%0); 1043 1044 if (operands[1] == const1_rtx | 1151 (match_operand:QI 1 "general_operand" "*qn,m"))] 1152 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" 1153 "* 1154{ 1155 rtx link; 1156 if (operands[1] == const0_rtx && REG_P (operands[0])) 1157 return AS2 (xor%B0,%0,%0); 1158 1159 if (operands[1] == const1_rtx |
1160 && ! NON_QI_REG_P (operands[0]) |
|
1045 && (link = find_reg_note (insn, REG_WAS_0, 0)) 1046 /* Make sure the insn that stored the 0 is still present. */ 1047 && ! INSN_DELETED_P (XEXP (link, 0)) 1048 && GET_CODE (XEXP (link, 0)) != NOTE 1049 /* Make sure cross jumping didn't happen here. */ 1050 && no_labels_between_p (XEXP (link, 0), insn) 1051 /* Make sure the reg hasn't been clobbered. */ 1052 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) --- 5 unchanged lines hidden (view full) --- 1058 { 1059 abort (); 1060 return (AS2 (mov%L0,%k1,%k0)); 1061 } 1062 1063 return AS2 (mov%B0,%1,%0); 1064}") 1065 | 1161 && (link = find_reg_note (insn, REG_WAS_0, 0)) 1162 /* Make sure the insn that stored the 0 is still present. */ 1163 && ! INSN_DELETED_P (XEXP (link, 0)) 1164 && GET_CODE (XEXP (link, 0)) != NOTE 1165 /* Make sure cross jumping didn't happen here. */ 1166 && no_labels_between_p (XEXP (link, 0), insn) 1167 /* Make sure the reg hasn't been clobbered. */ 1168 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) --- 5 unchanged lines hidden (view full) --- 1174 { 1175 abort (); 1176 return (AS2 (mov%L0,%k1,%k0)); 1177 } 1178 1179 return AS2 (mov%B0,%1,%0); 1180}") 1181 |
1066(define_expand "movsf" 1067 [(set (match_operand:SF 0 "general_operand" "") 1068 (match_operand:SF 1 "general_operand" ""))] 1069 "" 1070 " 1071{ 1072 /* Special case memory->memory moves and pushes */ 1073 if (TARGET_MOVE 1074 && (reload_in_progress | reload_completed) == 0 1075 && GET_CODE (operands[0]) == MEM 1076 && (GET_CODE (operands[1]) == MEM || push_operand (operands[0], SFmode))) 1077 { 1078 rtx (*genfunc) PROTO((rtx, rtx)) = (push_operand (operands[0], SFmode)) 1079 ? gen_movsf_push 1080 : gen_movsf_mem; 1081 1082 emit_insn ((*genfunc) (operands[0], operands[1])); 1083 DONE; 1084 } 1085 1086 /* If we are loading a floating point constant that isn't 0 or 1 into a register, 1087 indicate we need the pic register loaded. This could be optimized into stores 1088 of constants if the target eventually moves to memory, but better safe than 1089 sorry. */ 1090 if (flag_pic 1091 && GET_CODE (operands[0]) != MEM 1092 && GET_CODE (operands[1]) == CONST_DOUBLE 1093 && !standard_80387_constant_p (operands[1])) 1094 { 1095 current_function_uses_pic_offset_table = 1; 1096 } 1097}") 1098 1099(define_insn "movsf_push_nomove" | 1182(define_insn "movsf_push" |
1100 [(set (match_operand:SF 0 "push_operand" "=<,<") | 1183 [(set (match_operand:SF 0 "push_operand" "=<,<") |
1101 (match_operand:SF 1 "general_operand" "gF,f"))] 1102 "!TARGET_MOVE" | 1184 (match_operand:SF 1 "general_operand" "*rfF,m"))] 1185 "GET_CODE (operands[1]) != MEM || reload_in_progress || reload_completed" |
1103 "* 1104{ 1105 if (STACK_REG_P (operands[1])) 1106 { 1107 rtx xops[3]; 1108 1109 if (! STACK_TOP_P (operands[1])) 1110 abort (); 1111 1112 xops[0] = AT_SP (SFmode); 1113 xops[1] = GEN_INT (4); 1114 xops[2] = stack_pointer_rtx; 1115 1116 output_asm_insn (AS2 (sub%L2,%1,%2), xops); 1117 1118 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) 1119 output_asm_insn (AS1 (fstp%S0,%0), xops); 1120 else 1121 output_asm_insn (AS1 (fst%S0,%0), xops); | 1186 "* 1187{ 1188 if (STACK_REG_P (operands[1])) 1189 { 1190 rtx xops[3]; 1191 1192 if (! STACK_TOP_P (operands[1])) 1193 abort (); 1194 1195 xops[0] = AT_SP (SFmode); 1196 xops[1] = GEN_INT (4); 1197 xops[2] = stack_pointer_rtx; 1198 1199 output_asm_insn (AS2 (sub%L2,%1,%2), xops); 1200 1201 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) 1202 output_asm_insn (AS1 (fstp%S0,%0), xops); 1203 else 1204 output_asm_insn (AS1 (fst%S0,%0), xops); |
1205 |
|
1122 RET; 1123 } | 1206 RET; 1207 } |
1124 return AS1 (push%L1,%1); | 1208 1209 return AS1 (push%L0,%1); |
1125}") 1126 | 1210}") 1211 |
1127(define_insn "movsf_push" 1128 [(set (match_operand:SF 0 "push_operand" "=<,<,<,<") 1129 (match_operand:SF 1 "general_operand" "rF,f,m,m")) 1130 (clobber (match_scratch:SI 2 "=X,X,r,X"))] | 1212(define_insn "movsf_push_memory" 1213 [(set (match_operand:SF 0 "push_operand" "=<") 1214 (match_operand:SF 1 "memory_operand" "m"))] 1215 "TARGET_PUSH_MEMORY" 1216 "* return AS1 (push%L0,%1);") 1217 1218(define_expand "movsf" 1219 [(set (match_operand:SF 0 "general_operand" "") 1220 (match_operand:SF 1 "general_operand" ""))] |
1131 "" | 1221 "" |
1132 "* | 1222 " |
1133{ | 1223{ |
1134 if (STACK_REG_P (operands[1])) | 1224 /* Don't generate memory->memory moves, go through a register */ 1225 if (TARGET_MOVE 1226 && (reload_in_progress | reload_completed) == 0 1227 && GET_CODE (operands[0]) == MEM 1228 && GET_CODE (operands[1]) == MEM) |
1135 { | 1229 { |
1136 rtx xops[3]; | 1230 operands[1] = force_reg (SFmode, operands[1]); 1231 } |
1137 | 1232 |
1138 if (! STACK_TOP_P (operands[1])) 1139 abort (); | 1233 /* If we are loading a floating point constant that isn't 0 or 1 1234 into a register, indicate we need the pic register loaded. This could 1235 be optimized into stores of constants if the target eventually moves 1236 to memory, but better safe than sorry. */ 1237 else if ((reload_in_progress | reload_completed) == 0 1238 && GET_CODE (operands[0]) != MEM 1239 && GET_CODE (operands[1]) == CONST_DOUBLE 1240 && !standard_80387_constant_p (operands[1])) 1241 { 1242 rtx insn, note, fp_const; |
1140 | 1243 |
1141 xops[0] = AT_SP (SFmode); 1142 xops[1] = GEN_INT (4); 1143 xops[2] = stack_pointer_rtx; | 1244 fp_const = force_const_mem (SFmode, operands[1]); 1245 if (flag_pic) 1246 current_function_uses_pic_offset_table = 1; |
1144 | 1247 |
1145 output_asm_insn (AS2 (sub%L2,%1,%2), xops); | 1248 insn = emit_insn (gen_rtx_SET (SFmode, operands[0], fp_const)); 1249 note = find_reg_note (insn, REG_EQUAL, NULL_RTX); |
1146 | 1250 |
1147 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) 1148 output_asm_insn (AS1 (fstp%S0,%0), xops); | 1251 if (note) 1252 XEXP (note, 0) = operands[1]; |
1149 else | 1253 else |
1150 output_asm_insn (AS1 (fst%S0,%0), xops); 1151 RET; | 1254 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1], REG_NOTES (insn)); |
1152 } | 1255 } |
1153 1154 else if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != REG) 1155 return AS1 (push%L1,%1); 1156 1157 else 1158 { 1159 output_asm_insn (AS2 (mov%L2,%1,%2), operands); 1160 return AS1 (push%L2,%2); 1161 } | |
1162}") 1163 | 1256}") 1257 |
1164;; Special memory<->memory pattern that combine will recreate from the 1165;; moves to pseudos. 1166(define_insn "movsf_mem" 1167 [(set (match_operand:SF 0 "memory_operand" "=m") 1168 (match_operand:SF 1 "memory_operand" "m")) 1169 (clobber (match_scratch:SI 2 "=&r"))] 1170 "" 1171 "* 1172{ 1173 output_asm_insn (AS2 (mov%L2,%1,%2), operands); 1174 return AS2 (mov%L0,%2,%0); 1175}") 1176 | |
1177;; For the purposes of regclass, prefer FLOAT_REGS. | 1258;; For the purposes of regclass, prefer FLOAT_REGS. |
1178(define_insn "movsf_normal" 1179 [(set (match_operand:SF 0 "general_operand" "=*rfm,*rf,f,!*rm") | 1259(define_insn "" 1260 [(set (match_operand:SF 0 "nonimmediate_operand" "=*rfm,*rf,f,!*rm") |
1180 (match_operand:SF 1 "general_operand" "*rf,*rfm,fG,fF"))] 1181 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" 1182 "* 1183{ 1184 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 1185 1186 /* First handle a `pop' insn or a `fld %st(0)' */ 1187 --- 10 unchanged lines hidden (view full) --- 1198 if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1])) 1199 { 1200 output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); 1201 RET; 1202 } 1203 1204 if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0])) 1205 { | 1261 (match_operand:SF 1 "general_operand" "*rf,*rfm,fG,fF"))] 1262 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" 1263 "* 1264{ 1265 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 1266 1267 /* First handle a `pop' insn or a `fld %st(0)' */ 1268 --- 10 unchanged lines hidden (view full) --- 1279 if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1])) 1280 { 1281 output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); 1282 RET; 1283 } 1284 1285 if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0])) 1286 { |
1206 output_to_reg (operands[0], stack_top_dies); | 1287 output_to_reg (operands[0], stack_top_dies, 0); |
1207 RET; 1208 } 1209 1210 /* Handle other kinds of writes from the 387 */ 1211 1212 if (STACK_TOP_P (operands[1])) 1213 { 1214 if (stack_top_dies) --- 8 unchanged lines hidden (view full) --- 1223 return output_move_const_single (operands); 1224 1225 if (STACK_TOP_P (operands[0])) 1226 return AS1 (fld%z1,%y1); 1227 1228 /* Handle all SFmode moves not involving the 387 */ 1229 1230 return singlemove_string (operands); | 1288 RET; 1289 } 1290 1291 /* Handle other kinds of writes from the 387 */ 1292 1293 if (STACK_TOP_P (operands[1])) 1294 { 1295 if (stack_top_dies) --- 8 unchanged lines hidden (view full) --- 1304 return output_move_const_single (operands); 1305 1306 if (STACK_TOP_P (operands[0])) 1307 return AS1 (fld%z1,%y1); 1308 1309 /* Handle all SFmode moves not involving the 387 */ 1310 1311 return singlemove_string (operands); |
1231}") | 1312}" 1313 [(set_attr "type" "fld")]) |
1232 | 1314 |
1315 |
|
1233(define_insn "swapsf" 1234 [(set (match_operand:SF 0 "register_operand" "f") 1235 (match_operand:SF 1 "register_operand" "f")) 1236 (set (match_dup 1) 1237 (match_dup 0))] 1238 "" 1239 "* 1240{ 1241 if (STACK_TOP_P (operands[0])) 1242 return AS1 (fxch,%1); 1243 else 1244 return AS1 (fxch,%0); 1245}") 1246 | 1316(define_insn "swapsf" 1317 [(set (match_operand:SF 0 "register_operand" "f") 1318 (match_operand:SF 1 "register_operand" "f")) 1319 (set (match_dup 1) 1320 (match_dup 0))] 1321 "" 1322 "* 1323{ 1324 if (STACK_TOP_P (operands[0])) 1325 return AS1 (fxch,%1); 1326 else 1327 return AS1 (fxch,%0); 1328}") 1329 |
1247(define_expand "movdf" 1248 [(set (match_operand:DF 0 "general_operand" "") 1249 (match_operand:DF 1 "general_operand" ""))] 1250 "" 1251 " 1252{ 1253 /* Special case memory->memory moves and pushes */ 1254 if (TARGET_MOVE 1255 && (reload_in_progress | reload_completed) == 0 1256 && GET_CODE (operands[0]) == MEM 1257 && (GET_CODE (operands[1]) == MEM || push_operand (operands[0], DFmode))) 1258 { 1259 rtx (*genfunc) PROTO((rtx, rtx)) = (push_operand (operands[0], DFmode)) 1260 ? gen_movdf_push 1261 : gen_movdf_mem; 1262 1263 emit_insn ((*genfunc) (operands[0], operands[1])); 1264 DONE; 1265 } 1266 1267 /* If we are loading a floating point constant that isn't 0 or 1 into a register, 1268 indicate we need the pic register loaded. This could be optimized into stores 1269 of constants if the target eventually moves to memory, but better safe than 1270 sorry. */ 1271 if (flag_pic 1272 && GET_CODE (operands[0]) != MEM 1273 && GET_CODE (operands[1]) == CONST_DOUBLE 1274 && !standard_80387_constant_p (operands[1])) 1275 { 1276 current_function_uses_pic_offset_table = 1; 1277 } 1278}") 1279 1280(define_insn "movdf_push_nomove" | 1330(define_insn "movdf_push" |
1281 [(set (match_operand:DF 0 "push_operand" "=<,<") | 1331 [(set (match_operand:DF 0 "push_operand" "=<,<") |
1282 (match_operand:DF 1 "general_operand" "gF,f"))] 1283 "!TARGET_MOVE" | 1332 (match_operand:DF 1 "general_operand" "*rfF,o"))] 1333 "GET_CODE (operands[1]) != MEM || reload_in_progress || reload_completed" |
1284 "* 1285{ 1286 if (STACK_REG_P (operands[1])) 1287 { 1288 rtx xops[3]; 1289 | 1334 "* 1335{ 1336 if (STACK_REG_P (operands[1])) 1337 { 1338 rtx xops[3]; 1339 |
1290 xops[0] = AT_SP (SFmode); | 1340 xops[0] = AT_SP (DFmode); |
1291 xops[1] = GEN_INT (8); 1292 xops[2] = stack_pointer_rtx; 1293 1294 output_asm_insn (AS2 (sub%L2,%1,%2), xops); 1295 1296 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) 1297 output_asm_insn (AS1 (fstp%Q0,%0), xops); 1298 else 1299 output_asm_insn (AS1 (fst%Q0,%0), xops); 1300 1301 RET; 1302 } | 1341 xops[1] = GEN_INT (8); 1342 xops[2] = stack_pointer_rtx; 1343 1344 output_asm_insn (AS2 (sub%L2,%1,%2), xops); 1345 1346 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) 1347 output_asm_insn (AS1 (fstp%Q0,%0), xops); 1348 else 1349 output_asm_insn (AS1 (fst%Q0,%0), xops); 1350 1351 RET; 1352 } |
1303 else 1304 return output_move_double (operands); | 1353 1354 if (which_alternative == 1) 1355 return output_move_pushmem (operands, insn, GET_MODE_SIZE (DFmode), 0, 0); 1356 1357 return output_move_double (operands); |
1305}") 1306 | 1358}") 1359 |
1307(define_insn "movdf_push" 1308 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<,<") 1309 (match_operand:DF 1 "general_operand" "rF,f,o,o,o")) 1310 (clobber (match_scratch:SI 2 "=X,X,&r,&r,X")) 1311 (clobber (match_scratch:SI 3 "=X,X,&r,X,X"))] | 1360(define_insn "movdf_push_memory" 1361 [(set (match_operand:DF 0 "push_operand" "=<") 1362 (match_operand:DF 1 "memory_operand" "o"))] 1363 "TARGET_PUSH_MEMORY" 1364 "* return output_move_pushmem (operands, insn, GET_MODE_SIZE (DFmode),0,0);") 1365 1366(define_expand "movdf" 1367 [(set (match_operand:DF 0 "general_operand" "") 1368 (match_operand:DF 1 "general_operand" ""))] |
1312 "" | 1369 "" |
1313 "* | 1370 " |
1314{ | 1371{ |
1315 if (STACK_REG_P (operands[1])) | 1372 /* Don't generate memory->memory moves, go through a register */ 1373 if (TARGET_MOVE 1374 && (reload_in_progress | reload_completed) == 0 1375 && GET_CODE (operands[0]) == MEM 1376 && GET_CODE (operands[1]) == MEM) |
1316 { | 1377 { |
1317 rtx xops[3]; | 1378 operands[1] = force_reg (DFmode, operands[1]); 1379 } |
1318 | 1380 |
1319 xops[0] = AT_SP (SFmode); 1320 xops[1] = GEN_INT (8); 1321 xops[2] = stack_pointer_rtx; | 1381 /* If we are loading a floating point constant that isn't 0 or 1 into a 1382 register, indicate we need the pic register loaded. This could be 1383 optimized into stores of constants if the target eventually moves to 1384 memory, but better safe than sorry. */ 1385 else if ((reload_in_progress | reload_completed) == 0 1386 && GET_CODE (operands[0]) != MEM 1387 && GET_CODE (operands[1]) == CONST_DOUBLE 1388 && !standard_80387_constant_p (operands[1])) 1389 { 1390 rtx insn, note, fp_const; |
1322 | 1391 |
1323 output_asm_insn (AS2 (sub%L2,%1,%2), xops); | 1392 fp_const = force_const_mem (DFmode, operands[1]); 1393 if (flag_pic) 1394 current_function_uses_pic_offset_table = 1; |
1324 | 1395 |
1325 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) 1326 output_asm_insn (AS1 (fstp%Q0,%0), xops); 1327 else 1328 output_asm_insn (AS1 (fst%Q0,%0), xops); | 1396 insn = emit_insn (gen_rtx_SET (DFmode, operands[0], fp_const)); 1397 note = find_reg_note (insn, REG_EQUAL, NULL_RTX); |
1329 | 1398 |
1330 RET; | 1399 if (note) 1400 XEXP (note, 0) = operands[1]; 1401 else 1402 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1], REG_NOTES (insn)); |
1331 } | 1403 } |
1332 1333 else if (GET_CODE (operands[1]) != MEM) 1334 return output_move_double (operands); 1335 1336 else 1337 return output_move_pushmem (operands, insn, GET_MODE_SIZE (DFmode), 2, 4); | |
1338}") 1339 | 1404}") 1405 |
1340(define_insn "movdf_mem" 1341 [(set (match_operand:DF 0 "memory_operand" "=o,o") 1342 (match_operand:DF 1 "memory_operand" "o,o")) 1343 (clobber (match_scratch:SI 2 "=&r,&r")) 1344 (clobber (match_scratch:SI 3 "=&r,X"))] 1345 "" 1346 "* return output_move_memory (operands, insn, GET_MODE_SIZE (DFmode), 2, 4);") 1347 | |
1348;; For the purposes of regclass, prefer FLOAT_REGS. | 1406;; For the purposes of regclass, prefer FLOAT_REGS. |
1349(define_insn "movdf_normal" 1350 [(set (match_operand:DF 0 "general_operand" "=f,fm,!*rf,!*rm") | 1407(define_insn "" 1408 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,fm,!*rf,!*rm") |
1351 (match_operand:DF 1 "general_operand" "fmG,f,*rfm,*rfF"))] | 1409 (match_operand:DF 1 "general_operand" "fmG,f,*rfm,*rfF"))] |
1352 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" | 1410 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) 1411 || (GET_CODE (operands[1]) != MEM)" |
1353 "* 1354{ 1355 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 1356 1357 /* First handle a `pop' insn or a `fld %st(0)' */ 1358 1359 if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1])) 1360 { --- 8 unchanged lines hidden (view full) --- 1369 if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1])) 1370 { 1371 output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); 1372 RET; 1373 } 1374 1375 if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0])) 1376 { | 1412 "* 1413{ 1414 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 1415 1416 /* First handle a `pop' insn or a `fld %st(0)' */ 1417 1418 if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1])) 1419 { --- 8 unchanged lines hidden (view full) --- 1428 if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1])) 1429 { 1430 output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); 1431 RET; 1432 } 1433 1434 if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0])) 1435 { |
1377 output_to_reg (operands[0], stack_top_dies); | 1436 output_to_reg (operands[0], stack_top_dies, 0); |
1378 RET; 1379 } 1380 1381 /* Handle other kinds of writes from the 387 */ 1382 1383 if (STACK_TOP_P (operands[1])) 1384 { 1385 if (stack_top_dies) --- 8 unchanged lines hidden (view full) --- 1394 return output_move_const_single (operands); 1395 1396 if (STACK_TOP_P (operands[0])) 1397 return AS1 (fld%z1,%y1); 1398 1399 /* Handle all DFmode moves not involving the 387 */ 1400 1401 return output_move_double (operands); | 1437 RET; 1438 } 1439 1440 /* Handle other kinds of writes from the 387 */ 1441 1442 if (STACK_TOP_P (operands[1])) 1443 { 1444 if (stack_top_dies) --- 8 unchanged lines hidden (view full) --- 1453 return output_move_const_single (operands); 1454 1455 if (STACK_TOP_P (operands[0])) 1456 return AS1 (fld%z1,%y1); 1457 1458 /* Handle all DFmode moves not involving the 387 */ 1459 1460 return output_move_double (operands); |
1402}") | 1461}" 1462 [(set_attr "type" "fld")]) |
1403 | 1463 |
1464 1465 |
|
1404(define_insn "swapdf" 1405 [(set (match_operand:DF 0 "register_operand" "f") 1406 (match_operand:DF 1 "register_operand" "f")) 1407 (set (match_dup 1) 1408 (match_dup 0))] 1409 "" 1410 "* 1411{ 1412 if (STACK_TOP_P (operands[0])) 1413 return AS1 (fxch,%1); 1414 else 1415 return AS1 (fxch,%0); 1416}") 1417 | 1466(define_insn "swapdf" 1467 [(set (match_operand:DF 0 "register_operand" "f") 1468 (match_operand:DF 1 "register_operand" "f")) 1469 (set (match_dup 1) 1470 (match_dup 0))] 1471 "" 1472 "* 1473{ 1474 if (STACK_TOP_P (operands[0])) 1475 return AS1 (fxch,%1); 1476 else 1477 return AS1 (fxch,%0); 1478}") 1479 |
1418(define_expand "movxf" 1419 [(set (match_operand:XF 0 "general_operand" "") 1420 (match_operand:XF 1 "general_operand" ""))] 1421 "" 1422 " 1423{ 1424 /* Special case memory->memory moves and pushes */ 1425 if (TARGET_MOVE 1426 && (reload_in_progress | reload_completed) == 0 1427 && GET_CODE (operands[0]) == MEM 1428 && (GET_CODE (operands[1]) == MEM || push_operand (operands[0], XFmode))) 1429 { 1430 rtx (*genfunc) PROTO((rtx, rtx)) = (push_operand (operands[0], XFmode)) 1431 ? gen_movxf_push 1432 : gen_movxf_mem; 1433 1434 emit_insn ((*genfunc) (operands[0], operands[1])); 1435 DONE; 1436 } 1437 1438 /* If we are loading a floating point constant that isn't 0 or 1 into a register, 1439 indicate we need the pic register loaded. This could be optimized into stores 1440 of constants if the target eventually moves to memory, but better safe than 1441 sorry. */ 1442 if (flag_pic 1443 && GET_CODE (operands[0]) != MEM 1444 && GET_CODE (operands[1]) == CONST_DOUBLE 1445 && !standard_80387_constant_p (operands[1])) 1446 { 1447 current_function_uses_pic_offset_table = 1; 1448 } 1449}") 1450 1451 1452(define_insn "movxf_push_nomove" | 1480(define_insn "movxf_push" |
1453 [(set (match_operand:XF 0 "push_operand" "=<,<") | 1481 [(set (match_operand:XF 0 "push_operand" "=<,<") |
1454 (match_operand:XF 1 "general_operand" "gF,f"))] 1455 "!TARGET_MOVE" | 1482 (match_operand:XF 1 "general_operand" "*rfF,o"))] 1483 "GET_CODE (operands[1]) != MEM || reload_in_progress || reload_completed" |
1456 "* 1457{ 1458 if (STACK_REG_P (operands[1])) 1459 { 1460 rtx xops[3]; 1461 | 1484 "* 1485{ 1486 if (STACK_REG_P (operands[1])) 1487 { 1488 rtx xops[3]; 1489 |
1462 xops[0] = AT_SP (SFmode); | 1490 xops[0] = AT_SP (XFmode); |
1463 xops[1] = GEN_INT (12); 1464 xops[2] = stack_pointer_rtx; 1465 1466 output_asm_insn (AS2 (sub%L2,%1,%2), xops); | 1491 xops[1] = GEN_INT (12); 1492 xops[2] = stack_pointer_rtx; 1493 1494 output_asm_insn (AS2 (sub%L2,%1,%2), xops); |
1495 |
|
1467 output_asm_insn (AS1 (fstp%T0,%0), xops); 1468 if (! find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) 1469 output_asm_insn (AS1 (fld%T0,%0), xops); 1470 1471 RET; 1472 } | 1496 output_asm_insn (AS1 (fstp%T0,%0), xops); 1497 if (! find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) 1498 output_asm_insn (AS1 (fld%T0,%0), xops); 1499 1500 RET; 1501 } |
1473 else 1474 return output_move_double (operands); | 1502 1503 if (which_alternative == 1) 1504 return output_move_pushmem (operands, insn, GET_MODE_SIZE (XFmode), 0, 0); 1505 1506 return output_move_double (operands); |
1475 }") 1476 | 1507 }") 1508 |
1477(define_insn "movxf_push" 1478 [(set (match_operand:XF 0 "push_operand" "=<,<,<,<,<") 1479 (match_operand:XF 1 "general_operand" "rF,f,o,o,o")) 1480 (clobber (match_scratch:SI 2 "=X,X,&r,&r,X")) 1481 (clobber (match_scratch:SI 3 "=X,X,&r,X,X"))] | 1509(define_insn "movxf_push_memory" 1510 [(set (match_operand:XF 0 "push_operand" "=<") 1511 (match_operand:XF 1 "memory_operand" "o"))] 1512 "TARGET_PUSH_MEMORY" 1513 "* return output_move_pushmem (operands, insn, GET_MODE_SIZE (XFmode),0,0);") 1514 1515(define_expand "movxf" 1516 [(set (match_operand:XF 0 "general_operand" "") 1517 (match_operand:XF 1 "general_operand" ""))] |
1482 "" | 1518 "" |
1483 "* | 1519 " |
1484{ | 1520{ |
1485 if (STACK_REG_P (operands[1])) | 1521 /* Don't generate memory->memory moves, go through a register */ 1522 if (TARGET_MOVE 1523 && (reload_in_progress | reload_completed) == 0 1524 && GET_CODE (operands[0]) == MEM 1525 && GET_CODE (operands[1]) == MEM) |
1486 { | 1526 { |
1487 rtx xops[3]; | 1527 operands[1] = force_reg (XFmode, operands[1]); 1528 } |
1488 | 1529 |
1489 xops[0] = AT_SP (SFmode); 1490 xops[1] = GEN_INT (12); 1491 xops[2] = stack_pointer_rtx; | 1530 /* If we are loading a floating point constant that isn't 0 or 1 1531 into a register, indicate we need the pic register loaded. This could 1532 be optimized into stores of constants if the target eventually moves 1533 to memory, but better safe than sorry. */ 1534 else if ((reload_in_progress | reload_completed) == 0 1535 && GET_CODE (operands[0]) != MEM 1536 && GET_CODE (operands[1]) == CONST_DOUBLE 1537 && !standard_80387_constant_p (operands[1])) 1538 { 1539 rtx insn, note, fp_const; |
1492 | 1540 |
1493 output_asm_insn (AS2 (sub%L2,%1,%2), xops); 1494 output_asm_insn (AS1 (fstp%T0,%0), xops); 1495 if (! find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) 1496 output_asm_insn (AS1 (fld%T0,%0), xops); | 1541 fp_const = force_const_mem (XFmode, operands[1]); 1542 if (flag_pic) 1543 current_function_uses_pic_offset_table = 1; |
1497 | 1544 |
1498 RET; 1499 } | 1545 insn = emit_insn (gen_rtx_SET (XFmode, operands[0], fp_const)); 1546 note = find_reg_note (insn, REG_EQUAL, NULL_RTX); |
1500 | 1547 |
1501 else if (GET_CODE (operands[1]) != MEM 1502 || GET_CODE (operands[2]) != REG) 1503 return output_move_double (operands); 1504 1505 else 1506 return output_move_pushmem (operands, insn, GET_MODE_SIZE (XFmode), 2, 4); | 1548 if (note) 1549 XEXP (note, 0) = operands[1]; 1550 else 1551 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1], REG_NOTES (insn)); 1552 } |
1507}") 1508 | 1553}") 1554 |
1509(define_insn "movxf_mem" 1510 [(set (match_operand:XF 0 "memory_operand" "=o,o") 1511 (match_operand:XF 1 "memory_operand" "o,o")) 1512 (clobber (match_scratch:SI 2 "=&r,&r")) 1513 (clobber (match_scratch:SI 3 "=&r,X"))] 1514 "" 1515 "* return output_move_memory (operands, insn, GET_MODE_SIZE (XFmode), 2, 4);") | |
1516 | 1555 |
1517(define_insn "movxf_normal" 1518 [(set (match_operand:XF 0 "general_operand" "=f,fm,!*rf,!*rm") | 1556(define_insn "" 1557 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,fm,!*rf,!*rm") |
1519 (match_operand:XF 1 "general_operand" "fmG,f,*rfm,*rfF"))] | 1558 (match_operand:XF 1 "general_operand" "fmG,f,*rfm,*rfF"))] |
1520 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" | 1559 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) 1560 || (GET_CODE (operands[1]) != MEM)" |
1521 "* 1522{ 1523 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 1524 1525 /* First handle a `pop' insn or a `fld %st(0)' */ 1526 1527 if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1])) 1528 { --- 8 unchanged lines hidden (view full) --- 1537 if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1])) 1538 { 1539 output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); 1540 RET; 1541 } 1542 1543 if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0])) 1544 { | 1561 "* 1562{ 1563 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 1564 1565 /* First handle a `pop' insn or a `fld %st(0)' */ 1566 1567 if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1])) 1568 { --- 8 unchanged lines hidden (view full) --- 1577 if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1])) 1578 { 1579 output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); 1580 RET; 1581 } 1582 1583 if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0])) 1584 { |
1545 output_to_reg (operands[0], stack_top_dies); | 1585 output_to_reg (operands[0], stack_top_dies, 0); |
1546 RET; 1547 } 1548 1549 /* Handle other kinds of writes from the 387 */ 1550 1551 if (STACK_TOP_P (operands[1])) 1552 { 1553 output_asm_insn (AS1 (fstp%z0,%y0), operands); --- 11 unchanged lines hidden (view full) --- 1565 if (STACK_TOP_P (operands[0])) 1566 return AS1 (fld%z1,%y1); 1567 1568 /* Handle all XFmode moves not involving the 387 */ 1569 1570 return output_move_double (operands); 1571}") 1572 | 1586 RET; 1587 } 1588 1589 /* Handle other kinds of writes from the 387 */ 1590 1591 if (STACK_TOP_P (operands[1])) 1592 { 1593 output_asm_insn (AS1 (fstp%z0,%y0), operands); --- 11 unchanged lines hidden (view full) --- 1605 if (STACK_TOP_P (operands[0])) 1606 return AS1 (fld%z1,%y1); 1607 1608 /* Handle all XFmode moves not involving the 387 */ 1609 1610 return output_move_double (operands); 1611}") 1612 |
1573(define_insn "swapxf" | 1613(define_insn "swapxf" |
1574 [(set (match_operand:XF 0 "register_operand" "f") 1575 (match_operand:XF 1 "register_operand" "f")) 1576 (set (match_dup 1) 1577 (match_dup 0))] 1578 "" 1579 "* 1580{ 1581 if (STACK_TOP_P (operands[0])) 1582 return AS1 (fxch,%1); 1583 else 1584 return AS1 (fxch,%0); 1585}") 1586 1587(define_insn "" | 1614 [(set (match_operand:XF 0 "register_operand" "f") 1615 (match_operand:XF 1 "register_operand" "f")) 1616 (set (match_dup 1) 1617 (match_dup 0))] 1618 "" 1619 "* 1620{ 1621 if (STACK_TOP_P (operands[0])) 1622 return AS1 (fxch,%1); 1623 else 1624 return AS1 (fxch,%0); 1625}") 1626 1627(define_insn "" |
1588 [(set (match_operand:DI 0 "push_operand" "=<,<,<,<") 1589 (match_operand:DI 1 "general_operand" "riF,o,o,o")) 1590 (clobber (match_scratch:SI 2 "=X,&r,&r,X")) 1591 (clobber (match_scratch:SI 3 "=X,&r,X,X"))] | 1628 [(set (match_operand:DI 0 "push_operand" "=<") 1629 (match_operand:DI 1 "general_operand" "riF"))] |
1592 "" | 1630 "" |
1593 "* 1594{ 1595 if (GET_CODE (operands[1]) != MEM) 1596 return output_move_double (operands); | 1631 "* return output_move_double (operands);") |
1597 | 1632 |
1598 else 1599 return output_move_pushmem (operands, insn, GET_MODE_SIZE (DImode), 2, 4); 1600}") | 1633(define_insn "" 1634 [(set (match_operand:DI 0 "push_operand" "=<") 1635 (match_operand:DI 1 "memory_operand" "o"))] 1636 "TARGET_PUSH_MEMORY" 1637 "* return output_move_pushmem (operands, insn, GET_MODE_SIZE (DImode),0,0);") |
1601 | 1638 |
1602(define_insn "movdi" 1603 [(set (match_operand:DI 0 "general_operand" "=o,o,r,rm") 1604 (match_operand:DI 1 "general_operand" "o,o,m,riF")) 1605 (clobber (match_scratch:SI 2 "=&r,&r,X,X")) 1606 (clobber (match_scratch:SI 3 "=&r,X,X,X"))] | 1639(define_expand "movdi" 1640 [(set (match_operand:DI 0 "general_operand" "") 1641 (match_operand:DI 1 "general_operand" ""))] |
1607 "" | 1642 "" |
1608 "* | 1643 " |
1609{ | 1644{ |
1610 rtx low[2], high[2], xop[6]; 1611 1612 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 1613 return output_move_double (operands); 1614 else 1615 return output_move_memory (operands, insn, GET_MODE_SIZE (DImode), 2, 4); | 1645 /* Don't generate memory->memory moves, go through a register */ 1646 if (TARGET_MOVE 1647 && (reload_in_progress | reload_completed) == 0 1648 && GET_CODE (operands[0]) == MEM 1649 && GET_CODE (operands[1]) == MEM) 1650 { 1651 operands[1] = force_reg (DImode, operands[1]); 1652 } |
1616}") 1617 | 1653}") 1654 |
1655(define_insn "" 1656 [(set (match_operand:DI 0 "general_operand" "=g,r") 1657 (match_operand:DI 1 "general_operand" "riF,m"))] 1658 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) 1659 || (GET_CODE (operands[1]) != MEM)" 1660 "* return output_move_double (operands);") 1661 |
|
1618 1619;;- conversion instructions 1620;;- NONE 1621 1622;;- zero extension instructions 1623;; See comments by `andsi' for when andl is faster than movzx. 1624 1625(define_insn "zero_extendhisi2" | 1662 1663;;- conversion instructions 1664;;- NONE 1665 1666;;- zero extension instructions 1667;; See comments by `andsi' for when andl is faster than movzx. 1668 1669(define_insn "zero_extendhisi2" |
1626 [(set (match_operand:SI 0 "general_operand" "=r") 1627 (zero_extend:SI 1628 (match_operand:HI 1 "nonimmediate_operand" "rm")))] | 1670 [(set (match_operand:SI 0 "register_operand" "=r,&r,?r") 1671 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,rm,rm")))] |
1629 "" 1630 "* | 1672 "" 1673 "* |
1631{ 1632 if ((!TARGET_386 || REGNO (operands[0]) == 0) | 1674 { 1675 rtx xops[2]; 1676 1677 if ((TARGET_ZERO_EXTEND_WITH_AND || REGNO (operands[0]) == 0) |
1633 && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) 1634 { | 1678 && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) 1679 { |
1635 rtx xops[2]; | |
1636 xops[0] = operands[0]; 1637 xops[1] = GEN_INT (0xffff); 1638 output_asm_insn (AS2 (and%L0,%1,%k0), xops); 1639 RET; 1640 } | 1680 xops[0] = operands[0]; 1681 xops[1] = GEN_INT (0xffff); 1682 output_asm_insn (AS2 (and%L0,%1,%k0), xops); 1683 RET; 1684 } |
1685 if (TARGET_ZERO_EXTEND_WITH_AND && !reg_overlap_mentioned_p (operands[0], operands[1])) 1686 { 1687 output_asm_insn (AS2 (xor%L0,%0,%0),operands); 1688 output_asm_insn (AS2 (mov%W0,%1,%w0),operands); 1689 RET; 1690 } |
|
1641 | 1691 |
1692 if (TARGET_ZERO_EXTEND_WITH_AND) 1693 { 1694 xops[0] = operands[0]; 1695 xops[1] = GEN_INT (0xffff); 1696 if (i386_aligned_p (operands[1])) 1697 output_asm_insn (AS2 (mov%L0,%k1,%k0),operands); 1698 else 1699 output_asm_insn (AS2 (mov%W0,%1,%w0),operands); 1700 output_asm_insn (AS2 (and%L0,%1,%k0), xops); 1701 RET; 1702 } 1703 |
|
1642#ifdef INTEL_SYNTAX 1643 return AS2 (movzx,%1,%0); 1644#else 1645 return AS2 (movz%W0%L0,%1,%0); 1646#endif 1647}") 1648 | 1704#ifdef INTEL_SYNTAX 1705 return AS2 (movzx,%1,%0); 1706#else 1707 return AS2 (movz%W0%L0,%1,%0); 1708#endif 1709}") 1710 |
1711(define_split 1712 [(set (match_operand:SI 0 "register_operand" "") 1713 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] 1714 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !reg_overlap_mentioned_p (operands[0], operands[1])" 1715 [(set (match_dup 0) 1716 (const_int 0)) 1717 (set (strict_low_part (match_dup 2)) 1718 (match_dup 1))] 1719 "operands[2] = gen_rtx_REG (HImode, true_regnum (operands[0]));") 1720 1721 1722(define_split 1723 [(set (match_operand:SI 0 "register_operand" "") 1724 (zero_extend:SI (match_operand:HI 1 "memory_operand" "")))] 1725 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && reg_overlap_mentioned_p (operands[0], operands[1])" 1726 [(set (strict_low_part (match_dup 2)) 1727 (match_dup 1)) 1728 (set (match_dup 0) 1729 (and:SI (match_dup 0) 1730 (const_int 65535)))] 1731 "operands[2] = gen_rtx_REG (HImode, true_regnum (operands[0]));") 1732 |
|
1649(define_insn "zero_extendqihi2" | 1733(define_insn "zero_extendqihi2" |
1650 [(set (match_operand:HI 0 "general_operand" "=r") 1651 (zero_extend:HI 1652 (match_operand:QI 1 "nonimmediate_operand" "qm")))] | 1734 [(set (match_operand:HI 0 "register_operand" "=q,&q,?r") 1735 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm,qm")))] |
1653 "" 1654 "* | 1736 "" 1737 "* |
1655{ 1656 if ((!TARGET_386 || REGNO (operands[0]) == 0) 1657 && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) | 1738 { 1739 rtx xops[2]; 1740 1741 if ((TARGET_ZERO_EXTEND_WITH_AND || REGNO (operands[0]) == 0) 1742 && REG_P (operands[1]) 1743 && REGNO (operands[0]) == REGNO (operands[1])) |
1658 { | 1744 { |
1659 rtx xops[2]; | |
1660 xops[0] = operands[0]; 1661 xops[1] = GEN_INT (0xff); 1662 output_asm_insn (AS2 (and%L0,%1,%k0), xops); 1663 RET; 1664 } | 1745 xops[0] = operands[0]; 1746 xops[1] = GEN_INT (0xff); 1747 output_asm_insn (AS2 (and%L0,%1,%k0), xops); 1748 RET; 1749 } |
1665 | 1750 if (TARGET_ZERO_EXTEND_WITH_AND && QI_REG_P (operands[0])) 1751 { 1752 if(!reg_overlap_mentioned_p(operands[0],operands[1])) 1753 { 1754 output_asm_insn (AS2 (xor%L0,%k0,%k0), operands); 1755 output_asm_insn (AS2 (mov%B0,%1,%b0), operands); 1756 } 1757 else 1758 { 1759 xops[0] = operands[0]; 1760 xops[1] = GEN_INT (0xff); 1761 output_asm_insn (AS2 (mov%B0,%1,%b0),operands); 1762 output_asm_insn (AS2 (and%L0,%1,%k0), xops); 1763 } 1764 RET; 1765 } 1766 |
1666#ifdef INTEL_SYNTAX 1667 return AS2 (movzx,%1,%0); 1668#else 1669 return AS2 (movz%B0%W0,%1,%0); 1670#endif 1671}") 1672 | 1767#ifdef INTEL_SYNTAX 1768 return AS2 (movzx,%1,%0); 1769#else 1770 return AS2 (movz%B0%W0,%1,%0); 1771#endif 1772}") 1773 |
1774(define_split 1775 [(set (match_operand:HI 0 "register_operand" "") 1776 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] 1777 "reload_completed && QI_REG_P (operands[0]) && TARGET_ZERO_EXTEND_WITH_AND 1778 && !reg_overlap_mentioned_p (operands[0], operands[1])" 1779 [(set (match_dup 0) 1780 (const_int 0)) 1781 (set (strict_low_part (match_dup 2)) 1782 (match_dup 1))] 1783 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));") 1784 1785 1786(define_split 1787 [(set (match_operand:HI 0 "register_operand" "") 1788 (zero_extend:HI (match_operand:QI 1 "memory_operand" "")))] 1789 "reload_completed && QI_REG_P (operands[0]) && TARGET_ZERO_EXTEND_WITH_AND 1790 && reg_overlap_mentioned_p (operands[0], operands[1])" 1791 [(set (strict_low_part (match_dup 2)) 1792 (match_dup 1)) 1793 (set (match_dup 0) 1794 (and:HI (match_dup 0) 1795 (const_int 255)))] 1796 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));") 1797 1798(define_split 1799 [(set (match_operand:HI 0 "register_operand" "") 1800 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] 1801 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND" 1802 [(set (match_dup 0) 1803 (match_dup 2)) 1804 (set (match_dup 0) 1805 (and:HI (match_dup 0) 1806 (const_int 255)))] 1807 "if (GET_CODE (operands[1]) == SUBREG && SUBREG_WORD (operands[1]) == 0) 1808 operands[1] = SUBREG_REG (operands[1]); 1809 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG 1810 || REGNO (operands[0]) == REGNO (operands[1])) 1811 FAIL; 1812 operands[2] = gen_rtx_REG (HImode, REGNO (operands[1]));") 1813 |
|
1673(define_insn "zero_extendqisi2" | 1814(define_insn "zero_extendqisi2" |
1674 [(set (match_operand:SI 0 "general_operand" "=r") 1675 (zero_extend:SI 1676 (match_operand:QI 1 "nonimmediate_operand" "qm")))] | 1815 [(set (match_operand:SI 0 "register_operand" "=q,&q,?r") 1816 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm,qm")))] |
1677 "" 1678 "* | 1817 "" 1818 "* |
1679{ 1680 if ((!TARGET_386 || REGNO (operands[0]) == 0) 1681 && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) | 1819 { 1820 rtx xops[2]; 1821 1822 if ((TARGET_ZERO_EXTEND_WITH_AND || REGNO (operands[0]) == 0) 1823 && REG_P (operands[1]) 1824 && REGNO (operands[0]) == REGNO (operands[1])) |
1682 { | 1825 { |
1683 rtx xops[2]; | |
1684 xops[0] = operands[0]; 1685 xops[1] = GEN_INT (0xff); 1686 output_asm_insn (AS2 (and%L0,%1,%k0), xops); 1687 RET; 1688 } | 1826 xops[0] = operands[0]; 1827 xops[1] = GEN_INT (0xff); 1828 output_asm_insn (AS2 (and%L0,%1,%k0), xops); 1829 RET; 1830 } |
1831 if (TARGET_ZERO_EXTEND_WITH_AND && QI_REG_P (operands[0])) 1832 { 1833 if(!reg_overlap_mentioned_p (operands[0], operands[1])) 1834 { 1835 output_asm_insn (AS2 (xor%L0,%0,%0),operands); 1836 output_asm_insn (AS2 (mov%B0,%1,%b0),operands); 1837 } 1838 else 1839 { 1840 xops[0] = operands[0]; 1841 xops[1] = GEN_INT (0xff); 1842 output_asm_insn (AS2 (mov%B0,%1,%b0), operands); 1843 output_asm_insn (AS2 (and%L0,%1,%k0), xops); 1844 } 1845 RET; 1846 } |
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1689 | 1847 |
1848 if (TARGET_ZERO_EXTEND_WITH_AND && GET_CODE (operands[1]) == REG) 1849 { 1850 xops[0] = operands[0]; 1851 xops[1] = GEN_INT (0xff); 1852 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1])); 1853 output_asm_insn (AS2 (mov%L0,%1,%0), operands); 1854 output_asm_insn (AS2 (and%L0,%1,%k0), xops); 1855 RET; 1856 } 1857 |
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1690#ifdef INTEL_SYNTAX 1691 return AS2 (movzx,%1,%0); 1692#else 1693 return AS2 (movz%B0%L0,%1,%0); 1694#endif 1695}") 1696 | 1858#ifdef INTEL_SYNTAX 1859 return AS2 (movzx,%1,%0); 1860#else 1861 return AS2 (movz%B0%L0,%1,%0); 1862#endif 1863}") 1864 |
1865(define_split 1866 [(set (match_operand:SI 0 "register_operand" "") 1867 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] 1868 "reload_completed && QI_REG_P (operands[0]) && TARGET_ZERO_EXTEND_WITH_AND 1869 && !reg_overlap_mentioned_p (operands[0], operands[1])" 1870 [(set (match_dup 0) 1871 (const_int 0)) 1872 (set (strict_low_part (match_dup 2)) 1873 (match_dup 1))] 1874 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));") 1875 1876 1877(define_split 1878 [(set (match_operand:SI 0 "register_operand" "") 1879 (zero_extend:SI (match_operand:QI 1 "memory_operand" "")))] 1880 "reload_completed && QI_REG_P (operands[0]) && TARGET_ZERO_EXTEND_WITH_AND 1881 && reg_overlap_mentioned_p (operands[0], operands[1])" 1882 [(set (strict_low_part (match_dup 2)) 1883 (match_dup 1)) 1884 (set (match_dup 0) 1885 (and:SI (match_dup 0) 1886 (const_int 255)))] 1887 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));") 1888 1889(define_split 1890 [(set (match_operand:SI 0 "register_operand" "") 1891 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] 1892 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND 1893 && ! reg_overlap_mentioned_p (operands[0], operands[1])" 1894 [(set (match_dup 0) 1895 (match_dup 2)) 1896 (set (match_dup 0) 1897 (and:SI (match_dup 0) 1898 (const_int 255)))] 1899 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));") 1900 |
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1697(define_insn "zero_extendsidi2" | 1901(define_insn "zero_extendsidi2" |
1698 [(set (match_operand:DI 0 "register_operand" "=r") 1699 (zero_extend:DI 1700 (match_operand:SI 1 "register_operand" "0")))] | 1902 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?m") 1903 (zero_extend:DI (match_operand:SI 1 "register_operand" "0,rm,r")))] |
1701 "" 1702 "* | 1904 "" 1905 "* |
1703{ 1704 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 1705 return AS2 (xor%L0,%0,%0); | 1906 { 1907 rtx high[2], low[2], xops[4]; 1908 1909 if (REG_P (operands[0]) && REG_P (operands[1]) 1910 && REGNO (operands[0]) == REGNO (operands[1])) 1911 { 1912 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 1913 return AS2 (xor%L0,%0,%0); 1914 } 1915 1916 split_di (operands, 1, low, high); 1917 xops[0] = low[0]; 1918 xops[1] = operands[1]; 1919 xops[2] = high[0]; 1920 xops[3] = const0_rtx; 1921 1922 output_asm_insn (AS2 (mov%L0,%1,%0), xops); 1923 if (GET_CODE (low[0]) == MEM) 1924 output_asm_insn (AS2 (mov%L2,%3,%2), xops); 1925 else 1926 output_asm_insn (AS2 (xor%L2,%2,%2), xops); 1927 1928 RET; |
1706}") 1707 1708;;- sign extension instructions 1709 1710(define_insn "extendsidi2" 1711 [(set (match_operand:DI 0 "register_operand" "=r") | 1929}") 1930 1931;;- sign extension instructions 1932 1933(define_insn "extendsidi2" 1934 [(set (match_operand:DI 0 "register_operand" "=r") |
1712 (sign_extend:DI 1713 (match_operand:SI 1 "register_operand" "0")))] | 1935 (sign_extend:DI (match_operand:SI 1 "register_operand" "0")))] |
1714 "" 1715 "* 1716{ 1717 if (REGNO (operands[0]) == 0) 1718 { 1719 /* This used to be cwtl, but that extends HI to SI somehow. */ 1720#ifdef INTEL_SYNTAX 1721 return \"cdq\"; 1722#else 1723 return \"cltd\"; 1724#endif 1725 } 1726 | 1936 "" 1937 "* 1938{ 1939 if (REGNO (operands[0]) == 0) 1940 { 1941 /* This used to be cwtl, but that extends HI to SI somehow. */ 1942#ifdef INTEL_SYNTAX 1943 return \"cdq\"; 1944#else 1945 return \"cltd\"; 1946#endif 1947 } 1948 |
1727 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); | 1949 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
1728 output_asm_insn (AS2 (mov%L0,%0,%1), operands); 1729 1730 operands[0] = GEN_INT (31); 1731 return AS2 (sar%L1,%0,%1); 1732}") 1733 1734;; Note that the i386 programmers' manual says that the opcodes 1735;; are named movsx..., but the assembler on Unix does not accept that. 1736;; We use what the Unix assembler expects. 1737 1738(define_insn "extendhisi2" | 1950 output_asm_insn (AS2 (mov%L0,%0,%1), operands); 1951 1952 operands[0] = GEN_INT (31); 1953 return AS2 (sar%L1,%0,%1); 1954}") 1955 1956;; Note that the i386 programmers' manual says that the opcodes 1957;; are named movsx..., but the assembler on Unix does not accept that. 1958;; We use what the Unix assembler expects. 1959 1960(define_insn "extendhisi2" |
1739 [(set (match_operand:SI 0 "general_operand" "=r") 1740 (sign_extend:SI 1741 (match_operand:HI 1 "nonimmediate_operand" "rm")))] | 1961 [(set (match_operand:SI 0 "register_operand" "=r") 1962 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] |
1742 "" 1743 "* 1744{ 1745 if (REGNO (operands[0]) == 0 1746 && REG_P (operands[1]) && REGNO (operands[1]) == 0) 1747#ifdef INTEL_SYNTAX 1748 return \"cwde\"; 1749#else 1750 return \"cwtl\"; 1751#endif 1752 1753#ifdef INTEL_SYNTAX 1754 return AS2 (movsx,%1,%0); 1755#else 1756 return AS2 (movs%W0%L0,%1,%0); 1757#endif 1758}") 1759 1760(define_insn "extendqihi2" | 1963 "" 1964 "* 1965{ 1966 if (REGNO (operands[0]) == 0 1967 && REG_P (operands[1]) && REGNO (operands[1]) == 0) 1968#ifdef INTEL_SYNTAX 1969 return \"cwde\"; 1970#else 1971 return \"cwtl\"; 1972#endif 1973 1974#ifdef INTEL_SYNTAX 1975 return AS2 (movsx,%1,%0); 1976#else 1977 return AS2 (movs%W0%L0,%1,%0); 1978#endif 1979}") 1980 1981(define_insn "extendqihi2" |
1761 [(set (match_operand:HI 0 "general_operand" "=r") 1762 (sign_extend:HI 1763 (match_operand:QI 1 "nonimmediate_operand" "qm")))] | 1982 [(set (match_operand:HI 0 "register_operand" "=r") 1983 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))] |
1764 "" 1765 "* 1766{ 1767 if (REGNO (operands[0]) == 0 1768 && REG_P (operands[1]) && REGNO (operands[1]) == 0) 1769 return \"cbtw\"; 1770 1771#ifdef INTEL_SYNTAX 1772 return AS2 (movsx,%1,%0); 1773#else 1774 return AS2 (movs%B0%W0,%1,%0); 1775#endif 1776}") 1777 1778(define_insn "extendqisi2" | 1984 "" 1985 "* 1986{ 1987 if (REGNO (operands[0]) == 0 1988 && REG_P (operands[1]) && REGNO (operands[1]) == 0) 1989 return \"cbtw\"; 1990 1991#ifdef INTEL_SYNTAX 1992 return AS2 (movsx,%1,%0); 1993#else 1994 return AS2 (movs%B0%W0,%1,%0); 1995#endif 1996}") 1997 1998(define_insn "extendqisi2" |
1779 [(set (match_operand:SI 0 "general_operand" "=r") 1780 (sign_extend:SI 1781 (match_operand:QI 1 "nonimmediate_operand" "qm")))] | 1999 [(set (match_operand:SI 0 "register_operand" "=r") 2000 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))] |
1782 "" 1783 "* 1784{ 1785#ifdef INTEL_SYNTAX 1786 return AS2 (movsx,%1,%0); 1787#else 1788 return AS2 (movs%B0%L0,%1,%0); 1789#endif 1790}") | 2001 "" 2002 "* 2003{ 2004#ifdef INTEL_SYNTAX 2005 return AS2 (movsx,%1,%0); 2006#else 2007 return AS2 (movs%B0%L0,%1,%0); 2008#endif 2009}") |
2010 |
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1791 | 2011 |
2012;; Truncation of long long -> 32 bit 2013 2014(define_expand "truncdisi2" 2015 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m") 2016 (truncate:SI (match_operand:DI 1 "nonimmediate_operand" "ro,r")))] 2017 "" 2018 " 2019{ 2020 /* Don't generate memory->memory moves, go through a register */ 2021 if (TARGET_MOVE 2022 && (reload_in_progress | reload_completed) == 0 2023 && GET_CODE (operands[0]) == MEM 2024 && GET_CODE (operands[1]) == MEM) 2025 { 2026 rtx target = gen_reg_rtx (SImode); 2027 emit_insn (gen_truncdisi2 (target, operands[1])); 2028 emit_move_insn (operands[0], target); 2029 DONE; 2030 } 2031}") 2032 2033(define_insn "" 2034 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m") 2035 (truncate:SI (match_operand:DI 1 "nonimmediate_operand" "ro,r")))] 2036 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" 2037 "* 2038{ 2039 rtx low[2], high[2], xops[2]; 2040 2041 split_di (&operands[1], 1, low, high); 2042 xops[0] = operands[0]; 2043 xops[1] = low[0]; 2044 if (!rtx_equal_p (xops[0], xops[1])) 2045 output_asm_insn (AS2 (mov%L0,%1,%0), xops); 2046 2047 RET; 2048}") 2049 2050(define_insn "" 2051 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m") 2052 (truncate:SI (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "ro,r") 2053 (const_int 32))))] 2054 "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" 2055 "* 2056{ 2057 rtx low[2], high[2], xops[2]; 2058 2059 split_di (&operands[1], 1, low, high); 2060 xops[0] = operands[0]; 2061 xops[1] = high[0]; 2062 if (!rtx_equal_p (xops[0], xops[1])) 2063 output_asm_insn (AS2 (mov%L0,%1,%0), xops); 2064 2065 RET; 2066}") 2067 2068 2069 |
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1792;; Conversions between float and double. 1793 1794(define_insn "extendsfdf2" | 2070;; Conversions between float and double. 2071 2072(define_insn "extendsfdf2" |
1795 [(set (match_operand:DF 0 "general_operand" "=fm,f") | 2073 [(set (match_operand:DF 0 "nonimmediate_operand" "=fm,f") |
1796 (float_extend:DF | 2074 (float_extend:DF |
1797 (match_operand:SF 1 "general_operand" "f,fm")))] | 2075 (match_operand:SF 1 "nonimmediate_operand" "f,fm")))] |
1798 "TARGET_80387" 1799 "* 1800{ 1801 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 1802 1803 if (NON_STACK_REG_P (operands[1])) 1804 { 1805 output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); 1806 RET; 1807 } 1808 1809 if (NON_STACK_REG_P (operands[0])) 1810 { | 2076 "TARGET_80387" 2077 "* 2078{ 2079 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 2080 2081 if (NON_STACK_REG_P (operands[1])) 2082 { 2083 output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); 2084 RET; 2085 } 2086 2087 if (NON_STACK_REG_P (operands[0])) 2088 { |
1811 output_to_reg (operands[0], stack_top_dies); | 2089 output_to_reg (operands[0], stack_top_dies, 0); |
1812 RET; 1813 } 1814 1815 if (STACK_TOP_P (operands[0])) 1816 return AS1 (fld%z1,%y1); 1817 1818 if (GET_CODE (operands[0]) == MEM) 1819 { 1820 if (stack_top_dies) 1821 return AS1 (fstp%z0,%y0); 1822 else 1823 return AS1 (fst%z0,%y0); 1824 } 1825 1826 abort (); 1827}") 1828 1829(define_insn "extenddfxf2" | 2090 RET; 2091 } 2092 2093 if (STACK_TOP_P (operands[0])) 2094 return AS1 (fld%z1,%y1); 2095 2096 if (GET_CODE (operands[0]) == MEM) 2097 { 2098 if (stack_top_dies) 2099 return AS1 (fstp%z0,%y0); 2100 else 2101 return AS1 (fst%z0,%y0); 2102 } 2103 2104 abort (); 2105}") 2106 2107(define_insn "extenddfxf2" |
1830 [(set (match_operand:XF 0 "general_operand" "=fm,f,f,!*r") | 2108 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f,f,!*r") |
1831 (float_extend:XF | 2109 (float_extend:XF |
1832 (match_operand:DF 1 "general_operand" "f,fm,!*r,f")))] | 2110 (match_operand:DF 1 "nonimmediate_operand" "f,fm,!*r,f")))] |
1833 "TARGET_80387" 1834 "* 1835{ 1836 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 1837 1838 if (NON_STACK_REG_P (operands[1])) 1839 { 1840 output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); 1841 RET; 1842 } 1843 1844 if (NON_STACK_REG_P (operands[0])) 1845 { | 2111 "TARGET_80387" 2112 "* 2113{ 2114 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 2115 2116 if (NON_STACK_REG_P (operands[1])) 2117 { 2118 output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); 2119 RET; 2120 } 2121 2122 if (NON_STACK_REG_P (operands[0])) 2123 { |
1846 output_to_reg (operands[0], stack_top_dies); | 2124 output_to_reg (operands[0], stack_top_dies, 0); |
1847 RET; 1848 } 1849 1850 if (STACK_TOP_P (operands[0])) 1851 return AS1 (fld%z1,%y1); 1852 1853 if (GET_CODE (operands[0]) == MEM) 1854 { 1855 output_asm_insn (AS1 (fstp%z0,%y0), operands); 1856 if (! stack_top_dies) 1857 return AS1 (fld%z0,%y0); 1858 RET; 1859 } 1860 1861 abort (); 1862}") 1863 1864(define_insn "extendsfxf2" | 2125 RET; 2126 } 2127 2128 if (STACK_TOP_P (operands[0])) 2129 return AS1 (fld%z1,%y1); 2130 2131 if (GET_CODE (operands[0]) == MEM) 2132 { 2133 output_asm_insn (AS1 (fstp%z0,%y0), operands); 2134 if (! stack_top_dies) 2135 return AS1 (fld%z0,%y0); 2136 RET; 2137 } 2138 2139 abort (); 2140}") 2141 2142(define_insn "extendsfxf2" |
1865 [(set (match_operand:XF 0 "general_operand" "=fm,f,f,!*r") | 2143 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f,f,!*r") |
1866 (float_extend:XF | 2144 (float_extend:XF |
1867 (match_operand:SF 1 "general_operand" "f,fm,!*r,f")))] | 2145 (match_operand:SF 1 "nonimmediate_operand" "f,fm,!*r,f")))] |
1868 "TARGET_80387" 1869 "* 1870{ 1871 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 1872 1873 if (NON_STACK_REG_P (operands[1])) 1874 { 1875 output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); 1876 RET; 1877 } 1878 1879 if (NON_STACK_REG_P (operands[0])) 1880 { | 2146 "TARGET_80387" 2147 "* 2148{ 2149 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 2150 2151 if (NON_STACK_REG_P (operands[1])) 2152 { 2153 output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); 2154 RET; 2155 } 2156 2157 if (NON_STACK_REG_P (operands[0])) 2158 { |
1881 output_to_reg (operands[0], stack_top_dies); | 2159 output_to_reg (operands[0], stack_top_dies, 0); |
1882 RET; 1883 } 1884 1885 if (STACK_TOP_P (operands[0])) 1886 return AS1 (fld%z1,%y1); 1887 1888 if (GET_CODE (operands[0]) == MEM) 1889 { --- 44 unchanged lines hidden (view full) --- 1934 output_asm_insn (AS1 (fstp%z2,%y2), operands); 1935 return AS1 (fld%z2,%y2); 1936 } 1937 else 1938 abort (); 1939}") 1940 1941(define_insn "truncxfsf2" | 2160 RET; 2161 } 2162 2163 if (STACK_TOP_P (operands[0])) 2164 return AS1 (fld%z1,%y1); 2165 2166 if (GET_CODE (operands[0]) == MEM) 2167 { --- 44 unchanged lines hidden (view full) --- 2212 output_asm_insn (AS1 (fstp%z2,%y2), operands); 2213 return AS1 (fld%z2,%y2); 2214 } 2215 else 2216 abort (); 2217}") 2218 2219(define_insn "truncxfsf2" |
1942 [(set (match_operand:SF 0 "general_operand" "=m,!*r") | 2220 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,!*r") |
1943 (float_truncate:SF 1944 (match_operand:XF 1 "register_operand" "f,f")))] 1945 "TARGET_80387" 1946 "* 1947{ 1948 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 1949 1950 if (NON_STACK_REG_P (operands[0])) 1951 { 1952 if (stack_top_dies == 0) 1953 { 1954 output_asm_insn (AS1 (fld,%y1), operands); 1955 stack_top_dies = 1; 1956 } | 2221 (float_truncate:SF 2222 (match_operand:XF 1 "register_operand" "f,f")))] 2223 "TARGET_80387" 2224 "* 2225{ 2226 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 2227 2228 if (NON_STACK_REG_P (operands[0])) 2229 { 2230 if (stack_top_dies == 0) 2231 { 2232 output_asm_insn (AS1 (fld,%y1), operands); 2233 stack_top_dies = 1; 2234 } |
1957 output_to_reg (operands[0], stack_top_dies); | 2235 output_to_reg (operands[0], stack_top_dies, 0); |
1958 RET; 1959 } 1960 else if (GET_CODE (operands[0]) == MEM) 1961 { 1962 if (stack_top_dies) 1963 return AS1 (fstp%z0,%0); 1964 else 1965 { 1966 output_asm_insn (AS1 (fld,%y1), operands); 1967 return AS1 (fstp%z0,%0); 1968 } 1969 } 1970 else 1971 abort (); 1972}") 1973 1974(define_insn "truncxfdf2" | 2236 RET; 2237 } 2238 else if (GET_CODE (operands[0]) == MEM) 2239 { 2240 if (stack_top_dies) 2241 return AS1 (fstp%z0,%0); 2242 else 2243 { 2244 output_asm_insn (AS1 (fld,%y1), operands); 2245 return AS1 (fstp%z0,%0); 2246 } 2247 } 2248 else 2249 abort (); 2250}") 2251 2252(define_insn "truncxfdf2" |
1975 [(set (match_operand:DF 0 "general_operand" "=m,!*r") | 2253 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!*r") |
1976 (float_truncate:DF 1977 (match_operand:XF 1 "register_operand" "f,f")))] 1978 "TARGET_80387" 1979 "* 1980{ 1981 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 1982 1983 if (NON_STACK_REG_P (operands[0])) 1984 { 1985 if (stack_top_dies == 0) 1986 { 1987 output_asm_insn (AS1 (fld,%y1), operands); 1988 stack_top_dies = 1; 1989 } | 2254 (float_truncate:DF 2255 (match_operand:XF 1 "register_operand" "f,f")))] 2256 "TARGET_80387" 2257 "* 2258{ 2259 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 2260 2261 if (NON_STACK_REG_P (operands[0])) 2262 { 2263 if (stack_top_dies == 0) 2264 { 2265 output_asm_insn (AS1 (fld,%y1), operands); 2266 stack_top_dies = 1; 2267 } |
1990 output_to_reg (operands[0], stack_top_dies); | 2268 output_to_reg (operands[0], stack_top_dies, 0); |
1991 RET; 1992 } 1993 else if (GET_CODE (operands[0]) == MEM) 1994 { 1995 if (stack_top_dies) 1996 return AS1 (fstp%z0,%0); 1997 else 1998 { --- 25 unchanged lines hidden (view full) --- 2024 (match_dup 3))] 2025 "TARGET_80387" 2026 " 2027{ 2028 operands[2] = gen_reg_rtx (DImode); 2029 operands[3] = gen_lowpart (SImode, operands[2]); 2030 operands[4] = gen_reg_rtx (XFmode); 2031 operands[5] = (rtx) assign_386_stack_local (SImode, 0); | 2269 RET; 2270 } 2271 else if (GET_CODE (operands[0]) == MEM) 2272 { 2273 if (stack_top_dies) 2274 return AS1 (fstp%z0,%0); 2275 else 2276 { --- 25 unchanged lines hidden (view full) --- 2302 (match_dup 3))] 2303 "TARGET_80387" 2304 " 2305{ 2306 operands[2] = gen_reg_rtx (DImode); 2307 operands[3] = gen_lowpart (SImode, operands[2]); 2308 operands[4] = gen_reg_rtx (XFmode); 2309 operands[5] = (rtx) assign_386_stack_local (SImode, 0); |
2032 operands[6] = (rtx) assign_386_stack_local (SImode, 1); | 2310 operands[6] = (rtx) assign_386_stack_local (DImode, 1); |
2033}") 2034 2035(define_expand "fixuns_truncdfsi2" 2036 [(set (match_dup 4) 2037 (match_operand:DF 1 "register_operand" "")) 2038 (parallel [(set (match_dup 2) 2039 (fix:DI (fix:DF (match_dup 4)))) 2040 (clobber (match_dup 4)) --- 4 unchanged lines hidden (view full) --- 2045 (match_dup 3))] 2046 "TARGET_80387" 2047 " 2048{ 2049 operands[2] = gen_reg_rtx (DImode); 2050 operands[3] = gen_lowpart (SImode, operands[2]); 2051 operands[4] = gen_reg_rtx (DFmode); 2052 operands[5] = (rtx) assign_386_stack_local (SImode, 0); | 2311}") 2312 2313(define_expand "fixuns_truncdfsi2" 2314 [(set (match_dup 4) 2315 (match_operand:DF 1 "register_operand" "")) 2316 (parallel [(set (match_dup 2) 2317 (fix:DI (fix:DF (match_dup 4)))) 2318 (clobber (match_dup 4)) --- 4 unchanged lines hidden (view full) --- 2323 (match_dup 3))] 2324 "TARGET_80387" 2325 " 2326{ 2327 operands[2] = gen_reg_rtx (DImode); 2328 operands[3] = gen_lowpart (SImode, operands[2]); 2329 operands[4] = gen_reg_rtx (DFmode); 2330 operands[5] = (rtx) assign_386_stack_local (SImode, 0); |
2053 operands[6] = (rtx) assign_386_stack_local (SImode, 1); | 2331 operands[6] = (rtx) assign_386_stack_local (DImode, 1); |
2054}") 2055 2056(define_expand "fixuns_truncsfsi2" 2057 [(set (match_dup 4) 2058 (match_operand:SF 1 "register_operand" "")) 2059 (parallel [(set (match_dup 2) 2060 (fix:DI (fix:SF (match_dup 4)))) 2061 (clobber (match_dup 4)) --- 4 unchanged lines hidden (view full) --- 2066 (match_dup 3))] 2067 "TARGET_80387" 2068 " 2069{ 2070 operands[2] = gen_reg_rtx (DImode); 2071 operands[3] = gen_lowpart (SImode, operands[2]); 2072 operands[4] = gen_reg_rtx (SFmode); 2073 operands[5] = (rtx) assign_386_stack_local (SImode, 0); | 2332}") 2333 2334(define_expand "fixuns_truncsfsi2" 2335 [(set (match_dup 4) 2336 (match_operand:SF 1 "register_operand" "")) 2337 (parallel [(set (match_dup 2) 2338 (fix:DI (fix:SF (match_dup 4)))) 2339 (clobber (match_dup 4)) --- 4 unchanged lines hidden (view full) --- 2344 (match_dup 3))] 2345 "TARGET_80387" 2346 " 2347{ 2348 operands[2] = gen_reg_rtx (DImode); 2349 operands[3] = gen_lowpart (SImode, operands[2]); 2350 operands[4] = gen_reg_rtx (SFmode); 2351 operands[5] = (rtx) assign_386_stack_local (SImode, 0); |
2074 operands[6] = (rtx) assign_386_stack_local (SImode, 1); | 2352 operands[6] = (rtx) assign_386_stack_local (DImode, 1); |
2075}") 2076 2077;; Signed conversion to DImode. 2078 2079(define_expand "fix_truncxfdi2" 2080 [(set (match_dup 2) 2081 (match_operand:XF 1 "register_operand" "")) 2082 (parallel [(set (match_operand:DI 0 "general_operand" "") 2083 (fix:DI (fix:XF (match_dup 2)))) 2084 (clobber (match_dup 2)) 2085 (clobber (match_dup 3)) 2086 (clobber (match_dup 4)) 2087 (clobber (match_scratch:SI 5 ""))])] 2088 "TARGET_80387" 2089 " 2090{ 2091 operands[1] = copy_to_mode_reg (XFmode, operands[1]); 2092 operands[2] = gen_reg_rtx (XFmode); 2093 operands[3] = (rtx) assign_386_stack_local (SImode, 0); | 2353}") 2354 2355;; Signed conversion to DImode. 2356 2357(define_expand "fix_truncxfdi2" 2358 [(set (match_dup 2) 2359 (match_operand:XF 1 "register_operand" "")) 2360 (parallel [(set (match_operand:DI 0 "general_operand" "") 2361 (fix:DI (fix:XF (match_dup 2)))) 2362 (clobber (match_dup 2)) 2363 (clobber (match_dup 3)) 2364 (clobber (match_dup 4)) 2365 (clobber (match_scratch:SI 5 ""))])] 2366 "TARGET_80387" 2367 " 2368{ 2369 operands[1] = copy_to_mode_reg (XFmode, operands[1]); 2370 operands[2] = gen_reg_rtx (XFmode); 2371 operands[3] = (rtx) assign_386_stack_local (SImode, 0); |
2094 operands[4] = (rtx) assign_386_stack_local (SImode, 1); | 2372 operands[4] = (rtx) assign_386_stack_local (DImode, 1); |
2095}") 2096 2097(define_expand "fix_truncdfdi2" 2098 [(set (match_dup 2) 2099 (match_operand:DF 1 "register_operand" "")) 2100 (parallel [(set (match_operand:DI 0 "general_operand" "") 2101 (fix:DI (fix:DF (match_dup 2)))) 2102 (clobber (match_dup 2)) 2103 (clobber (match_dup 3)) 2104 (clobber (match_dup 4)) 2105 (clobber (match_scratch:SI 5 ""))])] 2106 "TARGET_80387" 2107 " 2108{ 2109 operands[1] = copy_to_mode_reg (DFmode, operands[1]); 2110 operands[2] = gen_reg_rtx (DFmode); 2111 operands[3] = (rtx) assign_386_stack_local (SImode, 0); | 2373}") 2374 2375(define_expand "fix_truncdfdi2" 2376 [(set (match_dup 2) 2377 (match_operand:DF 1 "register_operand" "")) 2378 (parallel [(set (match_operand:DI 0 "general_operand" "") 2379 (fix:DI (fix:DF (match_dup 2)))) 2380 (clobber (match_dup 2)) 2381 (clobber (match_dup 3)) 2382 (clobber (match_dup 4)) 2383 (clobber (match_scratch:SI 5 ""))])] 2384 "TARGET_80387" 2385 " 2386{ 2387 operands[1] = copy_to_mode_reg (DFmode, operands[1]); 2388 operands[2] = gen_reg_rtx (DFmode); 2389 operands[3] = (rtx) assign_386_stack_local (SImode, 0); |
2112 operands[4] = (rtx) assign_386_stack_local (SImode, 1); | 2390 operands[4] = (rtx) assign_386_stack_local (DImode, 1); |
2113}") 2114 2115(define_expand "fix_truncsfdi2" 2116 [(set (match_dup 2) 2117 (match_operand:SF 1 "register_operand" "")) 2118 (parallel [(set (match_operand:DI 0 "general_operand" "") 2119 (fix:DI (fix:SF (match_dup 2)))) 2120 (clobber (match_dup 2)) 2121 (clobber (match_dup 3)) 2122 (clobber (match_dup 4)) 2123 (clobber (match_scratch:SI 5 ""))])] 2124 "TARGET_80387" 2125 " 2126{ 2127 operands[1] = copy_to_mode_reg (SFmode, operands[1]); 2128 operands[2] = gen_reg_rtx (SFmode); 2129 operands[3] = (rtx) assign_386_stack_local (SImode, 0); | 2391}") 2392 2393(define_expand "fix_truncsfdi2" 2394 [(set (match_dup 2) 2395 (match_operand:SF 1 "register_operand" "")) 2396 (parallel [(set (match_operand:DI 0 "general_operand" "") 2397 (fix:DI (fix:SF (match_dup 2)))) 2398 (clobber (match_dup 2)) 2399 (clobber (match_dup 3)) 2400 (clobber (match_dup 4)) 2401 (clobber (match_scratch:SI 5 ""))])] 2402 "TARGET_80387" 2403 " 2404{ 2405 operands[1] = copy_to_mode_reg (SFmode, operands[1]); 2406 operands[2] = gen_reg_rtx (SFmode); 2407 operands[3] = (rtx) assign_386_stack_local (SImode, 0); |
2130 operands[4] = (rtx) assign_386_stack_local (SImode, 1); | 2408 operands[4] = (rtx) assign_386_stack_local (DImode, 1); |
2131}") 2132 2133;; These match a signed conversion of either DFmode or SFmode to DImode. 2134 2135(define_insn "" | 2409}") 2410 2411;; These match a signed conversion of either DFmode or SFmode to DImode. 2412 2413(define_insn "" |
2136 [(set (match_operand:DI 0 "general_operand" "=rm") 2137 (fix:DI (fix:XF (match_operand:XF 1 "register_operand" "f")))) | 2414 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") 2415 (fix:DI (fix:XF (match_operand:XF 1 "register_operand" "+f")))) |
2138 (clobber (match_dup 1)) 2139 (clobber (match_operand:SI 2 "memory_operand" "m")) | 2416 (clobber (match_dup 1)) 2417 (clobber (match_operand:SI 2 "memory_operand" "m")) |
2140 (clobber (match_operand:SI 3 "memory_operand" "m")) | 2418 (clobber (match_operand:DI 3 "memory_operand" "m")) |
2141 (clobber (match_scratch:SI 4 "=&q"))] 2142 "TARGET_80387" 2143 "* return output_fix_trunc (insn, operands);") 2144 2145(define_insn "" | 2419 (clobber (match_scratch:SI 4 "=&q"))] 2420 "TARGET_80387" 2421 "* return output_fix_trunc (insn, operands);") 2422 2423(define_insn "" |
2146 [(set (match_operand:DI 0 "general_operand" "=rm") 2147 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f")))) | 2424 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") 2425 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "+f")))) |
2148 (clobber (match_dup 1)) 2149 (clobber (match_operand:SI 2 "memory_operand" "m")) | 2426 (clobber (match_dup 1)) 2427 (clobber (match_operand:SI 2 "memory_operand" "m")) |
2150 (clobber (match_operand:SI 3 "memory_operand" "m")) | 2428 (clobber (match_operand:DI 3 "memory_operand" "m")) |
2151 (clobber (match_scratch:SI 4 "=&q"))] 2152 "TARGET_80387" 2153 "* return output_fix_trunc (insn, operands);") 2154 2155(define_insn "" | 2429 (clobber (match_scratch:SI 4 "=&q"))] 2430 "TARGET_80387" 2431 "* return output_fix_trunc (insn, operands);") 2432 2433(define_insn "" |
2156 [(set (match_operand:DI 0 "general_operand" "=rm") 2157 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f")))) | 2434 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") 2435 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "+f")))) |
2158 (clobber (match_dup 1)) 2159 (clobber (match_operand:SI 2 "memory_operand" "m")) | 2436 (clobber (match_dup 1)) 2437 (clobber (match_operand:SI 2 "memory_operand" "m")) |
2160 (clobber (match_operand:SI 3 "memory_operand" "m")) | 2438 (clobber (match_operand:DI 3 "memory_operand" "m")) |
2161 (clobber (match_scratch:SI 4 "=&q"))] 2162 "TARGET_80387" 2163 "* return output_fix_trunc (insn, operands);") 2164 2165;; Signed MODE_FLOAT conversion to SImode. 2166 2167(define_expand "fix_truncxfsi2" 2168 [(parallel [(set (match_operand:SI 0 "general_operand" "") 2169 (fix:SI 2170 (fix:XF (match_operand:XF 1 "register_operand" "")))) 2171 (clobber (match_dup 2)) 2172 (clobber (match_dup 3)) 2173 (clobber (match_scratch:SI 4 ""))])] 2174 "TARGET_80387" 2175 " 2176{ 2177 operands[2] = (rtx) assign_386_stack_local (SImode, 0); | 2439 (clobber (match_scratch:SI 4 "=&q"))] 2440 "TARGET_80387" 2441 "* return output_fix_trunc (insn, operands);") 2442 2443;; Signed MODE_FLOAT conversion to SImode. 2444 2445(define_expand "fix_truncxfsi2" 2446 [(parallel [(set (match_operand:SI 0 "general_operand" "") 2447 (fix:SI 2448 (fix:XF (match_operand:XF 1 "register_operand" "")))) 2449 (clobber (match_dup 2)) 2450 (clobber (match_dup 3)) 2451 (clobber (match_scratch:SI 4 ""))])] 2452 "TARGET_80387" 2453 " 2454{ 2455 operands[2] = (rtx) assign_386_stack_local (SImode, 0); |
2178 operands[3] = (rtx) assign_386_stack_local (SImode, 1); | 2456 operands[3] = (rtx) assign_386_stack_local (DImode, 1); |
2179}") 2180 2181(define_expand "fix_truncdfsi2" 2182 [(parallel [(set (match_operand:SI 0 "general_operand" "") 2183 (fix:SI 2184 (fix:DF (match_operand:DF 1 "register_operand" "")))) 2185 (clobber (match_dup 2)) 2186 (clobber (match_dup 3)) 2187 (clobber (match_scratch:SI 4 ""))])] 2188 "TARGET_80387" 2189 " 2190{ 2191 operands[2] = (rtx) assign_386_stack_local (SImode, 0); | 2457}") 2458 2459(define_expand "fix_truncdfsi2" 2460 [(parallel [(set (match_operand:SI 0 "general_operand" "") 2461 (fix:SI 2462 (fix:DF (match_operand:DF 1 "register_operand" "")))) 2463 (clobber (match_dup 2)) 2464 (clobber (match_dup 3)) 2465 (clobber (match_scratch:SI 4 ""))])] 2466 "TARGET_80387" 2467 " 2468{ 2469 operands[2] = (rtx) assign_386_stack_local (SImode, 0); |
2192 operands[3] = (rtx) assign_386_stack_local (SImode, 1); | 2470 operands[3] = (rtx) assign_386_stack_local (DImode, 1); |
2193}") 2194 2195(define_expand "fix_truncsfsi2" 2196 [(parallel [(set (match_operand:SI 0 "general_operand" "") 2197 (fix:SI 2198 (fix:SF (match_operand:SF 1 "register_operand" "")))) 2199 (clobber (match_dup 2)) 2200 (clobber (match_dup 3)) 2201 (clobber (match_scratch:SI 4 ""))])] 2202 "TARGET_80387" 2203 " 2204{ 2205 operands[2] = (rtx) assign_386_stack_local (SImode, 0); | 2471}") 2472 2473(define_expand "fix_truncsfsi2" 2474 [(parallel [(set (match_operand:SI 0 "general_operand" "") 2475 (fix:SI 2476 (fix:SF (match_operand:SF 1 "register_operand" "")))) 2477 (clobber (match_dup 2)) 2478 (clobber (match_dup 3)) 2479 (clobber (match_scratch:SI 4 ""))])] 2480 "TARGET_80387" 2481 " 2482{ 2483 operands[2] = (rtx) assign_386_stack_local (SImode, 0); |
2206 operands[3] = (rtx) assign_386_stack_local (SImode, 1); | 2484 operands[3] = (rtx) assign_386_stack_local (DImode, 1); |
2207}") 2208 2209(define_insn "" | 2485}") 2486 2487(define_insn "" |
2210 [(set (match_operand:SI 0 "general_operand" "=rm") | 2488 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
2211 (fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f")))) 2212 (clobber (match_operand:SI 2 "memory_operand" "m")) | 2489 (fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f")))) 2490 (clobber (match_operand:SI 2 "memory_operand" "m")) |
2213 (clobber (match_operand:SI 3 "memory_operand" "m")) | 2491 (clobber (match_operand:DI 3 "memory_operand" "m")) |
2214 (clobber (match_scratch:SI 4 "=&q"))] 2215 "TARGET_80387" 2216 "* return output_fix_trunc (insn, operands);") 2217 2218(define_insn "" | 2492 (clobber (match_scratch:SI 4 "=&q"))] 2493 "TARGET_80387" 2494 "* return output_fix_trunc (insn, operands);") 2495 2496(define_insn "" |
2219 [(set (match_operand:SI 0 "general_operand" "=rm") | 2497 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
2220 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f")))) 2221 (clobber (match_operand:SI 2 "memory_operand" "m")) | 2498 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f")))) 2499 (clobber (match_operand:SI 2 "memory_operand" "m")) |
2222 (clobber (match_operand:SI 3 "memory_operand" "m")) | 2500 (clobber (match_operand:DI 3 "memory_operand" "m")) |
2223 (clobber (match_scratch:SI 4 "=&q"))] 2224 "TARGET_80387" 2225 "* return output_fix_trunc (insn, operands);") 2226 2227(define_insn "" | 2501 (clobber (match_scratch:SI 4 "=&q"))] 2502 "TARGET_80387" 2503 "* return output_fix_trunc (insn, operands);") 2504 2505(define_insn "" |
2228 [(set (match_operand:SI 0 "general_operand" "=rm") | 2506 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
2229 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f")))) 2230 (clobber (match_operand:SI 2 "memory_operand" "m")) | 2507 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f")))) 2508 (clobber (match_operand:SI 2 "memory_operand" "m")) |
2231 (clobber (match_operand:SI 3 "memory_operand" "m")) | 2509 (clobber (match_operand:DI 3 "memory_operand" "m")) |
2232 (clobber (match_scratch:SI 4 "=&q"))] 2233 "TARGET_80387" 2234 "* return output_fix_trunc (insn, operands);") 2235 2236;; Conversion between fixed point and floating point. 2237;; The actual pattern that matches these is at the end of this file. 2238 2239;; ??? Possibly represent floatunssidf2 here in gcc2. --- 26 unchanged lines hidden (view full) --- 2266 [(set (match_operand:XF 0 "register_operand" "") 2267 (float:XF (match_operand:SI 1 "nonimmediate_operand" "")))] 2268 "TARGET_80387" 2269 "") 2270 2271(define_expand "floatdixf2" 2272 [(set (match_operand:XF 0 "register_operand" "") 2273 (float:XF (match_operand:DI 1 "nonimmediate_operand" "")))] | 2510 (clobber (match_scratch:SI 4 "=&q"))] 2511 "TARGET_80387" 2512 "* return output_fix_trunc (insn, operands);") 2513 2514;; Conversion between fixed point and floating point. 2515;; The actual pattern that matches these is at the end of this file. 2516 2517;; ??? Possibly represent floatunssidf2 here in gcc2. --- 26 unchanged lines hidden (view full) --- 2544 [(set (match_operand:XF 0 "register_operand" "") 2545 (float:XF (match_operand:SI 1 "nonimmediate_operand" "")))] 2546 "TARGET_80387" 2547 "") 2548 2549(define_expand "floatdixf2" 2550 [(set (match_operand:XF 0 "register_operand" "") 2551 (float:XF (match_operand:DI 1 "nonimmediate_operand" "")))] |
2274 "TARGET_80387" | 2552 "TARGET_80387 && LONG_DOUBLE_TYPE_SIZE == 96" |
2275 "") 2276 2277;; This will convert from SImode or DImode to MODE_FLOAT. 2278 2279(define_insn "" 2280 [(set (match_operand:XF 0 "register_operand" "=f") | 2553 "") 2554 2555;; This will convert from SImode or DImode to MODE_FLOAT. 2556 2557(define_insn "" 2558 [(set (match_operand:XF 0 "register_operand" "=f") |
2281 (float:XF (match_operand:DI 1 "general_operand" "rm")))] | 2559 (float:XF (match_operand:DI 1 "nonimmediate_operand" "rm")))] |
2282 "TARGET_80387" 2283 "* 2284{ 2285 if (NON_STACK_REG_P (operands[1])) 2286 { 2287 output_op_from_reg (operands[1], AS1 (fild%z0,%1)); 2288 RET; 2289 } --- 51 unchanged lines hidden (view full) --- 2341 else if (GET_CODE (operands[1]) == MEM) 2342 return AS1 (fild%z1,%1); 2343 else 2344 abort (); 2345}") 2346 2347(define_insn "" 2348 [(set (match_operand:XF 0 "register_operand" "=f,f") | 2560 "TARGET_80387" 2561 "* 2562{ 2563 if (NON_STACK_REG_P (operands[1])) 2564 { 2565 output_op_from_reg (operands[1], AS1 (fild%z0,%1)); 2566 RET; 2567 } --- 51 unchanged lines hidden (view full) --- 2619 else if (GET_CODE (operands[1]) == MEM) 2620 return AS1 (fild%z1,%1); 2621 else 2622 abort (); 2623}") 2624 2625(define_insn "" 2626 [(set (match_operand:XF 0 "register_operand" "=f,f") |
2349 (float:XF (match_operand:SI 1 "general_operand" "m,!*r")))] | 2627 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,!*r")))] |
2350 "TARGET_80387" 2351 "* 2352{ 2353 if (NON_STACK_REG_P (operands[1])) 2354 { 2355 output_op_from_reg (operands[1], AS1 (fild%z0,%1)); 2356 RET; 2357 } --- 17 unchanged lines hidden (view full) --- 2375 else if (GET_CODE (operands[1]) == MEM) 2376 return AS1 (fild%z1,%1); 2377 else 2378 abort (); 2379}") 2380 2381;;- add instructions 2382 | 2628 "TARGET_80387" 2629 "* 2630{ 2631 if (NON_STACK_REG_P (operands[1])) 2632 { 2633 output_op_from_reg (operands[1], AS1 (fild%z0,%1)); 2634 RET; 2635 } --- 17 unchanged lines hidden (view full) --- 2653 else if (GET_CODE (operands[1]) == MEM) 2654 return AS1 (fild%z1,%1); 2655 else 2656 abort (); 2657}") 2658 2659;;- add instructions 2660 |
2661(define_insn "addsidi3_1" 2662 [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r,o,!&r,!r,o,!o") 2663 (plus:DI (match_operand:DI 1 "general_operand" "0,0,0,o,riF,riF,o") 2664 (zero_extend:DI (match_operand:SI 2 "general_operand" "o,ri,ri,roi,roi,ri,ri")))) 2665 (clobber (match_scratch:SI 3 "=X,X,X,X,X,X,&r"))] 2666 "" 2667 "* 2668{ 2669 rtx low[3], high[3], xops[7], temp; 2670 2671 CC_STATUS_INIT; 2672 2673 split_di (operands, 2, low, high); 2674 high[2] = const0_rtx; 2675 low[2] = operands[2]; 2676 2677 if (!rtx_equal_p (operands[0], operands[1])) 2678 { 2679 xops[0] = high[0]; 2680 xops[1] = low[0]; 2681 xops[2] = high[1]; 2682 xops[3] = low[1]; 2683 2684 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 2685 { 2686 output_asm_insn (AS2 (mov%L1,%3,%1), xops); 2687 output_asm_insn (AS2 (mov%L0,%2,%0), xops); 2688 } 2689 else 2690 { 2691 xops[4] = high[2]; 2692 xops[5] = low[2]; 2693 xops[6] = operands[3]; 2694 output_asm_insn (AS2 (mov%L6,%3,%6), xops); 2695 output_asm_insn (AS2 (add%L6,%5,%6), xops); 2696 output_asm_insn (AS2 (mov%L1,%6,%1), xops); 2697 output_asm_insn (AS2 (mov%L6,%2,%6), xops); 2698 output_asm_insn (AS2 (adc%L6,%4,%6), xops); 2699 output_asm_insn (AS2 (mov%L0,%6,%0), xops); 2700 RET; 2701 } 2702 } 2703 2704 output_asm_insn (AS2 (add%L0,%2,%0), low); 2705 output_asm_insn (AS2 (adc%L0,%2,%0), high); 2706 RET; 2707}") 2708 2709(define_insn "addsidi3_2" 2710 [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r,o,&r,!&r,&r,o,o,!o") 2711 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "o,ri,ri,o,o,ri,ri,i,r")) 2712 (match_operand:DI 1 "general_operand" "0,0,0,iF,ro,roiF,riF,o,o"))) 2713 (clobber (match_scratch:SI 3 "=X,X,X,X,X,X,X,&r,&r"))] 2714 "" 2715 "* 2716{ 2717 rtx low[3], high[3], xops[7], temp; 2718 2719 CC_STATUS_INIT; 2720 2721 split_di (operands, 2, low, high); 2722 high[2] = const0_rtx; 2723 low[2] = operands[2]; 2724 2725 if (!rtx_equal_p (operands[0], operands[1])) 2726 { 2727 xops[0] = high[0]; 2728 xops[1] = low[0]; 2729 xops[2] = high[1]; 2730 xops[3] = low[1]; 2731 2732 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 2733 { 2734 if (rtx_equal_p (low[0], operands[2])) 2735 { 2736 output_asm_insn (AS2 (mov%L0,%2,%0), high); 2737 output_asm_insn (AS2 (add%L0,%1,%0), low); 2738 output_asm_insn (AS2 (adc%L0,%1,%0), high); 2739 RET; 2740 } 2741 if (rtx_equal_p (high[0], operands[2])) 2742 { 2743 if (GET_CODE (operands[0]) != MEM) 2744 { 2745 output_asm_insn (AS2 (mov%L0,%2,%0), low); 2746 output_asm_insn (AS2 (mov%L0,%2,%0), high); 2747 output_asm_insn (AS2 (add%L0,%1,%0), low); 2748 output_asm_insn (AS2 (adc%L0,%1,%0), high); 2749 } 2750 else 2751 { 2752 /* It's too late to ask for a scratch now - but this 2753 will probably not happen too often. */ 2754 output_asm_insn (AS2 (add%L1,%2,%1), low); 2755 output_asm_insn (AS2 (mov%L0,%1,%0), low); 2756 output_asm_insn (AS2 (mov%L1,%2,%1), low); 2757 output_asm_insn (AS2 (mov%L0,%2,%0), high); 2758 output_asm_insn (AS2 (adc%L0,%1,%0), high); 2759 output_asm_insn (AS2 (sub%L1,%0,%1), low); 2760 output_asm_insn (AS1 (neg%L1,%1), low); 2761 } 2762 RET; 2763 } 2764 output_asm_insn (AS2 (mov%L1,%3,%1), xops); 2765 output_asm_insn (AS2 (mov%L0,%2,%0), xops); 2766 } 2767 else 2768 { 2769 xops[4] = high[2]; 2770 xops[5] = low[2]; 2771 xops[6] = operands[3]; 2772 output_asm_insn (AS2 (mov%L6,%3,%6), xops); 2773 output_asm_insn (AS2 (add%L6,%5,%6), xops); 2774 output_asm_insn (AS2 (mov%L1,%6,%1), xops); 2775 output_asm_insn (AS2 (mov%L6,%2,%6), xops); 2776 output_asm_insn (AS2 (adc%L6,%4,%6), xops); 2777 output_asm_insn (AS2 (mov%L0,%6,%0), xops); 2778 RET; 2779 } 2780 } 2781 2782 output_asm_insn (AS2 (add%L0,%2,%0), low); 2783 output_asm_insn (AS2 (adc%L0,%2,%0), high); 2784 RET; 2785}") 2786 |
|
2383(define_insn "adddi3" | 2787(define_insn "adddi3" |
2384 [(set (match_operand:DI 0 "general_operand" "=&r,ro,o,&r,ro,o,&r,o,o,o") 2385 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,o,riF,o,or,riF,riF,o") 2386 (match_operand:DI 2 "general_operand" "o,riF,o,0,0,0,oriF,riF,o,o"))) 2387 (clobber (match_scratch:SI 3 "=X,X,&r,X,&r,&r,X,&r,&r,&r"))] | 2788 [(set (match_operand:DI 0 "general_operand" "=&r,&ro,!r,o,!&r,!o,!o") 2789 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0iF,or,riF,o") 2790 (match_operand:DI 2 "general_operand" "o,riF,0,or,or,oriF,o"))) 2791 (clobber (match_scratch:SI 3 "=X,X,X,&r,X,&r,&r"))] |
2388 "" 2389 "* 2390{ 2391 rtx low[3], high[3], xops[7], temp; 2392 2393 CC_STATUS_INIT; 2394 2395 if (rtx_equal_p (operands[0], operands[2])) --- 55 unchanged lines hidden (view full) --- 2451 output_asm_insn (AS2 (add%L0,%2,%0), high); 2452 2453 RET; 2454}") 2455 2456;; On a 486, it is faster to do movl/addl than to do a single leal if 2457;; operands[1] and operands[2] are both registers. 2458 | 2792 "" 2793 "* 2794{ 2795 rtx low[3], high[3], xops[7], temp; 2796 2797 CC_STATUS_INIT; 2798 2799 if (rtx_equal_p (operands[0], operands[2])) --- 55 unchanged lines hidden (view full) --- 2855 output_asm_insn (AS2 (add%L0,%2,%0), high); 2856 2857 RET; 2858}") 2859 2860;; On a 486, it is faster to do movl/addl than to do a single leal if 2861;; operands[1] and operands[2] are both registers. 2862 |
2459(define_insn "addsi3" 2460 [(set (match_operand:SI 0 "general_operand" "=?r,rm,r") 2461 (plus:SI (match_operand:SI 1 "general_operand" "%r,0,0") 2462 (match_operand:SI 2 "general_operand" "ri,ri,rm")))] | 2863(define_expand "addsi3" 2864 [(set (match_operand:SI 0 "nonimmediate_operand" "") 2865 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") 2866 (match_operand:SI 2 "general_operand" "")))] |
2463 "" | 2867 "" |
2868 "IX86_EXPAND_BINARY_OPERATOR (PLUS, SImode, operands);") 2869 2870(define_insn "" 2871 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r") 2872 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r") 2873 (match_operand:SI 2 "general_operand" "rmi,ri,ri")))] 2874 "ix86_binary_operator_ok (PLUS, SImode, operands)" |
|
2464 "* 2465{ | 2875 "* 2876{ |
2466 if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1])) | 2877 if (REG_P (operands[0]) && REG_P (operands[1]) 2878 && (REG_P (operands[2]) || GET_CODE (operands[2]) == CONST_INT) 2879 && REGNO (operands[0]) != REGNO (operands[1])) |
2467 { 2468 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) 2469 return AS2 (add%L0,%1,%0); 2470 2471 if (operands[2] == stack_pointer_rtx) 2472 { 2473 rtx temp; 2474 2475 temp = operands[1]; 2476 operands[1] = operands[2]; 2477 operands[2] = temp; 2478 } 2479 2480 if (operands[2] != stack_pointer_rtx) 2481 { 2482 CC_STATUS_INIT; 2483 operands[1] = SET_SRC (PATTERN (insn)); 2484 return AS2 (lea%L0,%a1,%0); 2485 } | 2880 { 2881 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) 2882 return AS2 (add%L0,%1,%0); 2883 2884 if (operands[2] == stack_pointer_rtx) 2885 { 2886 rtx temp; 2887 2888 temp = operands[1]; 2889 operands[1] = operands[2]; 2890 operands[2] = temp; 2891 } 2892 2893 if (operands[2] != stack_pointer_rtx) 2894 { 2895 CC_STATUS_INIT; 2896 operands[1] = SET_SRC (PATTERN (insn)); 2897 return AS2 (lea%L0,%a1,%0); 2898 } |
2486 2487 output_asm_insn (AS2 (mov%L0,%1,%0), operands); | |
2488 } 2489 | 2899 } 2900 |
2901 if (!rtx_equal_p (operands[0], operands[1])) 2902 output_asm_insn (AS2 (mov%L0,%1,%0), operands); 2903 |
|
2490 if (operands[2] == const1_rtx) 2491 return AS1 (inc%L0,%0); 2492 2493 if (operands[2] == constm1_rtx) 2494 return AS1 (dec%L0,%0); 2495 | 2904 if (operands[2] == const1_rtx) 2905 return AS1 (inc%L0,%0); 2906 2907 if (operands[2] == constm1_rtx) 2908 return AS1 (dec%L0,%0); 2909 |
2910 /* subl $-128,%ebx is smaller than addl $128,%ebx. */ 2911 if (GET_CODE (operands[2]) == CONST_INT 2912 && INTVAL (operands[2]) == 128) 2913 { 2914 /* This doesn't compute the carry bit in the same way 2915 * as add%L0, but we use inc and dec above and they 2916 * don't set the carry bit at all. If inc/dec don't need 2917 * a CC_STATUS_INIT, this doesn't either... */ 2918 operands[2] = GEN_INT (-128); 2919 return AS2 (sub%L0,%2,%0); 2920 } 2921 |
|
2496 return AS2 (add%L0,%2,%0); 2497}") 2498 | 2922 return AS2 (add%L0,%2,%0); 2923}") 2924 |
2925;; addsi3 is faster, so put this after. 2926 2927(define_insn "movsi_lea" 2928 [(set (match_operand:SI 0 "register_operand" "=r") 2929 (match_operand:QI 1 "address_operand" "p"))] 2930 "" 2931 "* 2932{ 2933 /* Adding a constant to a register is faster with an add. */ 2934 /* ??? can this ever happen? */ 2935 if (GET_CODE (operands[1]) == PLUS 2936 && GET_CODE (XEXP (operands[1], 1)) == CONST_INT 2937 && rtx_equal_p (operands[0], XEXP (operands[1], 0))) 2938 { 2939 operands[1] = XEXP (operands[1], 1); 2940 2941 if (operands[1] == const1_rtx) 2942 return AS1 (inc%L0,%0); 2943 2944 if (operands[1] == constm1_rtx) 2945 return AS1 (dec%L0,%0); 2946 2947 return AS2 (add%L0,%1,%0); 2948 } 2949 2950 CC_STATUS_INIT; 2951 return AS2 (lea%L0,%a1,%0); 2952}") 2953 |
|
2499;; ??? `lea' here, for three operand add? If leaw is used, only %bx, 2500;; %si and %di can appear in SET_SRC, and output_asm_insn might not be 2501;; able to handle the operand. But leal always works? 2502 | 2954;; ??? `lea' here, for three operand add? If leaw is used, only %bx, 2955;; %si and %di can appear in SET_SRC, and output_asm_insn might not be 2956;; able to handle the operand. But leal always works? 2957 |
2503(define_insn "addhi3" 2504 [(set (match_operand:HI 0 "general_operand" "=rm,r") 2505 (plus:HI (match_operand:HI 1 "general_operand" "%0,0") 2506 (match_operand:HI 2 "general_operand" "ri,rm")))] | 2958(define_expand "addhi3" 2959 [(set (match_operand:HI 0 "general_operand" "") 2960 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "") 2961 (match_operand:HI 2 "general_operand" "")))] |
2507 "" | 2962 "" |
2963 "IX86_EXPAND_BINARY_OPERATOR (PLUS, HImode, operands);") 2964 2965(define_insn "" 2966 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") 2967 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") 2968 (match_operand:HI 2 "general_operand" "ri,rm")))] 2969 "ix86_binary_operator_ok (PLUS, HImode, operands)" |
|
2508 "* 2509{ 2510 /* ??? what about offsettable memory references? */ | 2970 "* 2971{ 2972 /* ??? what about offsettable memory references? */ |
2511 if (QI_REG_P (operands[0]) | 2973 if (!TARGET_PENTIUMPRO /* partial stalls are just too painful to risk. */ 2974 && QI_REG_P (operands[0]) |
2512 && GET_CODE (operands[2]) == CONST_INT | 2975 && GET_CODE (operands[2]) == CONST_INT |
2513 && (INTVAL (operands[2]) & 0xff) == 0) | 2976 && (INTVAL (operands[2]) & 0xff) == 0 2977 && i386_cc_probably_useless_p (insn)) |
2514 { 2515 int byteval = (INTVAL (operands[2]) >> 8) & 0xff; 2516 CC_STATUS_INIT; 2517 2518 if (byteval == 1) 2519 return AS1 (inc%B0,%h0); 2520 else if (byteval == 255) 2521 return AS1 (dec%B0,%h0); 2522 2523 operands[2] = GEN_INT (byteval); 2524 return AS2 (add%B0,%2,%h0); 2525 } 2526 | 2978 { 2979 int byteval = (INTVAL (operands[2]) >> 8) & 0xff; 2980 CC_STATUS_INIT; 2981 2982 if (byteval == 1) 2983 return AS1 (inc%B0,%h0); 2984 else if (byteval == 255) 2985 return AS1 (dec%B0,%h0); 2986 2987 operands[2] = GEN_INT (byteval); 2988 return AS2 (add%B0,%2,%h0); 2989 } 2990 |
2991 /* Use a 32-bit operation when possible, to avoid the prefix penalty. */ 2992 if (REG_P (operands[0]) 2993 && i386_aligned_p (operands[2]) 2994 && i386_cc_probably_useless_p (insn)) 2995 { 2996 CC_STATUS_INIT; 2997 2998 if (GET_CODE (operands[2]) == CONST_INT) 2999 { 3000 HOST_WIDE_INT intval = 0xffff & INTVAL (operands[2]); 3001 3002 if (intval == 1) 3003 return AS1 (inc%L0,%k0); 3004 3005 if (intval == 0xffff) 3006 return AS1 (dec%L0,%k0); 3007 3008 operands[2] = i386_sext16_if_const (operands[2]); 3009 } 3010 return AS2 (add%L0,%k2,%k0); 3011 } 3012 |
|
2527 if (operands[2] == const1_rtx) 2528 return AS1 (inc%W0,%0); 2529 2530 if (operands[2] == constm1_rtx 2531 || (GET_CODE (operands[2]) == CONST_INT 2532 && INTVAL (operands[2]) == 65535)) 2533 return AS1 (dec%W0,%0); 2534 2535 return AS2 (add%W0,%2,%0); 2536}") 2537 | 3013 if (operands[2] == const1_rtx) 3014 return AS1 (inc%W0,%0); 3015 3016 if (operands[2] == constm1_rtx 3017 || (GET_CODE (operands[2]) == CONST_INT 3018 && INTVAL (operands[2]) == 65535)) 3019 return AS1 (dec%W0,%0); 3020 3021 return AS2 (add%W0,%2,%0); 3022}") 3023 |
2538(define_insn "addqi3" 2539 [(set (match_operand:QI 0 "general_operand" "=qm,q") 2540 (plus:QI (match_operand:QI 1 "general_operand" "%0,0") 2541 (match_operand:QI 2 "general_operand" "qn,qmn")))] | 3024(define_expand "addqi3" 3025 [(set (match_operand:QI 0 "general_operand" "") 3026 (plus:QI (match_operand:QI 1 "general_operand" "") 3027 (match_operand:QI 2 "general_operand" "")))] |
2542 "" | 3028 "" |
3029 "IX86_EXPAND_BINARY_OPERATOR (PLUS, QImode, operands);") 3030 3031(define_insn "" 3032 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q") 3033 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") 3034 (match_operand:QI 2 "general_operand" "qn,qmn")))] 3035 "ix86_binary_operator_ok (PLUS, QImode, operands)" |
|
2543 "* 2544{ 2545 if (operands[2] == const1_rtx) 2546 return AS1 (inc%B0,%0); 2547 2548 if (operands[2] == constm1_rtx 2549 || (GET_CODE (operands[2]) == CONST_INT 2550 && INTVAL (operands[2]) == 255)) --- 7 unchanged lines hidden (view full) --- 2558; pushl %ebp 2559; addl $-80,(%esp) 2560;instead of 2561; leal -80(%ebp),%eax 2562; pushl %eax 2563; 2564;(define_insn "" 2565; [(set (match_operand:SI 0 "push_operand" "=<") | 3036 "* 3037{ 3038 if (operands[2] == const1_rtx) 3039 return AS1 (inc%B0,%0); 3040 3041 if (operands[2] == constm1_rtx 3042 || (GET_CODE (operands[2]) == CONST_INT 3043 && INTVAL (operands[2]) == 255)) --- 7 unchanged lines hidden (view full) --- 3051; pushl %ebp 3052; addl $-80,(%esp) 3053;instead of 3054; leal -80(%ebp),%eax 3055; pushl %eax 3056; 3057;(define_insn "" 3058; [(set (match_operand:SI 0 "push_operand" "=<") |
2566; (plus:SI (match_operand:SI 1 "general_operand" "%r") 2567; (match_operand:SI 2 "general_operand" "ri")))] | 3059; (plus:SI (match_operand:SI 1 "register_operand" "%r") 3060; (match_operand:SI 2 "nonmemory_operand" "ri")))] |
2568; "" 2569; "* 2570;{ 2571; rtx xops[4]; 2572; xops[0] = operands[0]; 2573; xops[1] = operands[1]; 2574; xops[2] = operands[2]; | 3061; "" 3062; "* 3063;{ 3064; rtx xops[4]; 3065; xops[0] = operands[0]; 3066; xops[1] = operands[1]; 3067; xops[2] = operands[2]; |
2575; xops[3] = gen_rtx (MEM, SImode, stack_pointer_rtx); | 3068; xops[3] = gen_rtx_MEM (SImode, stack_pointer_rtx); |
2576; output_asm_insn (\"push%z1 %1\", xops); 2577; output_asm_insn (AS2 (add%z3,%2,%3), xops); 2578; RET; 2579;}") 2580 | 3069; output_asm_insn (\"push%z1 %1\", xops); 3070; output_asm_insn (AS2 (add%z3,%2,%3), xops); 3071; RET; 3072;}") 3073 |
2581;; addsi3 is faster, so put this after. 2582 2583(define_insn "movsi_lea" 2584 [(set (match_operand:SI 0 "register_operand" "=r") 2585 (match_operand:QI 1 "address_operand" "p"))] 2586 "" 2587 "* 2588{ 2589 CC_STATUS_INIT; 2590 /* Adding a constant to a register is faster with an add. */ 2591 /* ??? can this ever happen? */ 2592 if (GET_CODE (operands[1]) == PLUS 2593 && GET_CODE (XEXP (operands[1], 1)) == CONST_INT 2594 && rtx_equal_p (operands[0], XEXP (operands[1], 0))) 2595 { 2596 operands[1] = XEXP (operands[1], 1); 2597 2598 if (operands[1] == const1_rtx) 2599 return AS1 (inc%L0,%0); 2600 2601 if (operands[1] == constm1_rtx) 2602 return AS1 (dec%L0,%0); 2603 2604 return AS2 (add%L0,%1,%0); 2605 } 2606 return AS2 (lea%L0,%a1,%0); 2607}") 2608 | |
2609;; The patterns that match these are at the end of this file. 2610 2611(define_expand "addxf3" 2612 [(set (match_operand:XF 0 "register_operand" "") | 3074;; The patterns that match these are at the end of this file. 3075 3076(define_expand "addxf3" 3077 [(set (match_operand:XF 0 "register_operand" "") |
2613 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "") 2614 (match_operand:XF 2 "nonimmediate_operand" "")))] | 3078 (plus:XF (match_operand:XF 1 "register_operand" "") 3079 (match_operand:XF 2 "register_operand" "")))] |
2615 "TARGET_80387" 2616 "") 2617 2618(define_expand "adddf3" 2619 [(set (match_operand:DF 0 "register_operand" "") 2620 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "") 2621 (match_operand:DF 2 "nonimmediate_operand" "")))] 2622 "TARGET_80387" 2623 "") 2624 2625(define_expand "addsf3" 2626 [(set (match_operand:SF 0 "register_operand" "") 2627 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "") 2628 (match_operand:SF 2 "nonimmediate_operand" "")))] 2629 "TARGET_80387" 2630 "") 2631 2632;;- subtract instructions 2633 | 3080 "TARGET_80387" 3081 "") 3082 3083(define_expand "adddf3" 3084 [(set (match_operand:DF 0 "register_operand" "") 3085 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "") 3086 (match_operand:DF 2 "nonimmediate_operand" "")))] 3087 "TARGET_80387" 3088 "") 3089 3090(define_expand "addsf3" 3091 [(set (match_operand:SF 0 "register_operand" "") 3092 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "") 3093 (match_operand:SF 2 "nonimmediate_operand" "")))] 3094 "TARGET_80387" 3095 "") 3096 3097;;- subtract instructions 3098 |
3099(define_insn "subsidi3" 3100 [(set (match_operand:DI 0 "general_operand" "=&r,&ro,&r,!&r,o,o,!o") 3101 (minus:DI (match_operand:DI 1 "general_operand" "0iF,0,roiF,roiF,riF,o,o") 3102 (zero_extend:DI (match_operand:SI 2 "general_operand" "o,ri,ri,o,ri,i,r")))) 3103 (clobber (match_scratch:SI 3 "=X,X,X,X,X,&r,&r"))] 3104 "" 3105 "* 3106{ 3107 rtx low[3], high[3], xops[7]; 3108 3109 CC_STATUS_INIT; 3110 3111 split_di (operands, 2, low, high); 3112 high[2] = const0_rtx; 3113 low[2] = operands[2]; 3114 3115 if (!rtx_equal_p (operands[0], operands[1])) 3116 { 3117 xops[0] = high[0]; 3118 xops[1] = low[0]; 3119 xops[2] = high[1]; 3120 xops[3] = low[1]; 3121 3122 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 3123 { 3124 output_asm_insn (AS2 (mov%L1,%3,%1), xops); 3125 output_asm_insn (AS2 (mov%L0,%2,%0), xops); 3126 } 3127 else 3128 { 3129 xops[4] = high[2]; 3130 xops[5] = low[2]; 3131 xops[6] = operands[3]; 3132 output_asm_insn (AS2 (mov%L6,%3,%6), xops); 3133 output_asm_insn (AS2 (sub%L6,%5,%6), xops); 3134 output_asm_insn (AS2 (mov%L1,%6,%1), xops); 3135 output_asm_insn (AS2 (mov%L6,%2,%6), xops); 3136 output_asm_insn (AS2 (sbb%L6,%4,%6), xops); 3137 output_asm_insn (AS2 (mov%L0,%6,%0), xops); 3138 RET; 3139 } 3140 } 3141 3142 output_asm_insn (AS2 (sub%L0,%2,%0), low); 3143 output_asm_insn (AS2 (sbb%L0,%2,%0), high); 3144 RET; 3145}") 3146 |
|
2634(define_insn "subdi3" | 3147(define_insn "subdi3" |
2635 [(set (match_operand:DI 0 "general_operand" "=&r,ro,&r,o,o") 2636 (minus:DI (match_operand:DI 1 "general_operand" "0,0,roiF,riF,o") 2637 (match_operand:DI 2 "general_operand" "o,riF,roiF,riF,o"))) 2638 (clobber (match_scratch:SI 3 "=X,X,X,&r,&r"))] | 3148 [(set (match_operand:DI 0 "general_operand" "=&r,&ro,o,o,!&r,!o") 3149 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0iF,or,roiF,roiF") 3150 (match_operand:DI 2 "general_operand" "or,riF,or,iF,roiF,roiF"))) 3151 (clobber (match_scratch:SI 3 "=X,X,&r,&r,X,&r"))] |
2639 "" 2640 "* 2641{ 2642 rtx low[3], high[3], xops[7]; 2643 2644 CC_STATUS_INIT; 2645 2646 split_di (operands, 3, low, high); --- 46 unchanged lines hidden (view full) --- 2693 } 2694 2695 else 2696 output_asm_insn (AS2 (sub%L0,%2,%0), high); 2697 2698 RET; 2699}") 2700 | 3152 "" 3153 "* 3154{ 3155 rtx low[3], high[3], xops[7]; 3156 3157 CC_STATUS_INIT; 3158 3159 split_di (operands, 3, low, high); --- 46 unchanged lines hidden (view full) --- 3206 } 3207 3208 else 3209 output_asm_insn (AS2 (sub%L0,%2,%0), high); 3210 3211 RET; 3212}") 3213 |
2701(define_insn "subsi3" 2702 [(set (match_operand:SI 0 "general_operand" "=rm,r") 2703 (minus:SI (match_operand:SI 1 "general_operand" "0,0") 2704 (match_operand:SI 2 "general_operand" "ri,rm")))] | 3214(define_expand "subsi3" 3215 [(set (match_operand:SI 0 "nonimmediate_operand" "") 3216 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "") 3217 (match_operand:SI 2 "general_operand" "")))] |
2705 "" | 3218 "" |
3219 "IX86_EXPAND_BINARY_OPERATOR (MINUS, SImode, operands);") 3220 3221(define_insn "" 3222 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") 3223 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") 3224 (match_operand:SI 2 "general_operand" "ri,rm")))] 3225 "ix86_binary_operator_ok (MINUS, SImode, operands)" |
|
2706 "* return AS2 (sub%L0,%2,%0);") 2707 | 3226 "* return AS2 (sub%L0,%2,%0);") 3227 |
2708(define_insn "subhi3" 2709 [(set (match_operand:HI 0 "general_operand" "=rm,r") 2710 (minus:HI (match_operand:HI 1 "general_operand" "0,0") | 3228(define_expand "subhi3" 3229 [(set (match_operand:HI 0 "general_operand" "") 3230 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "") 3231 (match_operand:HI 2 "general_operand" "")))] 3232 "" 3233 "IX86_EXPAND_BINARY_OPERATOR (MINUS, HImode, operands);") 3234 3235(define_insn "" 3236 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") 3237 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") |
2711 (match_operand:HI 2 "general_operand" "ri,rm")))] | 3238 (match_operand:HI 2 "general_operand" "ri,rm")))] |
3239 "ix86_binary_operator_ok (MINUS, HImode, operands)" 3240 "* 3241{ 3242 if (REG_P (operands[0]) 3243 && i386_aligned_p (operands[2]) 3244 && i386_cc_probably_useless_p (insn)) 3245 { 3246 CC_STATUS_INIT; 3247 operands[2] = i386_sext16_if_const (operands[2]); 3248 return AS2 (sub%L0,%k2,%k0); 3249 } 3250 return AS2 (sub%W0,%2,%0); 3251}") 3252 3253(define_expand "subqi3" 3254 [(set (match_operand:QI 0 "general_operand" "") 3255 (minus:QI (match_operand:QI 1 "general_operand" "") 3256 (match_operand:QI 2 "general_operand" "")))] |
|
2712 "" | 3257 "" |
2713 "* return AS2 (sub%W0,%2,%0);") | 3258 "IX86_EXPAND_BINARY_OPERATOR (MINUS, QImode, operands);") |
2714 | 3259 |
2715(define_insn "subqi3" 2716 [(set (match_operand:QI 0 "general_operand" "=qm,q") 2717 (minus:QI (match_operand:QI 1 "general_operand" "0,0") | 3260(define_insn "" 3261 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q") 3262 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") |
2718 (match_operand:QI 2 "general_operand" "qn,qmn")))] | 3263 (match_operand:QI 2 "general_operand" "qn,qmn")))] |
2719 "" | 3264 "ix86_binary_operator_ok (MINUS, QImode, operands)" |
2720 "* return AS2 (sub%B0,%2,%0);") 2721 2722;; The patterns that match these are at the end of this file. 2723 2724(define_expand "subxf3" 2725 [(set (match_operand:XF 0 "register_operand" "") | 3265 "* return AS2 (sub%B0,%2,%0);") 3266 3267;; The patterns that match these are at the end of this file. 3268 3269(define_expand "subxf3" 3270 [(set (match_operand:XF 0 "register_operand" "") |
2726 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "") 2727 (match_operand:XF 2 "nonimmediate_operand" "")))] | 3271 (minus:XF (match_operand:XF 1 "register_operand" "") 3272 (match_operand:XF 2 "register_operand" "")))] |
2728 "TARGET_80387" 2729 "") 2730 2731(define_expand "subdf3" 2732 [(set (match_operand:DF 0 "register_operand" "") 2733 (minus:DF (match_operand:DF 1 "nonimmediate_operand" "") 2734 (match_operand:DF 2 "nonimmediate_operand" "")))] 2735 "TARGET_80387" --- 4 unchanged lines hidden (view full) --- 2740 (minus:SF (match_operand:SF 1 "nonimmediate_operand" "") 2741 (match_operand:SF 2 "nonimmediate_operand" "")))] 2742 "TARGET_80387" 2743 "") 2744 2745;;- multiply instructions 2746 2747;(define_insn "mulqi3" | 3273 "TARGET_80387" 3274 "") 3275 3276(define_expand "subdf3" 3277 [(set (match_operand:DF 0 "register_operand" "") 3278 (minus:DF (match_operand:DF 1 "nonimmediate_operand" "") 3279 (match_operand:DF 2 "nonimmediate_operand" "")))] 3280 "TARGET_80387" --- 4 unchanged lines hidden (view full) --- 3285 (minus:SF (match_operand:SF 1 "nonimmediate_operand" "") 3286 (match_operand:SF 2 "nonimmediate_operand" "")))] 3287 "TARGET_80387" 3288 "") 3289 3290;;- multiply instructions 3291 3292;(define_insn "mulqi3" |
2748; [(set (match_operand:QI 0 "general_operand" "=a") 2749; (mult:QI (match_operand:QI 1 "general_operand" "%0") 2750; (match_operand:QI 2 "general_operand" "qm")))] | 3293; [(set (match_operand:QI 0 "register_operand" "=a") 3294; (mult:QI (match_operand:QI 1 "register_operand" "%0") 3295; (match_operand:QI 2 "nonimmediate_operand" "qm")))] |
2751; "" 2752; "imul%B0 %2,%0") 2753 | 3296; "" 3297; "imul%B0 %2,%0") 3298 |
2754(define_insn "" 2755 [(set (match_operand:HI 0 "general_operand" "=r") 2756 (mult:HI (match_operand:HI 1 "general_operand" "%0") 2757 (match_operand:HI 2 "general_operand" "r")))] 2758 "GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x80" 2759 "* return AS2 (imul%W0,%2,%0);") 2760 | |
2761(define_insn "mulhi3" | 3299(define_insn "mulhi3" |
2762 [(set (match_operand:HI 0 "general_operand" "=r,r") 2763 (mult:HI (match_operand:HI 1 "general_operand" "%0,rm") | 3300 [(set (match_operand:HI 0 "register_operand" "=r,r") 3301 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%0,rm") |
2764 (match_operand:HI 2 "general_operand" "g,i")))] 2765 "" 2766 "* 2767{ 2768 if (GET_CODE (operands[1]) == REG 2769 && REGNO (operands[1]) == REGNO (operands[0]) 2770 && (GET_CODE (operands[2]) == MEM || GET_CODE (operands[2]) == REG)) 2771 /* Assembler has weird restrictions. */ 2772 return AS2 (imul%W0,%2,%0); 2773 return AS3 (imul%W0,%2,%1,%0); | 3302 (match_operand:HI 2 "general_operand" "g,i")))] 3303 "" 3304 "* 3305{ 3306 if (GET_CODE (operands[1]) == REG 3307 && REGNO (operands[1]) == REGNO (operands[0]) 3308 && (GET_CODE (operands[2]) == MEM || GET_CODE (operands[2]) == REG)) 3309 /* Assembler has weird restrictions. */ 3310 return AS2 (imul%W0,%2,%0); 3311 return AS3 (imul%W0,%2,%1,%0); |
2774}") | 3312}" 3313 [(set_attr "type" "imul")]) |
2775 | 3314 |
2776(define_insn "" 2777 [(set (match_operand:SI 0 "general_operand" "=r") 2778 (mult:SI (match_operand:SI 1 "general_operand" "%0") 2779 (match_operand:SI 2 "general_operand" "r")))] 2780 "GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x80" 2781 "* return AS2 (imul%L0,%2,%0);") 2782 | |
2783(define_insn "mulsi3" | 3315(define_insn "mulsi3" |
2784 [(set (match_operand:SI 0 "general_operand" "=r,r") 2785 (mult:SI (match_operand:SI 1 "general_operand" "%0,rm") | 3316 [(set (match_operand:SI 0 "register_operand" "=r,r") 3317 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,rm") |
2786 (match_operand:SI 2 "general_operand" "g,i")))] 2787 "" 2788 "* 2789{ 2790 if (GET_CODE (operands[1]) == REG 2791 && REGNO (operands[1]) == REGNO (operands[0]) 2792 && (GET_CODE (operands[2]) == MEM || GET_CODE (operands[2]) == REG)) 2793 /* Assembler has weird restrictions. */ 2794 return AS2 (imul%L0,%2,%0); 2795 return AS3 (imul%L0,%2,%1,%0); | 3318 (match_operand:SI 2 "general_operand" "g,i")))] 3319 "" 3320 "* 3321{ 3322 if (GET_CODE (operands[1]) == REG 3323 && REGNO (operands[1]) == REGNO (operands[0]) 3324 && (GET_CODE (operands[2]) == MEM || GET_CODE (operands[2]) == REG)) 3325 /* Assembler has weird restrictions. */ 3326 return AS2 (imul%L0,%2,%0); 3327 return AS3 (imul%L0,%2,%1,%0); |
2796}") | 3328}" 3329 [(set_attr "type" "imul")]) |
2797 2798(define_insn "umulqihi3" | 3330 3331(define_insn "umulqihi3" |
2799 [(set (match_operand:HI 0 "general_operand" "=a") 2800 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) | 3332 [(set (match_operand:HI 0 "register_operand" "=a") 3333 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0")) |
2801 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))] 2802 "" | 3334 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))] 3335 "" |
2803 "mul%B0 %2") | 3336 "mul%B0 %2" 3337 [(set_attr "type" "imul")]) |
2804 2805(define_insn "mulqihi3" | 3338 3339(define_insn "mulqihi3" |
2806 [(set (match_operand:HI 0 "general_operand" "=a") 2807 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) | 3340 [(set (match_operand:HI 0 "register_operand" "=a") 3341 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0")) |
2808 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))] 2809 "" | 3342 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))] 3343 "" |
2810 "imul%B0 %2") | 3344 "imul%B0 %2" 3345 [(set_attr "type" "imul")]) |
2811 2812(define_insn "umulsidi3" 2813 [(set (match_operand:DI 0 "register_operand" "=A") 2814 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) 2815 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))] 2816 "TARGET_WIDE_MULTIPLY" | 3346 3347(define_insn "umulsidi3" 3348 [(set (match_operand:DI 0 "register_operand" "=A") 3349 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) 3350 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))] 3351 "TARGET_WIDE_MULTIPLY" |
2817 "mul%L0 %2") | 3352 "mul%L0 %2" 3353 [(set_attr "type" "imul")]) |
2818 2819(define_insn "mulsidi3" 2820 [(set (match_operand:DI 0 "register_operand" "=A") 2821 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0")) 2822 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))] 2823 "TARGET_WIDE_MULTIPLY" | 3354 3355(define_insn "mulsidi3" 3356 [(set (match_operand:DI 0 "register_operand" "=A") 3357 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0")) 3358 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))] 3359 "TARGET_WIDE_MULTIPLY" |
2824 "imul%L0 %2") | 3360 "imul%L0 %2" 3361 [(set_attr "type" "imul")]) |
2825 2826(define_insn "umulsi3_highpart" 2827 [(set (match_operand:SI 0 "register_operand" "=d") 2828 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%a")) 2829 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) 2830 (const_int 32)))) 2831 (clobber (match_scratch:SI 3 "=a"))] 2832 "TARGET_WIDE_MULTIPLY" | 3362 3363(define_insn "umulsi3_highpart" 3364 [(set (match_operand:SI 0 "register_operand" "=d") 3365 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%a")) 3366 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) 3367 (const_int 32)))) 3368 (clobber (match_scratch:SI 3 "=a"))] 3369 "TARGET_WIDE_MULTIPLY" |
2833 "mul%L0 %2") | 3370 "mul%L0 %2" 3371 [(set_attr "type" "imul")]) |
2834 2835(define_insn "smulsi3_highpart" 2836 [(set (match_operand:SI 0 "register_operand" "=d") 2837 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%a")) 2838 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) 2839 (const_int 32)))) 2840 (clobber (match_scratch:SI 3 "=a"))] 2841 "TARGET_WIDE_MULTIPLY" | 3372 3373(define_insn "smulsi3_highpart" 3374 [(set (match_operand:SI 0 "register_operand" "=d") 3375 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%a")) 3376 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) 3377 (const_int 32)))) 3378 (clobber (match_scratch:SI 3 "=a"))] 3379 "TARGET_WIDE_MULTIPLY" |
2842 "imul%L0 %2") | 3380 "imul%L0 %2" 3381 [(set_attr "type" "imul")]) |
2843 2844;; The patterns that match these are at the end of this file. 2845 2846(define_expand "mulxf3" 2847 [(set (match_operand:XF 0 "register_operand" "") | 3382 3383;; The patterns that match these are at the end of this file. 3384 3385(define_expand "mulxf3" 3386 [(set (match_operand:XF 0 "register_operand" "") |
2848 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "") 2849 (match_operand:XF 2 "nonimmediate_operand" "")))] | 3387 (mult:XF (match_operand:XF 1 "register_operand" "") 3388 (match_operand:XF 2 "register_operand" "")))] |
2850 "TARGET_80387" 2851 "") 2852 2853(define_expand "muldf3" 2854 [(set (match_operand:DF 0 "register_operand" "") | 3389 "TARGET_80387" 3390 "") 3391 3392(define_expand "muldf3" 3393 [(set (match_operand:DF 0 "register_operand" "") |
2855 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "") | 3394 (mult:DF (match_operand:DF 1 "register_operand" "") |
2856 (match_operand:DF 2 "nonimmediate_operand" "")))] 2857 "TARGET_80387" 2858 "") 2859 2860(define_expand "mulsf3" 2861 [(set (match_operand:SF 0 "register_operand" "") | 3395 (match_operand:DF 2 "nonimmediate_operand" "")))] 3396 "TARGET_80387" 3397 "") 3398 3399(define_expand "mulsf3" 3400 [(set (match_operand:SF 0 "register_operand" "") |
2862 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "") | 3401 (mult:SF (match_operand:SF 1 "register_operand" "") |
2863 (match_operand:SF 2 "nonimmediate_operand" "")))] 2864 "TARGET_80387" 2865 "") 2866 2867;;- divide instructions 2868 2869(define_insn "divqi3" | 3402 (match_operand:SF 2 "nonimmediate_operand" "")))] 3403 "TARGET_80387" 3404 "") 3405 3406;;- divide instructions 3407 3408(define_insn "divqi3" |
2870 [(set (match_operand:QI 0 "general_operand" "=a") 2871 (div:QI (match_operand:HI 1 "general_operand" "0") 2872 (match_operand:QI 2 "general_operand" "qm")))] | 3409 [(set (match_operand:QI 0 "register_operand" "=a") 3410 (div:QI (match_operand:HI 1 "register_operand" "0") 3411 (match_operand:QI 2 "nonimmediate_operand" "qm")))] |
2873 "" 2874 "idiv%B0 %2") 2875 2876(define_insn "udivqi3" | 3412 "" 3413 "idiv%B0 %2") 3414 3415(define_insn "udivqi3" |
2877 [(set (match_operand:QI 0 "general_operand" "=a") 2878 (udiv:QI (match_operand:HI 1 "general_operand" "0") 2879 (match_operand:QI 2 "general_operand" "qm")))] | 3416 [(set (match_operand:QI 0 "register_operand" "=a") 3417 (udiv:QI (match_operand:HI 1 "register_operand" "0") 3418 (match_operand:QI 2 "nonimmediate_operand" "qm")))] |
2880 "" | 3419 "" |
2881 "div%B0 %2") | 3420 "div%B0 %2" 3421 [(set_attr "type" "idiv")]) |
2882 2883;; The patterns that match these are at the end of this file. 2884 2885(define_expand "divxf3" 2886 [(set (match_operand:XF 0 "register_operand" "") | 3422 3423;; The patterns that match these are at the end of this file. 3424 3425(define_expand "divxf3" 3426 [(set (match_operand:XF 0 "register_operand" "") |
2887 (div:XF (match_operand:XF 1 "nonimmediate_operand" "") 2888 (match_operand:XF 2 "nonimmediate_operand" "")))] | 3427 (div:XF (match_operand:XF 1 "register_operand" "") 3428 (match_operand:XF 2 "register_operand" "")))] |
2889 "TARGET_80387" 2890 "") 2891 2892(define_expand "divdf3" 2893 [(set (match_operand:DF 0 "register_operand" "") | 3429 "TARGET_80387" 3430 "") 3431 3432(define_expand "divdf3" 3433 [(set (match_operand:DF 0 "register_operand" "") |
2894 (div:DF (match_operand:DF 1 "nonimmediate_operand" "") 2895 (match_operand:DF 2 "nonimmediate_operand" "")))] 2896 "TARGET_80387" 2897 "") 2898 | 3434 (div:DF (match_operand:DF 1 "register_operand" "") 3435 (match_operand:DF 2 "nonimmediate_operand" "")))] 3436 "TARGET_80387" 3437 "") 3438 |
2899(define_expand "divsf3" 2900 [(set (match_operand:SF 0 "register_operand" "") | 3439(define_expand "divsf3" 3440 [(set (match_operand:SF 0 "register_operand" "") |
2901 (div:SF (match_operand:SF 1 "nonimmediate_operand" "") | 3441 (div:SF (match_operand:SF 1 "register_operand" "") |
2902 (match_operand:SF 2 "nonimmediate_operand" "")))] 2903 "TARGET_80387" 2904 "") 2905 2906;; Remainder instructions. 2907 2908(define_insn "divmodsi4" 2909 [(set (match_operand:SI 0 "register_operand" "=a") 2910 (div:SI (match_operand:SI 1 "register_operand" "0") | 3442 (match_operand:SF 2 "nonimmediate_operand" "")))] 3443 "TARGET_80387" 3444 "") 3445 3446;; Remainder instructions. 3447 3448(define_insn "divmodsi4" 3449 [(set (match_operand:SI 0 "register_operand" "=a") 3450 (div:SI (match_operand:SI 1 "register_operand" "0") |
2911 (match_operand:SI 2 "general_operand" "rm"))) | 3451 (match_operand:SI 2 "nonimmediate_operand" "rm"))) |
2912 (set (match_operand:SI 3 "register_operand" "=&d") 2913 (mod:SI (match_dup 1) (match_dup 2)))] 2914 "" 2915 "* 2916{ 2917#ifdef INTEL_SYNTAX 2918 output_asm_insn (\"cdq\", operands); 2919#else 2920 output_asm_insn (\"cltd\", operands); 2921#endif 2922 return AS1 (idiv%L0,%2); | 3452 (set (match_operand:SI 3 "register_operand" "=&d") 3453 (mod:SI (match_dup 1) (match_dup 2)))] 3454 "" 3455 "* 3456{ 3457#ifdef INTEL_SYNTAX 3458 output_asm_insn (\"cdq\", operands); 3459#else 3460 output_asm_insn (\"cltd\", operands); 3461#endif 3462 return AS1 (idiv%L0,%2); |
2923}") | 3463}" 3464 [(set_attr "type" "idiv")]) |
2924 2925(define_insn "divmodhi4" 2926 [(set (match_operand:HI 0 "register_operand" "=a") 2927 (div:HI (match_operand:HI 1 "register_operand" "0") | 3465 3466(define_insn "divmodhi4" 3467 [(set (match_operand:HI 0 "register_operand" "=a") 3468 (div:HI (match_operand:HI 1 "register_operand" "0") |
2928 (match_operand:HI 2 "general_operand" "rm"))) | 3469 (match_operand:HI 2 "nonimmediate_operand" "rm"))) |
2929 (set (match_operand:HI 3 "register_operand" "=&d") 2930 (mod:HI (match_dup 1) (match_dup 2)))] 2931 "" | 3470 (set (match_operand:HI 3 "register_operand" "=&d") 3471 (mod:HI (match_dup 1) (match_dup 2)))] 3472 "" |
2932 "cwtd\;idiv%W0 %2") | 3473 "cwtd\;idiv%W0 %2" 3474 [(set_attr "type" "idiv")]) |
2933 2934;; ??? Can we make gcc zero extend operand[0]? 2935(define_insn "udivmodsi4" 2936 [(set (match_operand:SI 0 "register_operand" "=a") 2937 (udiv:SI (match_operand:SI 1 "register_operand" "0") | 3475 3476;; ??? Can we make gcc zero extend operand[0]? 3477(define_insn "udivmodsi4" 3478 [(set (match_operand:SI 0 "register_operand" "=a") 3479 (udiv:SI (match_operand:SI 1 "register_operand" "0") |
2938 (match_operand:SI 2 "general_operand" "rm"))) | 3480 (match_operand:SI 2 "nonimmediate_operand" "rm"))) |
2939 (set (match_operand:SI 3 "register_operand" "=&d") 2940 (umod:SI (match_dup 1) (match_dup 2)))] 2941 "" 2942 "* 2943{ 2944 output_asm_insn (AS2 (xor%L3,%3,%3), operands); 2945 return AS1 (div%L0,%2); | 3481 (set (match_operand:SI 3 "register_operand" "=&d") 3482 (umod:SI (match_dup 1) (match_dup 2)))] 3483 "" 3484 "* 3485{ 3486 output_asm_insn (AS2 (xor%L3,%3,%3), operands); 3487 return AS1 (div%L0,%2); |
2946}") | 3488}" 3489 [(set_attr "type" "idiv")]) |
2947 2948;; ??? Can we make gcc zero extend operand[0]? 2949(define_insn "udivmodhi4" 2950 [(set (match_operand:HI 0 "register_operand" "=a") 2951 (udiv:HI (match_operand:HI 1 "register_operand" "0") | 3490 3491;; ??? Can we make gcc zero extend operand[0]? 3492(define_insn "udivmodhi4" 3493 [(set (match_operand:HI 0 "register_operand" "=a") 3494 (udiv:HI (match_operand:HI 1 "register_operand" "0") |
2952 (match_operand:HI 2 "general_operand" "rm"))) | 3495 (match_operand:HI 2 "nonimmediate_operand" "rm"))) |
2953 (set (match_operand:HI 3 "register_operand" "=&d") 2954 (umod:HI (match_dup 1) (match_dup 2)))] 2955 "" 2956 "* 2957{ 2958 output_asm_insn (AS2 (xor%W0,%3,%3), operands); 2959 return AS1 (div%W0,%2); | 3496 (set (match_operand:HI 3 "register_operand" "=&d") 3497 (umod:HI (match_dup 1) (match_dup 2)))] 3498 "" 3499 "* 3500{ 3501 output_asm_insn (AS2 (xor%W0,%3,%3), operands); 3502 return AS1 (div%W0,%2); |
2960}") | 3503}" 3504 [(set_attr "type" "idiv")]) |
2961 2962/* 2963;;this should be a valid double division which we may want to add 2964 2965(define_insn "" 2966 [(set (match_operand:SI 0 "register_operand" "=a") 2967 (udiv:DI (match_operand:DI 1 "register_operand" "a") | 3505 3506/* 3507;;this should be a valid double division which we may want to add 3508 3509(define_insn "" 3510 [(set (match_operand:SI 0 "register_operand" "=a") 3511 (udiv:DI (match_operand:DI 1 "register_operand" "a") |
2968 (match_operand:SI 2 "general_operand" "rm"))) | 3512 (match_operand:SI 2 "nonimmediate_operand" "rm"))) |
2969 (set (match_operand:SI 3 "register_operand" "=d") 2970 (umod:SI (match_dup 1) (match_dup 2)))] 2971 "" | 3513 (set (match_operand:SI 3 "register_operand" "=d") 3514 (umod:SI (match_dup 1) (match_dup 2)))] 3515 "" |
2972 "div%L0 %2,%0") | 3516 "div%L0 %2,%0" 3517 [(set_attr "type" "idiv")]) |
2973*/ 2974 2975;;- and instructions 2976 2977;; On i386, 2978;; movzbl %bl,%ebx 2979;; is faster than 2980;; andl $255,%ebx 2981;; 2982;; but if the reg is %eax, then the "andl" is faster. 2983;; 2984;; On i486, the "andl" is always faster than the "movzbl". 2985;; 2986;; On both i386 and i486, a three operand AND is as fast with movzbl or 2987;; movzwl as with andl, if operands[0] != operands[1]. 2988 2989;; The `r' in `rm' for operand 3 looks redundant, but it causes 2990;; optional reloads to be generated if op 3 is a pseudo in a stack slot. 2991 | 3518*/ 3519 3520;;- and instructions 3521 3522;; On i386, 3523;; movzbl %bl,%ebx 3524;; is faster than 3525;; andl $255,%ebx 3526;; 3527;; but if the reg is %eax, then the "andl" is faster. 3528;; 3529;; On i486, the "andl" is always faster than the "movzbl". 3530;; 3531;; On both i386 and i486, a three operand AND is as fast with movzbl or 3532;; movzwl as with andl, if operands[0] != operands[1]. 3533 3534;; The `r' in `rm' for operand 3 looks redundant, but it causes 3535;; optional reloads to be generated if op 3 is a pseudo in a stack slot. 3536 |
2992;; ??? What if we only change one byte of an offsettable memory reference? | |
2993(define_insn "andsi3" | 3537(define_insn "andsi3" |
2994 [(set (match_operand:SI 0 "general_operand" "=r,r,rm,r") 2995 (and:SI (match_operand:SI 1 "general_operand" "%rm,qm,0,0") 2996 (match_operand:SI 2 "general_operand" "L,K,ri,rm")))] | 3538 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") 3539 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 3540 (match_operand:SI 2 "general_operand" "ri,rm")))] |
2997 "" 2998 "* 2999{ | 3541 "" 3542 "* 3543{ |
3000 if (GET_CODE (operands[2]) == CONST_INT 3001 && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) | 3544 HOST_WIDE_INT intval; 3545 if (!rtx_equal_p (operands[0], operands[1]) 3546 && rtx_equal_p (operands[0], operands[2])) |
3002 { | 3547 { |
3003 if (INTVAL (operands[2]) == 0xffff && REG_P (operands[0]) | 3548 rtx tmp; 3549 tmp = operands[1]; 3550 operands[1] = operands[2]; 3551 operands[2] = tmp; 3552 } 3553 switch (GET_CODE (operands[2])) 3554 { 3555 case CONST_INT: 3556 if (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) 3557 break; 3558 intval = INTVAL (operands[2]); 3559 /* zero-extend 16->32? */ 3560 if (intval == 0xffff && REG_P (operands[0]) |
3004 && (! REG_P (operands[1]) 3005 || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0) | 3561 && (! REG_P (operands[1]) 3562 || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0) |
3006 && (TARGET_386 || ! rtx_equal_p (operands[0], operands[1]))) | 3563 && (!TARGET_ZERO_EXTEND_WITH_AND || ! rtx_equal_p (operands[0], operands[1]))) |
3007 { 3008 /* ??? tege: Should forget CC_STATUS only if we clobber a 3009 remembered operand. Fix that later. */ 3010 CC_STATUS_INIT; 3011#ifdef INTEL_SYNTAX 3012 return AS2 (movzx,%w1,%0); 3013#else 3014 return AS2 (movz%W0%L0,%w1,%0); 3015#endif 3016 } 3017 | 3564 { 3565 /* ??? tege: Should forget CC_STATUS only if we clobber a 3566 remembered operand. Fix that later. */ 3567 CC_STATUS_INIT; 3568#ifdef INTEL_SYNTAX 3569 return AS2 (movzx,%w1,%0); 3570#else 3571 return AS2 (movz%W0%L0,%w1,%0); 3572#endif 3573 } 3574 |
3018 if (INTVAL (operands[2]) == 0xff && REG_P (operands[0]) | 3575 /* zero extend 8->32? */ 3576 if (intval == 0xff && REG_P (operands[0]) |
3019 && !(REG_P (operands[1]) && NON_QI_REG_P (operands[1])) 3020 && (! REG_P (operands[1]) 3021 || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0) | 3577 && !(REG_P (operands[1]) && NON_QI_REG_P (operands[1])) 3578 && (! REG_P (operands[1]) 3579 || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0) |
3022 && (TARGET_386 || ! rtx_equal_p (operands[0], operands[1]))) | 3580 && (!TARGET_ZERO_EXTEND_WITH_AND || ! rtx_equal_p (operands[0], operands[1]))) |
3023 { 3024 /* ??? tege: Should forget CC_STATUS only if we clobber a 3025 remembered operand. Fix that later. */ 3026 CC_STATUS_INIT; 3027#ifdef INTEL_SYNTAX 3028 return AS2 (movzx,%b1,%0); 3029#else 3030 return AS2 (movz%B0%L0,%b1,%0); 3031#endif 3032 } 3033 | 3581 { 3582 /* ??? tege: Should forget CC_STATUS only if we clobber a 3583 remembered operand. Fix that later. */ 3584 CC_STATUS_INIT; 3585#ifdef INTEL_SYNTAX 3586 return AS2 (movzx,%b1,%0); 3587#else 3588 return AS2 (movz%B0%L0,%b1,%0); 3589#endif 3590 } 3591 |
3034 if (QI_REG_P (operands[0]) && ~(INTVAL (operands[2]) | 0xff) == 0) 3035 { 3036 CC_STATUS_INIT; | 3592 /* Check partial bytes.. non-QI-regs are not available */ 3593 if (REG_P (operands[0]) && ! QI_REG_P (operands[0])) 3594 break; |
3037 | 3595 |
3038 if (INTVAL (operands[2]) == 0xffffff00) | 3596 /* only low byte has zero bits? */ 3597 if (~(intval | 0xff) == 0) 3598 { 3599 intval &= 0xff; 3600 if (REG_P (operands[0])) |
3039 { | 3601 { |
3040 operands[2] = const0_rtx; 3041 return AS2 (mov%B0,%2,%b0); | 3602 if (intval == 0) 3603 { 3604 CC_STATUS_INIT; 3605 return AS2 (xor%B0,%b0,%b0); 3606 } 3607 3608 /* we're better off with the 32-bit version if reg != EAX */ 3609 /* the value is sign-extended in 8 bits */ 3610 if (REGNO (operands[0]) != 0 && (intval & 0x80)) 3611 break; |
3042 } 3043 | 3612 } 3613 |
3044 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff); | 3614 CC_STATUS_INIT; 3615 3616 operands[2] = GEN_INT (intval); 3617 3618 if (intval == 0) 3619 return AS2 (mov%B0,%2,%b0); 3620 |
3045 return AS2 (and%B0,%2,%b0); 3046 } 3047 | 3621 return AS2 (and%B0,%2,%b0); 3622 } 3623 |
3048 if (QI_REG_P (operands[0]) && ~(INTVAL (operands[2]) | 0xff00) == 0) | 3624 /* only second byte has zero? */ 3625 if (~(intval | 0xff00) == 0) |
3049 { 3050 CC_STATUS_INIT; 3051 | 3626 { 3627 CC_STATUS_INIT; 3628 |
3052 if (INTVAL (operands[2]) == 0xffff00ff) | 3629 intval = (intval >> 8) & 0xff; 3630 operands[2] = GEN_INT (intval); 3631 if (intval == 0) |
3053 { | 3632 { |
3054 operands[2] = const0_rtx; 3055 return AS2 (mov%B0,%2,%h0); | 3633 if (REG_P (operands[0])) 3634 return AS2 (xor%B0,%h0,%h0); 3635 operands[0] = adj_offsettable_operand (operands[0], 1); 3636 return AS2 (mov%B0,%2,%b0); |
3056 } 3057 | 3637 } 3638 |
3058 operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); 3059 return AS2 (and%B0,%2,%h0); | 3639 if (REG_P (operands[0])) 3640 return AS2 (and%B0,%2,%h0); 3641 3642 operands[0] = adj_offsettable_operand (operands[0], 1); 3643 return AS2 (and%B0,%2,%b0); |
3060 } 3061 | 3644 } 3645 |
3062 if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) == 0xffff0000) | 3646 if (REG_P (operands[0])) 3647 break; 3648 3649 /* third byte has zero bits? */ 3650 if (~(intval | 0xff0000) == 0) 3651 { 3652 intval = (intval >> 16) & 0xff; 3653 operands[0] = adj_offsettable_operand (operands[0], 2); 3654byte_and_operation: 3655 CC_STATUS_INIT; 3656 operands[2] = GEN_INT (intval); 3657 if (intval == 0) 3658 return AS2 (mov%B0,%2,%b0); 3659 return AS2 (and%B0,%2,%b0); 3660 } 3661 3662 /* fourth byte has zero bits? */ 3663 if (~(intval | 0xff000000) == 0) 3664 { 3665 intval = (intval >> 24) & 0xff; 3666 operands[0] = adj_offsettable_operand (operands[0], 3); 3667 goto byte_and_operation; 3668 } 3669 3670 /* Low word is zero? */ 3671 if (intval == 0xffff0000) |
3063 { | 3672 { |
3673word_zero_and_operation: 3674 CC_STATUS_INIT; |
|
3064 operands[2] = const0_rtx; 3065 return AS2 (mov%W0,%2,%w0); 3066 } | 3675 operands[2] = const0_rtx; 3676 return AS2 (mov%W0,%2,%w0); 3677 } |
3678 3679 /* High word is zero? */ 3680 if (intval == 0x0000ffff) 3681 { 3682 operands[0] = adj_offsettable_operand (operands[0], 2); 3683 goto word_zero_and_operation; 3684 } 3685 3686 default: 3687 break; |
|
3067 } 3068 3069 return AS2 (and%L0,%2,%0); 3070}") 3071 3072(define_insn "andhi3" | 3688 } 3689 3690 return AS2 (and%L0,%2,%0); 3691}") 3692 3693(define_insn "andhi3" |
3073 [(set (match_operand:HI 0 "general_operand" "=rm,r") 3074 (and:HI (match_operand:HI 1 "general_operand" "%0,0") | 3694 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") 3695 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") |
3075 (match_operand:HI 2 "general_operand" "ri,rm")))] 3076 "" 3077 "* 3078{ 3079 if (GET_CODE (operands[2]) == CONST_INT 3080 && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) 3081 { 3082 /* Can we ignore the upper byte? */ --- 22 unchanged lines hidden (view full) --- 3105 { 3106 operands[2] = const0_rtx; 3107 return AS2 (mov%B0,%2,%h0); 3108 } 3109 3110 operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); 3111 return AS2 (and%B0,%2,%h0); 3112 } | 3696 (match_operand:HI 2 "general_operand" "ri,rm")))] 3697 "" 3698 "* 3699{ 3700 if (GET_CODE (operands[2]) == CONST_INT 3701 && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) 3702 { 3703 /* Can we ignore the upper byte? */ --- 22 unchanged lines hidden (view full) --- 3726 { 3727 operands[2] = const0_rtx; 3728 return AS2 (mov%B0,%2,%h0); 3729 } 3730 3731 operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); 3732 return AS2 (and%B0,%2,%h0); 3733 } |
3734 3735 /* use 32-bit ops on registers when there are no sign issues.. */ 3736 if (REG_P (operands[0])) 3737 { 3738 if (!(INTVAL (operands[2]) & ~0x7fff)) 3739 return AS2 (and%L0,%2,%k0); 3740 } |
|
3113 } 3114 | 3741 } 3742 |
3743 if (REG_P (operands[0]) 3744 && i386_aligned_p (operands[2])) 3745 { 3746 CC_STATUS_INIT; 3747 /* If op[2] is constant, we should zero-extend it and */ 3748 /* make a note that op[0] has been zero-extended, so */ 3749 /* that we could use 32-bit ops on it forthwith, but */ 3750 /* there is no such reg-note available. Instead we do */ 3751 /* a sign extension as that can result in shorter asm */ 3752 operands[2] = i386_sext16_if_const (operands[2]); 3753 return AS2 (and%L0,%k2,%k0); 3754 } 3755 3756 /* Use a 32-bit word with the upper bits set, invalidate CC */ 3757 if (GET_CODE (operands[2]) == CONST_INT 3758 && i386_aligned_p (operands[0])) 3759 { 3760 HOST_WIDE_INT val = INTVAL (operands[2]); 3761 CC_STATUS_INIT; 3762 val |= ~0xffff; 3763 if (val != INTVAL (operands[2])) 3764 operands[2] = GEN_INT (val); 3765 return AS2 (and%L0,%k2,%k0); 3766 } 3767 |
|
3115 return AS2 (and%W0,%2,%0); 3116}") 3117 3118(define_insn "andqi3" | 3768 return AS2 (and%W0,%2,%0); 3769}") 3770 3771(define_insn "andqi3" |
3119 [(set (match_operand:QI 0 "general_operand" "=qm,q") 3120 (and:QI (match_operand:QI 1 "general_operand" "%0,0") | 3772 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q") 3773 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") |
3121 (match_operand:QI 2 "general_operand" "qn,qmn")))] 3122 "" 3123 "* return AS2 (and%B0,%2,%0);") 3124 3125/* I am nervous about these two.. add them later.. 3126;I presume this means that we have something in say op0= eax which is small 3127;and we want to and it with memory so we can do this by just an 3128;andb m,%al and have success. 3129(define_insn "" 3130 [(set (match_operand:SI 0 "general_operand" "=r") 3131 (and:SI (zero_extend:SI 3132 (match_operand:HI 1 "nonimmediate_operand" "rm")) 3133 (match_operand:SI 2 "general_operand" "0")))] 3134 "GET_CODE (operands[2]) == CONST_INT 3135 && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (HImode))" 3136 "and%W0 %1,%0") 3137 3138(define_insn "" | 3774 (match_operand:QI 2 "general_operand" "qn,qmn")))] 3775 "" 3776 "* return AS2 (and%B0,%2,%0);") 3777 3778/* I am nervous about these two.. add them later.. 3779;I presume this means that we have something in say op0= eax which is small 3780;and we want to and it with memory so we can do this by just an 3781;andb m,%al and have success. 3782(define_insn "" 3783 [(set (match_operand:SI 0 "general_operand" "=r") 3784 (and:SI (zero_extend:SI 3785 (match_operand:HI 1 "nonimmediate_operand" "rm")) 3786 (match_operand:SI 2 "general_operand" "0")))] 3787 "GET_CODE (operands[2]) == CONST_INT 3788 && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (HImode))" 3789 "and%W0 %1,%0") 3790 3791(define_insn "" |
3139 [(set (match_operand:SI 0 "general_operand" "=q") | 3792 [(set (match_operand:SI 0 "register_operand" "=q") |
3140 (and:SI 3141 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")) | 3793 (and:SI 3794 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")) |
3142 (match_operand:SI 2 "general_operand" "0")))] | 3795 (match_operand:SI 2 "register_operand" "0")))] |
3143 "GET_CODE (operands[2]) == CONST_INT 3144 && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (QImode))" 3145 "and%L0 %1,%0") 3146 3147*/ 3148 3149;;- Bit set (inclusive or) instructions 3150 | 3796 "GET_CODE (operands[2]) == CONST_INT 3797 && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (QImode))" 3798 "and%L0 %1,%0") 3799 3800*/ 3801 3802;;- Bit set (inclusive or) instructions 3803 |
3151;; ??? What if we only change one byte of an offsettable memory reference? | 3804;; This optimizes known byte-wide operations to memory, and in some cases 3805;; to QI registers.. Note that we don't want to use the QI registers too 3806;; aggressively, because often the 32-bit register instruction is the same 3807;; size, and likely to be faster on PentiumPro. |
3152(define_insn "iorsi3" | 3808(define_insn "iorsi3" |
3153 [(set (match_operand:SI 0 "general_operand" "=rm,r") 3154 (ior:SI (match_operand:SI 1 "general_operand" "%0,0") | 3809 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") 3810 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
3155 (match_operand:SI 2 "general_operand" "ri,rm")))] 3156 "" 3157 "* 3158{ | 3811 (match_operand:SI 2 "general_operand" "ri,rm")))] 3812 "" 3813 "* 3814{ |
3159 if (GET_CODE (operands[2]) == CONST_INT 3160 && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) | 3815 HOST_WIDE_INT intval; 3816 switch (GET_CODE (operands[2])) |
3161 { | 3817 { |
3162 if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) 3163 && (INTVAL (operands[2]) & ~0xff) == 0) 3164 { 3165 CC_STATUS_INIT; | 3818 case CONST_INT: |
3166 | 3819 |
3167 if (INTVAL (operands[2]) == 0xff) 3168 return AS2 (mov%B0,%2,%b0); | 3820 if (REG_P (operands[0]) && ! QI_REG_P (operands[0])) 3821 break; |
3169 | 3822 |
3170 return AS2 (or%B0,%2,%b0); | 3823 /* don't try to optimize volatile accesses */ 3824 if (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) 3825 break; 3826 3827 intval = INTVAL (operands[2]); 3828 if ((intval & ~0xff) == 0) 3829 { 3830 if (REG_P (operands[0])) 3831 { 3832 /* Do low byte access only for %eax or when high bit is set */ 3833 if (REGNO (operands[0]) != 0 && !(intval & 0x80)) 3834 break; 3835 } 3836 3837byte_or_operation: 3838 CC_STATUS_INIT; 3839 3840 if (intval != INTVAL (operands[2])) 3841 operands[2] = GEN_INT (intval); 3842 3843 if (intval == 0xff) 3844 return AS2 (mov%B0,%2,%b0); 3845 3846 return AS2 (or%B0,%2,%b0); |
3171 } 3172 | 3847 } 3848 |
3173 if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0) | 3849 /* second byte? */ 3850 if ((intval & ~0xff00) == 0) |
3174 { | 3851 { |
3175 CC_STATUS_INIT; 3176 operands[2] = GEN_INT (INTVAL (operands[2]) >> 8); | 3852 intval >>= 8; |
3177 | 3853 |
3178 if (INTVAL (operands[2]) == 0xff) 3179 return AS2 (mov%B0,%2,%h0); | 3854 if (REG_P (operands[0])) 3855 { 3856 CC_STATUS_INIT; 3857 operands[2] = GEN_INT (intval); 3858 if (intval == 0xff) 3859 return AS2 (mov%B0,%2,%h0); |
3180 | 3860 |
3181 return AS2 (or%B0,%2,%h0); | 3861 return AS2 (or%B0,%2,%h0); 3862 } 3863 3864 operands[0] = adj_offsettable_operand (operands[0], 1); 3865 goto byte_or_operation; |
3182 } | 3866 } |
3867 3868 if (REG_P (operands[0])) 3869 break; 3870 3871 /* third byte? */ 3872 if ((intval & ~0xff0000) == 0) 3873 { 3874 intval >>= 16; 3875 operands[0] = adj_offsettable_operand (operands[0], 2); 3876 goto byte_or_operation; 3877 } 3878 3879 /* fourth byte? */ 3880 if ((intval & ~0xff000000) == 0) 3881 { 3882 intval = (intval >> 24) & 0xff; 3883 operands[0] = adj_offsettable_operand (operands[0], 3); 3884 goto byte_or_operation; 3885 } 3886 3887 default: 3888 break; |
|
3183 } 3184 3185 return AS2 (or%L0,%2,%0); 3186}") 3187 3188(define_insn "iorhi3" | 3889 } 3890 3891 return AS2 (or%L0,%2,%0); 3892}") 3893 3894(define_insn "iorhi3" |
3189 [(set (match_operand:HI 0 "general_operand" "=rm,r") 3190 (ior:HI (match_operand:HI 1 "general_operand" "%0,0") | 3895 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") 3896 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") |
3191 (match_operand:HI 2 "general_operand" "ri,rm")))] 3192 "" 3193 "* 3194{ | 3897 (match_operand:HI 2 "general_operand" "ri,rm")))] 3898 "" 3899 "* 3900{ |
3195 if (GET_CODE (operands[2]) == CONST_INT 3196 && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) | 3901 HOST_WIDE_INT intval; 3902 switch (GET_CODE (operands[2])) |
3197 { | 3903 { |
3198 /* Can we ignore the upper byte? */ 3199 if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) 3200 && (INTVAL (operands[2]) & 0xff00) == 0) 3201 { 3202 CC_STATUS_INIT; 3203 if (INTVAL (operands[2]) & 0xffff0000) 3204 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); | 3904 case CONST_INT: |
3205 | 3905 |
3206 if (INTVAL (operands[2]) == 0xff) 3207 return AS2 (mov%B0,%2,%b0); | 3906 if (REG_P (operands[0]) && ! QI_REG_P (operands[0])) 3907 break; |
3208 | 3908 |
3209 return AS2 (or%B0,%2,%b0); | 3909 /* don't try to optimize volatile accesses */ 3910 if (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) 3911 break; 3912 3913 intval = 0xffff & INTVAL (operands[2]); 3914 3915 if ((intval & 0xff00) == 0) 3916 { 3917 if (REG_P (operands[0])) 3918 { 3919 /* Do low byte access only for %eax or when high bit is set */ 3920 if (REGNO (operands[0]) != 0 && !(intval & 0x80)) 3921 break; 3922 } 3923 3924byte_or_operation: 3925 CC_STATUS_INIT; 3926 3927 if (intval == 0xff) 3928 return AS2 (mov%B0,%2,%b0); 3929 3930 return AS2 (or%B0,%2,%b0); |
3210 } 3211 | 3931 } 3932 |
3212 /* Can we ignore the lower byte? */ 3213 /* ??? what about offsettable memory references? */ 3214 if (QI_REG_P (operands[0]) 3215 && (INTVAL (operands[2]) & 0xff) == 0) | 3933 /* high byte? */ 3934 if ((intval & 0xff) == 0) |
3216 { | 3935 { |
3217 CC_STATUS_INIT; 3218 operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); | 3936 intval >>= 8; 3937 operands[2] = GEN_INT (intval); |
3219 | 3938 |
3220 if (INTVAL (operands[2]) == 0xff) 3221 return AS2 (mov%B0,%2,%h0); | 3939 if (REG_P (operands[0])) 3940 { 3941 CC_STATUS_INIT; 3942 if (intval == 0xff) 3943 return AS2 (mov%B0,%2,%h0); |
3222 | 3944 |
3223 return AS2 (or%B0,%2,%h0); | 3945 return AS2 (or%B0,%2,%h0); 3946 } 3947 3948 operands[0] = adj_offsettable_operand (operands[0], 1); 3949 3950 goto byte_or_operation; |
3224 } | 3951 } |
3952 3953 default: 3954 break; |
|
3225 } 3226 | 3955 } 3956 |
3957 if (REG_P (operands[0]) 3958 && i386_aligned_p (operands[2])) 3959 { 3960 CC_STATUS_INIT; 3961 operands[2] = i386_sext16_if_const (operands[2]); 3962 return AS2 (or%L0,%k2,%k0); 3963 } 3964 3965 if (GET_CODE (operands[2]) == CONST_INT 3966 && i386_aligned_p (operands[0])) 3967 { 3968 CC_STATUS_INIT; 3969 intval = 0xffff & INTVAL (operands[2]); 3970 if (intval != INTVAL (operands[2])) 3971 operands[2] = GEN_INT (intval); 3972 return AS2 (or%L0,%2,%k0); 3973 } 3974 |
|
3227 return AS2 (or%W0,%2,%0); 3228}") 3229 3230(define_insn "iorqi3" | 3975 return AS2 (or%W0,%2,%0); 3976}") 3977 3978(define_insn "iorqi3" |
3231 [(set (match_operand:QI 0 "general_operand" "=qm,q") 3232 (ior:QI (match_operand:QI 1 "general_operand" "%0,0") | 3979 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q") 3980 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") |
3233 (match_operand:QI 2 "general_operand" "qn,qmn")))] 3234 "" 3235 "* return AS2 (or%B0,%2,%0);") 3236 3237;;- xor instructions 3238 | 3981 (match_operand:QI 2 "general_operand" "qn,qmn")))] 3982 "" 3983 "* return AS2 (or%B0,%2,%0);") 3984 3985;;- xor instructions 3986 |
3239;; ??? What if we only change one byte of an offsettable memory reference? | |
3240(define_insn "xorsi3" | 3987(define_insn "xorsi3" |
3241 [(set (match_operand:SI 0 "general_operand" "=rm,r") 3242 (xor:SI (match_operand:SI 1 "general_operand" "%0,0") | 3988 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") 3989 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
3243 (match_operand:SI 2 "general_operand" "ri,rm")))] 3244 "" 3245 "* 3246{ | 3990 (match_operand:SI 2 "general_operand" "ri,rm")))] 3991 "" 3992 "* 3993{ |
3247 if (GET_CODE (operands[2]) == CONST_INT 3248 && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) | 3994 HOST_WIDE_INT intval; 3995 switch (GET_CODE (operands[2])) |
3249 { | 3996 { |
3250 if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) 3251 && (INTVAL (operands[2]) & ~0xff) == 0) 3252 { 3253 CC_STATUS_INIT; | 3997 case CONST_INT: |
3254 | 3998 |
3255 if (INTVAL (operands[2]) == 0xff) 3256 return AS1 (not%B0,%b0); | 3999 if (REG_P (operands[0]) && ! QI_REG_P (operands[0])) 4000 break; |
3257 | 4001 |
3258 return AS2 (xor%B0,%2,%b0); | 4002 /* don't try to optimize volatile accesses */ 4003 if (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) 4004 break; 4005 4006 intval = INTVAL (operands[2]); 4007 if ((intval & ~0xff) == 0) 4008 { 4009 if (REG_P (operands[0])) 4010 { 4011 /* Do low byte access only for %eax or when high bit is set */ 4012 if (REGNO (operands[0]) != 0 && !(intval & 0x80)) 4013 break; 4014 } 4015 4016byte_xor_operation: 4017 CC_STATUS_INIT; 4018 4019 if (intval == 0xff) 4020 return AS1 (not%B0,%b0); 4021 4022 if (intval != INTVAL (operands[2])) 4023 operands[2] = GEN_INT (intval); 4024 return AS2 (xor%B0,%2,%b0); |
3259 } 3260 | 4025 } 4026 |
3261 if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0) | 4027 /* second byte? */ 4028 if ((intval & ~0xff00) == 0) |
3262 { | 4029 { |
3263 CC_STATUS_INIT; 3264 operands[2] = GEN_INT (INTVAL (operands[2]) >> 8); | 4030 intval >>= 8; |
3265 | 4031 |
3266 if (INTVAL (operands[2]) == 0xff) 3267 return AS1 (not%B0,%h0); | 4032 if (REG_P (operands[0])) 4033 { 4034 CC_STATUS_INIT; 4035 if (intval == 0xff) 4036 return AS1 (not%B0,%h0); |
3268 | 4037 |
3269 return AS2 (xor%B0,%2,%h0); | 4038 operands[2] = GEN_INT (intval); 4039 return AS2 (xor%B0,%2,%h0); 4040 } 4041 4042 operands[0] = adj_offsettable_operand (operands[0], 1); 4043 4044 goto byte_xor_operation; |
3270 } | 4045 } |
4046 4047 if (REG_P (operands[0])) 4048 break; 4049 4050 /* third byte? */ 4051 if ((intval & ~0xff0000) == 0) 4052 { 4053 intval >>= 16; 4054 operands[0] = adj_offsettable_operand (operands[0], 2); 4055 goto byte_xor_operation; 4056 } 4057 4058 /* fourth byte? */ 4059 if ((intval & ~0xff000000) == 0) 4060 { 4061 intval = (intval >> 24) & 0xff; 4062 operands[0] = adj_offsettable_operand (operands[0], 3); 4063 goto byte_xor_operation; 4064 } 4065 4066 default: 4067 break; |
|
3271 } 3272 3273 return AS2 (xor%L0,%2,%0); 3274}") 3275 3276(define_insn "xorhi3" | 4068 } 4069 4070 return AS2 (xor%L0,%2,%0); 4071}") 4072 4073(define_insn "xorhi3" |
3277 [(set (match_operand:HI 0 "general_operand" "=rm,r") 3278 (xor:HI (match_operand:HI 1 "general_operand" "%0,0") | 4074 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") 4075 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") |
3279 (match_operand:HI 2 "general_operand" "ri,rm")))] 3280 "" 3281 "* 3282{ 3283 if (GET_CODE (operands[2]) == CONST_INT 3284 && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) 3285 { 3286 /* Can we ignore the upper byte? */ --- 20 unchanged lines hidden (view full) --- 3307 3308 if (INTVAL (operands[2]) == 0xff) 3309 return AS1 (not%B0,%h0); 3310 3311 return AS2 (xor%B0,%2,%h0); 3312 } 3313 } 3314 | 4076 (match_operand:HI 2 "general_operand" "ri,rm")))] 4077 "" 4078 "* 4079{ 4080 if (GET_CODE (operands[2]) == CONST_INT 4081 && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) 4082 { 4083 /* Can we ignore the upper byte? */ --- 20 unchanged lines hidden (view full) --- 4104 4105 if (INTVAL (operands[2]) == 0xff) 4106 return AS1 (not%B0,%h0); 4107 4108 return AS2 (xor%B0,%2,%h0); 4109 } 4110 } 4111 |
4112 if (REG_P (operands[0]) 4113 && i386_aligned_p (operands[2])) 4114 { 4115 CC_STATUS_INIT; 4116 operands[2] = i386_sext16_if_const (operands[2]); 4117 return AS2 (xor%L0,%k2,%k0); 4118 } 4119 4120 if (GET_CODE (operands[2]) == CONST_INT 4121 && i386_aligned_p (operands[0])) 4122 { 4123 HOST_WIDE_INT intval; 4124 CC_STATUS_INIT; 4125 intval = 0xffff & INTVAL (operands[2]); 4126 if (intval != INTVAL (operands[2])) 4127 operands[2] = GEN_INT (intval); 4128 return AS2 (xor%L0,%2,%k0); 4129 } 4130 |
|
3315 return AS2 (xor%W0,%2,%0); 3316}") 3317 3318(define_insn "xorqi3" | 4131 return AS2 (xor%W0,%2,%0); 4132}") 4133 4134(define_insn "xorqi3" |
3319 [(set (match_operand:QI 0 "general_operand" "=qm,q") 3320 (xor:QI (match_operand:QI 1 "general_operand" "%0,0") | 4135 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q") 4136 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") |
3321 (match_operand:QI 2 "general_operand" "qn,qm")))] 3322 "" 3323 "* return AS2 (xor%B0,%2,%0);") 3324 | 4137 (match_operand:QI 2 "general_operand" "qn,qm")))] 4138 "" 4139 "* return AS2 (xor%B0,%2,%0);") 4140 |
4141;; logical operations for DImode 4142 4143 4144(define_insn "anddi3" 4145 [(set (match_operand:DI 0 "general_operand" "=&r,&ro,!r,o,!&r,!o,!o") 4146 (and:DI (match_operand:DI 1 "general_operand" "%0,0,0,0iF,or,riF,o") 4147 (match_operand:DI 2 "general_operand" "o,riF,0,or,or,oriF,o"))) 4148 (clobber (match_scratch:SI 3 "=X,X,X,&r,X,&r,&r"))] 4149 "" 4150 "#") 4151 4152(define_insn "iordi3" 4153 [(set (match_operand:DI 0 "general_operand" "=&r,&ro,!r,o,!&r,!o,!o") 4154 (ior:DI (match_operand:DI 1 "general_operand" "%0,0,0,0iF,or,riF,o") 4155 (match_operand:DI 2 "general_operand" "o,riF,0,or,or,oriF,o"))) 4156 (clobber (match_scratch:SI 3 "=X,X,X,&r,X,&r,&r"))] 4157 "" 4158 "#") 4159 4160(define_insn "xordi3" 4161 [(set (match_operand:DI 0 "general_operand" "=&r,&ro,!r,o,!&r,!o,!o") 4162 (xor:DI (match_operand:DI 1 "general_operand" "%0,0,0,0iF,or,riF,o") 4163 (match_operand:DI 2 "general_operand" "o,riF,0,or,or,oriF,o"))) 4164 (clobber (match_scratch:SI 3 "=X,X,X,&r,X,&r,&r"))] 4165 "" 4166 "#") 4167 4168(define_split 4169 [(set (match_operand:DI 0 "general_operand" "=&r,&ro,!r,o,!&r,!o,!o") 4170 (match_operator:DI 4 "ix86_logical_operator" 4171 [(match_operand:DI 1 "general_operand" "%0,0,0,0iF,or,riF,o") 4172 (match_operand:DI 2 "general_operand" "o,riF,0,or,or,oriF,o")])) 4173 (clobber (match_scratch:SI 3 "=X,X,X,&r,X,&r,&r"))] 4174 "reload_completed" 4175 [(const_int 0)] 4176 " 4177{ 4178 rtx low[3], high[3], xops[7], temp; 4179 rtx (*genfunc)() = (GET_CODE (operands[4]) == AND ? gen_andsi3 4180 : GET_CODE (operands[4]) == IOR ? gen_iorsi3 4181 : GET_CODE (operands[4]) == XOR ? gen_xorsi3 4182 : 0); 4183 4184 if (rtx_equal_p (operands[0], operands[2])) 4185 { 4186 temp = operands[1]; 4187 operands[1] = operands[2]; 4188 operands[2] = temp; 4189 } 4190 4191 split_di (operands, 3, low, high); 4192 if (!rtx_equal_p (operands[0], operands[1])) 4193 { 4194 xops[0] = high[0]; 4195 xops[1] = low[0]; 4196 xops[2] = high[1]; 4197 xops[3] = low[1]; 4198 4199 if (GET_CODE (operands[0]) != MEM) 4200 { 4201 emit_insn (gen_movsi (xops[1], xops[3])); 4202 emit_insn (gen_movsi (xops[0], xops[2])); 4203 } 4204 else 4205 { 4206 xops[4] = high[2]; 4207 xops[5] = low[2]; 4208 xops[6] = operands[3]; 4209 emit_insn (gen_movsi (xops[6], xops[3])); 4210 emit_insn ((*genfunc) (xops[6], xops[6], xops[5])); 4211 emit_insn (gen_movsi (xops[1], xops[6])); 4212 emit_insn (gen_movsi (xops[6], xops[2])); 4213 emit_insn ((*genfunc) (xops[6], xops[6], xops[4])); 4214 emit_insn (gen_movsi (xops[0], xops[6])); 4215 DONE; 4216 } 4217 } 4218 4219 if (GET_CODE (operands[3]) == REG && GET_CODE (operands[2]) != REG) 4220 { 4221 xops[0] = high[0]; 4222 xops[1] = low[0]; 4223 xops[2] = high[2]; 4224 xops[3] = low[2]; 4225 xops[4] = operands[3]; 4226 4227 emit_insn (gen_movsi (xops[4], xops[3])); 4228 emit_insn ((*genfunc) (xops[1], xops[1], xops[4])); 4229 emit_insn (gen_movsi (xops[4], xops[2])); 4230 emit_insn ((*genfunc) (xops[0], xops[0], xops[4])); 4231 } 4232 4233 else 4234 { 4235 emit_insn ((*genfunc) (low[0], low[0], low[2])); 4236 emit_insn ((*genfunc) (high[0], high[0], high[2])); 4237 } 4238 4239 DONE; 4240}") 4241 |
|
3325;;- negation instructions 3326 3327(define_insn "negdi2" 3328 [(set (match_operand:DI 0 "general_operand" "=&ro") 3329 (neg:DI (match_operand:DI 1 "general_operand" "0")))] 3330 "" 3331 "* 3332{ --- 7 unchanged lines hidden (view full) --- 3340 3341 output_asm_insn (AS1 (neg%L0,%0), low); 3342 output_asm_insn (AS2 (adc%L1,%0,%1), xops); 3343 output_asm_insn (AS1 (neg%L0,%0), high); 3344 RET; 3345}") 3346 3347(define_insn "negsi2" | 4242;;- negation instructions 4243 4244(define_insn "negdi2" 4245 [(set (match_operand:DI 0 "general_operand" "=&ro") 4246 (neg:DI (match_operand:DI 1 "general_operand" "0")))] 4247 "" 4248 "* 4249{ --- 7 unchanged lines hidden (view full) --- 4257 4258 output_asm_insn (AS1 (neg%L0,%0), low); 4259 output_asm_insn (AS2 (adc%L1,%0,%1), xops); 4260 output_asm_insn (AS1 (neg%L0,%0), high); 4261 RET; 4262}") 4263 4264(define_insn "negsi2" |
3348 [(set (match_operand:SI 0 "general_operand" "=rm") 3349 (neg:SI (match_operand:SI 1 "general_operand" "0")))] | 4265 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 4266 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))] |
3350 "" 3351 "neg%L0 %0") 3352 3353(define_insn "neghi2" | 4267 "" 4268 "neg%L0 %0") 4269 4270(define_insn "neghi2" |
3354 [(set (match_operand:HI 0 "general_operand" "=rm") 3355 (neg:HI (match_operand:HI 1 "general_operand" "0")))] | 4271 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") 4272 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))] |
3356 "" 3357 "neg%W0 %0") 3358 3359(define_insn "negqi2" | 4273 "" 4274 "neg%W0 %0") 4275 4276(define_insn "negqi2" |
3360 [(set (match_operand:QI 0 "general_operand" "=qm") 3361 (neg:QI (match_operand:QI 1 "general_operand" "0")))] | 4277 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") 4278 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))] |
3362 "" 3363 "neg%B0 %0") 3364 3365(define_insn "negsf2" 3366 [(set (match_operand:SF 0 "register_operand" "=f") | 4279 "" 4280 "neg%B0 %0") 4281 4282(define_insn "negsf2" 4283 [(set (match_operand:SF 0 "register_operand" "=f") |
3367 (neg:SF (match_operand:SF 1 "general_operand" "0")))] | 4284 (neg:SF (match_operand:SF 1 "register_operand" "0")))] |
3368 "TARGET_80387" 3369 "fchs") 3370 3371(define_insn "negdf2" 3372 [(set (match_operand:DF 0 "register_operand" "=f") | 4285 "TARGET_80387" 4286 "fchs") 4287 4288(define_insn "negdf2" 4289 [(set (match_operand:DF 0 "register_operand" "=f") |
3373 (neg:DF (match_operand:DF 1 "general_operand" "0")))] | 4290 (neg:DF (match_operand:DF 1 "register_operand" "0")))] |
3374 "TARGET_80387" 3375 "fchs") 3376 3377(define_insn "" 3378 [(set (match_operand:DF 0 "register_operand" "=f") | 4291 "TARGET_80387" 4292 "fchs") 4293 4294(define_insn "" 4295 [(set (match_operand:DF 0 "register_operand" "=f") |
3379 (neg:DF (float_extend:DF (match_operand:SF 1 "general_operand" "0"))))] | 4296 (neg:DF (float_extend:DF (match_operand:SF 1 "register_operand" "0"))))] |
3380 "TARGET_80387" 3381 "fchs") 3382 3383(define_insn "negxf2" 3384 [(set (match_operand:XF 0 "register_operand" "=f") | 4297 "TARGET_80387" 4298 "fchs") 4299 4300(define_insn "negxf2" 4301 [(set (match_operand:XF 0 "register_operand" "=f") |
3385 (neg:XF (match_operand:XF 1 "general_operand" "0")))] | 4302 (neg:XF (match_operand:XF 1 "register_operand" "0")))] |
3386 "TARGET_80387" 3387 "fchs") 3388 3389(define_insn "" 3390 [(set (match_operand:XF 0 "register_operand" "=f") | 4303 "TARGET_80387" 4304 "fchs") 4305 4306(define_insn "" 4307 [(set (match_operand:XF 0 "register_operand" "=f") |
3391 (neg:XF (float_extend:XF (match_operand:DF 1 "general_operand" "0"))))] | 4308 (neg:XF (float_extend:XF (match_operand:DF 1 "register_operand" "0"))))] |
3392 "TARGET_80387" 3393 "fchs") 3394 3395;; Absolute value instructions 3396 3397(define_insn "abssf2" 3398 [(set (match_operand:SF 0 "register_operand" "=f") | 4309 "TARGET_80387" 4310 "fchs") 4311 4312;; Absolute value instructions 4313 4314(define_insn "abssf2" 4315 [(set (match_operand:SF 0 "register_operand" "=f") |
3399 (abs:SF (match_operand:SF 1 "general_operand" "0")))] | 4316 (abs:SF (match_operand:SF 1 "register_operand" "0")))] |
3400 "TARGET_80387" | 4317 "TARGET_80387" |
3401 "fabs") | 4318 "fabs" 4319 [(set_attr "type" "fpop")]) |
3402 3403(define_insn "absdf2" 3404 [(set (match_operand:DF 0 "register_operand" "=f") | 4320 4321(define_insn "absdf2" 4322 [(set (match_operand:DF 0 "register_operand" "=f") |
3405 (abs:DF (match_operand:DF 1 "general_operand" "0")))] | 4323 (abs:DF (match_operand:DF 1 "register_operand" "0")))] |
3406 "TARGET_80387" | 4324 "TARGET_80387" |
3407 "fabs") | 4325 "fabs" 4326 [(set_attr "type" "fpop")]) |
3408 3409(define_insn "" 3410 [(set (match_operand:DF 0 "register_operand" "=f") | 4327 4328(define_insn "" 4329 [(set (match_operand:DF 0 "register_operand" "=f") |
3411 (abs:DF (float_extend:DF (match_operand:SF 1 "general_operand" "0"))))] | 4330 (abs:DF (float_extend:DF (match_operand:SF 1 "register_operand" "0"))))] |
3412 "TARGET_80387" | 4331 "TARGET_80387" |
3413 "fabs") | 4332 "fabs" 4333 [(set_attr "type" "fpop")]) |
3414 3415(define_insn "absxf2" 3416 [(set (match_operand:XF 0 "register_operand" "=f") | 4334 4335(define_insn "absxf2" 4336 [(set (match_operand:XF 0 "register_operand" "=f") |
3417 (abs:XF (match_operand:XF 1 "general_operand" "0")))] | 4337 (abs:XF (match_operand:XF 1 "register_operand" "0")))] |
3418 "TARGET_80387" | 4338 "TARGET_80387" |
3419 "fabs") | 4339 "fabs" 4340 [(set_attr "type" "fpop")]) |
3420 3421(define_insn "" 3422 [(set (match_operand:XF 0 "register_operand" "=f") | 4341 4342(define_insn "" 4343 [(set (match_operand:XF 0 "register_operand" "=f") |
3423 (abs:XF (float_extend:XF (match_operand:DF 1 "general_operand" "0"))))] | 4344 (abs:XF (float_extend:XF (match_operand:DF 1 "register_operand" "0"))))] |
3424 "TARGET_80387" | 4345 "TARGET_80387" |
3425 "fabs") | 4346 "fabs" 4347 [(set_attr "type" "fpop")]) |
3426 3427(define_insn "sqrtsf2" 3428 [(set (match_operand:SF 0 "register_operand" "=f") | 4348 4349(define_insn "sqrtsf2" 4350 [(set (match_operand:SF 0 "register_operand" "=f") |
3429 (sqrt:SF (match_operand:SF 1 "general_operand" "0")))] 3430 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 3431 && (TARGET_IEEE_FP || flag_fast_math) " | 4351 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))] 4352 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387" |
3432 "fsqrt") 3433 3434(define_insn "sqrtdf2" 3435 [(set (match_operand:DF 0 "register_operand" "=f") | 4353 "fsqrt") 4354 4355(define_insn "sqrtdf2" 4356 [(set (match_operand:DF 0 "register_operand" "=f") |
3436 (sqrt:DF (match_operand:DF 1 "general_operand" "0")))] | 4357 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))] |
3437 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 3438 && (TARGET_IEEE_FP || flag_fast_math) " 3439 "fsqrt") 3440 3441(define_insn "" 3442 [(set (match_operand:DF 0 "register_operand" "=f") 3443 (sqrt:DF (float_extend:DF | 4358 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 4359 && (TARGET_IEEE_FP || flag_fast_math) " 4360 "fsqrt") 4361 4362(define_insn "" 4363 [(set (match_operand:DF 0 "register_operand" "=f") 4364 (sqrt:DF (float_extend:DF |
3444 (match_operand:SF 1 "general_operand" "0"))))] 3445 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 3446 && (TARGET_IEEE_FP || flag_fast_math) " | 4365 (match_operand:SF 1 "register_operand" "0"))))] 4366 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387" |
3447 "fsqrt") 3448 3449(define_insn "sqrtxf2" 3450 [(set (match_operand:XF 0 "register_operand" "=f") | 4367 "fsqrt") 4368 4369(define_insn "sqrtxf2" 4370 [(set (match_operand:XF 0 "register_operand" "=f") |
3451 (sqrt:XF (match_operand:XF 1 "general_operand" "0")))] | 4371 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))] |
3452 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 3453 && (TARGET_IEEE_FP || flag_fast_math) " 3454 "fsqrt") 3455 3456(define_insn "" 3457 [(set (match_operand:XF 0 "register_operand" "=f") 3458 (sqrt:XF (float_extend:XF | 4372 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 4373 && (TARGET_IEEE_FP || flag_fast_math) " 4374 "fsqrt") 4375 4376(define_insn "" 4377 [(set (match_operand:XF 0 "register_operand" "=f") 4378 (sqrt:XF (float_extend:XF |
3459 (match_operand:DF 1 "general_operand" "0"))))] 3460 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 3461 && (TARGET_IEEE_FP || flag_fast_math) " | 4379 (match_operand:DF 1 "register_operand" "0"))))] 4380 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387" |
3462 "fsqrt") 3463 3464(define_insn "" 3465 [(set (match_operand:XF 0 "register_operand" "=f") 3466 (sqrt:XF (float_extend:XF | 4381 "fsqrt") 4382 4383(define_insn "" 4384 [(set (match_operand:XF 0 "register_operand" "=f") 4385 (sqrt:XF (float_extend:XF |
3467 (match_operand:SF 1 "general_operand" "0"))))] 3468 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 3469 && (TARGET_IEEE_FP || flag_fast_math) " | 4386 (match_operand:SF 1 "register_operand" "0"))))] 4387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387" |
3470 "fsqrt") 3471 3472(define_insn "sindf2" 3473 [(set (match_operand:DF 0 "register_operand" "=f") 3474 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))] | 4388 "fsqrt") 4389 4390(define_insn "sindf2" 4391 [(set (match_operand:DF 0 "register_operand" "=f") 4392 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))] |
3475 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 3476 && (TARGET_IEEE_FP || flag_fast_math) " | 4393 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math" |
3477 "fsin") 3478 3479(define_insn "sinsf2" 3480 [(set (match_operand:SF 0 "register_operand" "=f") 3481 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))] | 4394 "fsin") 4395 4396(define_insn "sinsf2" 4397 [(set (match_operand:SF 0 "register_operand" "=f") 4398 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))] |
3482 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 3483 && (TARGET_IEEE_FP || flag_fast_math) " | 4399 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math" |
3484 "fsin") 3485 3486(define_insn "" 3487 [(set (match_operand:DF 0 "register_operand" "=f") 3488 (unspec:DF [(float_extend:DF 3489 (match_operand:SF 1 "register_operand" "0"))] 1))] | 4400 "fsin") 4401 4402(define_insn "" 4403 [(set (match_operand:DF 0 "register_operand" "=f") 4404 (unspec:DF [(float_extend:DF 4405 (match_operand:SF 1 "register_operand" "0"))] 1))] |
3490 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 3491 && (TARGET_IEEE_FP || flag_fast_math) " | 4406 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math" |
3492 "fsin") 3493 3494(define_insn "sinxf2" 3495 [(set (match_operand:XF 0 "register_operand" "=f") 3496 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))] | 4407 "fsin") 4408 4409(define_insn "sinxf2" 4410 [(set (match_operand:XF 0 "register_operand" "=f") 4411 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))] |
3497 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 3498 && (TARGET_IEEE_FP || flag_fast_math) " | 4412 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math" |
3499 "fsin") 3500 3501(define_insn "cosdf2" 3502 [(set (match_operand:DF 0 "register_operand" "=f") 3503 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))] | 4413 "fsin") 4414 4415(define_insn "cosdf2" 4416 [(set (match_operand:DF 0 "register_operand" "=f") 4417 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))] |
3504 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 3505 && (TARGET_IEEE_FP || flag_fast_math) " | 4418 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math" |
3506 "fcos") 3507 3508(define_insn "cossf2" 3509 [(set (match_operand:SF 0 "register_operand" "=f") 3510 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))] | 4419 "fcos") 4420 4421(define_insn "cossf2" 4422 [(set (match_operand:SF 0 "register_operand" "=f") 4423 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))] |
3511 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 3512 && (TARGET_IEEE_FP || flag_fast_math) " | 4424 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math" |
3513 "fcos") 3514 3515(define_insn "" 3516 [(set (match_operand:DF 0 "register_operand" "=f") 3517 (unspec:DF [(float_extend:DF 3518 (match_operand:SF 1 "register_operand" "0"))] 2))] | 4425 "fcos") 4426 4427(define_insn "" 4428 [(set (match_operand:DF 0 "register_operand" "=f") 4429 (unspec:DF [(float_extend:DF 4430 (match_operand:SF 1 "register_operand" "0"))] 2))] |
3519 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 3520 && (TARGET_IEEE_FP || flag_fast_math) " | 4431 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math" |
3521 "fcos") 3522 3523(define_insn "cosxf2" 3524 [(set (match_operand:XF 0 "register_operand" "=f") 3525 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))] | 4432 "fcos") 4433 4434(define_insn "cosxf2" 4435 [(set (match_operand:XF 0 "register_operand" "=f") 4436 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))] |
3526 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 3527 && (TARGET_IEEE_FP || flag_fast_math) " | 4437 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math" |
3528 "fcos") 3529 3530;;- one complement instructions 3531 3532(define_insn "one_cmplsi2" | 4438 "fcos") 4439 4440;;- one complement instructions 4441 4442(define_insn "one_cmplsi2" |
3533 [(set (match_operand:SI 0 "general_operand" "=rm") 3534 (not:SI (match_operand:SI 1 "general_operand" "0")))] | 4443 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 4444 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))] |
3535 "" 3536 "not%L0 %0") 3537 3538(define_insn "one_cmplhi2" | 4445 "" 4446 "not%L0 %0") 4447 4448(define_insn "one_cmplhi2" |
3539 [(set (match_operand:HI 0 "general_operand" "=rm") 3540 (not:HI (match_operand:HI 1 "general_operand" "0")))] | 4449 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") 4450 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))] |
3541 "" 3542 "not%W0 %0") 3543 3544(define_insn "one_cmplqi2" | 4451 "" 4452 "not%W0 %0") 4453 4454(define_insn "one_cmplqi2" |
3545 [(set (match_operand:QI 0 "general_operand" "=qm") 3546 (not:QI (match_operand:QI 1 "general_operand" "0")))] | 4455 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") 4456 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0")))] |
3547 "" 3548 "not%B0 %0") 3549 3550;;- arithmetic shift instructions 3551 3552;; DImode shifts are implemented using the i386 "shift double" opcode, 3553;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count 3554;; is variable, then the count is in %cl and the "imm" operand is dropped --- 5 unchanged lines hidden (view full) --- 3560;; reg, else if the insn is a shift right double, bits are taken from the 3561;; low order bits of reg. So if %eax is "1234" and %edx is "5678", 3562;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345". 3563 3564;; Since sh[lr]d does not change the `reg' operand, that is done 3565;; separately, making all shifts emit pairs of shift double and normal 3566;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to 3567;; support a 63 bit shift, each shift where the count is in a reg expands | 4457 "" 4458 "not%B0 %0") 4459 4460;;- arithmetic shift instructions 4461 4462;; DImode shifts are implemented using the i386 "shift double" opcode, 4463;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count 4464;; is variable, then the count is in %cl and the "imm" operand is dropped --- 5 unchanged lines hidden (view full) --- 4470;; reg, else if the insn is a shift right double, bits are taken from the 4471;; low order bits of reg. So if %eax is "1234" and %edx is "5678", 4472;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345". 4473 4474;; Since sh[lr]d does not change the `reg' operand, that is done 4475;; separately, making all shifts emit pairs of shift double and normal 4476;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to 4477;; support a 63 bit shift, each shift where the count is in a reg expands |
3568;; to three pairs. If the overall shift is by N bits, then the first two 3569;; pairs shift by N / 2 and the last pair by N & 1. | 4478;; to a pair of shifts, a branch, a shift by 32 and a label. |
3570 3571;; If the shift count is a constant, we need never emit more than one 3572;; shift pair, instead using moves and sign extension for counts greater 3573;; than 31. 3574 3575(define_expand "ashldi3" 3576 [(set (match_operand:DI 0 "register_operand" "") 3577 (ashift:DI (match_operand:DI 1 "register_operand" "") --- 13 unchanged lines hidden (view full) --- 3591 3592 DONE; 3593}") 3594 3595(define_insn "ashldi3_const_int" 3596 [(set (match_operand:DI 0 "register_operand" "=&r") 3597 (ashift:DI (match_operand:DI 1 "register_operand" "0") 3598 (match_operand:QI 2 "const_int_operand" "J")))] | 4479 4480;; If the shift count is a constant, we need never emit more than one 4481;; shift pair, instead using moves and sign extension for counts greater 4482;; than 31. 4483 4484(define_expand "ashldi3" 4485 [(set (match_operand:DI 0 "register_operand" "") 4486 (ashift:DI (match_operand:DI 1 "register_operand" "") --- 13 unchanged lines hidden (view full) --- 4500 4501 DONE; 4502}") 4503 4504(define_insn "ashldi3_const_int" 4505 [(set (match_operand:DI 0 "register_operand" "=&r") 4506 (ashift:DI (match_operand:DI 1 "register_operand" "0") 4507 (match_operand:QI 2 "const_int_operand" "J")))] |
3599 "" | 4508 "CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')" |
3600 "* 3601{ 3602 rtx xops[4], low[1], high[1]; 3603 3604 CC_STATUS_INIT; 3605 3606 split_di (operands, 1, low, high); 3607 xops[0] = operands[2]; --- 18 unchanged lines hidden (view full) --- 3626 output_asm_insn (AS2 (sal%L2,%0,%2), xops); 3627 } 3628 RET; 3629}") 3630 3631(define_insn "ashldi3_non_const_int" 3632 [(set (match_operand:DI 0 "register_operand" "=&r") 3633 (ashift:DI (match_operand:DI 1 "register_operand" "0") | 4509 "* 4510{ 4511 rtx xops[4], low[1], high[1]; 4512 4513 CC_STATUS_INIT; 4514 4515 split_di (operands, 1, low, high); 4516 xops[0] = operands[2]; --- 18 unchanged lines hidden (view full) --- 4535 output_asm_insn (AS2 (sal%L2,%0,%2), xops); 4536 } 4537 RET; 4538}") 4539 4540(define_insn "ashldi3_non_const_int" 4541 [(set (match_operand:DI 0 "register_operand" "=&r") 4542 (ashift:DI (match_operand:DI 1 "register_operand" "0") |
3634 (match_operand:QI 2 "register_operand" "c"))) 3635 (clobber (match_dup 2))] | 4543 (match_operand:QI 2 "register_operand" "c")))] |
3636 "" 3637 "* 3638{ | 4544 "" 4545 "* 4546{ |
3639 rtx xops[4], low[1], high[1]; | 4547 rtx xops[5], low[1], high[1]; |
3640 3641 CC_STATUS_INIT; 3642 3643 split_di (operands, 1, low, high); 3644 xops[0] = operands[2]; | 4548 4549 CC_STATUS_INIT; 4550 4551 split_di (operands, 1, low, high); 4552 xops[0] = operands[2]; |
3645 xops[1] = const1_rtx; | 4553 xops[1] = GEN_INT (32); |
3646 xops[2] = low[0]; 3647 xops[3] = high[0]; | 4554 xops[2] = low[0]; 4555 xops[3] = high[0]; |
4556 xops[4] = gen_label_rtx (); |
|
3648 | 4557 |
3649 output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ 3650 | |
3651 output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); 3652 output_asm_insn (AS2 (sal%L2,%0,%2), xops); | 4558 output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); 4559 output_asm_insn (AS2 (sal%L2,%0,%2), xops); |
3653 output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); 3654 output_asm_insn (AS2 (sal%L2,%0,%2), xops); 3655 3656 xops[1] = GEN_INT (7); /* shift count & 1 */ 3657 3658 output_asm_insn (AS2 (shr%B0,%1,%0), xops); 3659 3660 output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); 3661 output_asm_insn (AS2 (sal%L2,%0,%2), xops); 3662 | 4560 output_asm_insn (AS2 (test%B0,%1,%b0), xops); 4561 output_asm_insn (AS1 (je,%X4), xops); 4562 output_asm_insn (AS2 (mov%L3,%2,%3), xops); /* Fast shift by 32 */ 4563 output_asm_insn (AS2 (xor%L2,%2,%2), xops); 4564 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", 4565 CODE_LABEL_NUMBER (xops[4])); |
3663 RET; 3664}") 3665 3666;; On i386 and i486, "addl reg,reg" is faster than "sall $1,reg" 3667;; On i486, movl/sall appears slightly faster than leal, but the leal 3668;; is smaller - use leal for now unless the shift count is 1. 3669 3670(define_insn "ashlsi3" | 4566 RET; 4567}") 4568 4569;; On i386 and i486, "addl reg,reg" is faster than "sall $1,reg" 4570;; On i486, movl/sall appears slightly faster than leal, but the leal 4571;; is smaller - use leal for now unless the shift count is 1. 4572 4573(define_insn "ashlsi3" |
3671 [(set (match_operand:SI 0 "general_operand" "=r,rm") 3672 (ashift:SI (match_operand:SI 1 "general_operand" "r,0") | 4574 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm") 4575 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "r,0") |
3673 (match_operand:SI 2 "nonmemory_operand" "M,cI")))] 3674 "" 3675 "* 3676{ 3677 if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1])) 3678 { | 4576 (match_operand:SI 2 "nonmemory_operand" "M,cI")))] 4577 "" 4578 "* 4579{ 4580 if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1])) 4581 { |
3679 if (!TARGET_386 && INTVAL (operands[2]) == 1) | 4582 if (TARGET_DOUBLE_WITH_ADD && INTVAL (operands[2]) == 1) |
3680 { 3681 output_asm_insn (AS2 (mov%L0,%1,%0), operands); 3682 return AS2 (add%L0,%1,%0); 3683 } 3684 else 3685 { 3686 CC_STATUS_INIT; 3687 3688 if (operands[1] == stack_pointer_rtx) 3689 { 3690 output_asm_insn (AS2 (mov%L0,%1,%0), operands); 3691 operands[1] = operands[0]; 3692 } | 4583 { 4584 output_asm_insn (AS2 (mov%L0,%1,%0), operands); 4585 return AS2 (add%L0,%1,%0); 4586 } 4587 else 4588 { 4589 CC_STATUS_INIT; 4590 4591 if (operands[1] == stack_pointer_rtx) 4592 { 4593 output_asm_insn (AS2 (mov%L0,%1,%0), operands); 4594 operands[1] = operands[0]; 4595 } |
3693 operands[1] = gen_rtx (MULT, SImode, operands[1], 3694 GEN_INT (1 << INTVAL (operands[2]))); | 4596 operands[1] = gen_rtx_MULT (SImode, operands[1], 4597 GEN_INT (1 << INTVAL (operands[2]))); |
3695 return AS2 (lea%L0,%a1,%0); 3696 } 3697 } 3698 3699 if (REG_P (operands[2])) 3700 return AS2 (sal%L0,%b2,%0); 3701 3702 if (REG_P (operands[0]) && operands[2] == const1_rtx) 3703 return AS2 (add%L0,%0,%0); 3704 3705 return AS2 (sal%L0,%2,%0); 3706}") 3707 3708(define_insn "ashlhi3" | 4598 return AS2 (lea%L0,%a1,%0); 4599 } 4600 } 4601 4602 if (REG_P (operands[2])) 4603 return AS2 (sal%L0,%b2,%0); 4604 4605 if (REG_P (operands[0]) && operands[2] == const1_rtx) 4606 return AS2 (add%L0,%0,%0); 4607 4608 return AS2 (sal%L0,%2,%0); 4609}") 4610 4611(define_insn "ashlhi3" |
3709 [(set (match_operand:HI 0 "general_operand" "=rm") 3710 (ashift:HI (match_operand:HI 1 "general_operand" "0") | 4612 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") 4613 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0") |
3711 (match_operand:HI 2 "nonmemory_operand" "cI")))] 3712 "" 3713 "* 3714{ 3715 if (REG_P (operands[2])) 3716 return AS2 (sal%W0,%b2,%0); 3717 3718 if (REG_P (operands[0]) && operands[2] == const1_rtx) 3719 return AS2 (add%W0,%0,%0); 3720 3721 return AS2 (sal%W0,%2,%0); 3722}") 3723 3724(define_insn "ashlqi3" | 4614 (match_operand:HI 2 "nonmemory_operand" "cI")))] 4615 "" 4616 "* 4617{ 4618 if (REG_P (operands[2])) 4619 return AS2 (sal%W0,%b2,%0); 4620 4621 if (REG_P (operands[0]) && operands[2] == const1_rtx) 4622 return AS2 (add%W0,%0,%0); 4623 4624 return AS2 (sal%W0,%2,%0); 4625}") 4626 4627(define_insn "ashlqi3" |
3725 [(set (match_operand:QI 0 "general_operand" "=qm") 3726 (ashift:QI (match_operand:QI 1 "general_operand" "0") | 4628 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") 4629 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0") |
3727 (match_operand:QI 2 "nonmemory_operand" "cI")))] 3728 "" 3729 "* 3730{ 3731 if (REG_P (operands[2])) 3732 return AS2 (sal%B0,%b2,%0); 3733 3734 if (REG_P (operands[0]) && operands[2] == const1_rtx) --- 19 unchanged lines hidden (view full) --- 3754 operands[2])); 3755 } 3756 else 3757 emit_insn (gen_ashrdi3_const_int (operands[0], operands[1], operands[2])); 3758 3759 DONE; 3760}") 3761 | 4630 (match_operand:QI 2 "nonmemory_operand" "cI")))] 4631 "" 4632 "* 4633{ 4634 if (REG_P (operands[2])) 4635 return AS2 (sal%B0,%b2,%0); 4636 4637 if (REG_P (operands[0]) && operands[2] == const1_rtx) --- 19 unchanged lines hidden (view full) --- 4657 operands[2])); 4658 } 4659 else 4660 emit_insn (gen_ashrdi3_const_int (operands[0], operands[1], operands[2])); 4661 4662 DONE; 4663}") 4664 |
4665(define_insn "ashldi3_32" 4666 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m") 4667 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "ro,r") 4668 (const_int 32)))] 4669 "" 4670 "* 4671{ 4672 rtx low[2], high[2], xops[4]; 4673 4674 split_di (operands, 2, low, high); 4675 xops[0] = high[0]; 4676 xops[1] = low[1]; 4677 xops[2] = low[0]; 4678 xops[3] = const0_rtx; 4679 if (!rtx_equal_p (xops[0], xops[1])) 4680 output_asm_insn (AS2 (mov%L0,%1,%0), xops); 4681 4682 if (GET_CODE (low[0]) == MEM) 4683 output_asm_insn (AS2 (mov%L2,%3,%2), xops); 4684 else 4685 output_asm_insn (AS2 (xor%L2,%2,%2), xops); 4686 4687 RET; 4688}") 4689 |
|
3762(define_insn "ashrdi3_const_int" 3763 [(set (match_operand:DI 0 "register_operand" "=&r") 3764 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 3765 (match_operand:QI 2 "const_int_operand" "J")))] | 4690(define_insn "ashrdi3_const_int" 4691 [(set (match_operand:DI 0 "register_operand" "=&r") 4692 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 4693 (match_operand:QI 2 "const_int_operand" "J")))] |
3766 "" | 4694 "CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')" |
3767 "* 3768{ 3769 rtx xops[4], low[1], high[1]; 3770 3771 CC_STATUS_INIT; 3772 3773 split_di (operands, 1, low, high); 3774 xops[0] = operands[2]; --- 20 unchanged lines hidden (view full) --- 3795 } 3796 3797 RET; 3798}") 3799 3800(define_insn "ashrdi3_non_const_int" 3801 [(set (match_operand:DI 0 "register_operand" "=&r") 3802 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | 4695 "* 4696{ 4697 rtx xops[4], low[1], high[1]; 4698 4699 CC_STATUS_INIT; 4700 4701 split_di (operands, 1, low, high); 4702 xops[0] = operands[2]; --- 20 unchanged lines hidden (view full) --- 4723 } 4724 4725 RET; 4726}") 4727 4728(define_insn "ashrdi3_non_const_int" 4729 [(set (match_operand:DI 0 "register_operand" "=&r") 4730 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
3803 (match_operand:QI 2 "register_operand" "c"))) 3804 (clobber (match_dup 2))] | 4731 (match_operand:QI 2 "register_operand" "c")))] |
3805 "" 3806 "* 3807{ | 4732 "" 4733 "* 4734{ |
3808 rtx xops[4], low[1], high[1]; | 4735 rtx xops[5], low[1], high[1]; |
3809 3810 CC_STATUS_INIT; 3811 3812 split_di (operands, 1, low, high); 3813 xops[0] = operands[2]; | 4736 4737 CC_STATUS_INIT; 4738 4739 split_di (operands, 1, low, high); 4740 xops[0] = operands[2]; |
3814 xops[1] = const1_rtx; | 4741 xops[1] = GEN_INT (32); |
3815 xops[2] = low[0]; 3816 xops[3] = high[0]; | 4742 xops[2] = low[0]; 4743 xops[3] = high[0]; |
4744 xops[4] = gen_label_rtx (); |
|
3817 | 4745 |
3818 output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ 3819 | |
3820 output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); 3821 output_asm_insn (AS2 (sar%L3,%0,%3), xops); | 4746 output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); 4747 output_asm_insn (AS2 (sar%L3,%0,%3), xops); |
3822 output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); 3823 output_asm_insn (AS2 (sar%L3,%0,%3), xops); 3824 3825 xops[1] = GEN_INT (7); /* shift count & 1 */ 3826 3827 output_asm_insn (AS2 (shr%B0,%1,%0), xops); 3828 3829 output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); 3830 output_asm_insn (AS2 (sar%L3,%0,%3), xops); 3831 | 4748 output_asm_insn (AS2 (test%B0,%1,%b0), xops); 4749 output_asm_insn (AS1 (je,%X4), xops); 4750 xops[1] = GEN_INT (31); 4751 output_asm_insn (AS2 (mov%L2,%3,%2), xops); 4752 output_asm_insn (AS2 (sar%L3,%1,%3), xops); /* shift by 32 */ 4753 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", 4754 CODE_LABEL_NUMBER (xops[4])); |
3832 RET; 3833}") 3834 3835(define_insn "ashrsi3" | 4755 RET; 4756}") 4757 4758(define_insn "ashrsi3" |
3836 [(set (match_operand:SI 0 "general_operand" "=rm") 3837 (ashiftrt:SI (match_operand:SI 1 "general_operand" "0") | 4759 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 4760 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
3838 (match_operand:SI 2 "nonmemory_operand" "cI")))] 3839 "" 3840 "* 3841{ 3842 if (REG_P (operands[2])) 3843 return AS2 (sar%L0,%b2,%0); 3844 else 3845 return AS2 (sar%L0,%2,%0); 3846}") 3847 3848(define_insn "ashrhi3" | 4761 (match_operand:SI 2 "nonmemory_operand" "cI")))] 4762 "" 4763 "* 4764{ 4765 if (REG_P (operands[2])) 4766 return AS2 (sar%L0,%b2,%0); 4767 else 4768 return AS2 (sar%L0,%2,%0); 4769}") 4770 4771(define_insn "ashrhi3" |
3849 [(set (match_operand:HI 0 "general_operand" "=rm") 3850 (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") | 4772 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") 4773 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") |
3851 (match_operand:HI 2 "nonmemory_operand" "cI")))] 3852 "" 3853 "* 3854{ 3855 if (REG_P (operands[2])) 3856 return AS2 (sar%W0,%b2,%0); 3857 else 3858 return AS2 (sar%W0,%2,%0); 3859}") 3860 3861(define_insn "ashrqi3" | 4774 (match_operand:HI 2 "nonmemory_operand" "cI")))] 4775 "" 4776 "* 4777{ 4778 if (REG_P (operands[2])) 4779 return AS2 (sar%W0,%b2,%0); 4780 else 4781 return AS2 (sar%W0,%2,%0); 4782}") 4783 4784(define_insn "ashrqi3" |
3862 [(set (match_operand:QI 0 "general_operand" "=qm") 3863 (ashiftrt:QI (match_operand:QI 1 "general_operand" "0") | 4785 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") 4786 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") |
3864 (match_operand:QI 2 "nonmemory_operand" "cI")))] 3865 "" 3866 "* 3867{ 3868 if (REG_P (operands[2])) 3869 return AS2 (sar%B0,%b2,%0); 3870 else 3871 return AS2 (sar%B0,%2,%0); --- 18 unchanged lines hidden (view full) --- 3890 operands[2])); 3891 } 3892 else 3893 emit_insn (gen_lshrdi3_const_int (operands[0], operands[1], operands[2])); 3894 3895 DONE; 3896}") 3897 | 4787 (match_operand:QI 2 "nonmemory_operand" "cI")))] 4788 "" 4789 "* 4790{ 4791 if (REG_P (operands[2])) 4792 return AS2 (sar%B0,%b2,%0); 4793 else 4794 return AS2 (sar%B0,%2,%0); --- 18 unchanged lines hidden (view full) --- 4813 operands[2])); 4814 } 4815 else 4816 emit_insn (gen_lshrdi3_const_int (operands[0], operands[1], operands[2])); 4817 4818 DONE; 4819}") 4820 |
4821(define_insn "lshrdi3_32" 4822 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m") 4823 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "ro,r") 4824 (const_int 32)))] 4825 "" 4826 "* 4827{ 4828 rtx low[2], high[2], xops[4]; 4829 4830 split_di (operands, 2, low, high); 4831 xops[0] = low[0]; 4832 xops[1] = high[1]; 4833 xops[2] = high[0]; 4834 xops[3] = const0_rtx; 4835 if (!rtx_equal_p (xops[0], xops[1])) 4836 output_asm_insn (AS2 (mov%L0,%1,%0), xops); 4837 4838 if (GET_CODE (low[0]) == MEM) 4839 output_asm_insn (AS2 (mov%L2,%3,%2), xops); 4840 else 4841 output_asm_insn (AS2 (xor%L2,%2,%2), xops); 4842 4843 RET; 4844}") 4845 |
|
3898(define_insn "lshrdi3_const_int" 3899 [(set (match_operand:DI 0 "register_operand" "=&r") 3900 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") 3901 (match_operand:QI 2 "const_int_operand" "J")))] | 4846(define_insn "lshrdi3_const_int" 4847 [(set (match_operand:DI 0 "register_operand" "=&r") 4848 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") 4849 (match_operand:QI 2 "const_int_operand" "J")))] |
3902 "" | 4850 "CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')" |
3903 "* 3904{ 3905 rtx xops[4], low[1], high[1]; 3906 3907 CC_STATUS_INIT; 3908 3909 split_di (operands, 1, low, high); 3910 xops[0] = operands[2]; --- 19 unchanged lines hidden (view full) --- 3930 } 3931 3932 RET; 3933}") 3934 3935(define_insn "lshrdi3_non_const_int" 3936 [(set (match_operand:DI 0 "register_operand" "=&r") 3937 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | 4851 "* 4852{ 4853 rtx xops[4], low[1], high[1]; 4854 4855 CC_STATUS_INIT; 4856 4857 split_di (operands, 1, low, high); 4858 xops[0] = operands[2]; --- 19 unchanged lines hidden (view full) --- 4878 } 4879 4880 RET; 4881}") 4882 4883(define_insn "lshrdi3_non_const_int" 4884 [(set (match_operand:DI 0 "register_operand" "=&r") 4885 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") |
3938 (match_operand:QI 2 "register_operand" "c"))) 3939 (clobber (match_dup 2))] | 4886 (match_operand:QI 2 "register_operand" "c")))] |
3940 "" 3941 "* 3942{ | 4887 "" 4888 "* 4889{ |
3943 rtx xops[4], low[1], high[1]; | 4890 rtx xops[5], low[1], high[1]; |
3944 3945 CC_STATUS_INIT; 3946 3947 split_di (operands, 1, low, high); 3948 xops[0] = operands[2]; | 4891 4892 CC_STATUS_INIT; 4893 4894 split_di (operands, 1, low, high); 4895 xops[0] = operands[2]; |
3949 xops[1] = const1_rtx; | 4896 xops[1] = GEN_INT (32); |
3950 xops[2] = low[0]; 3951 xops[3] = high[0]; | 4897 xops[2] = low[0]; 4898 xops[3] = high[0]; |
4899 xops[4] = gen_label_rtx (); |
|
3952 | 4900 |
3953 output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ 3954 | |
3955 output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); 3956 output_asm_insn (AS2 (shr%L3,%0,%3), xops); | 4901 output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); 4902 output_asm_insn (AS2 (shr%L3,%0,%3), xops); |
3957 output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); 3958 output_asm_insn (AS2 (shr%L3,%0,%3), xops); 3959 3960 xops[1] = GEN_INT (7); /* shift count & 1 */ 3961 3962 output_asm_insn (AS2 (shr%B0,%1,%0), xops); 3963 3964 output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); 3965 output_asm_insn (AS2 (shr%L3,%0,%3), xops); 3966 | 4903 output_asm_insn (AS2 (test%B0,%1,%b0), xops); 4904 output_asm_insn (AS1 (je,%X4), xops); 4905 output_asm_insn (AS2 (mov%L2,%3,%2), xops); /* Fast shift by 32 */ 4906 output_asm_insn (AS2 (xor%L3,%3,%3), xops); 4907 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", 4908 CODE_LABEL_NUMBER (xops[4])); |
3967 RET; 3968}") 3969 3970(define_insn "lshrsi3" | 4909 RET; 4910}") 4911 4912(define_insn "lshrsi3" |
3971 [(set (match_operand:SI 0 "general_operand" "=rm") 3972 (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") | 4913 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 4914 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
3973 (match_operand:SI 2 "nonmemory_operand" "cI")))] 3974 "" 3975 "* 3976{ 3977 if (REG_P (operands[2])) 3978 return AS2 (shr%L0,%b2,%0); 3979 else 3980 return AS2 (shr%L0,%2,%1); 3981}") 3982 3983(define_insn "lshrhi3" | 4915 (match_operand:SI 2 "nonmemory_operand" "cI")))] 4916 "" 4917 "* 4918{ 4919 if (REG_P (operands[2])) 4920 return AS2 (shr%L0,%b2,%0); 4921 else 4922 return AS2 (shr%L0,%2,%1); 4923}") 4924 4925(define_insn "lshrhi3" |
3984 [(set (match_operand:HI 0 "general_operand" "=rm") 3985 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") | 4926 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") 4927 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") |
3986 (match_operand:HI 2 "nonmemory_operand" "cI")))] 3987 "" 3988 "* 3989{ 3990 if (REG_P (operands[2])) 3991 return AS2 (shr%W0,%b2,%0); 3992 else 3993 return AS2 (shr%W0,%2,%0); 3994}") 3995 3996(define_insn "lshrqi3" | 4928 (match_operand:HI 2 "nonmemory_operand" "cI")))] 4929 "" 4930 "* 4931{ 4932 if (REG_P (operands[2])) 4933 return AS2 (shr%W0,%b2,%0); 4934 else 4935 return AS2 (shr%W0,%2,%0); 4936}") 4937 4938(define_insn "lshrqi3" |
3997 [(set (match_operand:QI 0 "general_operand" "=qm") 3998 (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") | 4939 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") 4940 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") |
3999 (match_operand:QI 2 "nonmemory_operand" "cI")))] 4000 "" 4001 "* 4002{ 4003 if (REG_P (operands[2])) 4004 return AS2 (shr%B0,%b2,%0); 4005 else 4006 return AS2 (shr%B0,%2,%0); 4007}") 4008 4009;;- rotate instructions 4010 4011(define_insn "rotlsi3" | 4941 (match_operand:QI 2 "nonmemory_operand" "cI")))] 4942 "" 4943 "* 4944{ 4945 if (REG_P (operands[2])) 4946 return AS2 (shr%B0,%b2,%0); 4947 else 4948 return AS2 (shr%B0,%2,%0); 4949}") 4950 4951;;- rotate instructions 4952 4953(define_insn "rotlsi3" |
4012 [(set (match_operand:SI 0 "general_operand" "=rm") 4013 (rotate:SI (match_operand:SI 1 "general_operand" "0") | 4954 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 4955 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
4014 (match_operand:SI 2 "nonmemory_operand" "cI")))] 4015 "" 4016 "* 4017{ 4018 if (REG_P (operands[2])) 4019 return AS2 (rol%L0,%b2,%0); 4020 else 4021 return AS2 (rol%L0,%2,%0); 4022}") 4023 4024(define_insn "rotlhi3" | 4956 (match_operand:SI 2 "nonmemory_operand" "cI")))] 4957 "" 4958 "* 4959{ 4960 if (REG_P (operands[2])) 4961 return AS2 (rol%L0,%b2,%0); 4962 else 4963 return AS2 (rol%L0,%2,%0); 4964}") 4965 4966(define_insn "rotlhi3" |
4025 [(set (match_operand:HI 0 "general_operand" "=rm") 4026 (rotate:HI (match_operand:HI 1 "general_operand" "0") | 4967 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") 4968 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0") |
4027 (match_operand:HI 2 "nonmemory_operand" "cI")))] 4028 "" 4029 "* 4030{ 4031 if (REG_P (operands[2])) 4032 return AS2 (rol%W0,%b2,%0); 4033 else 4034 return AS2 (rol%W0,%2,%0); 4035}") 4036 4037(define_insn "rotlqi3" | 4969 (match_operand:HI 2 "nonmemory_operand" "cI")))] 4970 "" 4971 "* 4972{ 4973 if (REG_P (operands[2])) 4974 return AS2 (rol%W0,%b2,%0); 4975 else 4976 return AS2 (rol%W0,%2,%0); 4977}") 4978 4979(define_insn "rotlqi3" |
4038 [(set (match_operand:QI 0 "general_operand" "=qm") 4039 (rotate:QI (match_operand:QI 1 "general_operand" "0") | 4980 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") 4981 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0") |
4040 (match_operand:QI 2 "nonmemory_operand" "cI")))] 4041 "" 4042 "* 4043{ 4044 if (REG_P (operands[2])) 4045 return AS2 (rol%B0,%b2,%0); 4046 else 4047 return AS2 (rol%B0,%2,%0); 4048}") 4049 4050(define_insn "rotrsi3" | 4982 (match_operand:QI 2 "nonmemory_operand" "cI")))] 4983 "" 4984 "* 4985{ 4986 if (REG_P (operands[2])) 4987 return AS2 (rol%B0,%b2,%0); 4988 else 4989 return AS2 (rol%B0,%2,%0); 4990}") 4991 4992(define_insn "rotrsi3" |
4051 [(set (match_operand:SI 0 "general_operand" "=rm") 4052 (rotatert:SI (match_operand:SI 1 "general_operand" "0") | 4993 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 4994 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
4053 (match_operand:SI 2 "nonmemory_operand" "cI")))] 4054 "" 4055 "* 4056{ 4057 if (REG_P (operands[2])) 4058 return AS2 (ror%L0,%b2,%0); 4059 else 4060 return AS2 (ror%L0,%2,%0); 4061}") 4062 4063(define_insn "rotrhi3" | 4995 (match_operand:SI 2 "nonmemory_operand" "cI")))] 4996 "" 4997 "* 4998{ 4999 if (REG_P (operands[2])) 5000 return AS2 (ror%L0,%b2,%0); 5001 else 5002 return AS2 (ror%L0,%2,%0); 5003}") 5004 5005(define_insn "rotrhi3" |
4064 [(set (match_operand:HI 0 "general_operand" "=rm") 4065 (rotatert:HI (match_operand:HI 1 "general_operand" "0") | 5006 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") 5007 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0") |
4066 (match_operand:HI 2 "nonmemory_operand" "cI")))] 4067 "" 4068 "* 4069{ 4070 if (REG_P (operands[2])) 4071 return AS2 (ror%W0,%b2,%0); 4072 else 4073 return AS2 (ror%W0,%2,%0); 4074}") 4075 4076(define_insn "rotrqi3" | 5008 (match_operand:HI 2 "nonmemory_operand" "cI")))] 5009 "" 5010 "* 5011{ 5012 if (REG_P (operands[2])) 5013 return AS2 (ror%W0,%b2,%0); 5014 else 5015 return AS2 (ror%W0,%2,%0); 5016}") 5017 5018(define_insn "rotrqi3" |
4077 [(set (match_operand:QI 0 "general_operand" "=qm") 4078 (rotatert:QI (match_operand:QI 1 "general_operand" "0") | 5019 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") 5020 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0") |
4079 (match_operand:QI 2 "nonmemory_operand" "cI")))] 4080 "" 4081 "* 4082{ 4083 if (REG_P (operands[2])) 4084 return AS2 (ror%B0,%b2,%0); 4085 else 4086 return AS2 (ror%B0,%2,%0); 4087}") 4088 4089/* 4090;; This usually looses. But try a define_expand to recognize a few case 4091;; we can do efficiently, such as accessing the "high" QImode registers, 4092;; %ah, %bh, %ch, %dh. | 5021 (match_operand:QI 2 "nonmemory_operand" "cI")))] 5022 "" 5023 "* 5024{ 5025 if (REG_P (operands[2])) 5026 return AS2 (ror%B0,%b2,%0); 5027 else 5028 return AS2 (ror%B0,%2,%0); 5029}") 5030 5031/* 5032;; This usually looses. But try a define_expand to recognize a few case 5033;; we can do efficiently, such as accessing the "high" QImode registers, 5034;; %ah, %bh, %ch, %dh. |
5035;; ??? Note this has a botch on the mode of operand 0, which needs to be 5036;; fixed if this is ever enabled. |
|
4093(define_insn "insv" 4094 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+&r") | 5037(define_insn "insv" 5038 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+&r") |
4095 (match_operand:SI 1 "general_operand" "i") 4096 (match_operand:SI 2 "general_operand" "i")) 4097 (match_operand:SI 3 "general_operand" "ri"))] | 5039 (match_operand:SI 1 "immediate_operand" "i") 5040 (match_operand:SI 2 "immediate_operand" "i")) 5041 (match_operand:SI 3 "nonmemory_operand" "ri"))] |
4098 "" 4099 "* 4100{ 4101 if (INTVAL (operands[1]) + INTVAL (operands[2]) > GET_MODE_BITSIZE (SImode)) 4102 abort (); 4103 if (GET_CODE (operands[3]) == CONST_INT) 4104 { 4105 unsigned int mask = (1 << INTVAL (operands[1])) - 1; 4106 operands[1] = GEN_INT (~(mask << INTVAL (operands[2]))); 4107 output_asm_insn (AS2 (and%L0,%1,%0), operands); 4108 operands[3] = GEN_INT (INTVAL (operands[3]) << INTVAL (operands[2])); 4109 output_asm_insn (AS2 (or%L0,%3,%0), operands); 4110 } 4111 else 4112 { | 5042 "" 5043 "* 5044{ 5045 if (INTVAL (operands[1]) + INTVAL (operands[2]) > GET_MODE_BITSIZE (SImode)) 5046 abort (); 5047 if (GET_CODE (operands[3]) == CONST_INT) 5048 { 5049 unsigned int mask = (1 << INTVAL (operands[1])) - 1; 5050 operands[1] = GEN_INT (~(mask << INTVAL (operands[2]))); 5051 output_asm_insn (AS2 (and%L0,%1,%0), operands); 5052 operands[3] = GEN_INT (INTVAL (operands[3]) << INTVAL (operands[2])); 5053 output_asm_insn (AS2 (or%L0,%3,%0), operands); 5054 } 5055 else 5056 { |
4113 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0])); | 5057 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); |
4114 if (INTVAL (operands[2])) 4115 output_asm_insn (AS2 (ror%L0,%2,%0), operands); 4116 output_asm_insn (AS3 (shrd%L0,%1,%3,%0), operands); 4117 operands[2] = GEN_INT (BITS_PER_WORD 4118 - INTVAL (operands[1]) - INTVAL (operands[2])); 4119 if (INTVAL (operands[2])) 4120 output_asm_insn (AS2 (ror%L0,%2,%0), operands); 4121 } 4122 RET; 4123}") 4124*/ 4125/* 4126;; ??? There are problems with the mode of operand[3]. The point of this 4127;; is to represent an HImode move to a "high byte" register. 4128 4129(define_expand "insv" 4130 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "") 4131 (match_operand:SI 1 "immediate_operand" "") 4132 (match_operand:SI 2 "immediate_operand" "")) | 5058 if (INTVAL (operands[2])) 5059 output_asm_insn (AS2 (ror%L0,%2,%0), operands); 5060 output_asm_insn (AS3 (shrd%L0,%1,%3,%0), operands); 5061 operands[2] = GEN_INT (BITS_PER_WORD 5062 - INTVAL (operands[1]) - INTVAL (operands[2])); 5063 if (INTVAL (operands[2])) 5064 output_asm_insn (AS2 (ror%L0,%2,%0), operands); 5065 } 5066 RET; 5067}") 5068*/ 5069/* 5070;; ??? There are problems with the mode of operand[3]. The point of this 5071;; is to represent an HImode move to a "high byte" register. 5072 5073(define_expand "insv" 5074 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "") 5075 (match_operand:SI 1 "immediate_operand" "") 5076 (match_operand:SI 2 "immediate_operand" "")) |
4133 (match_operand:QI 3 "general_operand" "ri"))] | 5077 (match_operand:QI 3 "nonmemory_operand" "ri"))] |
4134 "" 4135 " 4136{ 4137 if (GET_CODE (operands[1]) != CONST_INT 4138 || GET_CODE (operands[2]) != CONST_INT) 4139 FAIL; 4140 4141 if (! (INTVAL (operands[1]) == 8 4142 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 0)) 4143 && ! INTVAL (operands[1]) == 1) 4144 FAIL; 4145}") | 5078 "" 5079 " 5080{ 5081 if (GET_CODE (operands[1]) != CONST_INT 5082 || GET_CODE (operands[2]) != CONST_INT) 5083 FAIL; 5084 5085 if (! (INTVAL (operands[1]) == 8 5086 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 0)) 5087 && ! INTVAL (operands[1]) == 1) 5088 FAIL; 5089}") |
4146 4147;; ??? Are these constraints right? 4148(define_insn "" 4149 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+&qo") 4150 (const_int 8) 4151 (const_int 8)) 4152 (match_operand:QI 1 "general_operand" "qn"))] 4153 "" 4154 "* 4155{ 4156 if (REG_P (operands[0])) 4157 return AS2 (mov%B0,%1,%h0); 4158 4159 operands[0] = adj_offsettable_operand (operands[0], 1); 4160 return AS2 (mov%B0,%1,%0); 4161}") | |
4162*/ 4163 4164;; On i386, the register count for a bit operation is *not* truncated, 4165;; so SHIFT_COUNT_TRUNCATED must not be defined. 4166 4167;; On i486, the shift & or/and code is faster than bts or btr. If 4168;; operands[0] is a MEM, the bt[sr] is half as fast as the normal code. 4169 4170;; On i386, bts is a little faster if operands[0] is a reg, and a 4171;; little slower if operands[0] is a MEM, than the shift & or/and code. 4172;; Use bts & btr, since they reload better. 4173 4174;; General bit set and clear. 4175(define_insn "" | 5090*/ 5091 5092;; On i386, the register count for a bit operation is *not* truncated, 5093;; so SHIFT_COUNT_TRUNCATED must not be defined. 5094 5095;; On i486, the shift & or/and code is faster than bts or btr. If 5096;; operands[0] is a MEM, the bt[sr] is half as fast as the normal code. 5097 5098;; On i386, bts is a little faster if operands[0] is a reg, and a 5099;; little slower if operands[0] is a MEM, than the shift & or/and code. 5100;; Use bts & btr, since they reload better. 5101 5102;; General bit set and clear. 5103(define_insn "" |
4176 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+rm") | 5104 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+rm") |
4177 (const_int 1) | 5105 (const_int 1) |
4178 (match_operand:SI 2 "general_operand" "r")) | 5106 (match_operand:SI 2 "register_operand" "r")) |
4179 (match_operand:SI 3 "const_int_operand" "n"))] | 5107 (match_operand:SI 3 "const_int_operand" "n"))] |
4180 "TARGET_386 && GET_CODE (operands[2]) != CONST_INT" | 5108 "TARGET_USE_BIT_TEST && GET_CODE (operands[2]) != CONST_INT" |
4181 "* 4182{ 4183 CC_STATUS_INIT; 4184 4185 if (INTVAL (operands[3]) == 1) 4186 return AS2 (bts%L0,%2,%0); 4187 else 4188 return AS2 (btr%L0,%2,%0); 4189}") 4190 4191;; Bit complement. See comments on previous pattern. 4192;; ??? Is this really worthwhile? 4193(define_insn "" | 5109 "* 5110{ 5111 CC_STATUS_INIT; 5112 5113 if (INTVAL (operands[3]) == 1) 5114 return AS2 (bts%L0,%2,%0); 5115 else 5116 return AS2 (btr%L0,%2,%0); 5117}") 5118 5119;; Bit complement. See comments on previous pattern. 5120;; ??? Is this really worthwhile? 5121(define_insn "" |
4194 [(set (match_operand:SI 0 "general_operand" "=rm") | 5122 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
4195 (xor:SI (ashift:SI (const_int 1) | 5123 (xor:SI (ashift:SI (const_int 1) |
4196 (match_operand:SI 1 "general_operand" "r")) 4197 (match_operand:SI 2 "general_operand" "0")))] 4198 "TARGET_386 && GET_CODE (operands[1]) != CONST_INT" | 5124 (match_operand:SI 1 "register_operand" "r")) 5125 (match_operand:SI 2 "nonimmediate_operand" "0")))] 5126 "TARGET_USE_BIT_TEST && GET_CODE (operands[1]) != CONST_INT" |
4199 "* 4200{ 4201 CC_STATUS_INIT; 4202 4203 return AS2 (btc%L0,%1,%0); 4204}") 4205 4206(define_insn "" | 5127 "* 5128{ 5129 CC_STATUS_INIT; 5130 5131 return AS2 (btc%L0,%1,%0); 5132}") 5133 5134(define_insn "" |
4207 [(set (match_operand:SI 0 "general_operand" "=rm") 4208 (xor:SI (match_operand:SI 1 "general_operand" "0") | 5135 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 5136 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
4209 (ashift:SI (const_int 1) | 5137 (ashift:SI (const_int 1) |
4210 (match_operand:SI 2 "general_operand" "r"))))] 4211 "TARGET_386 && GET_CODE (operands[2]) != CONST_INT" | 5138 (match_operand:SI 2 "register_operand" "r"))))] 5139 "TARGET_USE_BIT_TEST && GET_CODE (operands[2]) != CONST_INT" |
4212 "* 4213{ 4214 CC_STATUS_INIT; 4215 4216 return AS2 (btc%L0,%2,%0); 4217}") 4218 4219;; Recognizers for bit-test instructions. --- 4 unchanged lines hidden (view full) --- 4224 4225;; ??? The first argument of a zero_extract must not be reloaded, so 4226;; don't allow a MEM in the operand predicate without allowing it in the 4227;; constraint. 4228 4229(define_insn "" 4230 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r") 4231 (const_int 1) | 5140 "* 5141{ 5142 CC_STATUS_INIT; 5143 5144 return AS2 (btc%L0,%2,%0); 5145}") 5146 5147;; Recognizers for bit-test instructions. --- 4 unchanged lines hidden (view full) --- 5152 5153;; ??? The first argument of a zero_extract must not be reloaded, so 5154;; don't allow a MEM in the operand predicate without allowing it in the 5155;; constraint. 5156 5157(define_insn "" 5158 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r") 5159 (const_int 1) |
4232 (match_operand:SI 1 "general_operand" "r")))] | 5160 (match_operand:SI 1 "register_operand" "r")))] |
4233 "GET_CODE (operands[1]) != CONST_INT" 4234 "* 4235{ 4236 cc_status.flags |= CC_Z_IN_NOT_C; 4237 return AS2 (bt%L0,%1,%0); 4238}") 4239 4240(define_insn "" --- 26 unchanged lines hidden (view full) --- 4267 4268 return AS2 (test%L0,%1,%0); 4269}") 4270 4271;; ??? All bets are off if operand 0 is a volatile MEM reference. 4272;; The CPU may access unspecified bytes around the actual target byte. 4273 4274(define_insn "" | 5161 "GET_CODE (operands[1]) != CONST_INT" 5162 "* 5163{ 5164 cc_status.flags |= CC_Z_IN_NOT_C; 5165 return AS2 (bt%L0,%1,%0); 5166}") 5167 5168(define_insn "" --- 26 unchanged lines hidden (view full) --- 5195 5196 return AS2 (test%L0,%1,%0); 5197}") 5198 5199;; ??? All bets are off if operand 0 is a volatile MEM reference. 5200;; The CPU may access unspecified bytes around the actual target byte. 5201 5202(define_insn "" |
4275 [(set (cc0) (zero_extract (match_operand:QI 0 "general_operand" "rm") | 5203 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m") |
4276 (match_operand:SI 1 "const_int_operand" "n") 4277 (match_operand:SI 2 "const_int_operand" "n")))] 4278 "GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0])" 4279 "* 4280{ 4281 unsigned int mask; 4282 4283 mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]); --- 114 unchanged lines hidden (view full) --- 4398 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") 4399 4400(define_insn "" 4401 [(set (match_operand:QI 0 "register_operand" "=q") 4402 (gt:QI (cc0) (const_int 0)))] 4403 "" 4404 "* 4405{ | 5204 (match_operand:SI 1 "const_int_operand" "n") 5205 (match_operand:SI 2 "const_int_operand" "n")))] 5206 "GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0])" 5207 "* 5208{ 5209 unsigned int mask; 5210 5211 mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]); --- 114 unchanged lines hidden (view full) --- 5326 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") 5327 5328(define_insn "" 5329 [(set (match_operand:QI 0 "register_operand" "=q") 5330 (gt:QI (cc0) (const_int 0)))] 5331 "" 5332 "* 5333{ |
4406 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) | 5334 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387) 5335 && ! (cc_prev_status.flags & CC_FCOMI)) |
4407 return AS1 (sete,%0); 4408 4409 OUTPUT_JUMP (\"setg %0\", \"seta %0\", NULL_PTR); 4410}") 4411 4412(define_expand "sgtu" 4413 [(match_dup 1) 4414 (set (match_operand:QI 0 "register_operand" "") --- 15 unchanged lines hidden (view full) --- 4430 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") 4431 4432(define_insn "" 4433 [(set (match_operand:QI 0 "register_operand" "=q") 4434 (lt:QI (cc0) (const_int 0)))] 4435 "" 4436 "* 4437{ | 5336 return AS1 (sete,%0); 5337 5338 OUTPUT_JUMP (\"setg %0\", \"seta %0\", NULL_PTR); 5339}") 5340 5341(define_expand "sgtu" 5342 [(match_dup 1) 5343 (set (match_operand:QI 0 "register_operand" "") --- 15 unchanged lines hidden (view full) --- 5359 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") 5360 5361(define_insn "" 5362 [(set (match_operand:QI 0 "register_operand" "=q") 5363 (lt:QI (cc0) (const_int 0)))] 5364 "" 5365 "* 5366{ |
4438 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) | 5367 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387) 5368 && ! (cc_prev_status.flags & CC_FCOMI)) |
4439 return AS1 (sete,%0); 4440 4441 OUTPUT_JUMP (\"setl %0\", \"setb %0\", \"sets %0\"); 4442}") 4443 4444(define_expand "sltu" 4445 [(match_dup 1) 4446 (set (match_operand:QI 0 "register_operand" "") --- 15 unchanged lines hidden (view full) --- 4462 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") 4463 4464(define_insn "" 4465 [(set (match_operand:QI 0 "register_operand" "=q") 4466 (ge:QI (cc0) (const_int 0)))] 4467 "" 4468 "* 4469{ | 5369 return AS1 (sete,%0); 5370 5371 OUTPUT_JUMP (\"setl %0\", \"setb %0\", \"sets %0\"); 5372}") 5373 5374(define_expand "sltu" 5375 [(match_dup 1) 5376 (set (match_operand:QI 0 "register_operand" "") --- 15 unchanged lines hidden (view full) --- 5392 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") 5393 5394(define_insn "" 5395 [(set (match_operand:QI 0 "register_operand" "=q") 5396 (ge:QI (cc0) (const_int 0)))] 5397 "" 5398 "* 5399{ |
4470 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) | 5400 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387) 5401 && ! (cc_prev_status.flags & CC_FCOMI)) |
4471 return AS1 (sete,%0); 4472 4473 OUTPUT_JUMP (\"setge %0\", \"setae %0\", \"setns %0\"); 4474}") 4475 4476(define_expand "sgeu" 4477 [(match_dup 1) 4478 (set (match_operand:QI 0 "register_operand" "") --- 15 unchanged lines hidden (view full) --- 4494 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") 4495 4496(define_insn "" 4497 [(set (match_operand:QI 0 "register_operand" "=q") 4498 (le:QI (cc0) (const_int 0)))] 4499 "" 4500 "* 4501{ | 5402 return AS1 (sete,%0); 5403 5404 OUTPUT_JUMP (\"setge %0\", \"setae %0\", \"setns %0\"); 5405}") 5406 5407(define_expand "sgeu" 5408 [(match_dup 1) 5409 (set (match_operand:QI 0 "register_operand" "") --- 15 unchanged lines hidden (view full) --- 5425 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") 5426 5427(define_insn "" 5428 [(set (match_operand:QI 0 "register_operand" "=q") 5429 (le:QI (cc0) (const_int 0)))] 5430 "" 5431 "* 5432{ |
4502 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) | 5433 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387) 5434 && ! (cc_prev_status.flags & CC_FCOMI)) |
4503 return AS1 (setb,%0); 4504 4505 OUTPUT_JUMP (\"setle %0\", \"setbe %0\", NULL_PTR); 4506}") 4507 4508(define_expand "sleu" 4509 [(match_dup 1) 4510 (set (match_operand:QI 0 "register_operand" "") --- 37 unchanged lines hidden (view full) --- 4548 (label_ref (match_operand 0 "" "")) 4549 (pc)))] 4550 "" 4551 "* 4552{ 4553 if (cc_prev_status.flags & CC_Z_IN_NOT_C) 4554 return \"jnc %l0\"; 4555 else | 5435 return AS1 (setb,%0); 5436 5437 OUTPUT_JUMP (\"setle %0\", \"setbe %0\", NULL_PTR); 5438}") 5439 5440(define_expand "sleu" 5441 [(match_dup 1) 5442 (set (match_operand:QI 0 "register_operand" "") --- 37 unchanged lines hidden (view full) --- 5480 (label_ref (match_operand 0 "" "")) 5481 (pc)))] 5482 "" 5483 "* 5484{ 5485 if (cc_prev_status.flags & CC_Z_IN_NOT_C) 5486 return \"jnc %l0\"; 5487 else |
5488 if (cc_prev_status.flags & CC_TEST_AX) 5489 { 5490 operands[1] = gen_rtx_REG (SImode, 0); 5491 operands[2] = GEN_INT (0x4000); 5492 output_asm_insn (AS2 (testl,%2,%1), operands); 5493 return AS1 (jne,%l0); 5494 } 5495 |
|
4556 return \"je %l0\"; 4557}") 4558 4559(define_expand "bne" 4560 [(match_dup 1) 4561 (set (pc) 4562 (if_then_else (ne (cc0) 4563 (const_int 0)) --- 16 unchanged lines hidden (view full) --- 4580 (label_ref (match_operand 0 "" "")) 4581 (pc)))] 4582 "" 4583 "* 4584{ 4585 if (cc_prev_status.flags & CC_Z_IN_NOT_C) 4586 return \"jc %l0\"; 4587 else | 5496 return \"je %l0\"; 5497}") 5498 5499(define_expand "bne" 5500 [(match_dup 1) 5501 (set (pc) 5502 (if_then_else (ne (cc0) 5503 (const_int 0)) --- 16 unchanged lines hidden (view full) --- 5520 (label_ref (match_operand 0 "" "")) 5521 (pc)))] 5522 "" 5523 "* 5524{ 5525 if (cc_prev_status.flags & CC_Z_IN_NOT_C) 5526 return \"jc %l0\"; 5527 else |
5528 if (cc_prev_status.flags & CC_TEST_AX) 5529 { 5530 operands[1] = gen_rtx_REG (SImode, 0); 5531 operands[2] = GEN_INT (0x4000); 5532 output_asm_insn (AS2 (testl,%2,%1), operands); 5533 return AS1 (je,%l0); 5534 } 5535 |
|
4588 return \"jne %l0\"; 4589}") 4590 4591(define_expand "bgt" 4592 [(match_dup 1) 4593 (set (pc) 4594 (if_then_else (gt (cc0) 4595 (const_int 0)) --- 6 unchanged lines hidden (view full) --- 4602 [(set (pc) 4603 (if_then_else (gt (cc0) 4604 (const_int 0)) 4605 (label_ref (match_operand 0 "" "")) 4606 (pc)))] 4607 "" 4608 "* 4609{ | 5536 return \"jne %l0\"; 5537}") 5538 5539(define_expand "bgt" 5540 [(match_dup 1) 5541 (set (pc) 5542 (if_then_else (gt (cc0) 5543 (const_int 0)) --- 6 unchanged lines hidden (view full) --- 5550 [(set (pc) 5551 (if_then_else (gt (cc0) 5552 (const_int 0)) 5553 (label_ref (match_operand 0 "" "")) 5554 (pc)))] 5555 "" 5556 "* 5557{ |
4610 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) | 5558 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387) 5559 && ! (cc_prev_status.flags & CC_FCOMI)) |
4611 return AS1 (je,%l0); 4612 | 5560 return AS1 (je,%l0); 5561 |
5562 if (cc_prev_status.flags & CC_TEST_AX) 5563 { 5564 operands[1] = gen_rtx_REG (SImode, 0); 5565 operands[2] = GEN_INT (0x4100); 5566 output_asm_insn (AS2 (testl,%2,%1), operands); 5567 return AS1 (je,%l0); 5568 } |
|
4613 OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR); 4614}") 4615 4616(define_expand "bgtu" 4617 [(match_dup 1) 4618 (set (pc) 4619 (if_then_else (gtu (cc0) 4620 (const_int 0)) --- 25 unchanged lines hidden (view full) --- 4646 [(set (pc) 4647 (if_then_else (lt (cc0) 4648 (const_int 0)) 4649 (label_ref (match_operand 0 "" "")) 4650 (pc)))] 4651 "" 4652 "* 4653{ | 5569 OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR); 5570}") 5571 5572(define_expand "bgtu" 5573 [(match_dup 1) 5574 (set (pc) 5575 (if_then_else (gtu (cc0) 5576 (const_int 0)) --- 25 unchanged lines hidden (view full) --- 5602 [(set (pc) 5603 (if_then_else (lt (cc0) 5604 (const_int 0)) 5605 (label_ref (match_operand 0 "" "")) 5606 (pc)))] 5607 "" 5608 "* 5609{ |
4654 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) | 5610 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387) 5611 && ! (cc_prev_status.flags & CC_FCOMI)) |
4655 return AS1 (je,%l0); 4656 | 5612 return AS1 (je,%l0); 5613 |
5614 if (cc_prev_status.flags & CC_TEST_AX) 5615 { 5616 operands[1] = gen_rtx_REG (SImode, 0); 5617 operands[2] = GEN_INT (0x100); 5618 output_asm_insn (AS2 (testl,%2,%1), operands); 5619 return AS1 (jne,%l0); 5620 } |
|
4657 OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\"); 4658}") 4659 4660(define_expand "bltu" 4661 [(match_dup 1) 4662 (set (pc) 4663 (if_then_else (ltu (cc0) 4664 (const_int 0)) --- 25 unchanged lines hidden (view full) --- 4690 [(set (pc) 4691 (if_then_else (ge (cc0) 4692 (const_int 0)) 4693 (label_ref (match_operand 0 "" "")) 4694 (pc)))] 4695 "" 4696 "* 4697{ | 5621 OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\"); 5622}") 5623 5624(define_expand "bltu" 5625 [(match_dup 1) 5626 (set (pc) 5627 (if_then_else (ltu (cc0) 5628 (const_int 0)) --- 25 unchanged lines hidden (view full) --- 5654 [(set (pc) 5655 (if_then_else (ge (cc0) 5656 (const_int 0)) 5657 (label_ref (match_operand 0 "" "")) 5658 (pc)))] 5659 "" 5660 "* 5661{ |
4698 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) | 5662 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387) 5663 && ! (cc_prev_status.flags & CC_FCOMI)) |
4699 return AS1 (je,%l0); | 5664 return AS1 (je,%l0); |
4700 | 5665 if (cc_prev_status.flags & CC_TEST_AX) 5666 { 5667 operands[1] = gen_rtx_REG (SImode, 0); 5668 operands[2] = GEN_INT (0x100); 5669 output_asm_insn (AS2 (testl,%2,%1), operands); 5670 return AS1 (je,%l0); 5671 } |
4701 OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\"); 4702}") 4703 4704(define_expand "bgeu" 4705 [(match_dup 1) 4706 (set (pc) 4707 (if_then_else (geu (cc0) 4708 (const_int 0)) --- 25 unchanged lines hidden (view full) --- 4734 [(set (pc) 4735 (if_then_else (le (cc0) 4736 (const_int 0)) 4737 (label_ref (match_operand 0 "" "")) 4738 (pc)))] 4739 "" 4740 "* 4741{ | 5672 OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\"); 5673}") 5674 5675(define_expand "bgeu" 5676 [(match_dup 1) 5677 (set (pc) 5678 (if_then_else (geu (cc0) 5679 (const_int 0)) --- 25 unchanged lines hidden (view full) --- 5705 [(set (pc) 5706 (if_then_else (le (cc0) 5707 (const_int 0)) 5708 (label_ref (match_operand 0 "" "")) 5709 (pc)))] 5710 "" 5711 "* 5712{ |
4742 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) | 5713 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387) 5714 && ! (cc_prev_status.flags & CC_FCOMI)) |
4743 return AS1 (jb,%l0); | 5715 return AS1 (jb,%l0); |
5716 if (cc_prev_status.flags & CC_TEST_AX) 5717 { 5718 operands[1] = gen_rtx_REG (SImode, 0); 5719 operands[2] = GEN_INT (0x4100); 5720 output_asm_insn (AS2 (testl,%2,%1), operands); 5721 return AS1 (jne,%l0); 5722 } |
|
4744 4745 OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR); 4746}") 4747 4748(define_expand "bleu" 4749 [(match_dup 1) 4750 (set (pc) 4751 (if_then_else (leu (cc0) --- 21 unchanged lines hidden (view full) --- 4773 (pc) 4774 (label_ref (match_operand 0 "" ""))))] 4775 "" 4776 "* 4777{ 4778 if (cc_prev_status.flags & CC_Z_IN_NOT_C) 4779 return \"jc %l0\"; 4780 else | 5723 5724 OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR); 5725}") 5726 5727(define_expand "bleu" 5728 [(match_dup 1) 5729 (set (pc) 5730 (if_then_else (leu (cc0) --- 21 unchanged lines hidden (view full) --- 5752 (pc) 5753 (label_ref (match_operand 0 "" ""))))] 5754 "" 5755 "* 5756{ 5757 if (cc_prev_status.flags & CC_Z_IN_NOT_C) 5758 return \"jc %l0\"; 5759 else |
5760 if (cc_prev_status.flags & CC_TEST_AX) 5761 { 5762 operands[1] = gen_rtx_REG (SImode, 0); 5763 operands[2] = GEN_INT (0x4000); 5764 output_asm_insn (AS2 (testl,%2,%1), operands); 5765 return AS1 (je,%l0); 5766 } |
|
4781 return \"jne %l0\"; 4782}") 4783 4784(define_insn "" 4785 [(set (pc) 4786 (if_then_else (ne (cc0) 4787 (const_int 0)) 4788 (pc) 4789 (label_ref (match_operand 0 "" ""))))] 4790 "" 4791 "* 4792{ 4793 if (cc_prev_status.flags & CC_Z_IN_NOT_C) 4794 return \"jnc %l0\"; 4795 else | 5767 return \"jne %l0\"; 5768}") 5769 5770(define_insn "" 5771 [(set (pc) 5772 (if_then_else (ne (cc0) 5773 (const_int 0)) 5774 (pc) 5775 (label_ref (match_operand 0 "" ""))))] 5776 "" 5777 "* 5778{ 5779 if (cc_prev_status.flags & CC_Z_IN_NOT_C) 5780 return \"jnc %l0\"; 5781 else |
5782 if (cc_prev_status.flags & CC_TEST_AX) 5783 { 5784 operands[1] = gen_rtx_REG (SImode, 0); 5785 operands[2] = GEN_INT (0x4000); 5786 output_asm_insn (AS2 (testl,%2,%1), operands); 5787 return AS1 (jne,%l0); 5788 } |
|
4796 return \"je %l0\"; 4797}") 4798 4799(define_insn "" 4800 [(set (pc) 4801 (if_then_else (gt (cc0) 4802 (const_int 0)) 4803 (pc) 4804 (label_ref (match_operand 0 "" ""))))] 4805 "" 4806 "* 4807{ | 5789 return \"je %l0\"; 5790}") 5791 5792(define_insn "" 5793 [(set (pc) 5794 (if_then_else (gt (cc0) 5795 (const_int 0)) 5796 (pc) 5797 (label_ref (match_operand 0 "" ""))))] 5798 "" 5799 "* 5800{ |
4808 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) | 5801 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387) 5802 && ! (cc_prev_status.flags & CC_FCOMI)) |
4809 return AS1 (jne,%l0); | 5803 return AS1 (jne,%l0); |
4810 | 5804 if (cc_prev_status.flags & CC_TEST_AX) 5805 { 5806 operands[1] = gen_rtx_REG (SImode, 0); 5807 operands[2] = GEN_INT (0x4100); 5808 output_asm_insn (AS2 (testl,%2,%1), operands); 5809 return AS1 (jne,%l0); 5810 } |
4811 OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR); 4812}") 4813 4814(define_insn "" 4815 [(set (pc) 4816 (if_then_else (gtu (cc0) 4817 (const_int 0)) 4818 (pc) --- 5 unchanged lines hidden (view full) --- 4824 [(set (pc) 4825 (if_then_else (lt (cc0) 4826 (const_int 0)) 4827 (pc) 4828 (label_ref (match_operand 0 "" ""))))] 4829 "" 4830 "* 4831{ | 5811 OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR); 5812}") 5813 5814(define_insn "" 5815 [(set (pc) 5816 (if_then_else (gtu (cc0) 5817 (const_int 0)) 5818 (pc) --- 5 unchanged lines hidden (view full) --- 5824 [(set (pc) 5825 (if_then_else (lt (cc0) 5826 (const_int 0)) 5827 (pc) 5828 (label_ref (match_operand 0 "" ""))))] 5829 "" 5830 "* 5831{ |
4832 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) | 5832 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387) 5833 && ! (cc_prev_status.flags & CC_FCOMI)) |
4833 return AS1 (jne,%l0); | 5834 return AS1 (jne,%l0); |
5835 if (cc_prev_status.flags & CC_TEST_AX) 5836 { 5837 operands[1] = gen_rtx_REG (SImode, 0); 5838 operands[2] = GEN_INT (0x100); 5839 output_asm_insn (AS2 (testl,%2,%1), operands); 5840 return AS1 (je,%l0); 5841 } |
|
4834 4835 OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\"); 4836}") 4837 4838(define_insn "" 4839 [(set (pc) 4840 (if_then_else (ltu (cc0) 4841 (const_int 0)) --- 6 unchanged lines hidden (view full) --- 4848 [(set (pc) 4849 (if_then_else (ge (cc0) 4850 (const_int 0)) 4851 (pc) 4852 (label_ref (match_operand 0 "" ""))))] 4853 "" 4854 "* 4855{ | 5842 5843 OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\"); 5844}") 5845 5846(define_insn "" 5847 [(set (pc) 5848 (if_then_else (ltu (cc0) 5849 (const_int 0)) --- 6 unchanged lines hidden (view full) --- 5856 [(set (pc) 5857 (if_then_else (ge (cc0) 5858 (const_int 0)) 5859 (pc) 5860 (label_ref (match_operand 0 "" ""))))] 5861 "" 5862 "* 5863{ |
4856 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) | 5864 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387) 5865 && ! (cc_prev_status.flags & CC_FCOMI)) |
4857 return AS1 (jne,%l0); | 5866 return AS1 (jne,%l0); |
4858 | 5867 if (cc_prev_status.flags & CC_TEST_AX) 5868 { 5869 operands[1] = gen_rtx_REG (SImode, 0); 5870 operands[2] = GEN_INT (0x100); 5871 output_asm_insn (AS2 (testl,%2,%1), operands); 5872 return AS1 (jne,%l0); 5873 } |
4859 OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\"); 4860}") 4861 4862(define_insn "" 4863 [(set (pc) 4864 (if_then_else (geu (cc0) 4865 (const_int 0)) 4866 (pc) --- 5 unchanged lines hidden (view full) --- 4872 [(set (pc) 4873 (if_then_else (le (cc0) 4874 (const_int 0)) 4875 (pc) 4876 (label_ref (match_operand 0 "" ""))))] 4877 "" 4878 "* 4879{ | 5874 OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\"); 5875}") 5876 5877(define_insn "" 5878 [(set (pc) 5879 (if_then_else (geu (cc0) 5880 (const_int 0)) 5881 (pc) --- 5 unchanged lines hidden (view full) --- 5887 [(set (pc) 5888 (if_then_else (le (cc0) 5889 (const_int 0)) 5890 (pc) 5891 (label_ref (match_operand 0 "" ""))))] 5892 "" 5893 "* 5894{ |
4880 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) | 5895 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387) 5896 && ! (cc_prev_status.flags & CC_FCOMI)) |
4881 return AS1 (jae,%l0); 4882 | 5897 return AS1 (jae,%l0); 5898 |
5899 if (cc_prev_status.flags & CC_TEST_AX) 5900 { 5901 operands[1] = gen_rtx_REG (SImode, 0); 5902 operands[2] = GEN_INT (0x4100); 5903 output_asm_insn (AS2 (testl,%2,%1), operands); 5904 return AS1 (je,%l0); 5905 } |
|
4883 OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR); 4884}") 4885 4886(define_insn "" 4887 [(set (pc) 4888 (if_then_else (leu (cc0) 4889 (const_int 0)) 4890 (pc) --- 5 unchanged lines hidden (view full) --- 4896 4897(define_insn "jump" 4898 [(set (pc) 4899 (label_ref (match_operand 0 "" "")))] 4900 "" 4901 "jmp %l0") 4902 4903(define_insn "indirect_jump" | 5906 OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR); 5907}") 5908 5909(define_insn "" 5910 [(set (pc) 5911 (if_then_else (leu (cc0) 5912 (const_int 0)) 5913 (pc) --- 5 unchanged lines hidden (view full) --- 5919 5920(define_insn "jump" 5921 [(set (pc) 5922 (label_ref (match_operand 0 "" "")))] 5923 "" 5924 "jmp %l0") 5925 5926(define_insn "indirect_jump" |
4904 [(set (pc) (match_operand:SI 0 "general_operand" "rm"))] | 5927 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))] |
4905 "" 4906 "* 4907{ 4908 CC_STATUS_INIT; 4909 4910 return AS1 (jmp,%*%0); 4911}") 4912 --- 11 unchanged lines hidden (view full) --- 4924 (plus:SI (match_dup 0) 4925 (const_int -1)))])] 4926 "" 4927 "") 4928 4929(define_insn "" 4930 [(set (pc) 4931 (if_then_else (match_operator 0 "arithmetic_comparison_operator" | 5928 "" 5929 "* 5930{ 5931 CC_STATUS_INIT; 5932 5933 return AS1 (jmp,%*%0); 5934}") 5935 --- 11 unchanged lines hidden (view full) --- 5947 (plus:SI (match_dup 0) 5948 (const_int -1)))])] 5949 "" 5950 "") 5951 5952(define_insn "" 5953 [(set (pc) 5954 (if_then_else (match_operator 0 "arithmetic_comparison_operator" |
4932 [(plus:SI (match_operand:SI 1 "general_operand" "+r,m") | 5955 [(plus:SI (match_operand:SI 1 "nonimmediate_operand" "+r,m") |
4933 (match_operand:SI 2 "general_operand" "rmi,ri")) 4934 (const_int 0)]) 4935 (label_ref (match_operand 3 "" "")) 4936 (pc))) 4937 (set (match_dup 1) 4938 (plus:SI (match_dup 1) 4939 (match_dup 2)))] 4940 "" 4941 "* 4942{ 4943 CC_STATUS_INIT; 4944 if (operands[2] == constm1_rtx) 4945 output_asm_insn (AS1 (dec%L1,%1), operands); 4946 | 5956 (match_operand:SI 2 "general_operand" "rmi,ri")) 5957 (const_int 0)]) 5958 (label_ref (match_operand 3 "" "")) 5959 (pc))) 5960 (set (match_dup 1) 5961 (plus:SI (match_dup 1) 5962 (match_dup 2)))] 5963 "" 5964 "* 5965{ 5966 CC_STATUS_INIT; 5967 if (operands[2] == constm1_rtx) 5968 output_asm_insn (AS1 (dec%L1,%1), operands); 5969 |
4947 else if (operands[1] == const1_rtx) | 5970 else if (operands[2] == const1_rtx) |
4948 output_asm_insn (AS1 (inc%L1,%1), operands); 4949 4950 else 4951 output_asm_insn (AS2 (add%L1,%2,%1), operands); 4952 4953 return AS1 (%J0,%l3); 4954}") 4955 4956(define_insn "" 4957 [(set (pc) 4958 (if_then_else (match_operator 0 "arithmetic_comparison_operator" | 5971 output_asm_insn (AS1 (inc%L1,%1), operands); 5972 5973 else 5974 output_asm_insn (AS2 (add%L1,%2,%1), operands); 5975 5976 return AS1 (%J0,%l3); 5977}") 5978 5979(define_insn "" 5980 [(set (pc) 5981 (if_then_else (match_operator 0 "arithmetic_comparison_operator" |
4959 [(minus:SI (match_operand:SI 1 "general_operand" "+r,m") | 5982 [(minus:SI (match_operand:SI 1 "nonimmediate_operand" "+r,m") |
4960 (match_operand:SI 2 "general_operand" "rmi,ri")) 4961 (const_int 0)]) 4962 (label_ref (match_operand 3 "" "")) 4963 (pc))) 4964 (set (match_dup 1) 4965 (minus:SI (match_dup 1) 4966 (match_dup 2)))] 4967 "" --- 7 unchanged lines hidden (view full) --- 4975 output_asm_insn (AS1 (inc%L1,%1), operands); 4976 4977 else 4978 output_asm_insn (AS2 (sub%L1,%2,%1), operands); 4979 4980 return AS1 (%J0,%l3); 4981}") 4982 | 5983 (match_operand:SI 2 "general_operand" "rmi,ri")) 5984 (const_int 0)]) 5985 (label_ref (match_operand 3 "" "")) 5986 (pc))) 5987 (set (match_dup 1) 5988 (minus:SI (match_dup 1) 5989 (match_dup 2)))] 5990 "" --- 7 unchanged lines hidden (view full) --- 5998 output_asm_insn (AS1 (inc%L1,%1), operands); 5999 6000 else 6001 output_asm_insn (AS2 (sub%L1,%2,%1), operands); 6002 6003 return AS1 (%J0,%l3); 6004}") 6005 |
6006(define_insn "" 6007 [(set (pc) 6008 (if_then_else (ne (match_operand:SI 0 "general_operand" "+g") 6009 (const_int 0)) 6010 (label_ref (match_operand 1 "" "")) 6011 (pc))) 6012 (set (match_dup 0) 6013 (plus:SI (match_dup 0) 6014 (const_int -1)))] 6015 "" 6016 "* 6017{ 6018 CC_STATUS_INIT; 6019 operands[2] = const1_rtx; 6020 output_asm_insn (AS2 (sub%L0,%2,%0), operands); 6021 return \"jnc %l1\"; 6022}") 6023 6024(define_insn "" 6025 [(set (pc) 6026 (if_then_else (eq (match_operand:SI 0 "general_operand" "+g") 6027 (const_int 0)) 6028 (label_ref (match_operand 1 "" "")) 6029 (pc))) 6030 (set (match_dup 0) 6031 (plus:SI (match_dup 0) 6032 (const_int -1)))] 6033 "" 6034 "* 6035{ 6036 CC_STATUS_INIT; 6037 operands[2] = const1_rtx; 6038 output_asm_insn (AS2 (sub%L0,%2,%0), operands); 6039 return \"jc %l1\"; 6040}") 6041 6042(define_insn "" 6043 [(set (pc) 6044 (if_then_else (ne (match_operand:SI 0 "general_operand" "+g") 6045 (const_int 1)) 6046 (label_ref (match_operand 1 "" "")) 6047 (pc))) 6048 (set (match_dup 0) 6049 (plus:SI (match_dup 0) 6050 (const_int -1)))] 6051 "" 6052 "* 6053{ 6054 CC_STATUS_INIT; 6055 output_asm_insn (AS1 (dec%L0,%0), operands); 6056 return \"jnz %l1\"; 6057}") 6058 6059(define_insn "" 6060 [(set (pc) 6061 (if_then_else (eq (match_operand:SI 0 "general_operand" "+g") 6062 (const_int 1)) 6063 (label_ref (match_operand 1 "" "")) 6064 (pc))) 6065 (set (match_dup 0) 6066 (plus:SI (match_dup 0) 6067 (const_int -1)))] 6068 "" 6069 "* 6070{ 6071 CC_STATUS_INIT; 6072 output_asm_insn (AS1 (dec%L0,%0), operands); 6073 return \"jz %l1\"; 6074}") 6075 6076(define_insn "" 6077 [(set (pc) 6078 (if_then_else (ne (match_operand:SI 0 "general_operand" "+g") 6079 (const_int -1)) 6080 (label_ref (match_operand 1 "" "")) 6081 (pc))) 6082 (set (match_dup 0) 6083 (plus:SI (match_dup 0) 6084 (const_int 1)))] 6085 "" 6086 "* 6087{ 6088 CC_STATUS_INIT; 6089 output_asm_insn (AS1 (inc%L0,%0), operands); 6090 return \"jnz %l1\"; 6091}") 6092 6093(define_insn "" 6094 [(set (pc) 6095 (if_then_else (eq (match_operand:SI 0 "general_operand" "+g") 6096 (const_int -1)) 6097 (label_ref (match_operand 1 "" "")) 6098 (pc))) 6099 (set (match_dup 0) 6100 (plus:SI (match_dup 0) 6101 (const_int 1)))] 6102 "" 6103 "* 6104{ 6105 CC_STATUS_INIT; 6106 output_asm_insn (AS1 (inc%L0,%0), operands); 6107 return \"jz %l1\"; 6108}") 6109 |
|
4983;; Implement switch statements when generating PIC code. Switches are 4984;; implemented by `tablejump' when not using -fpic. 4985 4986;; Emit code here to do the range checking and make the index zero based. 4987 4988(define_expand "casesi" 4989 [(set (match_dup 5) | 6110;; Implement switch statements when generating PIC code. Switches are 6111;; implemented by `tablejump' when not using -fpic. 6112 6113;; Emit code here to do the range checking and make the index zero based. 6114 6115(define_expand "casesi" 6116 [(set (match_dup 5) |
4990 (minus:SI (match_operand:SI 0 "general_operand" "") | 6117 (match_operand:SI 0 "general_operand" "")) 6118 (set (match_dup 6) 6119 (minus:SI (match_dup 5) |
4991 (match_operand:SI 1 "general_operand" ""))) 4992 (set (cc0) | 6120 (match_operand:SI 1 "general_operand" ""))) 6121 (set (cc0) |
4993 (compare:CC (match_dup 5) | 6122 (compare:CC (match_dup 6) |
4994 (match_operand:SI 2 "general_operand" ""))) 4995 (set (pc) 4996 (if_then_else (gtu (cc0) 4997 (const_int 0)) 4998 (label_ref (match_operand 4 "" "")) 4999 (pc))) 5000 (parallel 5001 [(set (pc) 5002 (minus:SI (reg:SI 3) | 6123 (match_operand:SI 2 "general_operand" ""))) 6124 (set (pc) 6125 (if_then_else (gtu (cc0) 6126 (const_int 0)) 6127 (label_ref (match_operand 4 "" "")) 6128 (pc))) 6129 (parallel 6130 [(set (pc) 6131 (minus:SI (reg:SI 3) |
5003 (mem:SI (plus:SI (mult:SI (match_dup 5) | 6132 (mem:SI (plus:SI (mult:SI (match_dup 6) |
5004 (const_int 4)) 5005 (label_ref (match_operand 3 "" "")))))) | 6133 (const_int 4)) 6134 (label_ref (match_operand 3 "" "")))))) |
5006 (clobber (match_scratch:SI 6 ""))])] | 6135 (clobber (match_scratch:SI 7 ""))])] |
5007 "flag_pic" 5008 " 5009{ 5010 operands[5] = gen_reg_rtx (SImode); | 6136 "flag_pic" 6137 " 6138{ 6139 operands[5] = gen_reg_rtx (SImode); |
6140 operands[6] = gen_reg_rtx (SImode); |
|
5011 current_function_uses_pic_offset_table = 1; 5012}") 5013 5014;; Implement a casesi insn. 5015 5016;; Each entry in the "addr_diff_vec" looks like this as the result of the 5017;; two rules below: 5018;; --- 37 unchanged lines hidden (view full) --- 5056 xops[0] = operands[0]; 5057 xops[1] = operands[1]; 5058 xops[2] = operands[2]; 5059 xops[3] = pic_offset_table_rtx; 5060 5061 output_asm_insn (AS2 (mov%L2,%3,%2), xops); 5062 output_asm_insn (\"sub%L2 %l1@GOTOFF(%3,%0,4),%2\", xops); 5063 output_asm_insn (AS1 (jmp,%*%2), xops); | 6141 current_function_uses_pic_offset_table = 1; 6142}") 6143 6144;; Implement a casesi insn. 6145 6146;; Each entry in the "addr_diff_vec" looks like this as the result of the 6147;; two rules below: 6148;; --- 37 unchanged lines hidden (view full) --- 6186 xops[0] = operands[0]; 6187 xops[1] = operands[1]; 6188 xops[2] = operands[2]; 6189 xops[3] = pic_offset_table_rtx; 6190 6191 output_asm_insn (AS2 (mov%L2,%3,%2), xops); 6192 output_asm_insn (\"sub%L2 %l1@GOTOFF(%3,%0,4),%2\", xops); 6193 output_asm_insn (AS1 (jmp,%*%2), xops); |
5064 ASM_OUTPUT_ALIGN_CODE (asm_out_file); | 6194 ASM_OUTPUT_ALIGN (asm_out_file, i386_align_jumps); |
5065 RET; 5066}") 5067 5068(define_insn "tablejump" | 6195 RET; 6196}") 6197 6198(define_insn "tablejump" |
5069 [(set (pc) (match_operand:SI 0 "general_operand" "rm")) | 6199 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm")) |
5070 (use (label_ref (match_operand 1 "" "")))] 5071 "" 5072 "* 5073{ 5074 CC_STATUS_INIT; 5075 5076 return AS1 (jmp,%*%0); 5077}") --- 229 unchanged lines hidden (view full) --- 5307 " 5308{ 5309 int i; 5310 5311 /* In order to give reg-stack an easier job in validating two 5312 coprocessor registers as containing a possible return value, 5313 simply pretend the untyped call returns a complex long double 5314 value. */ | 6200 (use (label_ref (match_operand 1 "" "")))] 6201 "" 6202 "* 6203{ 6204 CC_STATUS_INIT; 6205 6206 return AS1 (jmp,%*%0); 6207}") --- 229 unchanged lines hidden (view full) --- 6437 " 6438{ 6439 int i; 6440 6441 /* In order to give reg-stack an easier job in validating two 6442 coprocessor registers as containing a possible return value, 6443 simply pretend the untyped call returns a complex long double 6444 value. */ |
5315#if 1 5316 /* this may be part of (set (reg: ..) (call_insn ...)), and we can't 5317 directly set a fp register from the call. so we revert to the 5318 old behavior - jlemon@netcom.com (Jonathan Lemon) */ 5319 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); 5320#else | 6445 |
5321 emit_call_insn (TARGET_80387 | 6446 emit_call_insn (TARGET_80387 |
5322 ? gen_call_value (gen_rtx (REG, XCmode, FIRST_FLOAT_REG), 5323 operands[0], const0_rtx) | 6447 ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG), 6448 operands[0], const0_rtx) |
5324 : gen_call (operands[0], const0_rtx)); | 6449 : gen_call (operands[0], const0_rtx)); |
5325#endif | |
5326 5327 for (i = 0; i < XVECLEN (operands[2], 0); i++) 5328 { 5329 rtx set = XVECEXP (operands[2], 0, i); 5330 emit_move_insn (SET_DEST (set), SET_SRC (set)); 5331 } 5332 5333 /* The optimizer does not know that the call sets the function value --- 12 unchanged lines hidden (view full) --- 5346 [(unspec_volatile [(const_int 0)] 0)] 5347 "" 5348 "") 5349 5350;; Insn emitted into the body of a function to return from a function. 5351;; This is only done if the function's epilogue is known to be simple. 5352;; See comments for simple_386_epilogue in i386.c. 5353 | 6450 6451 for (i = 0; i < XVECLEN (operands[2], 0); i++) 6452 { 6453 rtx set = XVECEXP (operands[2], 0, i); 6454 emit_move_insn (SET_DEST (set), SET_SRC (set)); 6455 } 6456 6457 /* The optimizer does not know that the call sets the function value --- 12 unchanged lines hidden (view full) --- 6470 [(unspec_volatile [(const_int 0)] 0)] 6471 "" 6472 "") 6473 6474;; Insn emitted into the body of a function to return from a function. 6475;; This is only done if the function's epilogue is known to be simple. 6476;; See comments for simple_386_epilogue in i386.c. 6477 |
5354(define_insn "return" | 6478(define_expand "return" |
5355 [(return)] | 6479 [(return)] |
5356 "simple_386_epilogue ()" | 6480 "ix86_can_use_return_insn_p ()" 6481 "") 6482 6483(define_insn "return_internal" 6484 [(return)] 6485 "reload_completed" 6486 "ret") 6487 6488(define_insn "return_pop_internal" 6489 [(return) 6490 (use (match_operand:SI 0 "const_int_operand" ""))] 6491 "reload_completed" 6492 "ret %0") 6493 6494(define_insn "nop" 6495 [(const_int 0)] 6496 "" 6497 "nop") 6498 6499(define_expand "prologue" 6500 [(const_int 1)] 6501 "" 6502 " 6503{ 6504 ix86_expand_prologue (); 6505 DONE; 6506}") 6507 6508;; The use of UNSPEC here is currently not necessary - a simple SET of ebp 6509;; to itself would be enough. But this way we are safe even if some optimizer 6510;; becomes too clever in the future. 6511(define_insn "prologue_set_stack_ptr" 6512 [(set (reg:SI 7) 6513 (minus:SI (reg:SI 7) (match_operand:SI 0 "immediate_operand" "i"))) 6514 (set (reg:SI 6) (unspec:SI [(reg:SI 6)] 4))] 6515 "" |
5357 "* 5358{ | 6516 "* 6517{ |
5359 function_epilogue (asm_out_file, get_frame_size ()); | 6518 rtx xops [2]; 6519 6520 xops[0] = operands[0]; 6521 xops[1] = stack_pointer_rtx; 6522 output_asm_insn (AS2 (sub%L1,%0,%1), xops); |
5360 RET; 5361}") 5362 | 6523 RET; 6524}") 6525 |
5363(define_insn "nop" 5364 [(const_int 0)] | 6526(define_insn "prologue_set_got" 6527 [(set (match_operand:SI 0 "" "") 6528 (unspec_volatile 6529 [(plus:SI (match_dup 0) 6530 (plus:SI (match_operand:SI 1 "symbolic_operand" "") 6531 (minus:SI (pc) (match_operand 2 "" ""))))] 1))] |
5365 "" | 6532 "" |
5366 "nop") | 6533 "* 6534{ 6535 char buffer[64]; |
5367 | 6536 |
6537 if (TARGET_DEEP_BRANCH_PREDICTION) 6538 { 6539 sprintf (buffer, \"addl %s,%%0\", XSTR (operands[1], 0)); 6540 output_asm_insn (buffer, operands); 6541 } 6542 else 6543 { 6544 sprintf (buffer, \"addl %s+[.-%%X2],%%0\", XSTR (operands[1], 0)); 6545 output_asm_insn (buffer, operands); 6546 } 6547 RET; 6548}") 6549 6550(define_insn "prologue_get_pc" 6551 [(set (match_operand:SI 0 "" "") 6552 (unspec_volatile [(plus:SI (pc) (match_operand 1 "" ""))] 2))] 6553 "" 6554 "* 6555{ 6556 char buffer[64]; 6557 6558 output_asm_insn (AS1 (call,%X1), operands); 6559 if (! TARGET_DEEP_BRANCH_PREDICTION) 6560 { 6561 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (operands[1])); 6562 } 6563 RET; 6564}") 6565 6566(define_insn "prologue_get_pc_and_set_got" 6567 [(unspec_volatile [(match_operand:SI 0 "" "")] 3)] 6568 "" 6569 "* 6570{ 6571 operands[1] = gen_label_rtx (); 6572 output_asm_insn (AS1 (call,%X1), operands); 6573 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", 6574 CODE_LABEL_NUMBER (operands[1])); 6575 output_asm_insn (AS1 (pop%L0,%0), operands); 6576 output_asm_insn (\"addl $_GLOBAL_OFFSET_TABLE_+[.-%X1],%0\", operands); 6577 RET; 6578}") 6579 6580(define_expand "epilogue" 6581 [(const_int 1)] 6582 "" 6583 " 6584{ 6585 ix86_expand_epilogue (); 6586 DONE; 6587}") 6588 6589(define_insn "epilogue_set_stack_ptr" 6590 [(set (reg:SI 7) (reg:SI 6)) 6591 (clobber (reg:SI 6))] 6592 "" 6593 "* 6594{ 6595 rtx xops [2]; 6596 6597 xops[0] = frame_pointer_rtx; 6598 xops[1] = stack_pointer_rtx; 6599 output_asm_insn (AS2 (mov%L0,%0,%1), xops); 6600 RET; 6601}") 6602 6603(define_insn "leave" 6604 [(const_int 2) 6605 (clobber (reg:SI 6)) 6606 (clobber (reg:SI 7))] 6607 "" 6608 "leave") 6609 6610(define_insn "pop" 6611 [(set (match_operand:SI 0 "register_operand" "r") 6612 (mem:SI (reg:SI 7))) 6613 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))] 6614 "" 6615 "* 6616{ 6617 output_asm_insn (AS1 (pop%L0,%P0), operands); 6618 RET; 6619}") 6620 |
|
5368(define_expand "movstrsi" 5369 [(parallel [(set (match_operand:BLK 0 "memory_operand" "") 5370 (match_operand:BLK 1 "memory_operand" "")) 5371 (use (match_operand:SI 2 "const_int_operand" "")) 5372 (use (match_operand:SI 3 "const_int_operand" "")) 5373 (clobber (match_scratch:SI 4 "")) 5374 (clobber (match_dup 5)) 5375 (clobber (match_dup 6))])] --- 6 unchanged lines hidden (view full) --- 5382 FAIL; 5383 5384 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); 5385 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); 5386 5387 operands[5] = addr0; 5388 operands[6] = addr1; 5389 | 6621(define_expand "movstrsi" 6622 [(parallel [(set (match_operand:BLK 0 "memory_operand" "") 6623 (match_operand:BLK 1 "memory_operand" "")) 6624 (use (match_operand:SI 2 "const_int_operand" "")) 6625 (use (match_operand:SI 3 "const_int_operand" "")) 6626 (clobber (match_scratch:SI 4 "")) 6627 (clobber (match_dup 5)) 6628 (clobber (match_dup 6))])] --- 6 unchanged lines hidden (view full) --- 6635 FAIL; 6636 6637 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); 6638 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); 6639 6640 operands[5] = addr0; 6641 operands[6] = addr1; 6642 |
5390 operands[0] = gen_rtx (MEM, BLKmode, addr0); 5391 operands[1] = gen_rtx (MEM, BLKmode, addr1); | 6643 operands[0] = change_address (operands[0], VOIDmode, addr0); 6644 operands[1] = change_address (operands[1], VOIDmode, addr1); |
5392}") 5393 5394;; It might seem that operands 0 & 1 could use predicate register_operand. 5395;; But strength reduction might offset the MEM expression. So we let 5396;; reload put the address into %edi & %esi. 5397 5398(define_insn "" 5399 [(set (mem:BLK (match_operand:SI 0 "address_operand" "D")) --- 28 unchanged lines hidden (view full) --- 5428 if (INTVAL (operands[2]) & 0x01) 5429 output_asm_insn (\"movsb\", operands); 5430 } 5431 else 5432 abort (); 5433 RET; 5434}") 5435 | 6645}") 6646 6647;; It might seem that operands 0 & 1 could use predicate register_operand. 6648;; But strength reduction might offset the MEM expression. So we let 6649;; reload put the address into %edi & %esi. 6650 6651(define_insn "" 6652 [(set (mem:BLK (match_operand:SI 0 "address_operand" "D")) --- 28 unchanged lines hidden (view full) --- 6681 if (INTVAL (operands[2]) & 0x01) 6682 output_asm_insn (\"movsb\", operands); 6683 } 6684 else 6685 abort (); 6686 RET; 6687}") 6688 |
6689(define_expand "clrstrsi" 6690 [(set (match_dup 3) (const_int 0)) 6691 (parallel [(set (match_operand:BLK 0 "memory_operand" "") 6692 (const_int 0)) 6693 (use (match_operand:SI 1 "const_int_operand" "")) 6694 (use (match_operand:SI 2 "const_int_operand" "")) 6695 (use (match_dup 3)) 6696 (clobber (match_scratch:SI 4 "")) 6697 (clobber (match_dup 5))])] 6698 "" 6699 " 6700{ 6701 rtx addr0, addr1; 6702 6703 if (GET_CODE (operands[1]) != CONST_INT) 6704 FAIL; 6705 6706 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); 6707 6708 operands[3] = gen_reg_rtx (SImode); 6709 operands[5] = addr0; 6710 6711 operands[0] = gen_rtx_MEM (BLKmode, addr0); 6712}") 6713 6714;; It might seem that operand 0 could use predicate register_operand. 6715;; But strength reduction might offset the MEM expression. So we let 6716;; reload put the address into %edi. 6717 6718(define_insn "" 6719 [(set (mem:BLK (match_operand:SI 0 "address_operand" "D")) 6720 (const_int 0)) 6721 (use (match_operand:SI 1 "const_int_operand" "n")) 6722 (use (match_operand:SI 2 "immediate_operand" "i")) 6723 (use (match_operand:SI 3 "register_operand" "a")) 6724 (clobber (match_scratch:SI 4 "=&c")) 6725 (clobber (match_dup 0))] 6726 "" 6727 "* 6728{ 6729 rtx xops[2]; 6730 6731 output_asm_insn (\"cld\", operands); 6732 if (GET_CODE (operands[1]) == CONST_INT) 6733 { 6734 if (INTVAL (operands[1]) & ~0x03) 6735 { 6736 xops[0] = GEN_INT ((INTVAL (operands[1]) >> 2) & 0x3fffffff); 6737 xops[1] = operands[4]; 6738 6739 output_asm_insn (AS2 (mov%L1,%0,%1), xops); 6740#ifdef INTEL_SYNTAX 6741 output_asm_insn (\"rep stosd\", xops); 6742#else 6743 output_asm_insn (\"rep\;stosl\", xops); 6744#endif 6745 } 6746 if (INTVAL (operands[1]) & 0x02) 6747 output_asm_insn (\"stosw\", operands); 6748 if (INTVAL (operands[1]) & 0x01) 6749 output_asm_insn (\"stosb\", operands); 6750 } 6751 else 6752 abort (); 6753 RET; 6754}") 6755 |
|
5436(define_expand "cmpstrsi" 5437 [(parallel [(set (match_operand:SI 0 "general_operand" "") 5438 (compare:SI (match_operand:BLK 1 "general_operand" "") 5439 (match_operand:BLK 2 "general_operand" ""))) 5440 (use (match_operand:SI 3 "general_operand" "")) 5441 (use (match_operand:SI 4 "immediate_operand" "")) 5442 (clobber (match_dup 5)) 5443 (clobber (match_dup 6)) --- 5 unchanged lines hidden (view full) --- 5449 5450 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); 5451 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0)); 5452 operands[3] = copy_to_mode_reg (SImode, operands[3]); 5453 5454 operands[5] = addr1; 5455 operands[6] = addr2; 5456 | 6756(define_expand "cmpstrsi" 6757 [(parallel [(set (match_operand:SI 0 "general_operand" "") 6758 (compare:SI (match_operand:BLK 1 "general_operand" "") 6759 (match_operand:BLK 2 "general_operand" ""))) 6760 (use (match_operand:SI 3 "general_operand" "")) 6761 (use (match_operand:SI 4 "immediate_operand" "")) 6762 (clobber (match_dup 5)) 6763 (clobber (match_dup 6)) --- 5 unchanged lines hidden (view full) --- 6769 6770 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); 6771 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0)); 6772 operands[3] = copy_to_mode_reg (SImode, operands[3]); 6773 6774 operands[5] = addr1; 6775 operands[6] = addr2; 6776 |
5457 operands[1] = gen_rtx (MEM, BLKmode, addr1); 5458 operands[2] = gen_rtx (MEM, BLKmode, addr2); | 6777 operands[1] = gen_rtx_MEM (BLKmode, addr1); 6778 operands[2] = gen_rtx_MEM (BLKmode, addr2); |
5459 5460}") 5461 5462;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is 5463;; zero. Emit extra code to make sure that a zero-length compare is EQ. 5464 5465;; It might seem that operands 0 & 1 could use predicate register_operand. 5466;; But strength reduction might offset the MEM expression. So we let 5467;; reload put the address into %edi & %esi. 5468 5469;; ??? Most comparisons have a constant length, and it's therefore 5470;; possible to know that the length is non-zero, and to avoid the extra 5471;; code to handle zero-length compares. 5472 5473(define_insn "" | 6779 6780}") 6781 6782;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is 6783;; zero. Emit extra code to make sure that a zero-length compare is EQ. 6784 6785;; It might seem that operands 0 & 1 could use predicate register_operand. 6786;; But strength reduction might offset the MEM expression. So we let 6787;; reload put the address into %edi & %esi. 6788 6789;; ??? Most comparisons have a constant length, and it's therefore 6790;; possible to know that the length is non-zero, and to avoid the extra 6791;; code to handle zero-length compares. 6792 6793(define_insn "" |
5474 [(set (match_operand:SI 0 "general_operand" "=&r") | 6794 [(set (match_operand:SI 0 "register_operand" "=&r") |
5475 (compare:SI (mem:BLK (match_operand:SI 1 "address_operand" "S")) 5476 (mem:BLK (match_operand:SI 2 "address_operand" "D")))) 5477 (use (match_operand:SI 3 "register_operand" "c")) 5478 (use (match_operand:SI 4 "immediate_operand" "i")) 5479 (clobber (match_dup 1)) 5480 (clobber (match_dup 2)) 5481 (clobber (match_dup 3))] 5482 "" 5483 "* 5484{ | 6795 (compare:SI (mem:BLK (match_operand:SI 1 "address_operand" "S")) 6796 (mem:BLK (match_operand:SI 2 "address_operand" "D")))) 6797 (use (match_operand:SI 3 "register_operand" "c")) 6798 (use (match_operand:SI 4 "immediate_operand" "i")) 6799 (clobber (match_dup 1)) 6800 (clobber (match_dup 2)) 6801 (clobber (match_dup 3))] 6802 "" 6803 "* 6804{ |
5485 rtx xops[4], label; | 6805 rtx xops[2], label; |
5486 5487 label = gen_label_rtx (); 5488 5489 output_asm_insn (\"cld\", operands); 5490 output_asm_insn (AS2 (xor%L0,%0,%0), operands); 5491 output_asm_insn (\"repz\;cmps%B2\", operands); 5492 output_asm_insn (\"je %l0\", &label); 5493 5494 xops[0] = operands[0]; | 6806 6807 label = gen_label_rtx (); 6808 6809 output_asm_insn (\"cld\", operands); 6810 output_asm_insn (AS2 (xor%L0,%0,%0), operands); 6811 output_asm_insn (\"repz\;cmps%B2\", operands); 6812 output_asm_insn (\"je %l0\", &label); 6813 6814 xops[0] = operands[0]; |
5495 xops[1] = gen_rtx (MEM, QImode, 5496 gen_rtx (PLUS, SImode, operands[1], constm1_rtx)); 5497 xops[2] = gen_rtx (MEM, QImode, 5498 gen_rtx (PLUS, SImode, operands[2], constm1_rtx)); 5499 xops[3] = operands[3]; 5500 5501 output_asm_insn (AS2 (movz%B1%L0,%1,%0), xops); 5502 output_asm_insn (AS2 (movz%B2%L3,%2,%3), xops); 5503 5504 output_asm_insn (AS2 (sub%L0,%3,%0), xops); | 6815 xops[1] = const1_rtx; 6816 output_asm_insn (AS2 (sbb%L0,%0,%0), xops); 6817 if (QI_REG_P (xops[0])) 6818 output_asm_insn (AS2 (or%B0,%1,%b0), xops); 6819 else 6820 output_asm_insn (AS2 (or%L0,%1,%0), xops); 6821 |
5505 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (label)); 5506 RET; 5507}") 5508 5509(define_insn "" 5510 [(set (cc0) 5511 (compare:SI (mem:BLK (match_operand:SI 0 "address_operand" "S")) 5512 (mem:BLK (match_operand:SI 1 "address_operand" "D")))) --- 4 unchanged lines hidden (view full) --- 5517 (clobber (match_dup 2))] 5518 "" 5519 "* 5520{ 5521 rtx xops[2]; 5522 5523 cc_status.flags |= CC_NOT_SIGNED; 5524 | 6822 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (label)); 6823 RET; 6824}") 6825 6826(define_insn "" 6827 [(set (cc0) 6828 (compare:SI (mem:BLK (match_operand:SI 0 "address_operand" "S")) 6829 (mem:BLK (match_operand:SI 1 "address_operand" "D")))) --- 4 unchanged lines hidden (view full) --- 6834 (clobber (match_dup 2))] 6835 "" 6836 "* 6837{ 6838 rtx xops[2]; 6839 6840 cc_status.flags |= CC_NOT_SIGNED; 6841 |
5525 xops[0] = gen_rtx (REG, QImode, 0); | 6842 xops[0] = gen_rtx_REG (QImode, 0); |
5526 xops[1] = CONST0_RTX (QImode); 5527 5528 output_asm_insn (\"cld\", operands); 5529 output_asm_insn (AS2 (test%B0,%1,%0), xops); 5530 return \"repz\;cmps%B2\"; 5531}") 5532 | 6843 xops[1] = CONST0_RTX (QImode); 6844 6845 output_asm_insn (\"cld\", operands); 6846 output_asm_insn (AS2 (test%B0,%1,%0), xops); 6847 return \"repz\;cmps%B2\"; 6848}") 6849 |
5533(define_expand "ffssi2" 5534 [(set (match_dup 2) 5535 (plus:SI (ffs:SI (match_operand:SI 1 "general_operand" "")) 5536 (const_int -1))) 5537 (set (match_operand:SI 0 "general_operand" "") 5538 (plus:SI (match_dup 2) (const_int 1)))] 5539 "" 5540 "operands[2] = gen_reg_rtx (SImode);") 5541 | 6850 |
5542;; Note, you cannot optimize away the branch following the bsfl by assuming 5543;; that the destination is not modified if the input is 0, since not all 5544;; x86 implementations do this. 5545 | 6851;; Note, you cannot optimize away the branch following the bsfl by assuming 6852;; that the destination is not modified if the input is 0, since not all 6853;; x86 implementations do this. 6854 |
5546(define_insn "" 5547 [(set (match_operand:SI 0 "general_operand" "=&r") 5548 (plus:SI (ffs:SI (match_operand:SI 1 "general_operand" "rm")) 5549 (const_int -1)))] | 6855(define_expand "ffssi2" 6856 [(set (match_operand:SI 0 "general_operand" "") 6857 (ffs:SI (match_operand:SI 1 "general_operand" "")))] |
5550 "" | 6858 "" |
5551 "* | 6859 " |
5552{ | 6860{ |
5553 rtx xops[3]; 5554 static int ffssi_label_number; 5555 char buffer[30]; | 6861 rtx label = gen_label_rtx (), temp = gen_reg_rtx (SImode); |
5556 | 6862 |
5557 xops[0] = operands[0]; 5558 xops[1] = operands[1]; 5559 xops[2] = constm1_rtx; 5560 output_asm_insn (AS2 (bsf%L0,%1,%0), xops); 5561#ifdef LOCAL_LABEL_PREFIX 5562 sprintf (buffer, \"jnz %sLFFSSI%d\", 5563 LOCAL_LABEL_PREFIX, ffssi_label_number); 5564#else 5565 sprintf (buffer, \"jnz %sLFFSSI%d\", 5566 \"\", ffssi_label_number); 5567#endif 5568 output_asm_insn (buffer, xops); 5569 output_asm_insn (AS2 (mov%L0,%2,%0), xops); 5570#ifdef LOCAL_LABEL_PREFIX 5571 sprintf (buffer, \"%sLFFSSI%d:\", 5572 LOCAL_LABEL_PREFIX, ffssi_label_number); 5573#else 5574 sprintf (buffer, \"%sLFFSSI%d:\", 5575 \"\", ffssi_label_number); 5576#endif 5577 output_asm_insn (buffer, xops); | 6863 emit_insn (gen_ffssi_1 (temp, operands[1])); 6864 emit_cmp_insn (operands[1], const0_rtx, NE, NULL_RTX, SImode, 0, 0); 6865 emit_jump_insn (gen_bne (label)); 6866 emit_move_insn (temp, constm1_rtx); 6867 emit_label (label); 6868 temp = expand_binop (SImode, add_optab, temp, const1_rtx, 6869 operands[0], 0, OPTAB_WIDEN); |
5578 | 6870 |
5579 ffssi_label_number++; 5580 return \"\"; | 6871 if (temp != operands[0]) 6872 emit_move_insn (operands[0], temp); 6873 DONE; |
5581}") 5582 | 6874}") 6875 |
5583(define_expand "ffshi2" 5584 [(set (match_dup 2) 5585 (plus:HI (ffs:HI (match_operand:HI 1 "general_operand" "")) 5586 (const_int -1))) 5587 (set (match_operand:HI 0 "general_operand" "") 5588 (plus:HI (match_dup 2) (const_int 1)))] | 6876(define_insn "ffssi_1" 6877 [(set (match_operand:SI 0 "register_operand" "=r") 6878 (unspec:SI [(match_operand:SI 1 "nonimmediate_operand" "rm")] 5))] |
5589 "" | 6879 "" |
5590 "operands[2] = gen_reg_rtx (HImode);") | 6880 "* return AS2 (bsf%L0,%1,%0);") |
5591 | 6881 |
5592(define_insn "" 5593 [(set (match_operand:HI 0 "general_operand" "=&r") 5594 (plus:HI (ffs:HI (match_operand:SI 1 "general_operand" "rm")) 5595 (const_int -1)))] | 6882(define_expand "ffshi2" 6883 [(set (match_operand:SI 0 "general_operand" "") 6884 (ffs:HI (match_operand:HI 1 "general_operand" "")))] |
5596 "" | 6885 "" |
5597 "* | 6886 " |
5598{ | 6887{ |
5599 rtx xops[3]; 5600 static int ffshi_label_number; 5601 char buffer[30]; | 6888 rtx label = gen_label_rtx (), temp = gen_reg_rtx (HImode); |
5602 | 6889 |
5603 xops[0] = operands[0]; 5604 xops[1] = operands[1]; 5605 xops[2] = constm1_rtx; 5606 output_asm_insn (AS2 (bsf%W0,%1,%0), xops); 5607#ifdef LOCAL_LABEL_PREFIX 5608 sprintf (buffer, \"jnz %sLFFSHI%d\", 5609 LOCAL_LABEL_PREFIX, ffshi_label_number); 5610#else 5611 sprintf (buffer, \"jnz %sLFFSHI%d\", 5612 \"\", ffshi_label_number); 5613#endif 5614 output_asm_insn (buffer, xops); 5615 output_asm_insn (AS2 (mov%W0,%2,%0), xops); 5616#ifdef LOCAL_LABEL_PREFIX 5617 sprintf (buffer, \"%sLFFSHI%d:\", 5618 LOCAL_LABEL_PREFIX, ffshi_label_number); 5619#else 5620 sprintf (buffer, \"%sLFFSHI%d:\", 5621 \"\", ffshi_label_number); 5622#endif 5623 output_asm_insn (buffer, xops); | 6890 emit_insn (gen_ffshi_1 (temp, operands[1])); 6891 emit_cmp_insn (operands[1], const0_rtx, NE, NULL_RTX, HImode, 0, 0); 6892 emit_jump_insn (gen_bne (label)); 6893 emit_move_insn (temp, constm1_rtx); 6894 emit_label (label); 6895 temp = expand_binop (HImode, add_optab, temp, const1_rtx, 6896 operands[0], 0, OPTAB_WIDEN); |
5624 | 6897 |
5625 ffshi_label_number++; 5626 return \"\"; | 6898 if (temp != operands[0]) 6899 emit_move_insn (operands[0], temp); 6900 DONE; |
5627}") | 6901}") |
6902 6903(define_insn "ffshi_1" 6904 [(set (match_operand:HI 0 "register_operand" "=r") 6905 (unspec:HI [(match_operand:SI 1 "nonimmediate_operand" "rm")] 5))] 6906 "" 6907 "* return AS2 (bsf%W0,%1,%0);") |
|
5628 5629;; These patterns match the binary 387 instructions for addM3, subM3, 5630;; mulM3 and divM3. There are three patterns for each of DFmode and 5631;; SFmode. The first is the normal insn, the second the same insn but 5632;; with one operand a conversion, and the third the same insn but with 5633;; the other operand a conversion. The conversion may be SFmode or 5634;; SImode if the target mode DFmode, but only SImode if the target mode 5635;; is SFmode. 5636 5637(define_insn "" 5638 [(set (match_operand:DF 0 "register_operand" "=f,f") 5639 (match_operator:DF 3 "binary_387_op" 5640 [(match_operand:DF 1 "nonimmediate_operand" "0,fm") 5641 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))] 5642 "TARGET_80387" | 6908 6909;; These patterns match the binary 387 instructions for addM3, subM3, 6910;; mulM3 and divM3. There are three patterns for each of DFmode and 6911;; SFmode. The first is the normal insn, the second the same insn but 6912;; with one operand a conversion, and the third the same insn but with 6913;; the other operand a conversion. The conversion may be SFmode or 6914;; SImode if the target mode DFmode, but only SImode if the target mode 6915;; is SFmode. 6916 6917(define_insn "" 6918 [(set (match_operand:DF 0 "register_operand" "=f,f") 6919 (match_operator:DF 3 "binary_387_op" 6920 [(match_operand:DF 1 "nonimmediate_operand" "0,fm") 6921 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))] 6922 "TARGET_80387" |
5643 "* return output_387_binary_op (insn, operands);") | 6923 "* return output_387_binary_op (insn, operands);" 6924 [(set (attr "type") 6925 (cond [(match_operand:DF 3 "is_mul" "") 6926 (const_string "fpmul") 6927 (match_operand:DF 3 "is_div" "") 6928 (const_string "fpdiv") 6929 ] 6930 (const_string "fpop") 6931 ) 6932 )]) |
5644 5645(define_insn "" 5646 [(set (match_operand:DF 0 "register_operand" "=f") 5647 (match_operator:DF 3 "binary_387_op" | 6933 6934(define_insn "" 6935 [(set (match_operand:DF 0 "register_operand" "=f") 6936 (match_operator:DF 3 "binary_387_op" |
5648 [(float:DF (match_operand:SI 1 "general_operand" "rm")) 5649 (match_operand:DF 2 "general_operand" "0")]))] | 6937 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "rm")) 6938 (match_operand:DF 2 "register_operand" "0")]))] |
5650 "TARGET_80387" | 6939 "TARGET_80387" |
5651 "* return output_387_binary_op (insn, operands);") | 6940 "* return output_387_binary_op (insn, operands);" 6941 [(set (attr "type") 6942 (cond [(match_operand:DF 3 "is_mul" "") 6943 (const_string "fpmul") 6944 (match_operand:DF 3 "is_div" "") 6945 (const_string "fpdiv") 6946 ] 6947 (const_string "fpop") 6948 ) 6949 )]) |
5652 5653(define_insn "" 5654 [(set (match_operand:XF 0 "register_operand" "=f,f") 5655 (match_operator:XF 3 "binary_387_op" | 6950 6951(define_insn "" 6952 [(set (match_operand:XF 0 "register_operand" "=f,f") 6953 (match_operator:XF 3 "binary_387_op" |
5656 [(match_operand:XF 1 "nonimmediate_operand" "0,f") 5657 (match_operand:XF 2 "nonimmediate_operand" "f,0")]))] | 6954 [(match_operand:XF 1 "register_operand" "0,f") 6955 (match_operand:XF 2 "register_operand" "f,0")]))] |
5658 "TARGET_80387" | 6956 "TARGET_80387" |
5659 "* return output_387_binary_op (insn, operands);") | 6957 "* return output_387_binary_op (insn, operands);" 6958 [(set (attr "type") 6959 (cond [(match_operand:DF 3 "is_mul" "") 6960 (const_string "fpmul") 6961 (match_operand:DF 3 "is_div" "") 6962 (const_string "fpdiv") 6963 ] 6964 (const_string "fpop") 6965 ) 6966 )]) |
5660 5661(define_insn "" 5662 [(set (match_operand:XF 0 "register_operand" "=f") 5663 (match_operator:XF 3 "binary_387_op" | 6967 6968(define_insn "" 6969 [(set (match_operand:XF 0 "register_operand" "=f") 6970 (match_operator:XF 3 "binary_387_op" |
5664 [(float:XF (match_operand:SI 1 "general_operand" "rm")) 5665 (match_operand:XF 2 "general_operand" "0")]))] | 6971 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "rm")) 6972 (match_operand:XF 2 "register_operand" "0")]))] |
5666 "TARGET_80387" | 6973 "TARGET_80387" |
5667 "* return output_387_binary_op (insn, operands);") | 6974 "* return output_387_binary_op (insn, operands);" 6975 [(set (attr "type") 6976 (cond [(match_operand:DF 3 "is_mul" "") 6977 (const_string "fpmul") 6978 (match_operand:DF 3 "is_div" "") 6979 (const_string "fpdiv") 6980 ] 6981 (const_string "fpop") 6982 ) 6983 )]) |
5668 5669(define_insn "" 5670 [(set (match_operand:XF 0 "register_operand" "=f,f") 5671 (match_operator:XF 3 "binary_387_op" | 6984 6985(define_insn "" 6986 [(set (match_operand:XF 0 "register_operand" "=f,f") 6987 (match_operator:XF 3 "binary_387_op" |
5672 [(float_extend:XF (match_operand:SF 1 "general_operand" "fm,0")) 5673 (match_operand:XF 2 "general_operand" "0,f")]))] | 6988 [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0")) 6989 (match_operand:XF 2 "register_operand" "0,f")]))] |
5674 "TARGET_80387" | 6990 "TARGET_80387" |
5675 "* return output_387_binary_op (insn, operands);") | 6991 "* return output_387_binary_op (insn, operands);" 6992 [(set (attr "type") 6993 (cond [(match_operand:DF 3 "is_mul" "") 6994 (const_string "fpmul") 6995 (match_operand:DF 3 "is_div" "") 6996 (const_string "fpdiv") 6997 ] 6998 (const_string "fpop") 6999 ) 7000 )]) |
5676 5677(define_insn "" 5678 [(set (match_operand:XF 0 "register_operand" "=f") 5679 (match_operator:XF 3 "binary_387_op" | 7001 7002(define_insn "" 7003 [(set (match_operand:XF 0 "register_operand" "=f") 7004 (match_operator:XF 3 "binary_387_op" |
5680 [(match_operand:XF 1 "general_operand" "0") 5681 (float:XF (match_operand:SI 2 "general_operand" "rm"))]))] | 7005 [(match_operand:XF 1 "register_operand" "0") 7006 (float:XF (match_operand:SI 2 "nonimmediate_operand" "rm"))]))] |
5682 "TARGET_80387" | 7007 "TARGET_80387" |
5683 "* return output_387_binary_op (insn, operands);") | 7008 "* return output_387_binary_op (insn, operands);" 7009 [(set (attr "type") 7010 (cond [(match_operand:DF 3 "is_mul" "") 7011 (const_string "fpmul") 7012 (match_operand:DF 3 "is_div" "") 7013 (const_string "fpdiv") 7014 ] 7015 (const_string "fpop") 7016 ) 7017 )]) |
5684 5685(define_insn "" 5686 [(set (match_operand:XF 0 "register_operand" "=f,f") 5687 (match_operator:XF 3 "binary_387_op" | 7018 7019(define_insn "" 7020 [(set (match_operand:XF 0 "register_operand" "=f,f") 7021 (match_operator:XF 3 "binary_387_op" |
5688 [(match_operand:XF 1 "general_operand" "0,f") | 7022 [(match_operand:XF 1 "register_operand" "0,f") |
5689 (float_extend:XF | 7023 (float_extend:XF |
5690 (match_operand:SF 2 "general_operand" "fm,0"))]))] | 7024 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))] |
5691 "TARGET_80387" | 7025 "TARGET_80387" |
5692 "* return output_387_binary_op (insn, operands);") | 7026 "* return output_387_binary_op (insn, operands);" 7027 [(set (attr "type") 7028 (cond [(match_operand:DF 3 "is_mul" "") 7029 (const_string "fpmul") 7030 (match_operand:DF 3 "is_div" "") 7031 (const_string "fpdiv") 7032 ] 7033 (const_string "fpop") 7034 ) 7035 )]) |
5693 5694(define_insn "" 5695 [(set (match_operand:DF 0 "register_operand" "=f,f") 5696 (match_operator:DF 3 "binary_387_op" | 7036 7037(define_insn "" 7038 [(set (match_operand:DF 0 "register_operand" "=f,f") 7039 (match_operator:DF 3 "binary_387_op" |
5697 [(float_extend:DF (match_operand:SF 1 "general_operand" "fm,0")) 5698 (match_operand:DF 2 "general_operand" "0,f")]))] | 7040 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0")) 7041 (match_operand:DF 2 "register_operand" "0,f")]))] |
5699 "TARGET_80387" | 7042 "TARGET_80387" |
5700 "* return output_387_binary_op (insn, operands);") | 7043 "* return output_387_binary_op (insn, operands);" 7044 [(set (attr "type") 7045 (cond [(match_operand:DF 3 "is_mul" "") 7046 (const_string "fpmul") 7047 (match_operand:DF 3 "is_div" "") 7048 (const_string "fpdiv") 7049 ] 7050 (const_string "fpop") 7051 ) 7052 )]) |
5701 5702(define_insn "" 5703 [(set (match_operand:DF 0 "register_operand" "=f") 5704 (match_operator:DF 3 "binary_387_op" | 7053 7054(define_insn "" 7055 [(set (match_operand:DF 0 "register_operand" "=f") 7056 (match_operator:DF 3 "binary_387_op" |
5705 [(match_operand:DF 1 "general_operand" "0") 5706 (float:DF (match_operand:SI 2 "general_operand" "rm"))]))] | 7057 [(match_operand:DF 1 "register_operand" "0") 7058 (float:DF (match_operand:SI 2 "nonimmediate_operand" "rm"))]))] |
5707 "TARGET_80387" | 7059 "TARGET_80387" |
5708 "* return output_387_binary_op (insn, operands);") | 7060 "* return output_387_binary_op (insn, operands);" 7061 [(set (attr "type") 7062 (cond [(match_operand:DF 3 "is_mul" "") 7063 (const_string "fpmul") 7064 (match_operand:DF 3 "is_div" "") 7065 (const_string "fpdiv") 7066 ] 7067 (const_string "fpop") 7068 ) 7069 )]) |
5709 5710(define_insn "" 5711 [(set (match_operand:DF 0 "register_operand" "=f,f") 5712 (match_operator:DF 3 "binary_387_op" | 7070 7071(define_insn "" 7072 [(set (match_operand:DF 0 "register_operand" "=f,f") 7073 (match_operator:DF 3 "binary_387_op" |
5713 [(match_operand:DF 1 "general_operand" "0,f") | 7074 [(match_operand:DF 1 "register_operand" "0,f") |
5714 (float_extend:DF | 7075 (float_extend:DF |
5715 (match_operand:SF 2 "general_operand" "fm,0"))]))] | 7076 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))] |
5716 "TARGET_80387" | 7077 "TARGET_80387" |
5717 "* return output_387_binary_op (insn, operands);") | 7078 "* return output_387_binary_op (insn, operands);" 7079 [(set (attr "type") 7080 (cond [(match_operand:DF 3 "is_mul" "") 7081 (const_string "fpmul") 7082 (match_operand:DF 3 "is_div" "") 7083 (const_string "fpdiv") 7084 ] 7085 (const_string "fpop") 7086 ) 7087 )]) |
5718 5719(define_insn "" 5720 [(set (match_operand:SF 0 "register_operand" "=f,f") 5721 (match_operator:SF 3 "binary_387_op" 5722 [(match_operand:SF 1 "nonimmediate_operand" "0,fm") 5723 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))] 5724 "TARGET_80387" | 7088 7089(define_insn "" 7090 [(set (match_operand:SF 0 "register_operand" "=f,f") 7091 (match_operator:SF 3 "binary_387_op" 7092 [(match_operand:SF 1 "nonimmediate_operand" "0,fm") 7093 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))] 7094 "TARGET_80387" |
5725 "* return output_387_binary_op (insn, operands);") | 7095 "* return output_387_binary_op (insn, operands);" 7096 [(set (attr "type") 7097 (cond [(match_operand:DF 3 "is_mul" "") 7098 (const_string "fpmul") 7099 (match_operand:DF 3 "is_div" "") 7100 (const_string "fpdiv") 7101 ] 7102 (const_string "fpop") 7103 ) 7104 )]) |
5726 5727(define_insn "" 5728 [(set (match_operand:SF 0 "register_operand" "=f") 5729 (match_operator:SF 3 "binary_387_op" | 7105 7106(define_insn "" 7107 [(set (match_operand:SF 0 "register_operand" "=f") 7108 (match_operator:SF 3 "binary_387_op" |
5730 [(float:SF (match_operand:SI 1 "general_operand" "rm")) 5731 (match_operand:SF 2 "general_operand" "0")]))] | 7109 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "rm")) 7110 (match_operand:SF 2 "register_operand" "0")]))] |
5732 "TARGET_80387" | 7111 "TARGET_80387" |
5733 "* return output_387_binary_op (insn, operands);") | 7112 "* return output_387_binary_op (insn, operands);" 7113 [(set (attr "type") 7114 (cond [(match_operand:DF 3 "is_mul" "") 7115 (const_string "fpmul") 7116 (match_operand:DF 3 "is_div" "") 7117 (const_string "fpdiv") 7118 ] 7119 (const_string "fpop") 7120 ) 7121 )]) |
5734 5735(define_insn "" 5736 [(set (match_operand:SF 0 "register_operand" "=f") 5737 (match_operator:SF 3 "binary_387_op" | 7122 7123(define_insn "" 7124 [(set (match_operand:SF 0 "register_operand" "=f") 7125 (match_operator:SF 3 "binary_387_op" |
5738 [(match_operand:SF 1 "general_operand" "0") 5739 (float:SF (match_operand:SI 2 "general_operand" "rm"))]))] | 7126 [(match_operand:SF 1 "register_operand" "0") 7127 (float:SF (match_operand:SI 2 "nonimmediate_operand" "rm"))]))] |
5740 "TARGET_80387" | 7128 "TARGET_80387" |
5741 "* return output_387_binary_op (insn, operands);") | 7129 "* return output_387_binary_op (insn, operands);" 7130 [(set (attr "type") 7131 (cond [(match_operand:DF 3 "is_mul" "") 7132 (const_string "fpmul") 7133 (match_operand:DF 3 "is_div" "") 7134 (const_string "fpdiv") 7135 ] 7136 (const_string "fpop") 7137 ) 7138 )]) |
5742 5743(define_expand "strlensi" 5744 [(parallel [(set (match_dup 4) 5745 (unspec:SI [(mem:BLK (match_operand:BLK 1 "general_operand" "")) | 7139 7140(define_expand "strlensi" 7141 [(parallel [(set (match_dup 4) 7142 (unspec:SI [(mem:BLK (match_operand:BLK 1 "general_operand" "")) |
5746 (match_operand:QI 2 "register_operand" "") | 7143 (match_operand:QI 2 "immediate_operand" "") |
5747 (match_operand:SI 3 "immediate_operand" "")] 0)) 5748 (clobber (match_dup 1))]) 5749 (set (match_dup 5) 5750 (not:SI (match_dup 4))) 5751 (set (match_operand:SI 0 "register_operand" "") | 7144 (match_operand:SI 3 "immediate_operand" "")] 0)) 7145 (clobber (match_dup 1))]) 7146 (set (match_dup 5) 7147 (not:SI (match_dup 4))) 7148 (set (match_operand:SI 0 "register_operand" "") |
5752 (minus:SI (match_dup 5) 5753 (const_int 1)))] | 7149 (plus:SI (match_dup 5) 7150 (const_int -1)))] |
5754 "" 5755 " 5756{ | 7151 "" 7152 " 7153{ |
7154 if (TARGET_UNROLL_STRLEN && operands[2] == const0_rtx && optimize > 1) 7155 { 7156 rtx address; 7157 rtx scratch; 7158 7159 /* well it seems that some optimizer does not combine a call like 7160 foo(strlen(bar), strlen(bar)); 7161 when the move and the subtraction is done here. It does calculate 7162 the length just once when these instructions are done inside of 7163 output_strlen_unroll(). But I think since &bar[strlen(bar)] is 7164 often used and I use one fewer register for the lifetime of 7165 output_strlen_unroll() this is better. */ 7166 scratch = gen_reg_rtx (SImode); 7167 address = force_reg (SImode, XEXP (operands[1], 0)); 7168 7169 /* move address to scratch-register 7170 this is done here because the i586 can do the following and 7171 in the same cycle with the following move. */ 7172 if (GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) < 4) 7173 emit_insn (gen_movsi (scratch, address)); 7174 7175 emit_insn (gen_movsi (operands[0], address)); 7176 7177 if(TARGET_USE_Q_REG) 7178 emit_insn (gen_strlensi_unroll5 (operands[0], 7179 operands[3], 7180 scratch, 7181 operands[0])); 7182 else 7183 emit_insn (gen_strlensi_unroll4 (operands[0], 7184 operands[3], 7185 scratch, 7186 operands[0])); 7187 7188 /* gen_strlensi_unroll[45] returns the address of the zero 7189 at the end of the string, like memchr(), so compute the 7190 length by subtracting the startaddress. */ 7191 emit_insn (gen_subsi3 (operands[0], operands[0], address)); 7192 DONE; 7193 } 7194 |
|
5757 operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); 5758 operands[4] = gen_reg_rtx (SImode); 5759 operands[5] = gen_reg_rtx (SImode); 5760}") 5761 5762;; It might seem that operands 0 & 1 could use predicate register_operand. 5763;; But strength reduction might offset the MEM expression. So we let 5764;; reload put the address into %edi. 5765 5766(define_insn "" 5767 [(set (match_operand:SI 0 "register_operand" "=&c") 5768 (unspec:SI [(mem:BLK (match_operand:SI 1 "address_operand" "D")) | 7195 operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); 7196 operands[4] = gen_reg_rtx (SImode); 7197 operands[5] = gen_reg_rtx (SImode); 7198}") 7199 7200;; It might seem that operands 0 & 1 could use predicate register_operand. 7201;; But strength reduction might offset the MEM expression. So we let 7202;; reload put the address into %edi. 7203 7204(define_insn "" 7205 [(set (match_operand:SI 0 "register_operand" "=&c") 7206 (unspec:SI [(mem:BLK (match_operand:SI 1 "address_operand" "D")) |
5769 (match_operand:QI 2 "register_operand" "a") | 7207 (match_operand:QI 2 "immediate_operand" "a") |
5770 (match_operand:SI 3 "immediate_operand" "i")] 0)) 5771 (clobber (match_dup 1))] 5772 "" 5773 "* 5774{ 5775 rtx xops[2]; 5776 5777 xops[0] = operands[0]; 5778 xops[1] = constm1_rtx; 5779 output_asm_insn (\"cld\", operands); 5780 output_asm_insn (AS2 (mov%L0,%1,%0), xops); 5781 return \"repnz\;scas%B2\"; 5782}") | 7208 (match_operand:SI 3 "immediate_operand" "i")] 0)) 7209 (clobber (match_dup 1))] 7210 "" 7211 "* 7212{ 7213 rtx xops[2]; 7214 7215 xops[0] = operands[0]; 7216 xops[1] = constm1_rtx; 7217 output_asm_insn (\"cld\", operands); 7218 output_asm_insn (AS2 (mov%L0,%1,%0), xops); 7219 return \"repnz\;scas%B2\"; 7220}") |
7221 7222/* Conditional move define_insns. */ 7223 7224(define_expand "movsicc" 7225 [(set (match_operand:SI 0 "register_operand" "") 7226 (if_then_else:SI (match_operand 1 "comparison_operator" "") 7227 (match_operand:SI 2 "nonimmediate_operand" "") 7228 (match_operand:SI 3 "nonimmediate_operand" "")))] 7229 "TARGET_CMOVE" 7230 " 7231{ 7232 if (GET_MODE_CLASS (GET_MODE (i386_compare_op0)) != MODE_INT) 7233 FAIL; 7234 7235 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), 7236 GET_MODE (i386_compare_op0), 7237 i386_compare_op0, i386_compare_op1); 7238}") 7239 7240(define_insn "" 7241 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 7242 (if_then_else:SI (match_operator 1 "comparison_operator" 7243 [(match_operand:QI 2 "nonimmediate_operand" "q,m,q,m") 7244 (match_operand:QI 3 "general_operand" "qmn,qn,qmn,qn")]) 7245 (match_operand:SI 4 "nonimmediate_operand" "rm,rm,0,0") 7246 (match_operand:SI 5 "nonimmediate_operand" "0,0,rm,rm")))] 7247 "TARGET_CMOVE" 7248 "#") 7249 7250(define_insn "" 7251 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 7252 (if_then_else:SI (match_operator 1 "comparison_operator" 7253 [(match_operand 2 "nonimmediate_operand" "r,m,r,m") 7254 (match_operand 3 "general_operand" "rmi,ri,rmi,ri")]) 7255 (match_operand:SI 4 "nonimmediate_operand" "rm,rm,0,0") 7256 (match_operand:SI 5 "nonimmediate_operand" "0,0,rm,rm")))] 7257 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT" 7258 "#") 7259 7260(define_split 7261 [(set (match_operand:SI 0 "register_operand" "=r,r") 7262 (if_then_else:SI (match_operator 1 "comparison_operator" 7263 [(match_operand 2 "nonimmediate_operand" "") 7264 (const_int 0)]) 7265 (match_operand:SI 3 "nonimmediate_operand" "rm,0") 7266 (match_operand:SI 4 "nonimmediate_operand" "0,rm")))] 7267 "TARGET_CMOVE && reload_completed" 7268 [(set (cc0) 7269 (match_dup 2)) 7270 (set (match_dup 0) 7271 (if_then_else:SI (match_op_dup 1 [(cc0) (const_int 0)]) 7272 (match_dup 3) (match_dup 4)))] 7273 "") 7274 7275(define_split 7276 [(set (match_operand:SI 0 "register_operand" "=r,r") 7277 (if_then_else:SI (match_operator 1 "comparison_operator" 7278 [(match_operand 2 "nonimmediate_operand" "") 7279 (match_operand 3 "general_operand" "")]) 7280 (match_operand:SI 4 "nonimmediate_operand" "rm,0") 7281 (match_operand:SI 5 "nonimmediate_operand" "0,rm")))] 7282 "TARGET_CMOVE && reload_completed" 7283 [(set (cc0) (compare (match_dup 2) (match_dup 3))) 7284 (set (match_dup 0) 7285 (if_then_else:SI (match_op_dup 1 [(cc0) (const_int 0)]) 7286 (match_dup 4) (match_dup 5)))] 7287 "") 7288 7289(define_insn "" 7290 [(set (match_operand:SI 0 "register_operand" "=r,r") 7291 (if_then_else:SI (match_operator 1 "comparison_operator" 7292 [(cc0) (const_int 0)]) 7293 (match_operand:SI 2 "nonimmediate_operand" "rm,0") 7294 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))] 7295 "TARGET_CMOVE && reload_completed" 7296 "* return output_int_conditional_move (which_alternative, operands);") 7297 7298(define_expand "movhicc" 7299 [(set (match_operand:HI 0 "register_operand" "") 7300 (if_then_else:HI (match_operand 1 "comparison_operator" "") 7301 (match_operand:HI 2 "nonimmediate_operand" "") 7302 (match_operand:HI 3 "nonimmediate_operand" "")))] 7303 "TARGET_CMOVE" 7304 " 7305{ 7306 if (GET_MODE_CLASS (GET_MODE (i386_compare_op0)) != MODE_INT) 7307 FAIL; 7308 7309 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), 7310 GET_MODE (i386_compare_op0), 7311 i386_compare_op0, i386_compare_op1); 7312}") 7313 7314(define_insn "" 7315 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") 7316 (if_then_else:HI (match_operator 1 "comparison_operator" 7317 [(match_operand:QI 2 "nonimmediate_operand" "q,m,q,m") 7318 (match_operand:QI 3 "general_operand" "qmn,qn,qmn,qn")]) 7319 (match_operand:HI 4 "nonimmediate_operand" "rm,rm,0,0") 7320 (match_operand:HI 5 "nonimmediate_operand" "0,0,rm,rm")))] 7321 "TARGET_CMOVE" 7322 "#") 7323 7324(define_insn "" 7325 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") 7326 (if_then_else:HI (match_operator 1 "comparison_operator" 7327 [(match_operand 2 "nonimmediate_operand" "r,m,r,m") 7328 (match_operand 3 "general_operand" "rmi,ri,rmi,ri")]) 7329 (match_operand:HI 4 "nonimmediate_operand" "rm,rm,0,0") 7330 (match_operand:HI 5 "nonimmediate_operand" "0,0,rm,rm")))] 7331 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT" 7332 "#") 7333 7334(define_split 7335 [(set (match_operand:HI 0 "register_operand" "=r,r") 7336 (if_then_else:HI (match_operator 1 "comparison_operator" 7337 [(match_operand 2 "nonimmediate_operand" "") 7338 (const_int 0)]) 7339 (match_operand:HI 3 "nonimmediate_operand" "rm,0") 7340 (match_operand:HI 4 "nonimmediate_operand" "0,rm")))] 7341 "TARGET_CMOVE && reload_completed" 7342 [(set (cc0) 7343 (match_dup 2)) 7344 (set (match_dup 0) 7345 (if_then_else:HI (match_op_dup 1 [(cc0) (const_int 0)]) 7346 (match_dup 3) (match_dup 4)))] 7347 "") 7348 7349(define_split 7350 [(set (match_operand:HI 0 "register_operand" "=r,r") 7351 (if_then_else:HI (match_operator 1 "comparison_operator" 7352 [(match_operand 2 "nonimmediate_operand" "") 7353 (match_operand 3 "general_operand" "")]) 7354 (match_operand:HI 4 "nonimmediate_operand" "rm,0") 7355 (match_operand:HI 5 "nonimmediate_operand" "0,rm")))] 7356 "TARGET_CMOVE && reload_completed" 7357 [(set (cc0) 7358 (compare (match_dup 2) (match_dup 3))) 7359 (set (match_dup 0) 7360 (if_then_else:HI (match_op_dup 1 [(cc0) (const_int 0)]) 7361 (match_dup 4) (match_dup 5)))] 7362 "") 7363 7364(define_insn "" 7365 [(set (match_operand:HI 0 "register_operand" "=r,r") 7366 (if_then_else:HI (match_operator 1 "comparison_operator" 7367 [(cc0) (const_int 0)]) 7368 (match_operand:HI 2 "nonimmediate_operand" "rm,0") 7369 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))] 7370 "TARGET_CMOVE && reload_completed" 7371 "* return output_int_conditional_move (which_alternative, operands);") 7372 7373(define_expand "movsfcc" 7374 [(set (match_operand:SF 0 "register_operand" "") 7375 (if_then_else:SF (match_operand 1 "comparison_operator" "") 7376 (match_operand:SF 2 "register_operand" "") 7377 (match_operand:SF 3 "register_operand" "")))] 7378 "TARGET_CMOVE" 7379 " 7380{ 7381 rtx temp; 7382 7383 if (GET_MODE_CLASS (GET_MODE (i386_compare_op0)) != MODE_INT) 7384 FAIL; 7385 7386 /* The floating point conditional move instructions don't directly 7387 support conditions resulting from a signed integer comparison. */ 7388 7389 switch (GET_CODE (operands[1])) 7390 { 7391 case LT: 7392 case LE: 7393 case GE: 7394 case GT: 7395 temp = emit_store_flag (gen_reg_rtx (QImode), 7396 GET_CODE (operands[1]), i386_compare_op0, i386_compare_op1, 7397 VOIDmode, 0, 0); 7398 7399 if (!temp) 7400 FAIL; 7401 7402 operands[1] = gen_rtx_fmt_ee (NE, QImode, temp, const0_rtx); 7403 break; 7404 7405 default: 7406 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), 7407 GET_MODE (i386_compare_op0), 7408 i386_compare_op0, i386_compare_op1); 7409 break; 7410 } 7411}") 7412 7413(define_insn "" 7414 [(set (match_operand:SF 0 "register_operand" "=f,f,f,f") 7415 (if_then_else:SF (match_operator 1 "comparison_operator" 7416 [(match_operand:QI 2 "nonimmediate_operand" "q,m,q,m") 7417 (match_operand:QI 3 "general_operand" "qmn,qn,qmn,qn")]) 7418 (match_operand:SF 4 "register_operand" "f,f,0,0") 7419 (match_operand:SF 5 "register_operand" "0,0,f,f")))] 7420 "TARGET_CMOVE 7421 && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE 7422 && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT" 7423 "#") 7424 7425(define_insn "" 7426 [(set (match_operand:SF 0 "register_operand" "=f,f,f,f") 7427 (if_then_else:SF (match_operator 1 "comparison_operator" 7428 [(match_operand 2 "nonimmediate_operand" "r,m,r,m") 7429 (match_operand 3 "general_operand" "rmi,ri,rmi,ri")]) 7430 (match_operand:SF 4 "register_operand" "f,f,0,0") 7431 (match_operand:SF 5 "register_operand" "0,0,f,f")))] 7432 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT 7433 && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE 7434 && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT" 7435 "#") 7436 7437(define_split 7438 [(set (match_operand:SF 0 "register_operand" "=f,f") 7439 (if_then_else:SF (match_operator 1 "comparison_operator" 7440 [(match_operand 2 "nonimmediate_operand" "") 7441 (const_int 0)]) 7442 (match_operand:SF 3 "register_operand" "f,0") 7443 (match_operand:SF 4 "register_operand" "0,f")))] 7444 "TARGET_CMOVE && reload_completed" 7445 [(set (cc0) 7446 (match_dup 2)) 7447 (set (match_dup 0) 7448 (if_then_else:SF (match_op_dup 1 [(cc0) (const_int 0)]) 7449 (match_dup 3) (match_dup 4)))] 7450 "") 7451 7452(define_split 7453 [(set (match_operand:SF 0 "register_operand" "=f,f") 7454 (if_then_else:SF (match_operator 1 "comparison_operator" 7455 [(match_operand 2 "nonimmediate_operand" "") 7456 (match_operand 3 "general_operand" "")]) 7457 (match_operand:SF 4 "register_operand" "f,0") 7458 (match_operand:SF 5 "register_operand" "0,f")))] 7459 "TARGET_CMOVE && reload_completed" 7460 [(set (cc0) (compare (match_dup 2) (match_dup 3))) 7461 (set (match_dup 0) 7462 (if_then_else:SF (match_op_dup 1 [(cc0) (const_int 0)]) 7463 (match_dup 4) (match_dup 5)))] 7464 "") 7465 7466(define_insn "" 7467 [(set (match_operand:SF 0 "register_operand" "=f,f") 7468 (if_then_else:SF (match_operator 1 "comparison_operator" 7469 [(cc0) (const_int 0)]) 7470 (match_operand:SF 2 "register_operand" "f,0") 7471 (match_operand:SF 3 "register_operand" "0,f")))] 7472 "TARGET_CMOVE && reload_completed" 7473 "* return output_fp_conditional_move (which_alternative, operands);") 7474 7475(define_expand "movdfcc" 7476 [(set (match_operand:DF 0 "register_operand" "") 7477 (if_then_else:DF (match_operand 1 "comparison_operator" "") 7478 (match_operand:DF 2 "register_operand" "") 7479 (match_operand:DF 3 "register_operand" "")))] 7480 "TARGET_CMOVE" 7481 " 7482{ 7483 rtx temp; 7484 7485 if (GET_MODE_CLASS (GET_MODE (i386_compare_op0)) != MODE_INT) 7486 FAIL; 7487 7488 /* The floating point conditional move instructions don't directly 7489 support conditions resulting from a signed integer comparison. */ 7490 7491 switch (GET_CODE (operands[1])) 7492 { 7493 case LT: 7494 case LE: 7495 case GE: 7496 case GT: 7497 temp = emit_store_flag (gen_reg_rtx (QImode), 7498 GET_CODE (operands[1]), i386_compare_op0, i386_compare_op1, 7499 VOIDmode, 0, 0); 7500 7501 if (!temp) 7502 FAIL; 7503 7504 operands[1] = gen_rtx_fmt_ee (NE, QImode, temp, const0_rtx); 7505 break; 7506 7507 default: 7508 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), 7509 GET_MODE (i386_compare_op0), 7510 i386_compare_op0, i386_compare_op1); 7511 break; 7512 } 7513}") 7514 7515(define_insn "" 7516 [(set (match_operand:DF 0 "register_operand" "=f,f,f,f") 7517 (if_then_else:DF (match_operator 1 "comparison_operator" 7518 [(match_operand:QI 2 "nonimmediate_operand" "q,m,q,m") 7519 (match_operand:QI 3 "general_operand" "qmn,qn,qmn,qn")]) 7520 (match_operand:DF 4 "register_operand" "f,f,0,0") 7521 (match_operand:DF 5 "register_operand" "0,0,f,f")))] 7522 "TARGET_CMOVE 7523 && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE 7524 && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT" 7525 "#") 7526 7527(define_insn "" 7528 [(set (match_operand:DF 0 "register_operand" "=f,f,f,f") 7529 (if_then_else:DF (match_operator 1 "comparison_operator" 7530 [(match_operand 2 "nonimmediate_operand" "r,m,r,m") 7531 (match_operand 3 "general_operand" "rmi,ri,rmi,ri")]) 7532 (match_operand:DF 4 "register_operand" "f,f,0,0") 7533 (match_operand:DF 5 "register_operand" "0,0,f,f")))] 7534 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT 7535 && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE 7536 && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT" 7537 "#") 7538 7539(define_split 7540 [(set (match_operand:DF 0 "register_operand" "=f,f") 7541 (if_then_else:DF (match_operator 1 "comparison_operator" 7542 [(match_operand 2 "nonimmediate_operand" "") 7543 (const_int 0)]) 7544 (match_operand:DF 3 "register_operand" "f,0") 7545 (match_operand:DF 4 "register_operand" "0,f")))] 7546 "TARGET_CMOVE && reload_completed" 7547 [(set (cc0) 7548 (match_dup 2)) 7549 (set (match_dup 0) 7550 (if_then_else:DF (match_op_dup 1 [(cc0) (const_int 0)]) 7551 (match_dup 3) (match_dup 4)))] 7552 "") 7553 7554(define_split 7555 [(set (match_operand:DF 0 "register_operand" "=f,f") 7556 (if_then_else:DF (match_operator 1 "comparison_operator" 7557 [(match_operand 2 "nonimmediate_operand" "") 7558 (match_operand 3 "general_operand" "")]) 7559 (match_operand:DF 4 "register_operand" "f,0") 7560 (match_operand:DF 5 "register_operand" "0,f")))] 7561 "TARGET_CMOVE && reload_completed" 7562 [(set (cc0) (compare (match_dup 2) (match_dup 3))) 7563 (set (match_dup 0) 7564 (if_then_else:DF (match_op_dup 1 [(cc0) (const_int 0)]) 7565 (match_dup 4) (match_dup 5)))] 7566 "") 7567 7568(define_insn "" 7569 [(set (match_operand:DF 0 "register_operand" "=f,f") 7570 (if_then_else:DF (match_operator 1 "comparison_operator" 7571 [(cc0) (const_int 0)]) 7572 (match_operand:DF 2 "register_operand" "f,0") 7573 (match_operand:DF 3 "register_operand" "0,f")))] 7574 "TARGET_CMOVE && reload_completed" 7575 "* return output_fp_conditional_move (which_alternative, operands);") 7576 7577(define_expand "movxfcc" 7578 [(set (match_operand:XF 0 "register_operand" "") 7579 (if_then_else:XF (match_operand 1 "comparison_operator" "") 7580 (match_operand:XF 2 "register_operand" "") 7581 (match_operand:XF 3 "register_operand" "")))] 7582 "TARGET_CMOVE" 7583 " 7584{ 7585 rtx temp; 7586 7587 if (GET_MODE_CLASS (GET_MODE (i386_compare_op0)) != MODE_INT) 7588 FAIL; 7589 7590 /* The floating point conditional move instructions don't directly 7591 support conditions resulting from a signed integer comparison. */ 7592 7593 switch (GET_CODE (operands[1])) 7594 { 7595 case LT: 7596 case LE: 7597 case GE: 7598 case GT: 7599 temp = emit_store_flag (gen_reg_rtx (QImode), 7600 GET_CODE (operands[1]), i386_compare_op0, i386_compare_op1, 7601 VOIDmode, 0, 0); 7602 7603 if (!temp) 7604 FAIL; 7605 7606 operands[1] = gen_rtx_fmt_ee (NE, QImode, temp, const0_rtx); 7607 break; 7608 7609 default: 7610 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), 7611 GET_MODE (i386_compare_op0), 7612 i386_compare_op0, i386_compare_op1); 7613 break; 7614 } 7615}") 7616 7617(define_insn "" 7618 [(set (match_operand:XF 0 "register_operand" "=f,f,f,f") 7619 (if_then_else:XF (match_operator 1 "comparison_operator" 7620 [(match_operand:QI 2 "nonimmediate_operand" "q,m,q,m") 7621 (match_operand:QI 3 "general_operand" "qmn,qn,qmn,qn")]) 7622 (match_operand:XF 4 "register_operand" "f,f,0,0") 7623 (match_operand:XF 5 "register_operand" "0,0,f,f")))] 7624 "TARGET_CMOVE 7625 && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE 7626 && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT" 7627 "#") 7628 7629(define_insn "" 7630 [(set (match_operand:XF 0 "register_operand" "=f,f,f,f") 7631 (if_then_else:XF (match_operator 1 "comparison_operator" 7632 [(match_operand 2 "nonimmediate_operand" "r,m,r,m") 7633 (match_operand 3 "general_operand" "rmi,ri,rmi,ri")]) 7634 (match_operand:XF 4 "register_operand" "f,f,0,0") 7635 (match_operand:XF 5 "register_operand" "0,0,f,f")))] 7636 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT 7637 && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE 7638 && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT" 7639 "#") 7640 7641(define_split 7642 [(set (match_operand:XF 0 "register_operand" "=f,f") 7643 (if_then_else:XF (match_operator 1 "comparison_operator" 7644 [(match_operand 2 "nonimmediate_operand" "") 7645 (const_int 0)]) 7646 (match_operand:XF 3 "register_operand" "f,0") 7647 (match_operand:XF 4 "register_operand" "0,f")))] 7648 "TARGET_CMOVE && reload_completed" 7649 [(set (cc0) 7650 (match_dup 2)) 7651 (set (match_dup 0) 7652 (if_then_else:XF (match_op_dup 1 [(cc0) (const_int 0)]) 7653 (match_dup 3) (match_dup 4)))] 7654 "") 7655 7656(define_split 7657 [(set (match_operand:XF 0 "register_operand" "=f,f") 7658 (if_then_else:XF (match_operator 1 "comparison_operator" 7659 [(match_operand 2 "nonimmediate_operand" "") 7660 (match_operand 3 "general_operand" "")]) 7661 (match_operand:XF 4 "register_operand" "f,0") 7662 (match_operand:XF 5 "register_operand" "0,f")))] 7663 "TARGET_CMOVE && reload_completed" 7664 [(set (cc0) (compare (match_dup 2) (match_dup 3))) 7665 (set (match_dup 0) 7666 (if_then_else:XF (match_op_dup 1 [(cc0) (const_int 0)]) 7667 (match_dup 4) (match_dup 5)))] 7668 "") 7669 7670(define_insn "" 7671 [(set (match_operand:XF 0 "register_operand" "=f,f") 7672 (if_then_else:XF (match_operator 1 "comparison_operator" 7673 [(cc0) (const_int 0)]) 7674 (match_operand:XF 2 "register_operand" "f,0") 7675 (match_operand:XF 3 "register_operand" "0,f")))] 7676 "TARGET_CMOVE && reload_completed" 7677 "* return output_fp_conditional_move (which_alternative, operands);") 7678 7679(define_expand "movdicc" 7680 [(set (match_operand:DI 0 "register_operand" "") 7681 (if_then_else:DI (match_operand 1 "comparison_operator" "") 7682 (match_operand:DI 2 "nonimmediate_operand" "") 7683 (match_operand:DI 3 "nonimmediate_operand" "")))] 7684 "TARGET_CMOVE" 7685 " 7686{ 7687 if (GET_MODE_CLASS (GET_MODE (i386_compare_op0)) != MODE_INT) 7688 FAIL; 7689 7690 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), 7691 GET_MODE (i386_compare_op0), 7692 i386_compare_op0, i386_compare_op1); 7693}") 7694 7695(define_insn "" 7696 [(set (match_operand:DI 0 "register_operand" "=&r,&r,&r,&r") 7697 (if_then_else:DI (match_operator 1 "comparison_operator" 7698 [(match_operand:QI 2 "nonimmediate_operand" "q,m,q,m") 7699 (match_operand:QI 3 "general_operand" "qmn,qn,qmn,qn")]) 7700 (match_operand:DI 4 "nonimmediate_operand" "ro,ro,0,0") 7701 (match_operand:DI 5 "nonimmediate_operand" "0,0,ro,ro")))] 7702 "TARGET_CMOVE" 7703 "#") 7704 7705(define_insn "" 7706 [(set (match_operand:DI 0 "register_operand" "=&r,&r,&r,&r") 7707 (if_then_else:DI (match_operator 1 "comparison_operator" 7708 [(match_operand 2 "nonimmediate_operand" "r,m,r,m") 7709 (match_operand 3 "general_operand" "rmi,ri,rmi,ri")]) 7710 (match_operand:DI 4 "nonimmediate_operand" "ro,ro,0,0") 7711 (match_operand:DI 5 "nonimmediate_operand" "0,0,ro,ro")))] 7712 "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT" 7713 "#") 7714 7715(define_split 7716 [(set (match_operand:DI 0 "register_operand" "=&r,&r") 7717 (if_then_else:DI (match_operator 1 "comparison_operator" 7718 [(match_operand 2 "nonimmediate_operand" "") 7719 (const_int 0)]) 7720 (match_operand:DI 3 "nonimmediate_operand" "ro,0") 7721 (match_operand:DI 4 "nonimmediate_operand" "0,ro")))] 7722 "TARGET_CMOVE && reload_completed" 7723 [(set (cc0) 7724 (match_dup 2)) 7725 (set (match_dup 0) 7726 (if_then_else:DI (match_op_dup 1 [(cc0) (const_int 0)]) 7727 (match_dup 3) (match_dup 4)))] 7728 "") 7729 7730(define_split 7731 [(set (match_operand:DI 0 "register_operand" "=&r,&r") 7732 (if_then_else:DI (match_operator 1 "comparison_operator" 7733 [(match_operand 2 "nonimmediate_operand" "") 7734 (match_operand 3 "general_operand" "")]) 7735 (match_operand:DI 4 "nonimmediate_operand" "ro,0") 7736 (match_operand:DI 5 "nonimmediate_operand" "0,ro")))] 7737 "TARGET_CMOVE && reload_completed" 7738 [(set (cc0) (compare (match_dup 2) (match_dup 3))) 7739 (set (match_dup 0) 7740 (if_then_else:DI (match_op_dup 1 [(cc0) (const_int 0)]) 7741 (match_dup 4) (match_dup 5)))] 7742 "") 7743 7744(define_insn "" 7745 [(set (match_operand:DI 0 "register_operand" "=&r,&r") 7746 (if_then_else:DI (match_operator 1 "comparison_operator" 7747 [(cc0) (const_int 0)]) 7748 (match_operand:DI 2 "nonimmediate_operand" "ro,0") 7749 (match_operand:DI 3 "nonimmediate_operand" "0,ro")))] 7750 "TARGET_CMOVE && reload_completed" 7751 "* return output_int_conditional_move (which_alternative, operands);") 7752 7753(define_insn "strlensi_unroll" 7754 [(set (match_operand:SI 0 "register_operand" "=&r,&r") 7755 (unspec:SI [(mem:BLK (match_operand:SI 1 "address_operand" "r,r")) 7756 (match_operand:SI 2 "immediate_operand" "i,i")] 0)) 7757 (clobber (match_scratch:SI 3 "=&q,&r"))] 7758 "optimize > 1" 7759 "* return output_strlen_unroll (operands);") 7760 7761;; the only difference between the following patterns is the register preference 7762;; on a pentium using a q-register saves one clock cycle per 4 characters 7763 7764(define_insn "strlensi_unroll4" 7765 [(set (match_operand:SI 0 "register_operand" "=r,r") 7766 (unspec:SI [(mem:BLK (match_operand:SI 3 "register_operand" "0,0")) 7767 (match_operand:SI 1 "immediate_operand" "i,i") 7768 (match_operand:SI 2 "register_operand" "+q,!r")] 0)) 7769 (clobber (match_dup 2))] 7770 "(TARGET_USE_ANY_REG && optimize > 1)" 7771 "* return output_strlen_unroll (operands);") 7772 7773(define_insn "strlensi_unroll5" 7774 [(set (match_operand:SI 0 "register_operand" "=r") 7775 (unspec:SI [(mem:BLK (match_operand:SI 3 "register_operand" "0")) 7776 (match_operand:SI 1 "immediate_operand" "i") 7777 (match_operand:SI 2 "register_operand" "+q")] 0)) 7778 (clobber (match_dup 2))] 7779 "(TARGET_USE_Q_REG && optimize > 1)" 7780 "* return output_strlen_unroll (operands);" 7781) 7782 7783(define_insn "allocate_stack_worker" 7784 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3) 7785 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0))) 7786 (clobber (match_dup 0))] 7787 "TARGET_STACK_PROBE" 7788 "* return AS1(call,__alloca);") 7789 7790(define_expand "allocate_stack" 7791 [(set (match_operand:SI 0 "register_operand" "=r") 7792 (minus:SI (reg:SI 7) (match_operand:SI 1 "general_operand" ""))) 7793 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 1)))] 7794 "TARGET_STACK_PROBE" 7795 " 7796{ 7797#ifdef CHECK_STACK_LIMIT 7798 if (GET_CODE (operands[1]) == CONST_INT 7799 && INTVAL (operands[1]) < CHECK_STACK_LIMIT) 7800 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, 7801 operands[1])); 7802 else 7803#endif 7804 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode, 7805 operands[1]))); 7806 7807 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 7808 DONE; 7809}") 7810 7811(define_expand "exception_receiver" 7812 [(const_int 0)] 7813 "flag_pic" 7814 " 7815{ 7816 load_pic_register (1); 7817 DONE; 7818}") |
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