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i386.md (132727) i386.md (146906)
1;; GCC machine description for IA-32 and x86-64.
2;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3;; 2001, 2002, 2003, 2004
4;; Free Software Foundation, Inc.
5;; Mostly by William Schelter.
6;; x86_64 support added by Jan Hubicka
7;;
8;; This file is part of GCC.

--- 1247 unchanged lines hidden (view full) ---

1256(define_insn "*swapsi"
1257 [(set (match_operand:SI 0 "register_operand" "+r")
1258 (match_operand:SI 1 "register_operand" "+r"))
1259 (set (match_dup 1)
1260 (match_dup 0))]
1261 ""
1262 "xchg{l}\t%1, %0"
1263 [(set_attr "type" "imov")
1;; GCC machine description for IA-32 and x86-64.
2;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3;; 2001, 2002, 2003, 2004
4;; Free Software Foundation, Inc.
5;; Mostly by William Schelter.
6;; x86_64 support added by Jan Hubicka
7;;
8;; This file is part of GCC.

--- 1247 unchanged lines hidden (view full) ---

1256(define_insn "*swapsi"
1257 [(set (match_operand:SI 0 "register_operand" "+r")
1258 (match_operand:SI 1 "register_operand" "+r"))
1259 (set (match_dup 1)
1260 (match_dup 0))]
1261 ""
1262 "xchg{l}\t%1, %0"
1263 [(set_attr "type" "imov")
1264 (set_attr "mode" "SI")
1264 (set_attr "pent_pair" "np")
1265 (set_attr "athlon_decode" "vector")
1265 (set_attr "pent_pair" "np")
1266 (set_attr "athlon_decode" "vector")
1266 (set_attr "mode" "SI")
1267 (set_attr "modrm" "0")
1268 (set_attr "ppro_uops" "few")])
1269
1270(define_expand "movhi"
1271 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1272 (match_operand:HI 1 "general_operand" ""))]
1273 ""
1274 "ix86_expand_move (HImode, operands); DONE;")
1275

--- 96 unchanged lines hidden (view full) ---

1372 (set_attr "memory" "load")
1373 (set_attr "mode" "HI")])
1374
1375(define_insn "*swaphi_1"
1376 [(set (match_operand:HI 0 "register_operand" "+r")
1377 (match_operand:HI 1 "register_operand" "+r"))
1378 (set (match_dup 1)
1379 (match_dup 0))]
1267 (set_attr "ppro_uops" "few")])
1268
1269(define_expand "movhi"
1270 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1271 (match_operand:HI 1 "general_operand" ""))]
1272 ""
1273 "ix86_expand_move (HImode, operands); DONE;")
1274

--- 96 unchanged lines hidden (view full) ---

1371 (set_attr "memory" "load")
1372 (set_attr "mode" "HI")])
1373
1374(define_insn "*swaphi_1"
1375 [(set (match_operand:HI 0 "register_operand" "+r")
1376 (match_operand:HI 1 "register_operand" "+r"))
1377 (set (match_dup 1)
1378 (match_dup 0))]
1380 "TARGET_PARTIAL_REG_STALL"
1381 "xchg{w}\t%1, %0"
1379 "!TARGET_PARTIAL_REG_STALL || optimize_size"
1380 "xchg{l}\t%k1, %k0"
1382 [(set_attr "type" "imov")
1381 [(set_attr "type" "imov")
1382 (set_attr "mode" "SI")
1383 (set_attr "pent_pair" "np")
1383 (set_attr "pent_pair" "np")
1384 (set_attr "mode" "HI")
1385 (set_attr "modrm" "0")
1384 (set_attr "athlon_decode" "vector")
1386 (set_attr "ppro_uops" "few")])
1387
1388(define_insn "*swaphi_2"
1389 [(set (match_operand:HI 0 "register_operand" "+r")
1390 (match_operand:HI 1 "register_operand" "+r"))
1391 (set (match_dup 1)
1392 (match_dup 0))]
1385 (set_attr "ppro_uops" "few")])
1386
1387(define_insn "*swaphi_2"
1388 [(set (match_operand:HI 0 "register_operand" "+r")
1389 (match_operand:HI 1 "register_operand" "+r"))
1390 (set (match_dup 1)
1391 (match_dup 0))]
1393 "! TARGET_PARTIAL_REG_STALL"
1394 "xchg{l}\t%k1, %k0"
1392 "TARGET_PARTIAL_REG_STALL"
1393 "xchg{w}\t%1, %0"
1395 [(set_attr "type" "imov")
1394 [(set_attr "type" "imov")
1395 (set_attr "mode" "HI")
1396 (set_attr "pent_pair" "np")
1396 (set_attr "pent_pair" "np")
1397 (set_attr "mode" "SI")
1398 (set_attr "modrm" "0")
1397 (set_attr "athlon_decode" "vector")
1399 (set_attr "ppro_uops" "few")])
1400
1401(define_expand "movstricthi"
1402 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1403 (match_operand:HI 1 "general_operand" ""))]
1404 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1405{
1406 /* Don't generate memory->memory moves, go through a register */

--- 131 unchanged lines hidden (view full) ---

1538 {
1539 emit_insn (gen_movqi (op2, op1));
1540 op1 = op2;
1541 }
1542 emit_insn (gen_movqi (op0, op1));
1543 DONE;
1544})
1545
1398 (set_attr "ppro_uops" "few")])
1399
1400(define_expand "movstricthi"
1401 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1402 (match_operand:HI 1 "general_operand" ""))]
1403 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1404{
1405 /* Don't generate memory->memory moves, go through a register */

--- 131 unchanged lines hidden (view full) ---

1537 {
1538 emit_insn (gen_movqi (op2, op1));
1539 op1 = op2;
1540 }
1541 emit_insn (gen_movqi (op0, op1));
1542 DONE;
1543})
1544
1546(define_insn "*swapqi"
1545(define_insn "*swapqi_1"
1547 [(set (match_operand:QI 0 "register_operand" "+r")
1548 (match_operand:QI 1 "register_operand" "+r"))
1549 (set (match_dup 1)
1550 (match_dup 0))]
1546 [(set (match_operand:QI 0 "register_operand" "+r")
1547 (match_operand:QI 1 "register_operand" "+r"))
1548 (set (match_dup 1)
1549 (match_dup 0))]
1551 ""
1552 "xchg{b}\t%1, %0"
1550 "!TARGET_PARTIAL_REG_STALL || optimize_size"
1551 "xchg{l}\t%k1, %k0"
1553 [(set_attr "type" "imov")
1552 [(set_attr "type" "imov")
1553 (set_attr "mode" "SI")
1554 (set_attr "pent_pair" "np")
1554 (set_attr "pent_pair" "np")
1555 (set_attr "athlon_decode" "vector")
1556 (set_attr "ppro_uops" "few")])
1557
1558(define_insn "*swapqi_2"
1559 [(set (match_operand:QI 0 "register_operand" "+q")
1560 (match_operand:QI 1 "register_operand" "+q"))
1561 (set (match_dup 1)
1562 (match_dup 0))]
1563 "TARGET_PARTIAL_REG_STALL"
1564 "xchg{b}\t%1, %0"
1565 [(set_attr "type" "imov")
1555 (set_attr "mode" "QI")
1566 (set_attr "mode" "QI")
1556 (set_attr "modrm" "0")
1567 (set_attr "pent_pair" "np")
1568 (set_attr "athlon_decode" "vector")
1557 (set_attr "ppro_uops" "few")])
1558
1559(define_expand "movstrictqi"
1560 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1561 (match_operand:QI 1 "general_operand" ""))]
1562 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1563{
1564 /* Don't generate memory->memory moves, go through a register. */

--- 538 unchanged lines hidden (view full) ---

2103(define_insn "*swapdi_rex64"
2104 [(set (match_operand:DI 0 "register_operand" "+r")
2105 (match_operand:DI 1 "register_operand" "+r"))
2106 (set (match_dup 1)
2107 (match_dup 0))]
2108 "TARGET_64BIT"
2109 "xchg{q}\t%1, %0"
2110 [(set_attr "type" "imov")
1569 (set_attr "ppro_uops" "few")])
1570
1571(define_expand "movstrictqi"
1572 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1573 (match_operand:QI 1 "general_operand" ""))]
1574 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1575{
1576 /* Don't generate memory->memory moves, go through a register. */

--- 538 unchanged lines hidden (view full) ---

2115(define_insn "*swapdi_rex64"
2116 [(set (match_operand:DI 0 "register_operand" "+r")
2117 (match_operand:DI 1 "register_operand" "+r"))
2118 (set (match_dup 1)
2119 (match_dup 0))]
2120 "TARGET_64BIT"
2121 "xchg{q}\t%1, %0"
2122 [(set_attr "type" "imov")
2123 (set_attr "mode" "DI")
2111 (set_attr "pent_pair" "np")
2112 (set_attr "athlon_decode" "vector")
2124 (set_attr "pent_pair" "np")
2125 (set_attr "athlon_decode" "vector")
2113 (set_attr "mode" "DI")
2114 (set_attr "modrm" "0")
2115 (set_attr "ppro_uops" "few")])
2116
2126 (set_attr "ppro_uops" "few")])
2127
2117
2118(define_expand "movsf"
2119 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2120 (match_operand:SF 1 "general_operand" ""))]
2121 ""
2122 "ix86_expand_move (SFmode, operands); DONE;")
2123
2124(define_insn "*pushsf"
2125 [(set (match_operand:SF 0 "push_operand" "=<,<,<")

--- 4183 unchanged lines hidden (view full) ---

6309 {
6310 operands[1] = GEN_INT (-INTVAL (operands[1]));
6311 return "sub{b}\t{%1, %0|%0, %1}";
6312 }
6313 return "add{b}\t{%1, %0|%0, %1}";
6314 }
6315}
6316 [(set (attr "type")
2128(define_expand "movsf"
2129 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2130 (match_operand:SF 1 "general_operand" ""))]
2131 ""
2132 "ix86_expand_move (SFmode, operands); DONE;")
2133
2134(define_insn "*pushsf"
2135 [(set (match_operand:SF 0 "push_operand" "=<,<,<")

--- 4183 unchanged lines hidden (view full) ---

6319 {
6320 operands[1] = GEN_INT (-INTVAL (operands[1]));
6321 return "sub{b}\t{%1, %0|%0, %1}";
6322 }
6323 return "add{b}\t{%1, %0|%0, %1}";
6324 }
6325}
6326 [(set (attr "type")
6317 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6327 (if_then_else (match_operand:QI 1 "incdec_operand" "")
6318 (const_string "incdec")
6319 (const_string "alu1")))
6328 (const_string "incdec")
6329 (const_string "alu1")))
6330 (set (attr "memory")
6331 (if_then_else (match_operand 1 "memory_operand" "")
6332 (const_string "load")
6333 (const_string "none")))
6320 (set_attr "mode" "QI")])
6321
6322(define_insn "*addqi_2"
6323 [(set (reg 17)
6324 (compare
6325 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6326 (match_operand:QI 2 "general_operand" "qmni,qni"))
6327 (const_int 0)))

--- 1539 unchanged lines hidden (view full) ---

7867(define_expand "testqi_ccz_1"
7868 [(set (reg:CCZ 17)
7869 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7870 (match_operand:QI 1 "nonmemory_operand" ""))
7871 (const_int 0)))]
7872 ""
7873 "")
7874
6334 (set_attr "mode" "QI")])
6335
6336(define_insn "*addqi_2"
6337 [(set (reg 17)
6338 (compare
6339 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6340 (match_operand:QI 2 "general_operand" "qmni,qni"))
6341 (const_int 0)))

--- 1539 unchanged lines hidden (view full) ---

7881(define_expand "testqi_ccz_1"
7882 [(set (reg:CCZ 17)
7883 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7884 (match_operand:QI 1 "nonmemory_operand" ""))
7885 (const_int 0)))]
7886 ""
7887 "")
7888
7875(define_insn "*testqi_1"
7889(define_insn "*testqi_1_maybe_si"
7876 [(set (reg 17)
7890 [(set (reg 17)
7877 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
7878 (match_operand:QI 1 "general_operand" "n,n,qn,n"))
7879 (const_int 0)))]
7880 "ix86_match_ccmode (insn, CCNOmode)
7881 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7891 (compare
7892 (and:QI
7893 (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
7894 (match_operand:QI 1 "general_operand" "n,n,qn,n"))
7895 (const_int 0)))]
7896 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
7897 && ix86_match_ccmode (insn,
7898 GET_CODE (operands[1]) == CONST_INT
7899 && INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)"
7882{
7883 if (which_alternative == 3)
7884 {
7900{
7901 if (which_alternative == 3)
7902 {
7885 if (GET_CODE (operands[1]) == CONST_INT
7886 && (INTVAL (operands[1]) & 0xffffff00))
7903 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0)
7887 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7888 return "test{l}\t{%1, %k0|%k0, %1}";
7889 }
7890 return "test{b}\t{%1, %0|%0, %1}";
7891}
7892 [(set_attr "type" "test")
7893 (set_attr "modrm" "0,1,1,1")
7894 (set_attr "mode" "QI,QI,QI,SI")
7895 (set_attr "pent_pair" "uv,np,uv,np")])
7896
7904 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7905 return "test{l}\t{%1, %k0|%k0, %1}";
7906 }
7907 return "test{b}\t{%1, %0|%0, %1}";
7908}
7909 [(set_attr "type" "test")
7910 (set_attr "modrm" "0,1,1,1")
7911 (set_attr "mode" "QI,QI,QI,SI")
7912 (set_attr "pent_pair" "uv,np,uv,np")])
7913
7914(define_insn "*testqi_1"
7915 [(set (reg 17)
7916 (compare
7917 (and:QI
7918 (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm")
7919 (match_operand:QI 1 "general_operand" "n,n,qn"))
7920 (const_int 0)))]
7921 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
7922 && ix86_match_ccmode (insn, CCNOmode)"
7923 "test{b}\t{%1, %0|%0, %1}"
7924 [(set_attr "type" "test")
7925 (set_attr "modrm" "0,1,1")
7926 (set_attr "mode" "QI")
7927 (set_attr "pent_pair" "uv,np,uv")])
7928
7897(define_expand "testqi_ext_ccno_0"
7898 [(set (reg:CCNO 17)
7899 (compare:CCNO
7900 (and:SI
7901 (zero_extract:SI
7902 (match_operand 0 "ext_register_operand" "")
7903 (const_int 8)
7904 (const_int 8))

--- 102 unchanged lines hidden (view full) ---

8007 && INTVAL (operands[1]) > 32))
8008 && (GET_MODE (operands[0]) == SImode
8009 || GET_MODE (operands[0]) == DImode
8010 || GET_MODE (operands[0]) == HImode
8011 || GET_MODE (operands[0]) == QImode)"
8012 "#")
8013
8014(define_split
7929(define_expand "testqi_ext_ccno_0"
7930 [(set (reg:CCNO 17)
7931 (compare:CCNO
7932 (and:SI
7933 (zero_extract:SI
7934 (match_operand 0 "ext_register_operand" "")
7935 (const_int 8)
7936 (const_int 8))

--- 102 unchanged lines hidden (view full) ---

8039 && INTVAL (operands[1]) > 32))
8040 && (GET_MODE (operands[0]) == SImode
8041 || GET_MODE (operands[0]) == DImode
8042 || GET_MODE (operands[0]) == HImode
8043 || GET_MODE (operands[0]) == QImode)"
8044 "#")
8045
8046(define_split
8015 [(set (reg 17)
8016 (compare (zero_extract
8017 (match_operand 0 "nonimmediate_operand" "")
8018 (match_operand 1 "const_int_operand" "")
8019 (match_operand 2 "const_int_operand" ""))
8020 (const_int 0)))]
8047 [(set (match_operand 0 "flags_reg_operand" "")
8048 (match_operator 1 "compare_operator"
8049 [(zero_extract
8050 (match_operand 2 "nonimmediate_operand" "")
8051 (match_operand 3 "const_int_operand" "")
8052 (match_operand 4 "const_int_operand" ""))
8053 (const_int 0)]))]
8021 "ix86_match_ccmode (insn, CCNOmode)"
8054 "ix86_match_ccmode (insn, CCNOmode)"
8022 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
8055 [(set (match_dup 0) (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
8023{
8056{
8024 HOST_WIDE_INT len = INTVAL (operands[1]);
8025 HOST_WIDE_INT pos = INTVAL (operands[2]);
8057 rtx val = operands[2];
8058 HOST_WIDE_INT len = INTVAL (operands[3]);
8059 HOST_WIDE_INT pos = INTVAL (operands[4]);
8026 HOST_WIDE_INT mask;
8027 enum machine_mode mode, submode;
8028
8060 HOST_WIDE_INT mask;
8061 enum machine_mode mode, submode;
8062
8029 mode = GET_MODE (operands[0]);
8030 if (GET_CODE (operands[0]) == MEM)
8063 mode = GET_MODE (val);
8064 if (GET_CODE (val) == MEM)
8031 {
8032 /* ??? Combine likes to put non-volatile mem extractions in QImode
8033 no matter the size of the test. So find a mode that works. */
8065 {
8066 /* ??? Combine likes to put non-volatile mem extractions in QImode
8067 no matter the size of the test. So find a mode that works. */
8034 if (! MEM_VOLATILE_P (operands[0]))
8068 if (! MEM_VOLATILE_P (val))
8035 {
8036 mode = smallest_mode_for_size (pos + len, MODE_INT);
8069 {
8070 mode = smallest_mode_for_size (pos + len, MODE_INT);
8037 operands[0] = adjust_address (operands[0], mode, 0);
8071 val = adjust_address (val, mode, 0);
8038 }
8039 }
8072 }
8073 }
8040 else if (GET_CODE (operands[0]) == SUBREG
8041 && (submode = GET_MODE (SUBREG_REG (operands[0])),
8074 else if (GET_CODE (val) == SUBREG
8075 && (submode = GET_MODE (SUBREG_REG (val)),
8042 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
8043 && pos + len <= GET_MODE_BITSIZE (submode))
8044 {
8045 /* Narrow a paradoxical subreg to prevent partial register stalls. */
8046 mode = submode;
8076 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
8077 && pos + len <= GET_MODE_BITSIZE (submode))
8078 {
8079 /* Narrow a paradoxical subreg to prevent partial register stalls. */
8080 mode = submode;
8047 operands[0] = SUBREG_REG (operands[0]);
8081 val = SUBREG_REG (val);
8048 }
8049 else if (mode == HImode && pos + len <= 8)
8050 {
8051 /* Small HImode tests can be converted to QImode. */
8052 mode = QImode;
8082 }
8083 else if (mode == HImode && pos + len <= 8)
8084 {
8085 /* Small HImode tests can be converted to QImode. */
8086 mode = QImode;
8053 operands[0] = gen_lowpart (QImode, operands[0]);
8087 val = gen_lowpart (QImode, val);
8054 }
8055
8056 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8057 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8058
8088 }
8089
8090 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8091 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8092
8059 operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
8093 operands[2] = gen_rtx_AND (mode, val, gen_int_mode (mask, mode));
8060})
8061
8062;; Convert HImode/SImode test instructions with immediate to QImode ones.
8063;; i386 does not allow to encode test with 8bit sign extended immediate, so
8064;; this is relatively important trick.
8065;; Do the conversion only post-reload to avoid limiting of the register class
8066;; to QI regs.
8067(define_split
8094})
8095
8096;; Convert HImode/SImode test instructions with immediate to QImode ones.
8097;; i386 does not allow to encode test with 8bit sign extended immediate, so
8098;; this is relatively important trick.
8099;; Do the conversion only post-reload to avoid limiting of the register class
8100;; to QI regs.
8101(define_split
8068 [(set (reg 17)
8069 (compare
8070 (and (match_operand 0 "register_operand" "")
8071 (match_operand 1 "const_int_operand" ""))
8072 (const_int 0)))]
8102 [(set (match_operand 0 "flags_reg_operand" "")
8103 (match_operator 1 "compare_operator"
8104 [(and (match_operand 2 "register_operand" "")
8105 (match_operand 3 "const_int_operand" ""))
8106 (const_int 0)]))]
8073 "reload_completed
8107 "reload_completed
8074 && QI_REG_P (operands[0])
8108 && QI_REG_P (operands[2])
8109 && GET_MODE (operands[2]) != QImode
8075 && ((ix86_match_ccmode (insn, CCZmode)
8110 && ((ix86_match_ccmode (insn, CCZmode)
8076 && !(INTVAL (operands[1]) & ~(255 << 8)))
8111 && !(INTVAL (operands[3]) & ~(255 << 8)))
8077 || (ix86_match_ccmode (insn, CCNOmode)
8112 || (ix86_match_ccmode (insn, CCNOmode)
8078 && !(INTVAL (operands[1]) & ~(127 << 8))))
8079 && GET_MODE (operands[0]) != QImode"
8080 [(set (reg:CCNO 17)
8081 (compare:CCNO
8082 (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8083 (match_dup 1))
8084 (const_int 0)))]
8085 "operands[0] = gen_lowpart (SImode, operands[0]);
8086 operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);")
8113 && !(INTVAL (operands[3]) & ~(127 << 8))))"
8114 [(set (match_dup 0)
8115 (match_op_dup 1
8116 [(and:SI (zero_extract:SI (match_dup 2) (const_int 8) (const_int 8))
8117 (match_dup 3))
8118 (const_int 0)]))]
8119 "operands[2] = gen_lowpart (SImode, operands[2]);
8120 operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);")
8087
8088(define_split
8121
8122(define_split
8089 [(set (reg 17)
8090 (compare
8091 (and (match_operand 0 "nonimmediate_operand" "")
8092 (match_operand 1 "const_int_operand" ""))
8093 (const_int 0)))]
8123 [(set (match_operand 0 "flags_reg_operand" "")
8124 (match_operator 1 "compare_operator"
8125 [(and (match_operand 2 "nonimmediate_operand" "")
8126 (match_operand 3 "const_int_operand" ""))
8127 (const_int 0)]))]
8094 "reload_completed
8128 "reload_completed
8095 && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0]))
8129 && GET_MODE (operands[2]) != QImode
8130 && (!REG_P (operands[2]) || ANY_QI_REG_P (operands[2]))
8096 && ((ix86_match_ccmode (insn, CCZmode)
8131 && ((ix86_match_ccmode (insn, CCZmode)
8097 && !(INTVAL (operands[1]) & ~255))
8132 && !(INTVAL (operands[3]) & ~255))
8098 || (ix86_match_ccmode (insn, CCNOmode)
8133 || (ix86_match_ccmode (insn, CCNOmode)
8099 && !(INTVAL (operands[1]) & ~127)))
8100 && GET_MODE (operands[0]) != QImode"
8101 [(set (reg:CCNO 17)
8102 (compare:CCNO
8103 (and:QI (match_dup 0)
8104 (match_dup 1))
8105 (const_int 0)))]
8106 "operands[0] = gen_lowpart (QImode, operands[0]);
8107 operands[1] = gen_lowpart (QImode, operands[1]);")
8134 && !(INTVAL (operands[3]) & ~127)))"
8135 [(set (match_dup 0)
8136 (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
8137 (const_int 0)]))]
8138 "operands[2] = gen_lowpart (QImode, operands[2]);
8139 operands[3] = gen_lowpart (QImode, operands[3]);")
8108
8109
8110;; %%% This used to optimize known byte-wide and operations to memory,
8111;; and sometimes to QImode registers. If this is considered useful,
8112;; it should be done with splitters.
8113
8114(define_expand "anddi3"
8115 [(set (match_operand:DI 0 "nonimmediate_operand" "")

--- 260 unchanged lines hidden (view full) ---

8376 (match_operand:QI 1 "general_operand" "qi,qmi")))
8377 (clobber (reg:CC 17))]
8378 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8379 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8380 "and{b}\t{%1, %0|%0, %1}"
8381 [(set_attr "type" "alu1")
8382 (set_attr "mode" "QI")])
8383
8140
8141
8142;; %%% This used to optimize known byte-wide and operations to memory,
8143;; and sometimes to QImode registers. If this is considered useful,
8144;; it should be done with splitters.
8145
8146(define_expand "anddi3"
8147 [(set (match_operand:DI 0 "nonimmediate_operand" "")

--- 260 unchanged lines hidden (view full) ---

8408 (match_operand:QI 1 "general_operand" "qi,qmi")))
8409 (clobber (reg:CC 17))]
8410 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8411 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8412 "and{b}\t{%1, %0|%0, %1}"
8413 [(set_attr "type" "alu1")
8414 (set_attr "mode" "QI")])
8415
8384(define_insn "*andqi_2"
8416(define_insn "*andqi_2_maybe_si"
8385 [(set (reg 17)
8386 (compare (and:QI
8417 [(set (reg 17)
8418 (compare (and:QI
8387 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8388 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8419 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8420 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8389 (const_int 0)))
8390 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8391 (and:QI (match_dup 1) (match_dup 2)))]
8421 (const_int 0)))
8422 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8423 (and:QI (match_dup 1) (match_dup 2)))]
8392 "ix86_match_ccmode (insn, CCNOmode)
8393 && ix86_binary_operator_ok (AND, QImode, operands)"
8424 "ix86_binary_operator_ok (AND, QImode, operands)
8425 && ix86_match_ccmode (insn,
8426 GET_CODE (operands[2]) == CONST_INT
8427 && INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)"
8394{
8395 if (which_alternative == 2)
8396 {
8428{
8429 if (which_alternative == 2)
8430 {
8397 if (GET_CODE (operands[2]) == CONST_INT
8398 && (INTVAL (operands[2]) & 0xffffff00))
8431 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
8399 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8400 return "and{l}\t{%2, %k0|%k0, %2}";
8401 }
8402 return "and{b}\t{%2, %0|%0, %2}";
8403}
8404 [(set_attr "type" "alu")
8405 (set_attr "mode" "QI,QI,SI")])
8406
8432 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8433 return "and{l}\t{%2, %k0|%k0, %2}";
8434 }
8435 return "and{b}\t{%2, %0|%0, %2}";
8436}
8437 [(set_attr "type" "alu")
8438 (set_attr "mode" "QI,QI,SI")])
8439
8440(define_insn "*andqi_2"
8441 [(set (reg 17)
8442 (compare (and:QI
8443 (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8444 (match_operand:QI 2 "general_operand" "qim,qi"))
8445 (const_int 0)))
8446 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8447 (and:QI (match_dup 1) (match_dup 2)))]
8448 "ix86_match_ccmode (insn, CCNOmode)
8449 && ix86_binary_operator_ok (AND, QImode, operands)"
8450 "and{b}\t{%2, %0|%0, %2}"
8451 [(set_attr "type" "alu")
8452 (set_attr "mode" "QI")])
8453
8407(define_insn "*andqi_2_slp"
8408 [(set (reg 17)
8409 (compare (and:QI
8410 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8411 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8412 (const_int 0)))
8413 (set (strict_low_part (match_dup 0))
8414 (and:QI (match_dup 0) (match_dup 1)))]

--- 1147 unchanged lines hidden (view full) ---

9562 (set_attr "mode" "QI")])
9563
9564;; Changing of sign for FP values is doable using integer unit too.
9565
9566(define_expand "negsf2"
9567 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9568 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9569 (clobber (reg:CC 17))])]
8454(define_insn "*andqi_2_slp"
8455 [(set (reg 17)
8456 (compare (and:QI
8457 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8458 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8459 (const_int 0)))
8460 (set (strict_low_part (match_dup 0))
8461 (and:QI (match_dup 0) (match_dup 1)))]

--- 1147 unchanged lines hidden (view full) ---

9609 (set_attr "mode" "QI")])
9610
9611;; Changing of sign for FP values is doable using integer unit too.
9612
9613(define_expand "negsf2"
9614 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9615 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9616 (clobber (reg:CC 17))])]
9570 "TARGET_80387"
9571 "if (TARGET_SSE)
9617 "TARGET_80387 || TARGET_SSE_MATH"
9618 "if (TARGET_SSE_MATH)
9572 {
9573 /* In case operand is in memory, we will not use SSE. */
9574 if (memory_operand (operands[0], VOIDmode)
9575 && rtx_equal_p (operands[0], operands[1]))
9576 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9577 else
9578 {
9579 /* Using SSE is tricky, since we need bitwise negation of -0

--- 56 unchanged lines hidden (view full) ---

9636 (clobber (reg:CC 17))])])
9637
9638(define_split
9639 [(set (match_operand:SF 0 "register_operand" "")
9640 (neg:SF (match_operand:SF 1 "register_operand" "")))
9641 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
9642 (clobber (reg:CC 17))]
9643 "reload_completed && SSE_REG_P (operands[0])"
9619 {
9620 /* In case operand is in memory, we will not use SSE. */
9621 if (memory_operand (operands[0], VOIDmode)
9622 && rtx_equal_p (operands[0], operands[1]))
9623 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9624 else
9625 {
9626 /* Using SSE is tricky, since we need bitwise negation of -0

--- 56 unchanged lines hidden (view full) ---

9683 (clobber (reg:CC 17))])])
9684
9685(define_split
9686 [(set (match_operand:SF 0 "register_operand" "")
9687 (neg:SF (match_operand:SF 1 "register_operand" "")))
9688 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
9689 (clobber (reg:CC 17))]
9690 "reload_completed && SSE_REG_P (operands[0])"
9644 [(set (subreg:TI (match_dup 0) 0)
9645 (xor:TI (match_dup 1)
9646 (match_dup 2)))]
9691 [(set (match_dup 0)
9692 (xor:V4SF (match_dup 1)
9693 (match_dup 2)))]
9647{
9694{
9648 operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0);
9649 operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0);
9695 operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
9696 operands[1] = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
9650 if (operands_match_p (operands[0], operands[2]))
9651 {
9652 rtx tmp;
9653 tmp = operands[1];
9654 operands[1] = operands[2];
9655 operands[2] = tmp;
9656 }
9657})
9658
9659
9660;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9661;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9662;; to itself.
9663(define_insn "*negsf2_if"
9664 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9665 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9666 (clobber (reg:CC 17))]
9697 if (operands_match_p (operands[0], operands[2]))
9698 {
9699 rtx tmp;
9700 tmp = operands[1];
9701 operands[1] = operands[2];
9702 operands[2] = tmp;
9703 }
9704})
9705
9706
9707;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9708;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9709;; to itself.
9710(define_insn "*negsf2_if"
9711 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9712 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9713 (clobber (reg:CC 17))]
9667 "TARGET_80387 && !TARGET_SSE
9714 "TARGET_80387
9668 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9669 "#")
9670
9671(define_split
9672 [(set (match_operand:SF 0 "fp_register_operand" "")
9673 (neg:SF (match_operand:SF 1 "register_operand" "")))
9674 (clobber (reg:CC 17))]
9675 "TARGET_80387 && reload_completed"

--- 26 unchanged lines hidden (view full) ---

9702 operands[0] = adjust_address (operands[0], QImode, size - 1);
9703 operands[1] = gen_int_mode (0x80, QImode);
9704})
9705
9706(define_expand "negdf2"
9707 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9708 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9709 (clobber (reg:CC 17))])]
9715 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9716 "#")
9717
9718(define_split
9719 [(set (match_operand:SF 0 "fp_register_operand" "")
9720 (neg:SF (match_operand:SF 1 "register_operand" "")))
9721 (clobber (reg:CC 17))]
9722 "TARGET_80387 && reload_completed"

--- 26 unchanged lines hidden (view full) ---

9749 operands[0] = adjust_address (operands[0], QImode, size - 1);
9750 operands[1] = gen_int_mode (0x80, QImode);
9751})
9752
9753(define_expand "negdf2"
9754 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9755 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9756 (clobber (reg:CC 17))])]
9710 "TARGET_80387"
9711 "if (TARGET_SSE2)
9757 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
9758 "if (TARGET_SSE2 && TARGET_SSE_MATH)
9712 {
9713 /* In case operand is in memory, we will not use SSE. */
9714 if (memory_operand (operands[0], VOIDmode)
9715 && rtx_equal_p (operands[0], operands[1]))
9716 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9717 else
9718 {
9719 /* Using SSE is tricky, since we need bitwise negation of -0

--- 84 unchanged lines hidden (view full) ---

9804 operands[2] = gen_lowpart (DImode, operands[2]);")
9805
9806(define_split
9807 [(set (match_operand:DF 0 "register_operand" "")
9808 (neg:DF (match_operand:DF 1 "register_operand" "")))
9809 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
9810 (clobber (reg:CC 17))]
9811 "reload_completed && SSE_REG_P (operands[0])"
9759 {
9760 /* In case operand is in memory, we will not use SSE. */
9761 if (memory_operand (operands[0], VOIDmode)
9762 && rtx_equal_p (operands[0], operands[1]))
9763 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9764 else
9765 {
9766 /* Using SSE is tricky, since we need bitwise negation of -0

--- 84 unchanged lines hidden (view full) ---

9851 operands[2] = gen_lowpart (DImode, operands[2]);")
9852
9853(define_split
9854 [(set (match_operand:DF 0 "register_operand" "")
9855 (neg:DF (match_operand:DF 1 "register_operand" "")))
9856 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
9857 (clobber (reg:CC 17))]
9858 "reload_completed && SSE_REG_P (operands[0])"
9812 [(set (subreg:TI (match_dup 0) 0)
9813 (xor:TI (match_dup 1)
9814 (match_dup 2)))]
9859 [(set (match_dup 0)
9860 (xor:V2DF (match_dup 1)
9861 (match_dup 2)))]
9815{
9816 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
9862{
9863 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
9817 operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0);
9818 operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0);
9864 operands[1] = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
9819 /* Avoid possible reformatting on the operands. */
9820 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
9821 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
9822 if (operands_match_p (operands[0], operands[2]))
9823 {
9824 rtx tmp;
9825 tmp = operands[1];
9826 operands[1] = operands[2];

--- 142 unchanged lines hidden (view full) ---

9969 (set_attr "ppro_uops" "few")])
9970
9971;; Absolute value instructions
9972
9973(define_expand "abssf2"
9974 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9975 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9976 (clobber (reg:CC 17))])]
9865 /* Avoid possible reformatting on the operands. */
9866 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
9867 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
9868 if (operands_match_p (operands[0], operands[2]))
9869 {
9870 rtx tmp;
9871 tmp = operands[1];
9872 operands[1] = operands[2];

--- 142 unchanged lines hidden (view full) ---

10015 (set_attr "ppro_uops" "few")])
10016
10017;; Absolute value instructions
10018
10019(define_expand "abssf2"
10020 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
10021 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
10022 (clobber (reg:CC 17))])]
9977 "TARGET_80387"
9978 "if (TARGET_SSE)
10023 "TARGET_80387 || TARGET_SSE_MATH"
10024 "if (TARGET_SSE_MATH)
9979 {
9980 /* In case operand is in memory, we will not use SSE. */
9981 if (memory_operand (operands[0], VOIDmode)
9982 && rtx_equal_p (operands[0], operands[1]))
9983 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
9984 else
9985 {
9986 /* Using SSE is tricky, since we need bitwise negation of -0

--- 57 unchanged lines hidden (view full) ---

10044 (clobber (reg:CC 17))])])
10045
10046(define_split
10047 [(set (match_operand:SF 0 "register_operand" "")
10048 (abs:SF (match_operand:SF 1 "register_operand" "")))
10049 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
10050 (clobber (reg:CC 17))]
10051 "reload_completed && SSE_REG_P (operands[0])"
10025 {
10026 /* In case operand is in memory, we will not use SSE. */
10027 if (memory_operand (operands[0], VOIDmode)
10028 && rtx_equal_p (operands[0], operands[1]))
10029 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
10030 else
10031 {
10032 /* Using SSE is tricky, since we need bitwise negation of -0

--- 57 unchanged lines hidden (view full) ---

10090 (clobber (reg:CC 17))])])
10091
10092(define_split
10093 [(set (match_operand:SF 0 "register_operand" "")
10094 (abs:SF (match_operand:SF 1 "register_operand" "")))
10095 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
10096 (clobber (reg:CC 17))]
10097 "reload_completed && SSE_REG_P (operands[0])"
10052 [(set (subreg:TI (match_dup 0) 0)
10053 (and:TI (match_dup 1)
10054 (match_dup 2)))]
10098 [(set (match_dup 0)
10099 (and:V4SF (match_dup 1)
10100 (match_dup 2)))]
10055{
10101{
10056 operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0);
10057 operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0);
10102 operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
10103 operands[1] = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
10058 if (operands_match_p (operands[0], operands[2]))
10059 {
10060 rtx tmp;
10061 tmp = operands[1];
10062 operands[1] = operands[2];
10063 operands[2] = tmp;
10064 }
10065})
10066
10067;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10068;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10069;; to itself.
10070(define_insn "*abssf2_if"
10071 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
10072 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
10073 (clobber (reg:CC 17))]
10104 if (operands_match_p (operands[0], operands[2]))
10105 {
10106 rtx tmp;
10107 tmp = operands[1];
10108 operands[1] = operands[2];
10109 operands[2] = tmp;
10110 }
10111})
10112
10113;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10114;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10115;; to itself.
10116(define_insn "*abssf2_if"
10117 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
10118 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
10119 (clobber (reg:CC 17))]
10074 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
10120 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands)"
10075 "#")
10076
10077(define_split
10078 [(set (match_operand:SF 0 "fp_register_operand" "")
10079 (abs:SF (match_operand:SF 1 "register_operand" "")))
10080 (clobber (reg:CC 17))]
10081 "TARGET_80387 && reload_completed"
10082 [(set (match_dup 0)

--- 25 unchanged lines hidden (view full) ---

10108 operands[0] = adjust_address (operands[0], QImode, size - 1);
10109 operands[1] = gen_int_mode (~0x80, QImode);
10110})
10111
10112(define_expand "absdf2"
10113 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
10114 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
10115 (clobber (reg:CC 17))])]
10121 "#")
10122
10123(define_split
10124 [(set (match_operand:SF 0 "fp_register_operand" "")
10125 (abs:SF (match_operand:SF 1 "register_operand" "")))
10126 (clobber (reg:CC 17))]
10127 "TARGET_80387 && reload_completed"
10128 [(set (match_dup 0)

--- 25 unchanged lines hidden (view full) ---

10154 operands[0] = adjust_address (operands[0], QImode, size - 1);
10155 operands[1] = gen_int_mode (~0x80, QImode);
10156})
10157
10158(define_expand "absdf2"
10159 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
10160 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
10161 (clobber (reg:CC 17))])]
10116 "TARGET_80387"
10117 "if (TARGET_SSE2)
10162 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
10163 "if (TARGET_SSE2 && TARGET_SSE_MATH)
10118 {
10119 /* In case operand is in memory, we will not use SSE. */
10120 if (memory_operand (operands[0], VOIDmode)
10121 && rtx_equal_p (operands[0], operands[1]))
10122 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
10123 else
10124 {
10125 /* Using SSE is tricky, since we need bitwise negation of -0

--- 72 unchanged lines hidden (view full) ---

10198 (clobber (reg:CC 17))])])
10199
10200(define_split
10201 [(set (match_operand:DF 0 "register_operand" "")
10202 (abs:DF (match_operand:DF 1 "register_operand" "")))
10203 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
10204 (clobber (reg:CC 17))]
10205 "reload_completed && SSE_REG_P (operands[0])"
10164 {
10165 /* In case operand is in memory, we will not use SSE. */
10166 if (memory_operand (operands[0], VOIDmode)
10167 && rtx_equal_p (operands[0], operands[1]))
10168 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
10169 else
10170 {
10171 /* Using SSE is tricky, since we need bitwise negation of -0

--- 72 unchanged lines hidden (view full) ---

10244 (clobber (reg:CC 17))])])
10245
10246(define_split
10247 [(set (match_operand:DF 0 "register_operand" "")
10248 (abs:DF (match_operand:DF 1 "register_operand" "")))
10249 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
10250 (clobber (reg:CC 17))]
10251 "reload_completed && SSE_REG_P (operands[0])"
10206 [(set (subreg:TI (match_dup 0) 0)
10207 (and:TI (match_dup 1)
10208 (match_dup 2)))]
10252 [(set (match_dup 0)
10253 (and:V2DF (match_dup 1)
10254 (match_dup 2)))]
10209{
10210 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
10255{
10256 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
10211 operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0);
10212 operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0);
10257 operands[1] = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
10213 /* Avoid possible reformatting on the operands. */
10214 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
10215 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
10216 if (operands_match_p (operands[0], operands[2]))
10217 {
10218 rtx tmp;
10219 tmp = operands[1];
10220 operands[1] = operands[2];

--- 157 unchanged lines hidden (view full) ---

10378 (not:DI (match_dup 1)))]
10379 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10380 && ix86_unary_operator_ok (NOT, DImode, operands)"
10381 "#"
10382 [(set_attr "type" "alu1")
10383 (set_attr "mode" "DI")])
10384
10385(define_split
10258 /* Avoid possible reformatting on the operands. */
10259 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
10260 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
10261 if (operands_match_p (operands[0], operands[2]))
10262 {
10263 rtx tmp;
10264 tmp = operands[1];
10265 operands[1] = operands[2];

--- 157 unchanged lines hidden (view full) ---

10423 (not:DI (match_dup 1)))]
10424 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10425 && ix86_unary_operator_ok (NOT, DImode, operands)"
10426 "#"
10427 [(set_attr "type" "alu1")
10428 (set_attr "mode" "DI")])
10429
10430(define_split
10386 [(set (reg 17)
10387 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10388 (const_int 0)))
10389 (set (match_operand:DI 0 "nonimmediate_operand" "")
10390 (not:DI (match_dup 1)))]
10431 [(set (match_operand 0 "flags_reg_operand" "")
10432 (match_operator 2 "compare_operator"
10433 [(not:DI (match_operand:DI 3 "nonimmediate_operand" ""))
10434 (const_int 0)]))
10435 (set (match_operand:DI 1 "nonimmediate_operand" "")
10436 (not:DI (match_dup 3)))]
10391 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10437 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10392 [(parallel [(set (reg:CCNO 17)
10393 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10394 (const_int 0)))
10395 (set (match_dup 0)
10396 (xor:DI (match_dup 1) (const_int -1)))])]
10438 [(parallel [(set (match_dup 0)
10439 (match_op_dup 2
10440 [(xor:DI (match_dup 3) (const_int -1))
10441 (const_int 0)]))
10442 (set (match_dup 1)
10443 (xor:DI (match_dup 3) (const_int -1)))])]
10397 "")
10398
10399(define_expand "one_cmplsi2"
10400 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10401 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10402 ""
10403 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10404

--- 22 unchanged lines hidden (view full) ---

10427 (not:SI (match_dup 1)))]
10428 "ix86_match_ccmode (insn, CCNOmode)
10429 && ix86_unary_operator_ok (NOT, SImode, operands)"
10430 "#"
10431 [(set_attr "type" "alu1")
10432 (set_attr "mode" "SI")])
10433
10434(define_split
10444 "")
10445
10446(define_expand "one_cmplsi2"
10447 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10448 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10449 ""
10450 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10451

--- 22 unchanged lines hidden (view full) ---

10474 (not:SI (match_dup 1)))]
10475 "ix86_match_ccmode (insn, CCNOmode)
10476 && ix86_unary_operator_ok (NOT, SImode, operands)"
10477 "#"
10478 [(set_attr "type" "alu1")
10479 (set_attr "mode" "SI")])
10480
10481(define_split
10435 [(set (reg 17)
10436 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10437 (const_int 0)))
10438 (set (match_operand:SI 0 "nonimmediate_operand" "")
10439 (not:SI (match_dup 1)))]
10482 [(set (match_operand 0 "flags_reg_operand" "")
10483 (match_operator 2 "compare_operator"
10484 [(not:SI (match_operand:SI 3 "nonimmediate_operand" ""))
10485 (const_int 0)]))
10486 (set (match_operand:SI 1 "nonimmediate_operand" "")
10487 (not:SI (match_dup 3)))]
10440 "ix86_match_ccmode (insn, CCNOmode)"
10488 "ix86_match_ccmode (insn, CCNOmode)"
10441 [(parallel [(set (reg:CCNO 17)
10442 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10443 (const_int 0)))
10444 (set (match_dup 0)
10445 (xor:SI (match_dup 1) (const_int -1)))])]
10489 [(parallel [(set (match_dup 0)
10490 (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
10491 (const_int 0)]))
10492 (set (match_dup 1)
10493 (xor:SI (match_dup 3) (const_int -1)))])]
10446 "")
10447
10448;; ??? Currently never generated - xor is used instead.
10449(define_insn "*one_cmplsi2_2_zext"
10450 [(set (reg 17)
10451 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10452 (const_int 0)))
10453 (set (match_operand:DI 0 "register_operand" "=r")
10454 (zero_extend:DI (not:SI (match_dup 1))))]
10455 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10456 && ix86_unary_operator_ok (NOT, SImode, operands)"
10457 "#"
10458 [(set_attr "type" "alu1")
10459 (set_attr "mode" "SI")])
10460
10461(define_split
10494 "")
10495
10496;; ??? Currently never generated - xor is used instead.
10497(define_insn "*one_cmplsi2_2_zext"
10498 [(set (reg 17)
10499 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10500 (const_int 0)))
10501 (set (match_operand:DI 0 "register_operand" "=r")
10502 (zero_extend:DI (not:SI (match_dup 1))))]
10503 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10504 && ix86_unary_operator_ok (NOT, SImode, operands)"
10505 "#"
10506 [(set_attr "type" "alu1")
10507 (set_attr "mode" "SI")])
10508
10509(define_split
10462 [(set (reg 17)
10463 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10464 (const_int 0)))
10465 (set (match_operand:DI 0 "register_operand" "")
10466 (zero_extend:DI (not:SI (match_dup 1))))]
10510 [(set (match_operand 0 "flags_reg_operand" "")
10511 (match_operator 2 "compare_operator"
10512 [(not:SI (match_operand:SI 3 "register_operand" ""))
10513 (const_int 0)]))
10514 (set (match_operand:DI 1 "register_operand" "")
10515 (zero_extend:DI (not:SI (match_dup 3))))]
10467 "ix86_match_ccmode (insn, CCNOmode)"
10516 "ix86_match_ccmode (insn, CCNOmode)"
10468 [(parallel [(set (reg:CCNO 17)
10469 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10470 (const_int 0)))
10471 (set (match_dup 0)
10472 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10517 [(parallel [(set (match_dup 0)
10518 (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
10519 (const_int 0)]))
10520 (set (match_dup 1)
10521 (zero_extend:DI (xor:SI (match_dup 3) (const_int -1))))])]
10473 "")
10474
10475(define_expand "one_cmplhi2"
10476 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10477 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10478 "TARGET_HIMODE_MATH"
10479 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10480

--- 13 unchanged lines hidden (view full) ---

10494 (not:HI (match_dup 1)))]
10495 "ix86_match_ccmode (insn, CCNOmode)
10496 && ix86_unary_operator_ok (NEG, HImode, operands)"
10497 "#"
10498 [(set_attr "type" "alu1")
10499 (set_attr "mode" "HI")])
10500
10501(define_split
10522 "")
10523
10524(define_expand "one_cmplhi2"
10525 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10526 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10527 "TARGET_HIMODE_MATH"
10528 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10529

--- 13 unchanged lines hidden (view full) ---

10543 (not:HI (match_dup 1)))]
10544 "ix86_match_ccmode (insn, CCNOmode)
10545 && ix86_unary_operator_ok (NEG, HImode, operands)"
10546 "#"
10547 [(set_attr "type" "alu1")
10548 (set_attr "mode" "HI")])
10549
10550(define_split
10502 [(set (reg 17)
10503 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10504 (const_int 0)))
10505 (set (match_operand:HI 0 "nonimmediate_operand" "")
10506 (not:HI (match_dup 1)))]
10551 [(set (match_operand 0 "flags_reg_operand" "")
10552 (match_operator 2 "compare_operator"
10553 [(not:HI (match_operand:HI 3 "nonimmediate_operand" ""))
10554 (const_int 0)]))
10555 (set (match_operand:HI 1 "nonimmediate_operand" "")
10556 (not:HI (match_dup 3)))]
10507 "ix86_match_ccmode (insn, CCNOmode)"
10557 "ix86_match_ccmode (insn, CCNOmode)"
10508 [(parallel [(set (reg:CCNO 17)
10509 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10510 (const_int 0)))
10511 (set (match_dup 0)
10512 (xor:HI (match_dup 1) (const_int -1)))])]
10558 [(parallel [(set (match_dup 0)
10559 (match_op_dup 2 [(xor:HI (match_dup 3) (const_int -1))
10560 (const_int 0)]))
10561 (set (match_dup 1)
10562 (xor:HI (match_dup 3) (const_int -1)))])]
10513 "")
10514
10515;; %%% Potential partial reg stall on alternative 1. What to do?
10516(define_expand "one_cmplqi2"
10517 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10518 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10519 "TARGET_QIMODE_MATH"
10520 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")

--- 16 unchanged lines hidden (view full) ---

10537 (not:QI (match_dup 1)))]
10538 "ix86_match_ccmode (insn, CCNOmode)
10539 && ix86_unary_operator_ok (NOT, QImode, operands)"
10540 "#"
10541 [(set_attr "type" "alu1")
10542 (set_attr "mode" "QI")])
10543
10544(define_split
10563 "")
10564
10565;; %%% Potential partial reg stall on alternative 1. What to do?
10566(define_expand "one_cmplqi2"
10567 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10568 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10569 "TARGET_QIMODE_MATH"
10570 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")

--- 16 unchanged lines hidden (view full) ---

10587 (not:QI (match_dup 1)))]
10588 "ix86_match_ccmode (insn, CCNOmode)
10589 && ix86_unary_operator_ok (NOT, QImode, operands)"
10590 "#"
10591 [(set_attr "type" "alu1")
10592 (set_attr "mode" "QI")])
10593
10594(define_split
10545 [(set (reg 17)
10546 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10547 (const_int 0)))
10548 (set (match_operand:QI 0 "nonimmediate_operand" "")
10549 (not:QI (match_dup 1)))]
10595 [(set (match_operand 0 "flags_reg_operand" "")
10596 (match_operator 2 "compare_operator"
10597 [(not:QI (match_operand:QI 3 "nonimmediate_operand" ""))
10598 (const_int 0)]))
10599 (set (match_operand:QI 1 "nonimmediate_operand" "")
10600 (not:QI (match_dup 3)))]
10550 "ix86_match_ccmode (insn, CCNOmode)"
10601 "ix86_match_ccmode (insn, CCNOmode)"
10551 [(parallel [(set (reg:CCNO 17)
10552 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10553 (const_int 0)))
10554 (set (match_dup 0)
10555 (xor:QI (match_dup 1) (const_int -1)))])]
10602 [(parallel [(set (match_dup 0)
10603 (match_op_dup 2 [(xor:QI (match_dup 3) (const_int -1))
10604 (const_int 0)]))
10605 (set (match_dup 1)
10606 (xor:QI (match_dup 3) (const_int -1)))])]
10556 "")
10557
10558;; Arithmetic shift instructions
10559
10560;; DImode shifts are implemented using the i386 "shift double" opcode,
10561;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10562;; is variable, then the count is in %cl and the "imm" operand is dropped
10563;; from the assembler input.

--- 6434 unchanged lines hidden (view full) ---

16998 (if_then_else (match_operator 1 "comparison_operator"
16999 [(match_operand 4 "nonimmediate_operand" "")
17000 (match_operand 5 "register_operand" "")])
17001 (match_operand 2 "nonimmediate_operand" "")
17002 (match_operand 3 "nonimmediate_operand" "")))
17003 (clobber (match_operand 6 "" ""))
17004 (clobber (reg:CC 17))]
17005 "!SSE_REG_P (operands[0]) && reload_completed
10607 "")
10608
10609;; Arithmetic shift instructions
10610
10611;; DImode shifts are implemented using the i386 "shift double" opcode,
10612;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10613;; is variable, then the count is in %cl and the "imm" operand is dropped
10614;; from the assembler input.

--- 6434 unchanged lines hidden (view full) ---

17049 (if_then_else (match_operator 1 "comparison_operator"
17050 [(match_operand 4 "nonimmediate_operand" "")
17051 (match_operand 5 "register_operand" "")])
17052 (match_operand 2 "nonimmediate_operand" "")
17053 (match_operand 3 "nonimmediate_operand" "")))
17054 (clobber (match_operand 6 "" ""))
17055 (clobber (reg:CC 17))]
17056 "!SSE_REG_P (operands[0]) && reload_completed
17006 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
17057 && (GET_MODE (operands[0]) == SFmode
17058 || (TARGET_SSE2 && GET_MODE (operands[0]) == DFmode))"
17007 [(const_int 0)]
17008{
17009 ix86_compare_op0 = operands[5];
17010 ix86_compare_op1 = operands[4];
17011 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
17012 VOIDmode, operands[5], operands[4]);
17013 ix86_expand_fp_movcc (operands);
17014 DONE;
17015})
17016
17017;; Split SSE based conditional move into sequence:
17018;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
17019;; and op2, op0 - zero op2 if comparison was false
17020;; nand op0, op3 - load op3 to op0 if comparison was false
17021;; or op2, op0 - get the nonzero one into the result.
17022(define_split
17059 [(const_int 0)]
17060{
17061 ix86_compare_op0 = operands[5];
17062 ix86_compare_op1 = operands[4];
17063 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
17064 VOIDmode, operands[5], operands[4]);
17065 ix86_expand_fp_movcc (operands);
17066 DONE;
17067})
17068
17069;; Split SSE based conditional move into sequence:
17070;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
17071;; and op2, op0 - zero op2 if comparison was false
17072;; nand op0, op3 - load op3 to op0 if comparison was false
17073;; or op2, op0 - get the nonzero one into the result.
17074(define_split
17023 [(set (match_operand 0 "register_operand" "")
17024 (if_then_else (match_operator 1 "sse_comparison_operator"
17025 [(match_operand 4 "register_operand" "")
17026 (match_operand 5 "nonimmediate_operand" "")])
17027 (match_operand 2 "register_operand" "")
17028 (match_operand 3 "register_operand" "")))
17075 [(set (match_operand:SF 0 "register_operand" "")
17076 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17077 [(match_operand:SF 4 "register_operand" "")
17078 (match_operand:SF 5 "nonimmediate_operand" "")])
17079 (match_operand:SF 2 "register_operand" "")
17080 (match_operand:SF 3 "register_operand" "")))
17029 (clobber (match_operand 6 "" ""))
17030 (clobber (reg:CC 17))]
17031 "SSE_REG_P (operands[0]) && reload_completed"
17032 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
17081 (clobber (match_operand 6 "" ""))
17082 (clobber (reg:CC 17))]
17083 "SSE_REG_P (operands[0]) && reload_completed"
17084 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
17033 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
17034 (subreg:TI (match_dup 4) 0)))
17035 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
17036 (subreg:TI (match_dup 3) 0)))
17037 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
17038 (subreg:TI (match_dup 7) 0)))]
17085 (set (match_dup 2) (and:V4SF (match_dup 2)
17086 (match_dup 8)))
17087 (set (match_dup 8) (and:V4SF (not:V4SF (match_dup 8))
17088 (match_dup 3)))
17089 (set (match_dup 0) (ior:V4SF (match_dup 6)
17090 (match_dup 7)))]
17039{
17091{
17092 /* If op2 == op3, op3 would be clobbered before it is used. */
17093 if (operands_match_p (operands[2], operands[3]))
17094 {
17095 emit_move_insn (operands[0], operands[2]);
17096 DONE;
17097 }
17098
17099 PUT_MODE (operands[1], GET_MODE (operands[0]));
17100 if (operands_match_p (operands[0], operands[4]))
17101 operands[6] = operands[4], operands[7] = operands[2];
17102 else
17103 operands[6] = operands[2], operands[7] = operands[4];
17104 operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
17105 operands[2] = simplify_gen_subreg (V4SFmode, operands[2], SFmode, 0);
17106 operands[3] = simplify_gen_subreg (V4SFmode, operands[3], SFmode, 0);
17107 operands[8] = simplify_gen_subreg (V4SFmode, operands[4], SFmode, 0);
17108 operands[6] = simplify_gen_subreg (V4SFmode, operands[6], SFmode, 0);
17109 operands[7] = simplify_gen_subreg (V4SFmode, operands[7], SFmode, 0);
17110})
17111
17112(define_split
17113 [(set (match_operand:DF 0 "register_operand" "")
17114 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17115 [(match_operand:DF 4 "register_operand" "")
17116 (match_operand:DF 5 "nonimmediate_operand" "")])
17117 (match_operand:DF 2 "register_operand" "")
17118 (match_operand:DF 3 "register_operand" "")))
17119 (clobber (match_operand 6 "" ""))
17120 (clobber (reg:CC 17))]
17121 "SSE_REG_P (operands[0]) && reload_completed"
17122 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
17123 (set (match_dup 2) (and:V2DF (match_dup 2)
17124 (match_dup 8)))
17125 (set (match_dup 8) (and:V2DF (not:V2DF (match_dup 8))
17126 (match_dup 3)))
17127 (set (match_dup 0) (ior:V2DF (match_dup 6)
17128 (match_dup 7)))]
17129{
17040 if (GET_MODE (operands[2]) == DFmode
17041 && TARGET_SSE_PARTIAL_REGS && !optimize_size)
17042 {
17043 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17044 emit_insn (gen_sse2_unpcklpd (op, op, op));
17045 op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17046 emit_insn (gen_sse2_unpcklpd (op, op, op));
17047 }

--- 5 unchanged lines hidden (view full) ---

17053 DONE;
17054 }
17055
17056 PUT_MODE (operands[1], GET_MODE (operands[0]));
17057 if (operands_match_p (operands[0], operands[4]))
17058 operands[6] = operands[4], operands[7] = operands[2];
17059 else
17060 operands[6] = operands[2], operands[7] = operands[4];
17130 if (GET_MODE (operands[2]) == DFmode
17131 && TARGET_SSE_PARTIAL_REGS && !optimize_size)
17132 {
17133 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17134 emit_insn (gen_sse2_unpcklpd (op, op, op));
17135 op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17136 emit_insn (gen_sse2_unpcklpd (op, op, op));
17137 }

--- 5 unchanged lines hidden (view full) ---

17143 DONE;
17144 }
17145
17146 PUT_MODE (operands[1], GET_MODE (operands[0]));
17147 if (operands_match_p (operands[0], operands[4]))
17148 operands[6] = operands[4], operands[7] = operands[2];
17149 else
17150 operands[6] = operands[2], operands[7] = operands[4];
17151 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
17152 operands[2] = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17153 operands[3] = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17154 operands[8] = simplify_gen_subreg (V2DFmode, operands[4], DFmode, 0);
17155 operands[6] = simplify_gen_subreg (V2DFmode, operands[6], DFmode, 0);
17156 operands[7] = simplify_gen_subreg (V2DFmode, operands[7], DFmode, 0);
17061})
17062
17063;; Special case of conditional move we can handle effectively.
17064;; Do not brother with the integer/floating point case, since these are
17065;; bot considerably slower, unlike in the generic case.
17066(define_insn "*sse_movsfcc_const0_1"
17067 [(set (match_operand:SF 0 "register_operand" "=&x")
17068 (if_then_else:SF (match_operator 1 "sse_comparison_operator"

--- 70 unchanged lines hidden (view full) ---

17139 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
17140 (match_operand:DF 5 "register_operand" "0")])
17141 (match_operand:DF 2 "const0_operand" "X")
17142 (match_operand:DF 3 "register_operand" "Y")))]
17143 "TARGET_SSE2"
17144 "#")
17145
17146(define_split
17157})
17158
17159;; Special case of conditional move we can handle effectively.
17160;; Do not brother with the integer/floating point case, since these are
17161;; bot considerably slower, unlike in the generic case.
17162(define_insn "*sse_movsfcc_const0_1"
17163 [(set (match_operand:SF 0 "register_operand" "=&x")
17164 (if_then_else:SF (match_operator 1 "sse_comparison_operator"

--- 70 unchanged lines hidden (view full) ---

17235 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
17236 (match_operand:DF 5 "register_operand" "0")])
17237 (match_operand:DF 2 "const0_operand" "X")
17238 (match_operand:DF 3 "register_operand" "Y")))]
17239 "TARGET_SSE2"
17240 "#")
17241
17242(define_split
17147 [(set (match_operand 0 "register_operand" "")
17148 (if_then_else (match_operator 1 "comparison_operator"
17149 [(match_operand 4 "nonimmediate_operand" "")
17150 (match_operand 5 "nonimmediate_operand" "")])
17151 (match_operand 2 "nonmemory_operand" "")
17152 (match_operand 3 "nonmemory_operand" "")))]
17243 [(set (match_operand:SF 0 "register_operand" "")
17244 (if_then_else:SF (match_operator 1 "comparison_operator"
17245 [(match_operand:SF 4 "nonimmediate_operand" "")
17246 (match_operand:SF 5 "nonimmediate_operand" "")])
17247 (match_operand:SF 2 "nonmemory_operand" "")
17248 (match_operand:SF 3 "nonmemory_operand" "")))]
17153 "SSE_REG_P (operands[0]) && reload_completed
17154 && (const0_operand (operands[2], GET_MODE (operands[0]))
17155 || const0_operand (operands[3], GET_MODE (operands[0])))"
17156 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
17249 "SSE_REG_P (operands[0]) && reload_completed
17250 && (const0_operand (operands[2], GET_MODE (operands[0]))
17251 || const0_operand (operands[3], GET_MODE (operands[0])))"
17252 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
17157 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
17158 (match_dup 7)))]
17253 (set (match_dup 8) (and:V4SF (match_dup 6) (match_dup 7)))]
17159{
17254{
17255 PUT_MODE (operands[1], GET_MODE (operands[0]));
17256 if (!sse_comparison_operator (operands[1], VOIDmode)
17257 || !rtx_equal_p (operands[0], operands[4]))
17258 {
17259 rtx tmp = operands[5];
17260 operands[5] = operands[4];
17261 operands[4] = tmp;
17262 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
17263 }
17264 if (!rtx_equal_p (operands[0], operands[4]))
17265 abort ();
17266 operands[8] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
17267 if (const0_operand (operands[2], GET_MODE (operands[2])))
17268 {
17269 operands[7] = operands[3];
17270 operands[6] = gen_rtx_NOT (V4SFmode, operands[5]);
17271 }
17272 else
17273 {
17274 operands[7] = operands[2];
17275 operands[6] = operands[8];
17276 }
17277 operands[7] = simplify_gen_subreg (V4SFmode, operands[7], SFmode, 0);
17278})
17279
17280(define_split
17281 [(set (match_operand:DF 0 "register_operand" "")
17282 (if_then_else:DF (match_operator 1 "comparison_operator"
17283 [(match_operand:DF 4 "nonimmediate_operand" "")
17284 (match_operand:DF 5 "nonimmediate_operand" "")])
17285 (match_operand:DF 2 "nonmemory_operand" "")
17286 (match_operand:DF 3 "nonmemory_operand" "")))]
17287 "SSE_REG_P (operands[0]) && reload_completed
17288 && (const0_operand (operands[2], GET_MODE (operands[0]))
17289 || const0_operand (operands[3], GET_MODE (operands[0])))"
17290 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
17291 (set (match_dup 8) (and:V2DF (match_dup 6) (match_dup 7)))]
17292{
17160 if (TARGET_SSE_PARTIAL_REGS && !optimize_size
17161 && GET_MODE (operands[2]) == DFmode)
17162 {
17163 if (REG_P (operands[2]))
17164 {
17165 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17166 emit_insn (gen_sse2_unpcklpd (op, op, op));
17167 }

--- 9 unchanged lines hidden (view full) ---

17177 {
17178 rtx tmp = operands[5];
17179 operands[5] = operands[4];
17180 operands[4] = tmp;
17181 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
17182 }
17183 if (!rtx_equal_p (operands[0], operands[4]))
17184 abort ();
17293 if (TARGET_SSE_PARTIAL_REGS && !optimize_size
17294 && GET_MODE (operands[2]) == DFmode)
17295 {
17296 if (REG_P (operands[2]))
17297 {
17298 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17299 emit_insn (gen_sse2_unpcklpd (op, op, op));
17300 }

--- 9 unchanged lines hidden (view full) ---

17310 {
17311 rtx tmp = operands[5];
17312 operands[5] = operands[4];
17313 operands[4] = tmp;
17314 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
17315 }
17316 if (!rtx_equal_p (operands[0], operands[4]))
17317 abort ();
17185 if (const0_operand (operands[2], GET_MODE (operands[0])))
17318 operands[8] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
17319 if (const0_operand (operands[2], GET_MODE (operands[2])))
17186 {
17187 operands[7] = operands[3];
17320 {
17321 operands[7] = operands[3];
17188 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
17189 0));
17322 operands[6] = gen_rtx_NOT (V2DFmode, operands[8]);
17190 }
17191 else
17192 {
17193 operands[7] = operands[2];
17323 }
17324 else
17325 {
17326 operands[7] = operands[2];
17194 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
17327 operands[6] = operands[8];
17195 }
17328 }
17196 operands[7] = simplify_gen_subreg (TImode, operands[7],
17197 GET_MODE (operands[7]), 0);
17329 operands[7] = simplify_gen_subreg (V2DFmode, operands[7], DFmode, 0);
17198})
17199
17200(define_expand "allocate_stack_worker"
17201 [(match_operand:SI 0 "register_operand" "")]
17202 "TARGET_STACK_PROBE"
17203{
17204 if (reload_completed)
17205 {

--- 108 unchanged lines hidden (view full) ---

17314 operands[2] = gen_lowpart (SImode, operands[2]);
17315 PUT_MODE (operands[3], SImode);")
17316
17317; Promote the QImode tests, as i386 has encoding of the AND
17318; instruction with 32-bit sign-extended immediate and thus the
17319; instruction size is unchanged, except in the %eax case for
17320; which it is increased by one byte, hence the ! optimize_size.
17321(define_split
17330})
17331
17332(define_expand "allocate_stack_worker"
17333 [(match_operand:SI 0 "register_operand" "")]
17334 "TARGET_STACK_PROBE"
17335{
17336 if (reload_completed)
17337 {

--- 108 unchanged lines hidden (view full) ---

17446 operands[2] = gen_lowpart (SImode, operands[2]);
17447 PUT_MODE (operands[3], SImode);")
17448
17449; Promote the QImode tests, as i386 has encoding of the AND
17450; instruction with 32-bit sign-extended immediate and thus the
17451; instruction size is unchanged, except in the %eax case for
17452; which it is increased by one byte, hence the ! optimize_size.
17453(define_split
17322 [(set (reg 17)
17323 (compare (and (match_operand 1 "aligned_operand" "")
17324 (match_operand 2 "const_int_operand" ""))
17325 (const_int 0)))
17326 (set (match_operand 0 "register_operand" "")
17327 (and (match_dup 1) (match_dup 2)))]
17454 [(set (match_operand 0 "flags_reg_operand" "")
17455 (match_operator 2 "compare_operator"
17456 [(and (match_operand 3 "aligned_operand" "")
17457 (match_operand 4 "const_int_operand" ""))
17458 (const_int 0)]))
17459 (set (match_operand 1 "register_operand" "")
17460 (and (match_dup 3) (match_dup 4)))]
17328 "! TARGET_PARTIAL_REG_STALL && reload_completed
17329 /* Ensure that the operand will remain sign-extended immediate. */
17461 "! TARGET_PARTIAL_REG_STALL && reload_completed
17462 /* Ensure that the operand will remain sign-extended immediate. */
17330 && ix86_match_ccmode (insn, INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)
17463 && ix86_match_ccmode (insn, INTVAL (operands[4]) >= 0 ? CCNOmode : CCZmode)
17331 && ! optimize_size
17464 && ! optimize_size
17332 && ((GET_MODE (operands[0]) == HImode && ! TARGET_FAST_PREFIX)
17333 || (GET_MODE (operands[0]) == QImode && TARGET_PROMOTE_QImode))"
17334 [(parallel [(set (reg:CCNO 17)
17335 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
17336 (const_int 0)))
17337 (set (match_dup 0)
17338 (and:SI (match_dup 1) (match_dup 2)))])]
17339 "operands[2]
17340 = gen_int_mode (INTVAL (operands[2])
17341 & GET_MODE_MASK (GET_MODE (operands[0])),
17342 SImode);
17343 operands[0] = gen_lowpart (SImode, operands[0]);
17344 operands[1] = gen_lowpart (SImode, operands[1]);")
17465 && ((GET_MODE (operands[1]) == HImode && ! TARGET_FAST_PREFIX)
17466 || (GET_MODE (operands[1]) == QImode && TARGET_PROMOTE_QImode))"
17467 [(parallel [(set (match_dup 0)
17468 (match_op_dup 2 [(and:SI (match_dup 3) (match_dup 4))
17469 (const_int 0)]))
17470 (set (match_dup 1)
17471 (and:SI (match_dup 3) (match_dup 4)))])]
17472{
17473 operands[4]
17474 = gen_int_mode (INTVAL (operands[4])
17475 & GET_MODE_MASK (GET_MODE (operands[1])), SImode);
17476 operands[1] = gen_lowpart (SImode, operands[1]);
17477 operands[3] = gen_lowpart (SImode, operands[3]);
17478})
17345
17346; Don't promote the QImode tests, as i386 doesn't have encoding of
17347; the TEST instruction with 32-bit sign-extended immediate and thus
17348; the instruction size would at least double, which is not what we
17349; want even with ! optimize_size.
17350(define_split
17479
17480; Don't promote the QImode tests, as i386 doesn't have encoding of
17481; the TEST instruction with 32-bit sign-extended immediate and thus
17482; the instruction size would at least double, which is not what we
17483; want even with ! optimize_size.
17484(define_split
17351 [(set (reg 17)
17352 (compare (and (match_operand:HI 0 "aligned_operand" "")
17353 (match_operand:HI 1 "const_int_operand" ""))
17354 (const_int 0)))]
17485 [(set (match_operand 0 "flags_reg_operand" "")
17486 (match_operator 1 "compare_operator"
17487 [(and (match_operand:HI 2 "aligned_operand" "")
17488 (match_operand:HI 3 "const_int_operand" ""))
17489 (const_int 0)]))]
17355 "! TARGET_PARTIAL_REG_STALL && reload_completed
17356 /* Ensure that the operand will remain sign-extended immediate. */
17490 "! TARGET_PARTIAL_REG_STALL && reload_completed
17491 /* Ensure that the operand will remain sign-extended immediate. */
17357 && ix86_match_ccmode (insn, INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)
17492 && ix86_match_ccmode (insn, INTVAL (operands[3]) >= 0 ? CCNOmode : CCZmode)
17358 && ! TARGET_FAST_PREFIX
17359 && ! optimize_size"
17493 && ! TARGET_FAST_PREFIX
17494 && ! optimize_size"
17360 [(set (reg:CCNO 17)
17361 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
17362 (const_int 0)))]
17363 "operands[1]
17364 = gen_int_mode (INTVAL (operands[1])
17365 & GET_MODE_MASK (GET_MODE (operands[0])),
17366 SImode);
17367 operands[0] = gen_lowpart (SImode, operands[0]);")
17495 [(set (match_dup 0)
17496 (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
17497 (const_int 0)]))]
17498{
17499 operands[3]
17500 = gen_int_mode (INTVAL (operands[3])
17501 & GET_MODE_MASK (GET_MODE (operands[2])), SImode);
17502 operands[2] = gen_lowpart (SImode, operands[2]);
17503})
17368
17369(define_split
17370 [(set (match_operand 0 "register_operand" "")
17371 (neg (match_operand 1 "register_operand" "")))
17372 (clobber (reg:CC 17))]
17373 "! TARGET_PARTIAL_REG_STALL && reload_completed
17374 && (GET_MODE (operands[0]) == HImode
17375 || (GET_MODE (operands[0]) == QImode

--- 156 unchanged lines hidden (view full) ---

17532 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
17533 && TARGET_SPLIT_LONG_MOVES"
17534 [(set (match_dup 2) (match_dup 1))
17535 (set (match_dup 0) (match_dup 2))]
17536 "")
17537
17538;; Don't compare memory with zero, load and use a test instead.
17539(define_peephole2
17504
17505(define_split
17506 [(set (match_operand 0 "register_operand" "")
17507 (neg (match_operand 1 "register_operand" "")))
17508 (clobber (reg:CC 17))]
17509 "! TARGET_PARTIAL_REG_STALL && reload_completed
17510 && (GET_MODE (operands[0]) == HImode
17511 || (GET_MODE (operands[0]) == QImode

--- 156 unchanged lines hidden (view full) ---

17668 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
17669 && TARGET_SPLIT_LONG_MOVES"
17670 [(set (match_dup 2) (match_dup 1))
17671 (set (match_dup 0) (match_dup 2))]
17672 "")
17673
17674;; Don't compare memory with zero, load and use a test instead.
17675(define_peephole2
17540 [(set (reg 17)
17541 (compare (match_operand:SI 0 "memory_operand" "")
17542 (const_int 0)))
17676 [(set (match_operand 0 "flags_reg_operand" "")
17677 (match_operator 1 "compare_operator"
17678 [(match_operand:SI 2 "memory_operand" "")
17679 (const_int 0)]))
17543 (match_scratch:SI 3 "r")]
17544 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
17680 (match_scratch:SI 3 "r")]
17681 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
17545 [(set (match_dup 3) (match_dup 0))
17546 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
17682 [(set (match_dup 3) (match_dup 2))
17683 (set (match_dup 0) (match_op_dup 1 [(match_dup 3) (const_int 0)]))]
17547 "")
17548
17549;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
17550;; Don't split NOTs with a displacement operand, because resulting XOR
17551;; will not be pairable anyway.
17552;;
17553;; On AMD K6, NOT is vector decoded with memory operand that can not be
17554;; represented using a modRM byte. The XOR replacement is long decoded,

--- 47 unchanged lines hidden (view full) ---

17602;; Non pairable "test imm, reg" instructions can be translated to
17603;; "and imm, reg" if reg dies. The "and" form is also shorter (one
17604;; byte opcode instead of two, have a short form for byte operands),
17605;; so do it for other CPUs as well. Given that the value was dead,
17606;; this should not create any new dependencies. Pass on the sub-word
17607;; versions if we're concerned about partial register stalls.
17608
17609(define_peephole2
17684 "")
17685
17686;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
17687;; Don't split NOTs with a displacement operand, because resulting XOR
17688;; will not be pairable anyway.
17689;;
17690;; On AMD K6, NOT is vector decoded with memory operand that can not be
17691;; represented using a modRM byte. The XOR replacement is long decoded,

--- 47 unchanged lines hidden (view full) ---

17739;; Non pairable "test imm, reg" instructions can be translated to
17740;; "and imm, reg" if reg dies. The "and" form is also shorter (one
17741;; byte opcode instead of two, have a short form for byte operands),
17742;; so do it for other CPUs as well. Given that the value was dead,
17743;; this should not create any new dependencies. Pass on the sub-word
17744;; versions if we're concerned about partial register stalls.
17745
17746(define_peephole2
17610 [(set (reg 17)
17611 (compare (and:SI (match_operand:SI 0 "register_operand" "")
17612 (match_operand:SI 1 "immediate_operand" ""))
17613 (const_int 0)))]
17747 [(set (match_operand 0 "flags_reg_operand" "")
17748 (match_operator 1 "compare_operator"
17749 [(and:SI (match_operand:SI 2 "register_operand" "")
17750 (match_operand:SI 3 "immediate_operand" ""))
17751 (const_int 0)]))]
17614 "ix86_match_ccmode (insn, CCNOmode)
17752 "ix86_match_ccmode (insn, CCNOmode)
17615 && (true_regnum (operands[0]) != 0
17616 || (GET_CODE (operands[1]) == CONST_INT
17617 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')))
17618 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17753 && (true_regnum (operands[2]) != 0
17754 || (GET_CODE (operands[3]) == CONST_INT
17755 && CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'K')))
17756 && peep2_reg_dead_p (1, operands[2])"
17619 [(parallel
17757 [(parallel
17620 [(set (reg:CCNO 17)
17621 (compare:CCNO (and:SI (match_dup 0)
17622 (match_dup 1))
17623 (const_int 0)))
17624 (set (match_dup 0)
17625 (and:SI (match_dup 0) (match_dup 1)))])]
17758 [(set (match_dup 0)
17759 (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
17760 (const_int 0)]))
17761 (set (match_dup 2)
17762 (and:SI (match_dup 2) (match_dup 3)))])]
17626 "")
17627
17628;; We don't need to handle HImode case, because it will be promoted to SImode
17629;; on ! TARGET_PARTIAL_REG_STALL
17630
17631(define_peephole2
17763 "")
17764
17765;; We don't need to handle HImode case, because it will be promoted to SImode
17766;; on ! TARGET_PARTIAL_REG_STALL
17767
17768(define_peephole2
17632 [(set (reg 17)
17633 (compare (and:QI (match_operand:QI 0 "register_operand" "")
17634 (match_operand:QI 1 "immediate_operand" ""))
17635 (const_int 0)))]
17769 [(set (match_operand 0 "flags_reg_operand" "")
17770 (match_operator 1 "compare_operator"
17771 [(and:QI (match_operand:QI 2 "register_operand" "")
17772 (match_operand:QI 3 "immediate_operand" ""))
17773 (const_int 0)]))]
17636 "! TARGET_PARTIAL_REG_STALL
17637 && ix86_match_ccmode (insn, CCNOmode)
17774 "! TARGET_PARTIAL_REG_STALL
17775 && ix86_match_ccmode (insn, CCNOmode)
17638 && true_regnum (operands[0]) != 0
17639 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17776 && true_regnum (operands[2]) != 0
17777 && peep2_reg_dead_p (1, operands[2])"
17640 [(parallel
17778 [(parallel
17641 [(set (reg:CCNO 17)
17642 (compare:CCNO (and:QI (match_dup 0)
17643 (match_dup 1))
17644 (const_int 0)))
17645 (set (match_dup 0)
17646 (and:QI (match_dup 0) (match_dup 1)))])]
17779 [(set (match_dup 0)
17780 (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
17781 (const_int 0)]))
17782 (set (match_dup 2)
17783 (and:QI (match_dup 2) (match_dup 3)))])]
17647 "")
17648
17649(define_peephole2
17784 "")
17785
17786(define_peephole2
17650 [(set (reg 17)
17651 (compare
17652 (and:SI
17653 (zero_extract:SI
17654 (match_operand 0 "ext_register_operand" "")
17655 (const_int 8)
17656 (const_int 8))
17657 (match_operand 1 "const_int_operand" ""))
17658 (const_int 0)))]
17787 [(set (match_operand 0 "flags_reg_operand" "")
17788 (match_operator 1 "compare_operator"
17789 [(and:SI
17790 (zero_extract:SI
17791 (match_operand 2 "ext_register_operand" "")
17792 (const_int 8)
17793 (const_int 8))
17794 (match_operand 3 "const_int_operand" ""))
17795 (const_int 0)]))]
17659 "! TARGET_PARTIAL_REG_STALL
17660 && ix86_match_ccmode (insn, CCNOmode)
17796 "! TARGET_PARTIAL_REG_STALL
17797 && ix86_match_ccmode (insn, CCNOmode)
17661 && true_regnum (operands[0]) != 0
17662 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17663 [(parallel [(set (reg:CCNO 17)
17664 (compare:CCNO
17665 (and:SI
17666 (zero_extract:SI
17667 (match_dup 0)
17668 (const_int 8)
17669 (const_int 8))
17670 (match_dup 1))
17671 (const_int 0)))
17672 (set (zero_extract:SI (match_dup 0)
17798 && true_regnum (operands[2]) != 0
17799 && peep2_reg_dead_p (1, operands[2])"
17800 [(parallel [(set (match_dup 0)
17801 (match_op_dup 1
17802 [(and:SI
17803 (zero_extract:SI
17804 (match_dup 2)
17805 (const_int 8)
17806 (const_int 8))
17807 (match_dup 3))
17808 (const_int 0)]))
17809 (set (zero_extract:SI (match_dup 2)
17673 (const_int 8)
17674 (const_int 8))
17675 (and:SI
17676 (zero_extract:SI
17810 (const_int 8)
17811 (const_int 8))
17812 (and:SI
17813 (zero_extract:SI
17677 (match_dup 0)
17814 (match_dup 2)
17678 (const_int 8)
17679 (const_int 8))
17815 (const_int 8)
17816 (const_int 8))
17680 (match_dup 1)))])]
17817 (match_dup 3)))])]
17681 "")
17682
17683;; Don't do logical operations with memory inputs.
17684(define_peephole2
17685 [(match_scratch:SI 2 "r")
17686 (parallel [(set (match_operand:SI 0 "register_operand" "")
17687 (match_operator:SI 3 "arith_or_logical_operator"
17688 [(match_dup 0)

--- 285 unchanged lines hidden (view full) ---

17974 "optimize_size"
17975 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17976 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17977 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17978 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17979 "")
17980
17981;; Convert compares with 1 to shorter inc/dec operations when CF is not
17818 "")
17819
17820;; Don't do logical operations with memory inputs.
17821(define_peephole2
17822 [(match_scratch:SI 2 "r")
17823 (parallel [(set (match_operand:SI 0 "register_operand" "")
17824 (match_operator:SI 3 "arith_or_logical_operator"
17825 [(match_dup 0)

--- 285 unchanged lines hidden (view full) ---

18111 "optimize_size"
18112 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18113 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
18114 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18115 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18116 "")
18117
18118;; Convert compares with 1 to shorter inc/dec operations when CF is not
17982;; required and register dies.
18119;; required and register dies. Similarly for 128 to plus -128.
17983(define_peephole2
18120(define_peephole2
17984 [(set (reg 17)
17985 (compare (match_operand:SI 0 "register_operand" "")
17986 (match_operand:SI 1 "incdec_operand" "")))]
17987 "ix86_match_ccmode (insn, CCGCmode)
17988 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17989 [(parallel [(set (reg:CCGC 17)
17990 (compare:CCGC (match_dup 0)
17991 (match_dup 1)))
17992 (clobber (match_dup 0))])]
18121 [(set (match_operand 0 "flags_reg_operand" "")
18122 (match_operator 1 "compare_operator"
18123 [(match_operand 2 "register_operand" "")
18124 (match_operand 3 "const_int_operand" "")]))]
18125 "(INTVAL (operands[3]) == -1
18126 || INTVAL (operands[3]) == 1
18127 || INTVAL (operands[3]) == 128)
18128 && ix86_match_ccmode (insn, CCGCmode)
18129 && peep2_reg_dead_p (1, operands[2])"
18130 [(parallel [(set (match_dup 0)
18131 (match_op_dup 1 [(match_dup 2) (match_dup 3)]))
18132 (clobber (match_dup 2))])]
17993 "")
18133 "")
17994
17995(define_peephole2
17996 [(set (reg 17)
17997 (compare (match_operand:HI 0 "register_operand" "")
17998 (match_operand:HI 1 "incdec_operand" "")))]
17999 "ix86_match_ccmode (insn, CCGCmode)
18000 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18001 [(parallel [(set (reg:CCGC 17)
18002 (compare:CCGC (match_dup 0)
18003 (match_dup 1)))
18004 (clobber (match_dup 0))])]
18005 "")
18006
18007(define_peephole2
18008 [(set (reg 17)
18009 (compare (match_operand:QI 0 "register_operand" "")
18010 (match_operand:QI 1 "incdec_operand" "")))]
18011 "ix86_match_ccmode (insn, CCGCmode)
18012 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18013 [(parallel [(set (reg:CCGC 17)
18014 (compare:CCGC (match_dup 0)
18015 (match_dup 1)))
18016 (clobber (match_dup 0))])]
18017 "")
18018
18019;; Convert compares with 128 to shorter add -128
18020(define_peephole2
18021 [(set (reg 17)
18022 (compare (match_operand:SI 0 "register_operand" "")
18023 (const_int 128)))]
18024 "ix86_match_ccmode (insn, CCGCmode)
18025 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18026 [(parallel [(set (reg:CCGC 17)
18027 (compare:CCGC (match_dup 0)
18028 (const_int 128)))
18029 (clobber (match_dup 0))])]
18030 "")
18031
18032(define_peephole2
18033 [(set (reg 17)
18034 (compare (match_operand:HI 0 "register_operand" "")
18035 (const_int 128)))]
18036 "ix86_match_ccmode (insn, CCGCmode)
18037 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18038 [(parallel [(set (reg:CCGC 17)
18039 (compare:CCGC (match_dup 0)
18040 (const_int 128)))
18041 (clobber (match_dup 0))])]
18042 "")
18043
18044(define_peephole2
18045 [(match_scratch:DI 0 "r")
18046 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
18047 (clobber (reg:CC 17))
18048 (clobber (mem:BLK (scratch)))])]
18049 "optimize_size || !TARGET_SUB_ESP_4"
18050 [(clobber (match_dup 0))

--- 270 unchanged lines hidden (view full) ---

18321(define_insn "*call_value_1"
18322 [(set (match_operand 0 "" "")
18323 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
18324 (match_operand:SI 2 "" "")))]
18325 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
18326{
18327 if (constant_call_address_operand (operands[1], QImode))
18328 return "call\t%P1";
18134
18135(define_peephole2
18136 [(match_scratch:DI 0 "r")
18137 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
18138 (clobber (reg:CC 17))
18139 (clobber (mem:BLK (scratch)))])]
18140 "optimize_size || !TARGET_SUB_ESP_4"
18141 [(clobber (match_dup 0))

--- 270 unchanged lines hidden (view full) ---

18412(define_insn "*call_value_1"
18413 [(set (match_operand 0 "" "")
18414 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
18415 (match_operand:SI 2 "" "")))]
18416 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
18417{
18418 if (constant_call_address_operand (operands[1], QImode))
18419 return "call\t%P1";
18329 return "call\t%*%1";
18420 return "call\t%A1";
18330}
18331 [(set_attr "type" "callv")])
18332
18333(define_insn "*sibcall_value_1"
18334 [(set (match_operand 0 "" "")
18335 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
18336 (match_operand:SI 2 "" "")))]
18337 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
18338{
18339 if (constant_call_address_operand (operands[1], QImode))
18340 return "jmp\t%P1";
18421}
18422 [(set_attr "type" "callv")])
18423
18424(define_insn "*sibcall_value_1"
18425 [(set (match_operand 0 "" "")
18426 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
18427 (match_operand:SI 2 "" "")))]
18428 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
18429{
18430 if (constant_call_address_operand (operands[1], QImode))
18431 return "jmp\t%P1";
18341 return "jmp\t%*%1";
18432 return "jmp\t%A1";
18342}
18343 [(set_attr "type" "callv")])
18344
18345(define_insn "*call_value_1_rex64"
18346 [(set (match_operand 0 "" "")
18347 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
18348 (match_operand:DI 2 "" "")))]
18349 "!SIBLING_CALL_P (insn) && TARGET_64BIT"

--- 67 unchanged lines hidden (view full) ---

18417 CODE_LABEL_NUMBER (operands[2]));
18418 RET;
18419})
18420
18421 ;; Pentium III SIMD instructions.
18422
18423;; Moves for SSE/MMX regs.
18424
18433}
18434 [(set_attr "type" "callv")])
18435
18436(define_insn "*call_value_1_rex64"
18437 [(set (match_operand 0 "" "")
18438 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
18439 (match_operand:DI 2 "" "")))]
18440 "!SIBLING_CALL_P (insn) && TARGET_64BIT"

--- 67 unchanged lines hidden (view full) ---

18508 CODE_LABEL_NUMBER (operands[2]));
18509 RET;
18510})
18511
18512 ;; Pentium III SIMD instructions.
18513
18514;; Moves for SSE/MMX regs.
18515
18425(define_insn "movv4sf_internal"
18516(define_insn "*movv4sf_internal"
18426 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
18427 (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))]
18517 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
18518 (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))]
18428 "TARGET_SSE"
18519 "TARGET_SSE
18520 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18429 "@
18430 xorps\t%0, %0
18431 movaps\t{%1, %0|%0, %1}
18432 movaps\t{%1, %0|%0, %1}"
18433 [(set_attr "type" "ssemov")
18434 (set_attr "mode" "V4SF")])
18435
18436(define_split
18437 [(set (match_operand:V4SF 0 "register_operand" "")
18438 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
18521 "@
18522 xorps\t%0, %0
18523 movaps\t{%1, %0|%0, %1}
18524 movaps\t{%1, %0|%0, %1}"
18525 [(set_attr "type" "ssemov")
18526 (set_attr "mode" "V4SF")])
18527
18528(define_split
18529 [(set (match_operand:V4SF 0 "register_operand" "")
18530 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
18439 "TARGET_SSE"
18531 "TARGET_SSE && reload_completed"
18440 [(set (match_dup 0)
18441 (vec_merge:V4SF
18442 (vec_duplicate:V4SF (match_dup 1))
18443 (match_dup 2)
18444 (const_int 1)))]
18445{
18446 operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
18447 operands[2] = CONST0_RTX (V4SFmode);
18448})
18449
18532 [(set (match_dup 0)
18533 (vec_merge:V4SF
18534 (vec_duplicate:V4SF (match_dup 1))
18535 (match_dup 2)
18536 (const_int 1)))]
18537{
18538 operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
18539 operands[2] = CONST0_RTX (V4SFmode);
18540})
18541
18450(define_insn "movv4si_internal"
18542(define_insn "*movv4si_internal"
18451 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,x,m")
18452 (match_operand:V4SI 1 "vector_move_operand" "C,xm,x"))]
18543 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,x,m")
18544 (match_operand:V4SI 1 "vector_move_operand" "C,xm,x"))]
18453 "TARGET_SSE"
18545 "TARGET_SSE
18546 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18454{
18455 switch (which_alternative)
18456 {
18457 case 0:
18458 if (get_attr_mode (insn) == MODE_V4SF)
18459 return "xorps\t%0, %0";
18460 else
18461 return "pxor\t%0, %0";

--- 20 unchanged lines hidden (view full) ---

18482 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18483 (const_int 0))
18484 (ne (symbol_ref "optimize_size")
18485 (const_int 0)))
18486 (const_string "V4SF")
18487 (const_string "TI"))]
18488 (const_string "TI")))])
18489
18547{
18548 switch (which_alternative)
18549 {
18550 case 0:
18551 if (get_attr_mode (insn) == MODE_V4SF)
18552 return "xorps\t%0, %0";
18553 else
18554 return "pxor\t%0, %0";

--- 20 unchanged lines hidden (view full) ---

18575 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18576 (const_int 0))
18577 (ne (symbol_ref "optimize_size")
18578 (const_int 0)))
18579 (const_string "V4SF")
18580 (const_string "TI"))]
18581 (const_string "TI")))])
18582
18490(define_insn "movv2di_internal"
18583(define_insn "*movv2di_internal"
18491 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,x,m")
18492 (match_operand:V2DI 1 "vector_move_operand" "C,xm,x"))]
18584 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,x,m")
18585 (match_operand:V2DI 1 "vector_move_operand" "C,xm,x"))]
18493 "TARGET_SSE"
18586 "TARGET_SSE
18587 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18494{
18495 switch (which_alternative)
18496 {
18497 case 0:
18498 if (get_attr_mode (insn) == MODE_V4SF)
18499 return "xorps\t%0, %0";
18500 else
18501 return "pxor\t%0, %0";

--- 23 unchanged lines hidden (view full) ---

18525 (const_int 0)))
18526 (const_string "V4SF")
18527 (const_string "TI"))]
18528 (const_string "TI")))])
18529
18530(define_split
18531 [(set (match_operand:V2DF 0 "register_operand" "")
18532 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
18588{
18589 switch (which_alternative)
18590 {
18591 case 0:
18592 if (get_attr_mode (insn) == MODE_V4SF)
18593 return "xorps\t%0, %0";
18594 else
18595 return "pxor\t%0, %0";

--- 23 unchanged lines hidden (view full) ---

18619 (const_int 0)))
18620 (const_string "V4SF")
18621 (const_string "TI"))]
18622 (const_string "TI")))])
18623
18624(define_split
18625 [(set (match_operand:V2DF 0 "register_operand" "")
18626 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
18533 "TARGET_SSE2"
18627 "TARGET_SSE2 && reload_completed"
18534 [(set (match_dup 0)
18535 (vec_merge:V2DF
18536 (vec_duplicate:V2DF (match_dup 1))
18537 (match_dup 2)
18538 (const_int 1)))]
18539{
18540 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
18541 operands[2] = CONST0_RTX (V2DFmode);
18542})
18543
18628 [(set (match_dup 0)
18629 (vec_merge:V2DF
18630 (vec_duplicate:V2DF (match_dup 1))
18631 (match_dup 2)
18632 (const_int 1)))]
18633{
18634 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
18635 operands[2] = CONST0_RTX (V2DFmode);
18636})
18637
18544(define_insn "movv8qi_internal"
18545 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m")
18546 (match_operand:V8QI 1 "vector_move_operand" "C,ym,y"))]
18638(define_insn "*movv2si_internal"
18639 [(set (match_operand:V2SI 0 "nonimmediate_operand"
18640 "=y,y ,m,!y,!*Y,*x,?*x,?m")
18641 (match_operand:V2SI 1 "vector_move_operand"
18642 "C ,ym,y,*Y,y ,C ,*xm,*x"))]
18547 "TARGET_MMX
18548 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18549 "@
18550 pxor\t%0, %0
18551 movq\t{%1, %0|%0, %1}
18643 "TARGET_MMX
18644 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18645 "@
18646 pxor\t%0, %0
18647 movq\t{%1, %0|%0, %1}
18648 movq\t{%1, %0|%0, %1}
18649 movdq2q\t{%1, %0|%0, %1}
18650 movq2dq\t{%1, %0|%0, %1}
18651 pxor\t%0, %0
18652 movq\t{%1, %0|%0, %1}
18552 movq\t{%1, %0|%0, %1}"
18653 movq\t{%1, %0|%0, %1}"
18553 [(set_attr "type" "mmxmov")
18654 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov")
18554 (set_attr "mode" "DI")])
18555
18655 (set_attr "mode" "DI")])
18656
18556(define_insn "movv4hi_internal"
18557 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m")
18558 (match_operand:V4HI 1 "vector_move_operand" "C,ym,y"))]
18657(define_insn "*movv4hi_internal"
18658 [(set (match_operand:V4HI 0 "nonimmediate_operand"
18659 "=y,y ,m,!y,!*Y,*x,?*x,?m")
18660 (match_operand:V4HI 1 "vector_move_operand"
18661 "C ,ym,y,*Y,y ,C ,*xm,*x"))]
18559 "TARGET_MMX
18560 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18561 "@
18562 pxor\t%0, %0
18563 movq\t{%1, %0|%0, %1}
18662 "TARGET_MMX
18663 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18664 "@
18665 pxor\t%0, %0
18666 movq\t{%1, %0|%0, %1}
18667 movq\t{%1, %0|%0, %1}
18668 movdq2q\t{%1, %0|%0, %1}
18669 movq2dq\t{%1, %0|%0, %1}
18670 pxor\t%0, %0
18671 movq\t{%1, %0|%0, %1}
18564 movq\t{%1, %0|%0, %1}"
18672 movq\t{%1, %0|%0, %1}"
18565 [(set_attr "type" "mmxmov")
18673 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov")
18566 (set_attr "mode" "DI")])
18567
18674 (set_attr "mode" "DI")])
18675
18568(define_insn "movv2si_internal"
18569 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m")
18570 (match_operand:V2SI 1 "vector_move_operand" "C,ym,y"))]
18676(define_insn "*movv8qi_internal"
18677 [(set (match_operand:V8QI 0 "nonimmediate_operand"
18678 "=y,y ,m,!y,!*Y,*x,?*x,?m")
18679 (match_operand:V8QI 1 "vector_move_operand"
18680 "C ,ym,y,*Y,y ,C ,*xm,*x"))]
18571 "TARGET_MMX
18572 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18573 "@
18574 pxor\t%0, %0
18575 movq\t{%1, %0|%0, %1}
18681 "TARGET_MMX
18682 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18683 "@
18684 pxor\t%0, %0
18685 movq\t{%1, %0|%0, %1}
18686 movq\t{%1, %0|%0, %1}
18687 movdq2q\t{%1, %0|%0, %1}
18688 movq2dq\t{%1, %0|%0, %1}
18689 pxor\t%0, %0
18690 movq\t{%1, %0|%0, %1}
18576 movq\t{%1, %0|%0, %1}"
18691 movq\t{%1, %0|%0, %1}"
18577 [(set_attr "type" "mmxcvt")
18692 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov")
18578 (set_attr "mode" "DI")])
18579
18693 (set_attr "mode" "DI")])
18694
18580(define_insn "movv2sf_internal"
18581 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m")
18582 (match_operand:V2SF 1 "vector_move_operand" "C,ym,y"))]
18583 "TARGET_3DNOW
18695(define_insn "*movv2sf_internal"
18696 [(set (match_operand:V2SF 0 "nonimmediate_operand"
18697 "=y,y ,m,!y,!*Y,*x,?*x,?m")
18698 (match_operand:V2SF 1 "vector_move_operand"
18699 "C ,ym,y,*Y,y ,C ,*xm,*x"))]
18700 "TARGET_MMX
18584 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18585 "@
18586 pxor\t%0, %0
18587 movq\t{%1, %0|%0, %1}
18701 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18702 "@
18703 pxor\t%0, %0
18704 movq\t{%1, %0|%0, %1}
18705 movq\t{%1, %0|%0, %1}
18706 movdq2q\t{%1, %0|%0, %1}
18707 movq2dq\t{%1, %0|%0, %1}
18708 xorps\t%0, %0
18709 movq\t{%1, %0|%0, %1}
18588 movq\t{%1, %0|%0, %1}"
18710 movq\t{%1, %0|%0, %1}"
18589 [(set_attr "type" "mmxcvt")
18711 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov")
18590 (set_attr "mode" "DI")])
18591
18592(define_expand "movti"
18593 [(set (match_operand:TI 0 "nonimmediate_operand" "")
18594 (match_operand:TI 1 "nonimmediate_operand" ""))]
18595 "TARGET_SSE || TARGET_64BIT"
18596{
18597 if (TARGET_64BIT)
18598 ix86_expand_move (TImode, operands);
18599 else
18600 ix86_expand_vector_move (TImode, operands);
18601 DONE;
18602})
18603
18604(define_expand "movtf"
18605 [(set (match_operand:TF 0 "nonimmediate_operand" "")
18606 (match_operand:TF 1 "nonimmediate_operand" ""))]
18607 "TARGET_64BIT"
18608{
18712 (set_attr "mode" "DI")])
18713
18714(define_expand "movti"
18715 [(set (match_operand:TI 0 "nonimmediate_operand" "")
18716 (match_operand:TI 1 "nonimmediate_operand" ""))]
18717 "TARGET_SSE || TARGET_64BIT"
18718{
18719 if (TARGET_64BIT)
18720 ix86_expand_move (TImode, operands);
18721 else
18722 ix86_expand_vector_move (TImode, operands);
18723 DONE;
18724})
18725
18726(define_expand "movtf"
18727 [(set (match_operand:TF 0 "nonimmediate_operand" "")
18728 (match_operand:TF 1 "nonimmediate_operand" ""))]
18729 "TARGET_64BIT"
18730{
18609 if (TARGET_64BIT)
18610 ix86_expand_move (TFmode, operands);
18611 else
18612 ix86_expand_vector_move (TFmode, operands);
18731 ix86_expand_move (TFmode, operands);
18613 DONE;
18614})
18615
18732 DONE;
18733})
18734
18616(define_insn "movv2df_internal"
18735(define_insn "*movv2df_internal"
18617 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
18618 (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
18736 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
18737 (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
18619 "TARGET_SSE2
18738 "TARGET_SSE
18620 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18621{
18622 switch (which_alternative)
18623 {
18624 case 0:
18625 if (get_attr_mode (insn) == MODE_V4SF)
18626 return "xorps\t%0, %0";
18627 else

--- 5 unchanged lines hidden (view full) ---

18633 else
18634 return "movapd\t{%1, %0|%0, %1}";
18635 default:
18636 abort ();
18637 }
18638}
18639 [(set_attr "type" "ssemov")
18640 (set (attr "mode")
18739 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18740{
18741 switch (which_alternative)
18742 {
18743 case 0:
18744 if (get_attr_mode (insn) == MODE_V4SF)
18745 return "xorps\t%0, %0";
18746 else

--- 5 unchanged lines hidden (view full) ---

18752 else
18753 return "movapd\t{%1, %0|%0, %1}";
18754 default:
18755 abort ();
18756 }
18757}
18758 [(set_attr "type" "ssemov")
18759 (set (attr "mode")
18641 (cond [(eq_attr "alternative" "0,1")
18760 (cond [(eq (symbol_ref "TARGET_SSE2") (const_int 0))
18761 (const_string "V4SF")
18762 (eq_attr "alternative" "0,1")
18642 (if_then_else
18643 (ne (symbol_ref "optimize_size")
18644 (const_int 0))
18645 (const_string "V4SF")
18646 (const_string "V2DF"))
18647 (eq_attr "alternative" "2")
18648 (if_then_else
18649 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18650 (const_int 0))
18651 (ne (symbol_ref "optimize_size")
18652 (const_int 0)))
18653 (const_string "V4SF")
18654 (const_string "V2DF"))]
18655 (const_string "V2DF")))])
18656
18763 (if_then_else
18764 (ne (symbol_ref "optimize_size")
18765 (const_int 0))
18766 (const_string "V4SF")
18767 (const_string "V2DF"))
18768 (eq_attr "alternative" "2")
18769 (if_then_else
18770 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18771 (const_int 0))
18772 (ne (symbol_ref "optimize_size")
18773 (const_int 0)))
18774 (const_string "V4SF")
18775 (const_string "V2DF"))]
18776 (const_string "V2DF")))])
18777
18657(define_insn "movv8hi_internal"
18778(define_insn "*movv8hi_internal"
18658 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,x,m")
18659 (match_operand:V8HI 1 "vector_move_operand" "C,xm,x"))]
18779 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,x,m")
18780 (match_operand:V8HI 1 "vector_move_operand" "C,xm,x"))]
18660 "TARGET_SSE2
18781 "TARGET_SSE
18661 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18662{
18663 switch (which_alternative)
18664 {
18665 case 0:
18666 if (get_attr_mode (insn) == MODE_V4SF)
18667 return "xorps\t%0, %0";
18668 else

--- 21 unchanged lines hidden (view full) ---

18690 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18691 (const_int 0))
18692 (ne (symbol_ref "optimize_size")
18693 (const_int 0)))
18694 (const_string "V4SF")
18695 (const_string "TI"))]
18696 (const_string "TI")))])
18697
18782 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18783{
18784 switch (which_alternative)
18785 {
18786 case 0:
18787 if (get_attr_mode (insn) == MODE_V4SF)
18788 return "xorps\t%0, %0";
18789 else

--- 21 unchanged lines hidden (view full) ---

18811 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18812 (const_int 0))
18813 (ne (symbol_ref "optimize_size")
18814 (const_int 0)))
18815 (const_string "V4SF")
18816 (const_string "TI"))]
18817 (const_string "TI")))])
18818
18698(define_insn "movv16qi_internal"
18819(define_insn "*movv16qi_internal"
18699 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m")
18820 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m")
18700 (match_operand:V16QI 1 "nonimmediate_operand" "C,xm,x"))]
18701 "TARGET_SSE2
18821 (match_operand:V16QI 1 "vector_move_operand" "C,xm,x"))]
18822 "TARGET_SSE
18702 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18703{
18704 switch (which_alternative)
18705 {
18706 case 0:
18707 if (get_attr_mode (insn) == MODE_V4SF)
18708 return "xorps\t%0, %0";
18709 else

--- 24 unchanged lines hidden (view full) ---

18734 (const_int 0)))
18735 (const_string "V4SF")
18736 (const_string "TI"))]
18737 (const_string "TI")))])
18738
18739(define_expand "movv2df"
18740 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
18741 (match_operand:V2DF 1 "nonimmediate_operand" ""))]
18823 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18824{
18825 switch (which_alternative)
18826 {
18827 case 0:
18828 if (get_attr_mode (insn) == MODE_V4SF)
18829 return "xorps\t%0, %0";
18830 else

--- 24 unchanged lines hidden (view full) ---

18855 (const_int 0)))
18856 (const_string "V4SF")
18857 (const_string "TI"))]
18858 (const_string "TI")))])
18859
18860(define_expand "movv2df"
18861 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
18862 (match_operand:V2DF 1 "nonimmediate_operand" ""))]
18742 "TARGET_SSE2"
18863 "TARGET_SSE"
18743{
18744 ix86_expand_vector_move (V2DFmode, operands);
18745 DONE;
18746})
18747
18748(define_expand "movv8hi"
18749 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
18750 (match_operand:V8HI 1 "nonimmediate_operand" ""))]
18864{
18865 ix86_expand_vector_move (V2DFmode, operands);
18866 DONE;
18867})
18868
18869(define_expand "movv8hi"
18870 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
18871 (match_operand:V8HI 1 "nonimmediate_operand" ""))]
18751 "TARGET_SSE2"
18872 "TARGET_SSE"
18752{
18753 ix86_expand_vector_move (V8HImode, operands);
18754 DONE;
18755})
18756
18757(define_expand "movv16qi"
18758 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
18759 (match_operand:V16QI 1 "nonimmediate_operand" ""))]
18873{
18874 ix86_expand_vector_move (V8HImode, operands);
18875 DONE;
18876})
18877
18878(define_expand "movv16qi"
18879 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
18880 (match_operand:V16QI 1 "nonimmediate_operand" ""))]
18760 "TARGET_SSE2"
18881 "TARGET_SSE"
18761{
18762 ix86_expand_vector_move (V16QImode, operands);
18763 DONE;
18764})
18765
18766(define_expand "movv4sf"
18767 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
18768 (match_operand:V4SF 1 "nonimmediate_operand" ""))]

--- 46 unchanged lines hidden (view full) ---

18815{
18816 ix86_expand_vector_move (V8QImode, operands);
18817 DONE;
18818})
18819
18820(define_expand "movv2sf"
18821 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
18822 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
18882{
18883 ix86_expand_vector_move (V16QImode, operands);
18884 DONE;
18885})
18886
18887(define_expand "movv4sf"
18888 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
18889 (match_operand:V4SF 1 "nonimmediate_operand" ""))]

--- 46 unchanged lines hidden (view full) ---

18936{
18937 ix86_expand_vector_move (V8QImode, operands);
18938 DONE;
18939})
18940
18941(define_expand "movv2sf"
18942 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
18943 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
18823 "TARGET_3DNOW"
18944 "TARGET_MMX"
18824{
18825 ix86_expand_vector_move (V2SFmode, operands);
18826 DONE;
18827})
18828
18829(define_insn "*pushti"
18830 [(set (match_operand:TI 0 "push_operand" "=<")
18831 (match_operand:TI 1 "register_operand" "x"))]

--- 4 unchanged lines hidden (view full) ---

18836 [(set (match_operand:V2DF 0 "push_operand" "=<")
18837 (match_operand:V2DF 1 "register_operand" "x"))]
18838 "TARGET_SSE"
18839 "#")
18840
18841(define_insn "*pushv2di"
18842 [(set (match_operand:V2DI 0 "push_operand" "=<")
18843 (match_operand:V2DI 1 "register_operand" "x"))]
18945{
18946 ix86_expand_vector_move (V2SFmode, operands);
18947 DONE;
18948})
18949
18950(define_insn "*pushti"
18951 [(set (match_operand:TI 0 "push_operand" "=<")
18952 (match_operand:TI 1 "register_operand" "x"))]

--- 4 unchanged lines hidden (view full) ---

18957 [(set (match_operand:V2DF 0 "push_operand" "=<")
18958 (match_operand:V2DF 1 "register_operand" "x"))]
18959 "TARGET_SSE"
18960 "#")
18961
18962(define_insn "*pushv2di"
18963 [(set (match_operand:V2DI 0 "push_operand" "=<")
18964 (match_operand:V2DI 1 "register_operand" "x"))]
18844 "TARGET_SSE2"
18965 "TARGET_SSE"
18845 "#")
18846
18847(define_insn "*pushv8hi"
18848 [(set (match_operand:V8HI 0 "push_operand" "=<")
18849 (match_operand:V8HI 1 "register_operand" "x"))]
18966 "#")
18967
18968(define_insn "*pushv8hi"
18969 [(set (match_operand:V8HI 0 "push_operand" "=<")
18970 (match_operand:V8HI 1 "register_operand" "x"))]
18850 "TARGET_SSE2"
18971 "TARGET_SSE"
18851 "#")
18852
18853(define_insn "*pushv16qi"
18854 [(set (match_operand:V16QI 0 "push_operand" "=<")
18855 (match_operand:V16QI 1 "register_operand" "x"))]
18972 "#")
18973
18974(define_insn "*pushv16qi"
18975 [(set (match_operand:V16QI 0 "push_operand" "=<")
18976 (match_operand:V16QI 1 "register_operand" "x"))]
18856 "TARGET_SSE2"
18977 "TARGET_SSE"
18857 "#")
18858
18859(define_insn "*pushv4sf"
18860 [(set (match_operand:V4SF 0 "push_operand" "=<")
18861 (match_operand:V4SF 1 "register_operand" "x"))]
18862 "TARGET_SSE"
18863 "#")
18864
18865(define_insn "*pushv4si"
18866 [(set (match_operand:V4SI 0 "push_operand" "=<")
18867 (match_operand:V4SI 1 "register_operand" "x"))]
18978 "#")
18979
18980(define_insn "*pushv4sf"
18981 [(set (match_operand:V4SF 0 "push_operand" "=<")
18982 (match_operand:V4SF 1 "register_operand" "x"))]
18983 "TARGET_SSE"
18984 "#")
18985
18986(define_insn "*pushv4si"
18987 [(set (match_operand:V4SI 0 "push_operand" "=<")
18988 (match_operand:V4SI 1 "register_operand" "x"))]
18868 "TARGET_SSE2"
18989 "TARGET_SSE"
18869 "#")
18870
18871(define_insn "*pushv2si"
18872 [(set (match_operand:V2SI 0 "push_operand" "=<")
18873 (match_operand:V2SI 1 "register_operand" "y"))]
18874 "TARGET_MMX"
18875 "#")
18876

--- 7 unchanged lines hidden (view full) ---

18884 [(set (match_operand:V8QI 0 "push_operand" "=<")
18885 (match_operand:V8QI 1 "register_operand" "y"))]
18886 "TARGET_MMX"
18887 "#")
18888
18889(define_insn "*pushv2sf"
18890 [(set (match_operand:V2SF 0 "push_operand" "=<")
18891 (match_operand:V2SF 1 "register_operand" "y"))]
18990 "#")
18991
18992(define_insn "*pushv2si"
18993 [(set (match_operand:V2SI 0 "push_operand" "=<")
18994 (match_operand:V2SI 1 "register_operand" "y"))]
18995 "TARGET_MMX"
18996 "#")
18997

--- 7 unchanged lines hidden (view full) ---

19005 [(set (match_operand:V8QI 0 "push_operand" "=<")
19006 (match_operand:V8QI 1 "register_operand" "y"))]
19007 "TARGET_MMX"
19008 "#")
19009
19010(define_insn "*pushv2sf"
19011 [(set (match_operand:V2SF 0 "push_operand" "=<")
19012 (match_operand:V2SF 1 "register_operand" "y"))]
18892 "TARGET_3DNOW"
19013 "TARGET_MMX"
18893 "#")
18894
18895(define_split
18896 [(set (match_operand 0 "push_operand" "")
18897 (match_operand 1 "register_operand" ""))]
18898 "!TARGET_64BIT && reload_completed
18899 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
18900 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 3)))

--- 9 unchanged lines hidden (view full) ---

18910 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
18911 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 3)))
18912 (set (match_dup 2) (match_dup 1))]
18913 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
18914 stack_pointer_rtx);
18915 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
18916
18917
19014 "#")
19015
19016(define_split
19017 [(set (match_operand 0 "push_operand" "")
19018 (match_operand 1 "register_operand" ""))]
19019 "!TARGET_64BIT && reload_completed
19020 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
19021 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 3)))

--- 9 unchanged lines hidden (view full) ---

19031 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
19032 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 3)))
19033 (set (match_dup 2) (match_dup 1))]
19034 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
19035 stack_pointer_rtx);
19036 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
19037
19038
18918(define_insn "movti_internal"
19039(define_insn "*movti_internal"
18919 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
18920 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
18921 "TARGET_SSE && !TARGET_64BIT
18922 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18923{
18924 switch (which_alternative)
18925 {
18926 case 0:

--- 530 unchanged lines hidden (view full) ---

19457;;
19458;;
19459;; These are not called andti3 etc. because we really really don't want
19460;; the compiler to widen DImode ands to TImode ands and then try to move
19461;; into DImode subregs of SSE registers, and them together, and move out
19462;; of DImode subregs again!
19463;; SSE1 single precision floating point logical operation
19464(define_expand "sse_andv4sf3"
19040 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
19041 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
19042 "TARGET_SSE && !TARGET_64BIT
19043 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19044{
19045 switch (which_alternative)
19046 {
19047 case 0:

--- 530 unchanged lines hidden (view full) ---

19578;;
19579;;
19580;; These are not called andti3 etc. because we really really don't want
19581;; the compiler to widen DImode ands to TImode ands and then try to move
19582;; into DImode subregs of SSE registers, and them together, and move out
19583;; of DImode subregs again!
19584;; SSE1 single precision floating point logical operation
19585(define_expand "sse_andv4sf3"
19465 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19466 (and:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19467 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19586 [(set (match_operand:V4SF 0 "register_operand" "")
19587 (and:V4SF (match_operand:V4SF 1 "register_operand" "")
19588 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
19468 "TARGET_SSE"
19469 "")
19470
19471(define_insn "*sse_andv4sf3"
19589 "TARGET_SSE"
19590 "")
19591
19592(define_insn "*sse_andv4sf3"
19472 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19473 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19474 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19593 [(set (match_operand:V4SF 0 "register_operand" "=x")
19594 (and:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
19595 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19475 "TARGET_SSE
19476 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19477 "andps\t{%2, %0|%0, %2}"
19478 [(set_attr "type" "sselog")
19479 (set_attr "mode" "V4SF")])
19480
19596 "TARGET_SSE
19597 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19598 "andps\t{%2, %0|%0, %2}"
19599 [(set_attr "type" "sselog")
19600 (set_attr "mode" "V4SF")])
19601
19481(define_insn "*sse_andsf3"
19482 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19483 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19484 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19485 "TARGET_SSE
19486 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19487 "andps\t{%2, %0|%0, %2}"
19488 [(set_attr "type" "sselog")
19489 (set_attr "mode" "V4SF")])
19490
19491(define_expand "sse_nandv4sf3"
19602(define_expand "sse_nandv4sf3"
19492 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19493 (and:TI (not:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0))
19494 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19603 [(set (match_operand:V4SF 0 "register_operand" "")
19604 (and:V4SF (not:V4SF (match_operand:V4SF 1 "register_operand" ""))
19605 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
19495 "TARGET_SSE"
19496 "")
19497
19498(define_insn "*sse_nandv4sf3"
19606 "TARGET_SSE"
19607 "")
19608
19609(define_insn "*sse_nandv4sf3"
19499 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19500 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19501 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19610 [(set (match_operand:V4SF 0 "register_operand" "=x")
19611 (and:V4SF (not:V4SF (match_operand:V4SF 1 "register_operand" "0"))
19612 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19502 "TARGET_SSE"
19503 "andnps\t{%2, %0|%0, %2}"
19504 [(set_attr "type" "sselog")
19505 (set_attr "mode" "V4SF")])
19506
19613 "TARGET_SSE"
19614 "andnps\t{%2, %0|%0, %2}"
19615 [(set_attr "type" "sselog")
19616 (set_attr "mode" "V4SF")])
19617
19507(define_insn "*sse_nandsf3"
19508 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19509 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19510 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19511 "TARGET_SSE"
19512 "andnps\t{%2, %0|%0, %2}"
19513 [(set_attr "type" "sselog")
19514 (set_attr "mode" "V4SF")])
19515
19516(define_expand "sse_iorv4sf3"
19618(define_expand "sse_iorv4sf3"
19517 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19518 (ior:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19519 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19619 [(set (match_operand:V4SF 0 "register_operand" "")
19620 (ior:V4SF (match_operand:V4SF 1 "register_operand" "")
19621 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
19520 "TARGET_SSE"
19521 "")
19522
19523(define_insn "*sse_iorv4sf3"
19622 "TARGET_SSE"
19623 "")
19624
19625(define_insn "*sse_iorv4sf3"
19524 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19525 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19526 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19626 [(set (match_operand:V4SF 0 "register_operand" "=x")
19627 (ior:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
19628 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19527 "TARGET_SSE
19528 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19529 "orps\t{%2, %0|%0, %2}"
19530 [(set_attr "type" "sselog")
19531 (set_attr "mode" "V4SF")])
19532
19629 "TARGET_SSE
19630 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19631 "orps\t{%2, %0|%0, %2}"
19632 [(set_attr "type" "sselog")
19633 (set_attr "mode" "V4SF")])
19634
19533(define_insn "*sse_iorsf3"
19534 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19535 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19536 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19537 "TARGET_SSE
19538 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19539 "orps\t{%2, %0|%0, %2}"
19540 [(set_attr "type" "sselog")
19541 (set_attr "mode" "V4SF")])
19542
19543(define_expand "sse_xorv4sf3"
19635(define_expand "sse_xorv4sf3"
19544 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19545 (xor:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19546 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19547 "TARGET_SSE
19548 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19636 [(set (match_operand:V4SF 0 "register_operand" "")
19637 (xor:V4SF (match_operand:V4SF 1 "register_operand" "")
19638 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
19639 "TARGET_SSE"
19549 "")
19550
19551(define_insn "*sse_xorv4sf3"
19640 "")
19641
19642(define_insn "*sse_xorv4sf3"
19552 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19553 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19554 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19643 [(set (match_operand:V4SF 0 "register_operand" "=x")
19644 (xor:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
19645 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19555 "TARGET_SSE
19556 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19557 "xorps\t{%2, %0|%0, %2}"
19558 [(set_attr "type" "sselog")
19559 (set_attr "mode" "V4SF")])
19560
19646 "TARGET_SSE
19647 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19648 "xorps\t{%2, %0|%0, %2}"
19649 [(set_attr "type" "sselog")
19650 (set_attr "mode" "V4SF")])
19651
19561(define_insn "*sse_xorsf3"
19562 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19563 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19564 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19565 "TARGET_SSE
19566 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19567 "xorps\t{%2, %0|%0, %2}"
19568 [(set_attr "type" "sselog")
19569 (set_attr "mode" "V4SF")])
19570
19571;; SSE2 double precision floating point logical operation
19572
19573(define_expand "sse2_andv2df3"
19652;; SSE2 double precision floating point logical operation
19653
19654(define_expand "sse2_andv2df3"
19574 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19575 (and:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
19576 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19655 [(set (match_operand:V2DF 0 "register_operand" "")
19656 (and:V2DF (match_operand:V2DF 1 "register_operand" "")
19657 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
19577 "TARGET_SSE2"
19578 "")
19579
19580(define_insn "*sse2_andv2df3"
19658 "TARGET_SSE2"
19659 "")
19660
19661(define_insn "*sse2_andv2df3"
19581 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19582 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19583 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19662 [(set (match_operand:V2DF 0 "register_operand" "=x")
19663 (and:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
19664 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
19584 "TARGET_SSE2
19585 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19586 "andpd\t{%2, %0|%0, %2}"
19587 [(set_attr "type" "sselog")
19588 (set_attr "mode" "V2DF")])
19589
19665 "TARGET_SSE2
19666 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19667 "andpd\t{%2, %0|%0, %2}"
19668 [(set_attr "type" "sselog")
19669 (set_attr "mode" "V2DF")])
19670
19590(define_insn "*sse2_andv2df3"
19591 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19592 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19593 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19594 "TARGET_SSE2
19595 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19596 "andpd\t{%2, %0|%0, %2}"
19597 [(set_attr "type" "sselog")
19598 (set_attr "mode" "V2DF")])
19599
19600(define_expand "sse2_nandv2df3"
19671(define_expand "sse2_nandv2df3"
19601 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19602 (and:TI (not:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0))
19603 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19672 [(set (match_operand:V2DF 0 "register_operand" "")
19673 (and:V2DF (not:V2DF (match_operand:V2DF 1 "register_operand" ""))
19674 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
19604 "TARGET_SSE2"
19605 "")
19606
19607(define_insn "*sse2_nandv2df3"
19675 "TARGET_SSE2"
19676 "")
19677
19678(define_insn "*sse2_nandv2df3"
19608 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19609 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19610 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19679 [(set (match_operand:V2DF 0 "register_operand" "=x")
19680 (and:V2DF (not:V2DF (match_operand:V2DF 1 "register_operand" "0"))
19681 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
19611 "TARGET_SSE2"
19612 "andnpd\t{%2, %0|%0, %2}"
19613 [(set_attr "type" "sselog")
19614 (set_attr "mode" "V2DF")])
19615
19682 "TARGET_SSE2"
19683 "andnpd\t{%2, %0|%0, %2}"
19684 [(set_attr "type" "sselog")
19685 (set_attr "mode" "V2DF")])
19686
19616(define_insn "*sse_nandti3_df"
19617 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
19618 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19619 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
19620 "TARGET_SSE2"
19621 "andnpd\t{%2, %0|%0, %2}"
19622 [(set_attr "type" "sselog")
19623 (set_attr "mode" "V2DF")])
19624
19625(define_expand "sse2_iorv2df3"
19687(define_expand "sse2_iorv2df3"
19626 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19627 (ior:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
19628 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19688 [(set (match_operand:V2DF 0 "register_operand" "")
19689 (ior:V2DF (match_operand:V2DF 1 "register_operand" "")
19690 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
19629 "TARGET_SSE2"
19630 "")
19631
19632(define_insn "*sse2_iorv2df3"
19691 "TARGET_SSE2"
19692 "")
19693
19694(define_insn "*sse2_iorv2df3"
19633 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19634 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19635 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19695 [(set (match_operand:V2DF 0 "register_operand" "=x")
19696 (ior:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
19697 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
19636 "TARGET_SSE2
19637 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19638 "orpd\t{%2, %0|%0, %2}"
19639 [(set_attr "type" "sselog")
19640 (set_attr "mode" "V2DF")])
19641
19698 "TARGET_SSE2
19699 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19700 "orpd\t{%2, %0|%0, %2}"
19701 [(set_attr "type" "sselog")
19702 (set_attr "mode" "V2DF")])
19703
19642(define_insn "*sse2_iordf3"
19643 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19644 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19645 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19646 "TARGET_SSE2
19647 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19648 "orpd\t{%2, %0|%0, %2}"
19649 [(set_attr "type" "sselog")
19650 (set_attr "mode" "V2DF")])
19651
19652(define_expand "sse2_xorv2df3"
19704(define_expand "sse2_xorv2df3"
19653 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19654 (xor:TI (subreg:TI (match_operand:V2DF 1 "nonimmediate_operand" "") 0)
19655 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19705 [(set (match_operand:V2DF 0 "register_operand" "")
19706 (xor:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")
19707 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
19656 "TARGET_SSE2"
19657 "")
19658
19659(define_insn "*sse2_xorv2df3"
19708 "TARGET_SSE2"
19709 "")
19710
19711(define_insn "*sse2_xorv2df3"
19660 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19661 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19662 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19712 [(set (match_operand:V2DF 0 "register_operand" "=x")
19713 (xor:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
19714 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
19663 "TARGET_SSE2
19664 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19665 "xorpd\t{%2, %0|%0, %2}"
19666 [(set_attr "type" "sselog")
19667 (set_attr "mode" "V2DF")])
19668
19715 "TARGET_SSE2
19716 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19717 "xorpd\t{%2, %0|%0, %2}"
19718 [(set_attr "type" "sselog")
19719 (set_attr "mode" "V2DF")])
19720
19669(define_insn "*sse2_xordf3"
19670 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19671 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19672 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19673 "TARGET_SSE2
19674 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19675 "xorpd\t{%2, %0|%0, %2}"
19676 [(set_attr "type" "sselog")
19677 (set_attr "mode" "V2DF")])
19678
19679;; SSE2 integral logicals. These patterns must always come after floating
19680;; point ones since we don't want compiler to use integer opcodes on floating
19681;; point SSE values to avoid matching of subregs in the match_operand.
19682(define_insn "*sse2_andti3"
19683 [(set (match_operand:TI 0 "register_operand" "=x")
19684 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19685 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19686 "TARGET_SSE2

--- 3293 unchanged lines hidden --- 		19721;; SSE2 integral logicals. These patterns must always come after floating
19722;; point ones since we don't want compiler to use integer opcodes on floating
19723;; point SSE values to avoid matching of subregs in the match_operand.
19724(define_insn "*sse2_andti3"
19725 [(set (match_operand:TI 0 "register_operand" "=x")
19726 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19727 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19728 "TARGET_SSE2

--- 3293 unchanged lines hidden ---