1;; GCC machine description for IA-32 and x86-64. 2;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 3;; Free Software Foundation, Inc. 4;; Mostly by William Schelter. 5;; x86_64 support added by Jan Hubicka 6;; 7;; This file is part of GNU CC. 8;; --- 99 unchanged lines hidden (view full) --- 108;; "reload_completed && TARGET_64BIT". 109 110 111;; Processor type. This attribute must exactly match the processor_type 112;; enumeration in i386.h. 113(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4" 114 (const (symbol_ref "ix86_cpu"))) 115 |
116;; $FreeBSD: head/contrib/gcc/config/i386/i386.md 96294 2002-05-09 22:44:32Z obrien $ |
117 118;; A basic instruction type. Refinements due to arguments to be 119;; provided in other attributes. 120(define_attr "type" 121 "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx,fistp" 122 (const_string "other")) 123 124;; Main data type used by the insn --- 1605 unchanged lines hidden (view full) --- 1730{ 1731 operands[1] = constm1_rtx; 1732 return "or{l}\t{%1, %0|%0, %1}"; 1733} 1734 [(set_attr "type" "alu1") 1735 (set_attr "mode" "SI") 1736 (set_attr "length_immediate" "1")]) 1737 |
1738; The first alternative is used only to compute proper length of instruction. 1739; Reload's algorithm does not take into account the cost of spill instructions 1740; needed to free register in given class, so avoid it from choosing the first 1741; alternative when eax is not available. 1742 |
1743(define_insn "*movsi_1" |
1744 [(set (match_operand:SI 0 "nonimmediate_operand" "=*?a,r,*?a,m,!*y,!rm,!*y,!*Y,!rm,!*Y") 1745 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,*y,rm,*Y,*Y"))] |
1746 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" 1747{ 1748 switch (get_attr_type (insn)) 1749 { 1750 case TYPE_SSE: 1751 if (get_attr_mode (insn) == TImode) 1752 return "movdqa\t{%1, %0|%0, %1}"; 1753 return "movd\t{%1, %0|%0, %1}"; 1754 1755 case TYPE_MMX: |
1756 if (get_attr_mode (insn) == DImode) 1757 return "movq\t{%1, %0|%0, %1}"; |
1758 return "movd\t{%1, %0|%0, %1}"; 1759 1760 case TYPE_LEA: 1761 return "lea{l}\t{%1, %0|%0, %1}"; 1762 1763 default: 1764 if (flag_pic && SYMBOLIC_CONST (operands[1])) 1765 abort(); 1766 return "mov{l}\t{%1, %0|%0, %1}"; 1767 } 1768} 1769 [(set (attr "type") |
1770 (cond [(eq_attr "alternative" "4,5,6") |
1771 (const_string "mmx") |
1772 (eq_attr "alternative" "7,8,9") |
1773 (const_string "sse") 1774 (and (ne (symbol_ref "flag_pic") (const_int 0)) 1775 (match_operand:SI 1 "symbolic_operand" "")) 1776 (const_string "lea") 1777 ] 1778 (const_string "imov"))) |
1779 (set_attr "modrm" "0,*,0,*,*,*,*,*,*,*") 1780 (set_attr "mode" "SI,SI,SI,SI,SI,SI,DI,TI,SI,SI")]) |
1781 1782;; Stores and loads of ax to arbitary constant address. 1783;; We fake an second form of instruction to force reload to load address 1784;; into register when rax is not available 1785(define_insn "*movabssi_1_rex64" 1786 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r")) 1787 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))] 1788 "TARGET_64BIT" --- 56 unchanged lines hidden (view full) --- 1845(define_insn "*pushhi2_rex64" 1846 [(set (match_operand:HI 0 "push_operand" "=X") 1847 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))] 1848 "TARGET_64BIT" 1849 "push{q}\t%q1" 1850 [(set_attr "type" "push") 1851 (set_attr "mode" "QI")]) 1852 |
1853; The first alternative is used only to compute proper length of instruction. 1854; Reload's algorithm does not take into account the cost of spill instructions 1855; needed to free register in given class, so avoid it from choosing the first 1856; alternative when eax is not available. 1857 |
1858(define_insn "*movhi_1" |
1859 [(set (match_operand:HI 0 "nonimmediate_operand" "=*?a,r,r,*?a,r,m") |
1860 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))] 1861 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" 1862{ 1863 switch (get_attr_type (insn)) 1864 { 1865 case TYPE_IMOVX: 1866 /* movzwl is faster than movw on p2 due to partial word stalls, 1867 though not as fast as an aligned movl. */ --- 601 unchanged lines hidden (view full) --- 2469 operands[1] = constm1_rtx; 2470 return "or{q}\t{%1, %0|%0, %1}"; 2471} 2472 [(set_attr "type" "alu1") 2473 (set_attr "mode" "DI") 2474 (set_attr "length_immediate" "1")]) 2475 2476(define_insn "*movdi_2" |
2477 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y") |
2478 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))] 2479 "!TARGET_64BIT 2480 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 2481 "@ 2482 # 2483 # 2484 movq\t{%1, %0|%0, %1} 2485 movq\t{%1, %0|%0, %1} --- 236 unchanged lines hidden (view full) --- 2722(define_split 2723 [(set (match_operand:SF 0 "push_operand" "") 2724 (match_operand:SF 1 "register_operand" ""))] 2725 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))" 2726 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) 2727 (set (mem:SF (reg:DI 7)) (match_dup 1))]) 2728 2729(define_insn "*movsf_1" |
2730 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y") 2731 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf,rm,*y,*y"))] |
2732 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 2733 && (reload_in_progress || reload_completed 2734 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) 2735 || GET_CODE (operands[1]) != CONST_DOUBLE 2736 || memory_operand (operands[0], SFmode))" 2737{ 2738 switch (which_alternative) 2739 { --- 21 unchanged lines hidden (view full) --- 2761 return "fld1"; 2762 } 2763 abort(); 2764 2765 case 3: 2766 case 4: 2767 return "mov{l}\t{%1, %0|%0, %1}"; 2768 case 5: |
2769 if (TARGET_SSE2) 2770 return "pxor\t%0, %0"; 2771 else 2772 return "xorps\t%0, %0"; |
2773 case 6: 2774 if (TARGET_PARTIAL_REG_DEPENDENCY) 2775 return "movaps\t{%1, %0|%0, %1}"; 2776 else 2777 return "movss\t{%1, %0|%0, %1}"; 2778 case 7: 2779 case 8: 2780 return "movss\t{%1, %0|%0, %1}"; 2781 |
2782 case 9: 2783 case 10: 2784 return "movd\t{%1, %0|%0, %1}"; 2785 2786 case 11: 2787 return "movq\t{%1, %0|%0, %1}"; 2788 |
2789 default: 2790 abort(); 2791 } 2792} |
2793 [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse,mmx,mmx,mmx") 2794 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF,SI,SI,DI")]) |
2795 2796(define_insn "*swapsf" 2797 [(set (match_operand:SF 0 "register_operand" "+f") 2798 (match_operand:SF 1 "register_operand" "+f")) 2799 (set (match_dup 1) 2800 (match_dup 0))] 2801 "reload_completed || !TARGET_SSE" 2802{ --- 2343 unchanged lines hidden (view full) --- 5146 #" 5147 [(set_attr "type" "fmov,multi") 5148 (set_attr "mode" "DF") 5149 (set_attr "fp_int_src" "true")]) 5150 5151(define_expand "floatsidf2" 5152 [(set (match_operand:DF 0 "register_operand" "") 5153 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))] |
5154 "TARGET_80387 || TARGET_SSE2" |
5155 "") 5156 5157(define_insn "*floatsidf2_i387" 5158 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y") 5159 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))] 5160 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)" 5161 "@ 5162 fild%z1\t%1 --- 2186 unchanged lines hidden (view full) --- 7349 "@ 7350 imul{w}\t{%2, %1, %0|%0, %1, %2} 7351 imul{w}\t{%2, %1, %0|%0, %1, %2} 7352 imul{w}\t{%2, %0|%0, %2}" 7353 [(set_attr "type" "imul") 7354 (set_attr "prefix_0f" "0,0,1") 7355 (set_attr "mode" "HI")]) 7356 |
7357(define_expand "mulqi3" 7358 [(parallel [(set (match_operand:QI 0 "register_operand" "") 7359 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "") 7360 (match_operand:QI 2 "register_operand" ""))) 7361 (clobber (reg:CC 17))])] 7362 "TARGET_QIMODE_MATH" 7363 "") 7364 7365(define_insn "*mulqi3_1" |
7366 [(set (match_operand:QI 0 "register_operand" "=a") |
7367 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0") |
7368 (match_operand:QI 2 "nonimmediate_operand" "qm"))) 7369 (clobber (reg:CC 17))] |
7370 "TARGET_QIMODE_MATH 7371 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
7372 "mul{b}\t%2" 7373 [(set_attr "type" "imul") 7374 (set_attr "length_immediate" "0") 7375 (set_attr "mode" "QI")]) 7376 |
7377(define_expand "umulqihi3" 7378 [(parallel [(set (match_operand:HI 0 "register_operand" "") 7379 (mult:HI (zero_extend:HI 7380 (match_operand:QI 1 "nonimmediate_operand" "")) 7381 (zero_extend:HI 7382 (match_operand:QI 2 "register_operand" "")))) 7383 (clobber (reg:CC 17))])] 7384 "TARGET_QIMODE_MATH" 7385 "") 7386 7387(define_insn "*umulqihi3_1" |
7388 [(set (match_operand:HI 0 "register_operand" "=a") |
7389 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) |
7390 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm")))) 7391 (clobber (reg:CC 17))] |
7392 "TARGET_QIMODE_MATH 7393 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
7394 "mul{b}\t%2" 7395 [(set_attr "type" "imul") 7396 (set_attr "length_immediate" "0") 7397 (set_attr "mode" "QI")]) 7398 |
7399(define_expand "mulqihi3" 7400 [(parallel [(set (match_operand:HI 0 "register_operand" "") 7401 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")) 7402 (sign_extend:HI (match_operand:QI 2 "register_operand" "")))) 7403 (clobber (reg:CC 17))])] 7404 "TARGET_QIMODE_MATH" 7405 "") 7406 7407(define_insn "*mulqihi3_insn" |
7408 [(set (match_operand:HI 0 "register_operand" "=a") |
7409 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) |
7410 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm")))) 7411 (clobber (reg:CC 17))] |
7412 "TARGET_QIMODE_MATH 7413 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
7414 "imul{b}\t%2" 7415 [(set_attr "type" "imul") 7416 (set_attr "length_immediate" "0") 7417 (set_attr "mode" "QI")]) 7418 |
7419(define_expand "umulditi3" 7420 [(parallel [(set (match_operand:TI 0 "register_operand" "") 7421 (mult:TI (zero_extend:TI 7422 (match_operand:DI 1 "nonimmediate_operand" "")) 7423 (zero_extend:TI 7424 (match_operand:DI 2 "register_operand" "")))) 7425 (clobber (reg:CC 17))])] 7426 "TARGET_64BIT" 7427 "") 7428 7429(define_insn "*umulditi3_insn" |
7430 [(set (match_operand:TI 0 "register_operand" "=A") |
7431 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0")) |
7432 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm")))) 7433 (clobber (reg:CC 17))] |
7434 "TARGET_64BIT 7435 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
7436 "mul{q}\t%2" 7437 [(set_attr "type" "imul") 7438 (set_attr "ppro_uops" "few") 7439 (set_attr "length_immediate" "0") 7440 (set_attr "mode" "DI")]) 7441 7442;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers |
7443(define_expand "umulsidi3" 7444 [(parallel [(set (match_operand:DI 0 "register_operand" "") 7445 (mult:DI (zero_extend:DI 7446 (match_operand:SI 1 "nonimmediate_operand" "")) 7447 (zero_extend:DI 7448 (match_operand:SI 2 "register_operand" "")))) 7449 (clobber (reg:CC 17))])] 7450 "!TARGET_64BIT" 7451 "") 7452 7453(define_insn "*umulsidi3_insn" |
7454 [(set (match_operand:DI 0 "register_operand" "=A") |
7455 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0")) |
7456 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))) 7457 (clobber (reg:CC 17))] |
7458 "!TARGET_64BIT 7459 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
7460 "mul{l}\t%2" 7461 [(set_attr "type" "imul") 7462 (set_attr "ppro_uops" "few") 7463 (set_attr "length_immediate" "0") 7464 (set_attr "mode" "SI")]) 7465 |
7466(define_expand "mulditi3" 7467 [(parallel [(set (match_operand:TI 0 "register_operand" "") 7468 (mult:TI (sign_extend:TI 7469 (match_operand:DI 1 "nonimmediate_operand" "")) 7470 (sign_extend:TI 7471 (match_operand:DI 2 "register_operand" "")))) 7472 (clobber (reg:CC 17))])] 7473 "TARGET_64BIT" 7474 "") 7475 7476(define_insn "*mulditi3_insn" |
7477 [(set (match_operand:TI 0 "register_operand" "=A") |
7478 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0")) |
7479 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm")))) 7480 (clobber (reg:CC 17))] |
7481 "TARGET_64BIT 7482 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
7483 "imul{q}\t%2" 7484 [(set_attr "type" "imul") 7485 (set_attr "length_immediate" "0") 7486 (set_attr "mode" "DI")]) 7487 |
7488(define_expand "mulsidi3" 7489 [(parallel [(set (match_operand:DI 0 "register_operand" "") 7490 (mult:DI (sign_extend:DI 7491 (match_operand:SI 1 "nonimmediate_operand" "")) 7492 (sign_extend:DI 7493 (match_operand:SI 2 "register_operand" "")))) 7494 (clobber (reg:CC 17))])] 7495 "!TARGET_64BIT" 7496 "") 7497 7498(define_insn "*mulsidi3_insn" |
7499 [(set (match_operand:DI 0 "register_operand" "=A") |
7500 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0")) |
7501 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))) 7502 (clobber (reg:CC 17))] |
7503 "!TARGET_64BIT 7504 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
7505 "imul{l}\t%2" 7506 [(set_attr "type" "imul") 7507 (set_attr "length_immediate" "0") 7508 (set_attr "mode" "SI")]) 7509 |
7510(define_expand "umuldi3_highpart" 7511 [(parallel [(set (match_operand:DI 0 "register_operand" "") 7512 (truncate:DI 7513 (lshiftrt:TI 7514 (mult:TI (zero_extend:TI 7515 (match_operand:DI 1 "nonimmediate_operand" "")) 7516 (zero_extend:TI 7517 (match_operand:DI 2 "register_operand" ""))) 7518 (const_int 64)))) 7519 (clobber (match_scratch:DI 3 "")) 7520 (clobber (reg:CC 17))])] 7521 "TARGET_64BIT" 7522 "") 7523 |
7524(define_insn "*umuldi3_highpart_rex64" 7525 [(set (match_operand:DI 0 "register_operand" "=d") 7526 (truncate:DI 7527 (lshiftrt:TI 7528 (mult:TI (zero_extend:TI |
7529 (match_operand:DI 1 "nonimmediate_operand" "%a")) |
7530 (zero_extend:TI 7531 (match_operand:DI 2 "nonimmediate_operand" "rm"))) 7532 (const_int 64)))) |
7533 (clobber (match_scratch:DI 3 "=1")) |
7534 (clobber (reg:CC 17))] |
7535 "TARGET_64BIT 7536 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
7537 "mul{q}\t%2" 7538 [(set_attr "type" "imul") 7539 (set_attr "ppro_uops" "few") 7540 (set_attr "length_immediate" "0") 7541 (set_attr "mode" "DI")]) 7542 |
7543(define_expand "umulsi3_highpart" 7544 [(parallel [(set (match_operand:SI 0 "register_operand" "") 7545 (truncate:SI 7546 (lshiftrt:DI 7547 (mult:DI (zero_extend:DI 7548 (match_operand:SI 1 "nonimmediate_operand" "")) 7549 (zero_extend:DI 7550 (match_operand:SI 2 "register_operand" ""))) 7551 (const_int 32)))) 7552 (clobber (match_scratch:SI 3 "")) 7553 (clobber (reg:CC 17))])] 7554 "" 7555 "") 7556 7557(define_insn "*umulsi3_highpart_insn" |
7558 [(set (match_operand:SI 0 "register_operand" "=d") 7559 (truncate:SI 7560 (lshiftrt:DI 7561 (mult:DI (zero_extend:DI |
7562 (match_operand:SI 1 "nonimmediate_operand" "%a")) |
7563 (zero_extend:DI 7564 (match_operand:SI 2 "nonimmediate_operand" "rm"))) 7565 (const_int 32)))) |
7566 (clobber (match_scratch:SI 3 "=1")) |
7567 (clobber (reg:CC 17))] |
7568 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" |
7569 "mul{l}\t%2" 7570 [(set_attr "type" "imul") 7571 (set_attr "ppro_uops" "few") 7572 (set_attr "length_immediate" "0") 7573 (set_attr "mode" "SI")]) 7574 7575(define_insn "*umulsi3_highpart_zext" 7576 [(set (match_operand:DI 0 "register_operand" "=d") 7577 (zero_extend:DI (truncate:SI 7578 (lshiftrt:DI 7579 (mult:DI (zero_extend:DI |
7580 (match_operand:SI 1 "nonimmediate_operand" "%a")) |
7581 (zero_extend:DI 7582 (match_operand:SI 2 "nonimmediate_operand" "rm"))) 7583 (const_int 32))))) |
7584 (clobber (match_scratch:SI 3 "=1")) |
7585 (clobber (reg:CC 17))] |
7586 "TARGET_64BIT 7587 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
7588 "mul{l}\t%2" 7589 [(set_attr "type" "imul") 7590 (set_attr "ppro_uops" "few") 7591 (set_attr "length_immediate" "0") 7592 (set_attr "mode" "SI")]) 7593 |
7594(define_expand "smuldi3_highpart" 7595 [(parallel [(set (match_operand:DI 0 "register_operand" "=d") 7596 (truncate:DI 7597 (lshiftrt:TI 7598 (mult:TI (sign_extend:TI 7599 (match_operand:DI 1 "nonimmediate_operand" "")) 7600 (sign_extend:TI 7601 (match_operand:DI 2 "register_operand" ""))) 7602 (const_int 64)))) 7603 (clobber (match_scratch:DI 3 "")) 7604 (clobber (reg:CC 17))])] 7605 "TARGET_64BIT" 7606 "") 7607 |
7608(define_insn "*smuldi3_highpart_rex64" 7609 [(set (match_operand:DI 0 "register_operand" "=d") 7610 (truncate:DI 7611 (lshiftrt:TI 7612 (mult:TI (sign_extend:TI |
7613 (match_operand:DI 1 "nonimmediate_operand" "%a")) |
7614 (sign_extend:TI 7615 (match_operand:DI 2 "nonimmediate_operand" "rm"))) 7616 (const_int 64)))) |
7617 (clobber (match_scratch:DI 3 "=1")) |
7618 (clobber (reg:CC 17))] |
7619 "TARGET_64BIT 7620 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
7621 "imul{q}\t%2" 7622 [(set_attr "type" "imul") 7623 (set_attr "ppro_uops" "few") 7624 (set_attr "mode" "DI")]) 7625 |
7626(define_expand "smulsi3_highpart" 7627 [(parallel [(set (match_operand:SI 0 "register_operand" "") 7628 (truncate:SI 7629 (lshiftrt:DI 7630 (mult:DI (sign_extend:DI 7631 (match_operand:SI 1 "nonimmediate_operand" "")) 7632 (sign_extend:DI 7633 (match_operand:SI 2 "register_operand" ""))) 7634 (const_int 32)))) 7635 (clobber (match_scratch:SI 3 "")) 7636 (clobber (reg:CC 17))])] 7637 "" 7638 "") 7639 7640(define_insn "*smulsi3_highpart_insn" |
7641 [(set (match_operand:SI 0 "register_operand" "=d") 7642 (truncate:SI 7643 (lshiftrt:DI 7644 (mult:DI (sign_extend:DI |
7645 (match_operand:SI 1 "nonimmediate_operand" "%a")) |
7646 (sign_extend:DI 7647 (match_operand:SI 2 "nonimmediate_operand" "rm"))) 7648 (const_int 32)))) |
7649 (clobber (match_scratch:SI 3 "=1")) |
7650 (clobber (reg:CC 17))] |
7651 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" |
7652 "imul{l}\t%2" 7653 [(set_attr "type" "imul") 7654 (set_attr "ppro_uops" "few") 7655 (set_attr "mode" "SI")]) 7656 7657(define_insn "*smulsi3_highpart_zext" 7658 [(set (match_operand:DI 0 "register_operand" "=d") 7659 (zero_extend:DI (truncate:SI 7660 (lshiftrt:DI 7661 (mult:DI (sign_extend:DI |
7662 (match_operand:SI 1 "nonimmediate_operand" "%a")) |
7663 (sign_extend:DI 7664 (match_operand:SI 2 "nonimmediate_operand" "rm"))) 7665 (const_int 32))))) |
7666 (clobber (match_scratch:SI 3 "=1")) |
7667 (clobber (reg:CC 17))] |
7668 "TARGET_64BIT 7669 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
7670 "imul{l}\t%2" 7671 [(set_attr "type" "imul") 7672 (set_attr "ppro_uops" "few") 7673 (set_attr "mode" "SI")]) 7674 7675;; The patterns that match these are at the end of this file. 7676 7677(define_expand "mulxf3" --- 6013 unchanged lines hidden (view full) --- 13691{ 13692 int i; 13693 13694 /* In order to give reg-stack an easier job in validating two 13695 coprocessor registers as containing a possible return value, 13696 simply pretend the untyped call returns a complex long double 13697 value. */ 13698 |
13699 emit_call_insn (TARGET_FLOAT_RETURNS_IN_80387 |
13700 ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG), 13701 operands[0], const0_rtx, 13702 GEN_INT (SSE_REGPARM_MAX - 1)) 13703 : gen_call (operands[0], const0_rtx, 13704 GEN_INT (SSE_REGPARM_MAX - 1))); 13705 13706 for (i = 0; i < XVECLEN (operands[2], 0); i++) 13707 { --- 298 unchanged lines hidden (view full) --- 14006;; SImode if the target mode DFmode, but only SImode if the target mode 14007;; is SFmode. 14008 14009;; Gcc is slightly more smart about handling normal two address instructions 14010;; so use special patterns for add and mull. 14011(define_insn "*fop_sf_comm_nosse" 14012 [(set (match_operand:SF 0 "register_operand" "=f") 14013 (match_operator:SF 3 "binary_fp_operator" |
14014 [(match_operand:SF 1 "nonimmediate_operand" "%0") |
14015 (match_operand:SF 2 "nonimmediate_operand" "fm")]))] 14016 "TARGET_80387 && !TARGET_SSE_MATH |
14017 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' 14018 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
14019 "* return output_387_binary_op (insn, operands);" 14020 [(set (attr "type") 14021 (if_then_else (match_operand:SF 3 "mult_operator" "") 14022 (const_string "fmul") 14023 (const_string "fop"))) 14024 (set_attr "mode" "SF")]) 14025 14026(define_insn "*fop_sf_comm" 14027 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f") 14028 (match_operator:SF 3 "binary_fp_operator" |
14029 [(match_operand:SF 1 "nonimmediate_operand" "%0,0") |
14030 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))] 14031 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387 |
14032 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' 14033 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
14034 "* return output_387_binary_op (insn, operands);" 14035 [(set (attr "type") 14036 (if_then_else (eq_attr "alternative" "1") 14037 (const_string "sse") 14038 (if_then_else (match_operand:SF 3 "mult_operator" "") 14039 (const_string "fmul") 14040 (const_string "fop")))) 14041 (set_attr "mode" "SF")]) 14042 14043(define_insn "*fop_sf_comm_sse" 14044 [(set (match_operand:SF 0 "register_operand" "=x") 14045 (match_operator:SF 3 "binary_fp_operator" |
14046 [(match_operand:SF 1 "nonimmediate_operand" "%0") |
14047 (match_operand:SF 2 "nonimmediate_operand" "xm")]))] |
14048 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' 14049 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
14050 "* return output_387_binary_op (insn, operands);" 14051 [(set_attr "type" "sse") 14052 (set_attr "mode" "SF")]) 14053 14054(define_insn "*fop_df_comm_nosse" 14055 [(set (match_operand:DF 0 "register_operand" "=f") 14056 (match_operator:DF 3 "binary_fp_operator" |
14057 [(match_operand:DF 1 "nonimmediate_operand" "%0") |
14058 (match_operand:DF 2 "nonimmediate_operand" "fm")]))] 14059 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH) |
14060 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' 14061 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
14062 "* return output_387_binary_op (insn, operands);" 14063 [(set (attr "type") 14064 (if_then_else (match_operand:SF 3 "mult_operator" "") 14065 (const_string "fmul") 14066 (const_string "fop"))) 14067 (set_attr "mode" "DF")]) 14068 14069(define_insn "*fop_df_comm" 14070 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f") 14071 (match_operator:DF 3 "binary_fp_operator" |
14072 [(match_operand:DF 1 "nonimmediate_operand" "%0,0") |
14073 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))] 14074 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387 |
14075 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' 14076 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
14077 "* return output_387_binary_op (insn, operands);" 14078 [(set (attr "type") 14079 (if_then_else (eq_attr "alternative" "1") 14080 (const_string "sse") 14081 (if_then_else (match_operand:SF 3 "mult_operator" "") 14082 (const_string "fmul") 14083 (const_string "fop")))) 14084 (set_attr "mode" "DF")]) 14085 14086(define_insn "*fop_df_comm_sse" 14087 [(set (match_operand:DF 0 "register_operand" "=Y") 14088 (match_operator:DF 3 "binary_fp_operator" |
14089 [(match_operand:DF 1 "nonimmediate_operand" "%0") |
14090 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))] 14091 "TARGET_SSE2 && TARGET_SSE_MATH |
14092 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' 14093 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
14094 "* return output_387_binary_op (insn, operands);" 14095 [(set_attr "type" "sse") 14096 (set_attr "mode" "DF")]) 14097 14098(define_insn "*fop_xf_comm" 14099 [(set (match_operand:XF 0 "register_operand" "=f") 14100 (match_operator:XF 3 "binary_fp_operator" 14101 [(match_operand:XF 1 "register_operand" "%0") --- 617 unchanged lines hidden (view full) --- 14719 [(set_attr "type" "fpspc") 14720 (set_attr "mode" "XF") 14721 (set_attr "athlon_decode" "direct")]) 14722 14723(define_insn "*sqrtextenddfxf2" 14724 [(set (match_operand:XF 0 "register_operand" "=f") 14725 (sqrt:XF (float_extend:XF 14726 (match_operand:DF 1 "register_operand" "0"))))] |
14727 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387" |
14728 "fsqrt" 14729 [(set_attr "type" "fpspc") 14730 (set_attr "mode" "XF") 14731 (set_attr "athlon_decode" "direct")]) 14732 14733(define_insn "*sqrtextenddftf2" 14734 [(set (match_operand:TF 0 "register_operand" "=f") 14735 (sqrt:TF (float_extend:TF 14736 (match_operand:DF 1 "register_operand" "0"))))] 14737 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387" 14738 "fsqrt" 14739 [(set_attr "type" "fpspc") 14740 (set_attr "mode" "XF") 14741 (set_attr "athlon_decode" "direct")]) 14742 14743(define_insn "*sqrtextendsfxf2" 14744 [(set (match_operand:XF 0 "register_operand" "=f") 14745 (sqrt:XF (float_extend:XF 14746 (match_operand:SF 1 "register_operand" "0"))))] |
14747 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387" |
14748 "fsqrt" 14749 [(set_attr "type" "fpspc") 14750 (set_attr "mode" "XF") 14751 (set_attr "athlon_decode" "direct")]) 14752 14753(define_insn "*sqrtextendsftf2" 14754 [(set (match_operand:TF 0 "register_operand" "=f") 14755 (sqrt:TF (float_extend:TF --- 30 unchanged lines hidden (view full) --- 14786 && flag_unsafe_math_optimizations" 14787 "fsin" 14788 [(set_attr "type" "fpspc") 14789 (set_attr "mode" "DF")]) 14790 14791(define_insn "sinxf2" 14792 [(set (match_operand:XF 0 "register_operand" "=f") 14793 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))] |
14794 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387 |
14795 && flag_unsafe_math_optimizations" 14796 "fsin" 14797 [(set_attr "type" "fpspc") 14798 (set_attr "mode" "XF")]) 14799 14800(define_insn "sintf2" 14801 [(set (match_operand:TF 0 "register_operand" "=f") 14802 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))] --- 1103 unchanged lines hidden (view full) --- 15906 [(set (match_operand:DI 0 "register_operand" "=r,r") 15907 (if_then_else:DI (match_operator 1 "ix86_comparison_operator" 15908 [(reg 17) (const_int 0)]) 15909 (match_operand:DI 2 "nonimmediate_operand" "rm,0") 15910 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))] 15911 "TARGET_64BIT && TARGET_CMOVE 15912 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 15913 "@ |
15914 cmov%O2%C1\t{%2, %0|%0, %2} 15915 cmov%O2%c1\t{%3, %0|%0, %3}" |
15916 [(set_attr "type" "icmov") 15917 (set_attr "mode" "DI")]) 15918 15919(define_expand "movsicc" 15920 [(set (match_operand:SI 0 "register_operand" "") 15921 (if_then_else:SI (match_operand 1 "comparison_operator" "") 15922 (match_operand:SI 2 "general_operand" "") 15923 (match_operand:SI 3 "general_operand" "")))] --- 24 unchanged lines hidden (view full) --- 15948 [(set (match_operand:SI 0 "register_operand" "=r,r") 15949 (if_then_else:SI (match_operator 1 "ix86_comparison_operator" 15950 [(reg 17) (const_int 0)]) 15951 (match_operand:SI 2 "nonimmediate_operand" "rm,0") 15952 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))] 15953 "TARGET_CMOVE 15954 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 15955 "@ |
15956 cmov%O2%C1\t{%2, %0|%0, %2} 15957 cmov%O2%c1\t{%3, %0|%0, %3}" |
15958 [(set_attr "type" "icmov") 15959 (set_attr "mode" "SI")]) 15960 15961(define_expand "movhicc" 15962 [(set (match_operand:HI 0 "register_operand" "") 15963 (if_then_else:HI (match_operand 1 "comparison_operator" "") 15964 (match_operand:HI 2 "nonimmediate_operand" "") 15965 (match_operand:HI 3 "nonimmediate_operand" "")))] --- 4 unchanged lines hidden (view full) --- 15970 [(set (match_operand:HI 0 "register_operand" "=r,r") 15971 (if_then_else:HI (match_operator 1 "ix86_comparison_operator" 15972 [(reg 17) (const_int 0)]) 15973 (match_operand:HI 2 "nonimmediate_operand" "rm,0") 15974 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))] 15975 "TARGET_CMOVE 15976 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 15977 "@ |
15978 cmov%O2%C1\t{%2, %0|%0, %2} 15979 cmov%O2%c1\t{%3, %0|%0, %3}" |
15980 [(set_attr "type" "icmov") 15981 (set_attr "mode" "HI")]) 15982 15983(define_expand "movsfcc" 15984 [(set (match_operand:SF 0 "register_operand" "") 15985 (if_then_else:SF (match_operand 1 "comparison_operator" "") 15986 (match_operand:SF 2 "register_operand" "") 15987 (match_operand:SF 3 "register_operand" "")))] --- 6 unchanged lines hidden (view full) --- 15994 [(reg 17) (const_int 0)]) 15995 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0") 15996 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))] 15997 "TARGET_CMOVE 15998 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 15999 "@ 16000 fcmov%F1\t{%2, %0|%0, %2} 16001 fcmov%f1\t{%3, %0|%0, %3} |
16002 cmov%O2%C1\t{%2, %0|%0, %2} 16003 cmov%O2%c1\t{%3, %0|%0, %3}" |
16004 [(set_attr "type" "fcmov,fcmov,icmov,icmov") 16005 (set_attr "mode" "SF,SF,SI,SI")]) 16006 16007(define_expand "movdfcc" 16008 [(set (match_operand:DF 0 "register_operand" "") 16009 (if_then_else:DF (match_operand 1 "comparison_operator" "") 16010 (match_operand:DF 2 "register_operand" "") 16011 (match_operand:DF 3 "register_operand" "")))] --- 22 unchanged lines hidden (view full) --- 16034 [(reg 17) (const_int 0)]) 16035 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0") 16036 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))] 16037 "TARGET_64BIT && TARGET_CMOVE 16038 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 16039 "@ 16040 fcmov%F1\t{%2, %0|%0, %2} 16041 fcmov%f1\t{%3, %0|%0, %3} |
16042 cmov%O2%C1\t{%2, %0|%0, %2} 16043 cmov%O2%c1\t{%3, %0|%0, %3}" |
16044 [(set_attr "type" "fcmov,fcmov,icmov,icmov") 16045 (set_attr "mode" "DF")]) 16046 16047(define_split 16048 [(set (match_operand:DF 0 "register_operand" "") 16049 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 16050 [(match_operand 4 "" "") (const_int 0)]) 16051 (match_operand:DF 2 "nonimmediate_operand" "") --- 71 unchanged lines hidden (view full) --- 16123 (match_dup 1) 16124 (match_dup 2))) 16125 (clobber (reg:CC 17))] 16126 "TARGET_SSE && TARGET_IEEE_FP" 16127 "#") 16128 16129(define_insn "*minsf_nonieee" 16130 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x") |
16131 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
16132 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x")) 16133 (match_dup 1) 16134 (match_dup 2))) 16135 (clobber (reg:CC 17))] |
16136 "TARGET_SSE && !TARGET_IEEE_FP 16137 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
16138 "#") 16139 16140(define_split 16141 [(set (match_operand:SF 0 "register_operand" "") 16142 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "") 16143 (match_operand:SF 2 "nonimmediate_operand" "")) 16144 (match_operand:SF 3 "register_operand" "") 16145 (match_operand:SF 4 "nonimmediate_operand" ""))) --- 60 unchanged lines hidden (view full) --- 16206 (match_dup 1) 16207 (match_dup 2))) 16208 (clobber (reg:CC 17))] 16209 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH" 16210 "#") 16211 16212(define_insn "*mindf_nonieee" 16213 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y") |
16214 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
16215 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y")) 16216 (match_dup 1) 16217 (match_dup 2))) 16218 (clobber (reg:CC 17))] |
16219 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP 16220 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
16221 "#") 16222 16223(define_split 16224 [(set (match_operand:DF 0 "register_operand" "") 16225 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "") 16226 (match_operand:DF 2 "nonimmediate_operand" "")) 16227 (match_operand:DF 3 "register_operand" "") 16228 (match_operand:DF 4 "nonimmediate_operand" ""))) --- 59 unchanged lines hidden (view full) --- 16288 (match_dup 1) 16289 (match_dup 2))) 16290 (clobber (reg:CC 17))] 16291 "TARGET_SSE && TARGET_IEEE_FP" 16292 "#") 16293 16294(define_insn "*maxsf_nonieee" 16295 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x") |
16296 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
16297 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x")) 16298 (match_dup 1) 16299 (match_dup 2))) 16300 (clobber (reg:CC 17))] |
16301 "TARGET_SSE && !TARGET_IEEE_FP 16302 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
16303 "#") 16304 16305(define_split 16306 [(set (match_operand:SF 0 "register_operand" "") 16307 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "") 16308 (match_operand:SF 2 "nonimmediate_operand" "")) 16309 (match_operand:SF 3 "register_operand" "") 16310 (match_operand:SF 4 "nonimmediate_operand" ""))) --- 58 unchanged lines hidden (view full) --- 16369 (match_dup 1) 16370 (match_dup 2))) 16371 (clobber (reg:CC 17))] 16372 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP" 16373 "#") 16374 16375(define_insn "*maxdf_nonieee" 16376 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y") |
16377 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
16378 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y")) 16379 (match_dup 1) 16380 (match_dup 2))) 16381 (clobber (reg:CC 17))] |
16382 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP 16383 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
16384 "#") 16385 16386(define_split 16387 [(set (match_operand:DF 0 "register_operand" "") 16388 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "") 16389 (match_operand:DF 2 "nonimmediate_operand" "")) 16390 (match_operand:DF 3 "register_operand" "") 16391 (match_operand:DF 4 "nonimmediate_operand" ""))) --- 1715 unchanged lines hidden (view full) --- 18107 "TARGET_SSE || TARGET_3DNOW_A" 18108 "pmovmskb\t{%1, %0|%0, %1}" 18109 [(set_attr "type" "sse")]) 18110 18111(define_insn "mmx_maskmovq" 18112 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D")) 18113 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") 18114 (match_operand:V8QI 2 "register_operand" "y")] 32))] |
18115 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT" |
18116 ;; @@@ check ordering of operands in intel/nonintel syntax 18117 "maskmovq\t{%2, %1|%1, %2}" 18118 [(set_attr "type" "sse")]) 18119 |
18120(define_insn "mmx_maskmovq_rex" 18121 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D")) 18122 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") 18123 (match_operand:V8QI 2 "register_operand" "y")] 32))] 18124 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT" 18125 ;; @@@ check ordering of operands in intel/nonintel syntax 18126 "maskmovq\t{%2, %1|%1, %2}" 18127 [(set_attr "type" "sse")]) 18128 |
18129(define_insn "sse_movntv4sf" 18130 [(set (match_operand:V4SF 0 "memory_operand" "=m") 18131 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))] 18132 "TARGET_SSE" 18133 "movntps\t{%1, %0|%0, %1}" 18134 [(set_attr "type" "sse")]) 18135 18136(define_insn "sse_movntdi" --- 263 unchanged lines hidden (view full) --- 18400 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0) 18401 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18402 "TARGET_SSE" 18403 "andps\t{%2, %0|%0, %2}" 18404 [(set_attr "type" "sse")]) 18405 18406(define_insn "sse_andti3" 18407 [(set (match_operand:TI 0 "register_operand" "=x") |
18408 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
18409 (match_operand:TI 2 "nonimmediate_operand" "xm")))] |
18410 "TARGET_SSE && !TARGET_SSE2 18411 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
18412 "andps\t{%2, %0|%0, %2}" 18413 [(set_attr "type" "sse")]) 18414 18415(define_insn "*sse_andti3_sse2" 18416 [(set (match_operand:TI 0 "register_operand" "=x") |
18417 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
18418 (match_operand:TI 2 "nonimmediate_operand" "xm")))] |
18419 "TARGET_SSE2 18420 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
18421 "pand\t{%2, %0|%0, %2}" 18422 [(set_attr "type" "sse")]) 18423 18424(define_insn "*sse_nandti3_df" 18425 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) 18426 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)) 18427 (match_operand:TI 2 "nonimmediate_operand" "Ym")))] 18428 "TARGET_SSE2" --- 53 unchanged lines hidden (view full) --- 18482 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0) 18483 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18484 "TARGET_SSE" 18485 "orps\t{%2, %0|%0, %2}" 18486 [(set_attr "type" "sse")]) 18487 18488(define_insn "sse_iorti3" 18489 [(set (match_operand:TI 0 "register_operand" "=x") |
18490 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
18491 (match_operand:TI 2 "nonimmediate_operand" "xm")))] |
18492 "TARGET_SSE && !TARGET_SSE2 18493 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
18494 "orps\t{%2, %0|%0, %2}" 18495 [(set_attr "type" "sse")]) 18496 18497(define_insn "*sse_iorti3_sse2" 18498 [(set (match_operand:TI 0 "register_operand" "=x") |
18499 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
18500 (match_operand:TI 2 "nonimmediate_operand" "xm")))] |
18501 "TARGET_SSE2 18502 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
18503 "por\t{%2, %0|%0, %2}" 18504 [(set_attr "type" "sse")]) 18505 18506(define_insn "*sse_xorti3_df_1" 18507 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) 18508 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0) 18509 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))] 18510 "TARGET_SSE2" --- 21 unchanged lines hidden (view full) --- 18532 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0) 18533 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18534 "TARGET_SSE" 18535 "xorps\t{%2, %0|%0, %2}" 18536 [(set_attr "type" "sse")]) 18537 18538(define_insn "sse_xorti3" 18539 [(set (match_operand:TI 0 "register_operand" "=x") |
18540 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
18541 (match_operand:TI 2 "nonimmediate_operand" "xm")))] |
18542 "TARGET_SSE && !TARGET_SSE2 18543 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
18544 "xorps\t{%2, %0|%0, %2}" 18545 [(set_attr "type" "sse")]) 18546 18547(define_insn "*sse_xorti3_sse2" 18548 [(set (match_operand:TI 0 "register_operand" "=x") |
18549 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
18550 (match_operand:TI 2 "nonimmediate_operand" "xm")))] |
18551 "TARGET_SSE2 18552 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
18553 "pxor\t{%2, %0|%0, %2}" 18554 [(set_attr "type" "sse")]) 18555 18556;; Use xor, but don't show input operands so they aren't live before 18557;; this insn. 18558(define_insn "sse_clrv4sf" 18559 [(set (match_operand:V4SF 0 "register_operand" "=x") 18560 (unspec:V4SF [(const_int 0)] 45))] --- 453 unchanged lines hidden (view full) --- 19014;; MMX unsigned averages/sum of absolute differences 19015 19016(define_insn "mmx_uavgv8qi3" 19017 [(set (match_operand:V8QI 0 "register_operand" "=y") 19018 (ashiftrt:V8QI 19019 (plus:V8QI (plus:V8QI 19020 (match_operand:V8QI 1 "register_operand" "0") 19021 (match_operand:V8QI 2 "nonimmediate_operand" "ym")) |
19022 (const_vector:V8QI [(const_int 1) 19023 (const_int 1) 19024 (const_int 1) 19025 (const_int 1) 19026 (const_int 1) 19027 (const_int 1) 19028 (const_int 1) 19029 (const_int 1)])) |
19030 (const_int 1)))] 19031 "TARGET_SSE || TARGET_3DNOW_A" 19032 "pavgb\t{%2, %0|%0, %2}" 19033 [(set_attr "type" "sse")]) 19034 19035(define_insn "mmx_uavgv4hi3" 19036 [(set (match_operand:V4HI 0 "register_operand" "=y") 19037 (ashiftrt:V4HI 19038 (plus:V4HI (plus:V4HI 19039 (match_operand:V4HI 1 "register_operand" "0") 19040 (match_operand:V4HI 2 "nonimmediate_operand" "ym")) |
19041 (const_vector:V4HI [(const_int 1) 19042 (const_int 1) 19043 (const_int 1) 19044 (const_int 1)])) |
19045 (const_int 1)))] 19046 "TARGET_SSE || TARGET_3DNOW_A" 19047 "pavgw\t{%2, %0|%0, %2}" 19048 [(set_attr "type" "sse")]) 19049 19050(define_insn "mmx_psadbw" 19051 [(set (match_operand:V8QI 0 "register_operand" "=y") 19052 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "0") --- 697 unchanged lines hidden (view full) --- 19750 (truncate:V4HI 19751 (lshiftrt:V4SI 19752 (plus:V4SI 19753 (mult:V4SI 19754 (sign_extend:V4SI 19755 (match_operand:V4HI 1 "register_operand" "0")) 19756 (sign_extend:V4SI 19757 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) |
19758 (const_vector:V4SI [(const_int 32768) 19759 (const_int 32768) 19760 (const_int 32768) 19761 (const_int 32768)])) 19762 (const_int 16))))] |
19763 "TARGET_3DNOW" 19764 "pmulhrw\\t{%2, %0|%0, %2}" 19765 [(set_attr "type" "mmx")]) 19766 19767(define_insn "pswapdv2si2" 19768 [(set (match_operand:V2SI 0 "register_operand" "=y") 19769 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym") 19770 (parallel [(const_int 1) (const_int 0)])))] --- 66 unchanged lines hidden --- |