116c116
< ;; $FreeBSD: head/contrib/gcc/config/i386/i386.md 90286 2002-02-06 05:02:18Z obrien $
---
> ;; $FreeBSD: head/contrib/gcc/config/i386/i386.md 96294 2002-05-09 22:44:32Z obrien $
1737a1738,1742
> ; The first alternative is used only to compute proper length of instruction.
> ; Reload's algorithm does not take into account the cost of spill instructions
> ; needed to free register in given class, so avoid it from choosing the first
> ; alternative when eax is not available.
>
1739,1740c1744,1745
< [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!rm,!*Y,!rm,!*Y")
< (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,rm,*Y,*Y"))]
---
> [(set (match_operand:SI 0 "nonimmediate_operand" "=*?a,r,*?a,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
> (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,*y,rm,*Y,*Y"))]
1750a1756,1757
> if (get_attr_mode (insn) == DImode)
> return "movq\t{%1, %0|%0, %1}";
1763c1770
< (cond [(eq_attr "alternative" "4,5")
---
> (cond [(eq_attr "alternative" "4,5,6")
1765c1772
< (eq_attr "alternative" "6,7,8")
---
> (eq_attr "alternative" "7,8,9")
1772,1773c1779,1780
< (set_attr "modrm" "0,*,0,*,*,*,*,*,*")
< (set_attr "mode" "SI,SI,SI,SI,SI,SI,TI,SI,SI")])
---
> (set_attr "modrm" "0,*,0,*,*,*,*,*,*,*")
> (set_attr "mode" "SI,SI,SI,SI,SI,SI,DI,TI,SI,SI")])
1845a1853,1857
> ; The first alternative is used only to compute proper length of instruction.
> ; Reload's algorithm does not take into account the cost of spill instructions
> ; needed to free register in given class, so avoid it from choosing the first
> ; alternative when eax is not available.
>
1847c1859
< [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m")
---
> [(set (match_operand:HI 0 "nonimmediate_operand" "=*?a,r,r,*?a,r,m")
2465c2477
< [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,*Y,!*Y")
---
> [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
2718,2719c2730,2731
< [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m")
< (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf"))]
---
> [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
> (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf,rm,*y,*y"))]
2757c2769,2772
< return "pxor\t%0, %0";
---
> if (TARGET_SSE2)
> return "pxor\t%0, %0";
> else
> return "xorps\t%0, %0";
2766a2782,2788
> case 9:
> case 10:
> return "movd\t{%1, %0|%0, %1}";
>
> case 11:
> return "movq\t{%1, %0|%0, %1}";
>
2771,2772c2793,2794
< [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse")
< (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF")])
---
> [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse,mmx,mmx,mmx")
> (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF,SI,SI,DI")])
5132c5154
< ""
---
> "TARGET_80387 || TARGET_SSE2"
7335c7357,7365
< (define_insn "mulqi3"
---
> (define_expand "mulqi3"
> [(parallel [(set (match_operand:QI 0 "register_operand" "")
> (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
> (match_operand:QI 2 "register_operand" "")))
> (clobber (reg:CC 17))])]
> "TARGET_QIMODE_MATH"
> "")
>
> (define_insn "*mulqi3_1"
7337c7367
< (mult:QI (match_operand:QI 1 "register_operand" "%0")
---
> (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7340c7370,7371
< "TARGET_QIMODE_MATH"
---
> "TARGET_QIMODE_MATH
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7346c7377,7387
< (define_insn "umulqihi3"
---
> (define_expand "umulqihi3"
> [(parallel [(set (match_operand:HI 0 "register_operand" "")
> (mult:HI (zero_extend:HI
> (match_operand:QI 1 "nonimmediate_operand" ""))
> (zero_extend:HI
> (match_operand:QI 2 "register_operand" ""))))
> (clobber (reg:CC 17))])]
> "TARGET_QIMODE_MATH"
> "")
>
> (define_insn "*umulqihi3_1"
7348c7389
< (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
---
> (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7351c7392,7393
< "TARGET_QIMODE_MATH"
---
> "TARGET_QIMODE_MATH
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7357c7399,7407
< (define_insn "mulqihi3"
---
> (define_expand "mulqihi3"
> [(parallel [(set (match_operand:HI 0 "register_operand" "")
> (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
> (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
> (clobber (reg:CC 17))])]
> "TARGET_QIMODE_MATH"
> "")
>
> (define_insn "*mulqihi3_insn"
7359c7409
< (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
---
> (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7362c7412,7413
< "TARGET_QIMODE_MATH"
---
> "TARGET_QIMODE_MATH
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7368c7419,7429
< (define_insn "umulditi3"
---
> (define_expand "umulditi3"
> [(parallel [(set (match_operand:TI 0 "register_operand" "")
> (mult:TI (zero_extend:TI
> (match_operand:DI 1 "nonimmediate_operand" ""))
> (zero_extend:TI
> (match_operand:DI 2 "register_operand" ""))))
> (clobber (reg:CC 17))])]
> "TARGET_64BIT"
> "")
>
> (define_insn "*umulditi3_insn"
7370c7431
< (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "%0"))
---
> (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7373c7434,7435
< "TARGET_64BIT"
---
> "TARGET_64BIT
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7381c7443,7453
< (define_insn "umulsidi3"
---
> (define_expand "umulsidi3"
> [(parallel [(set (match_operand:DI 0 "register_operand" "")
> (mult:DI (zero_extend:DI
> (match_operand:SI 1 "nonimmediate_operand" ""))
> (zero_extend:DI
> (match_operand:SI 2 "register_operand" ""))))
> (clobber (reg:CC 17))])]
> "!TARGET_64BIT"
> "")
>
> (define_insn "*umulsidi3_insn"
7383c7455
< (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
---
> (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7386c7458,7459
< "!TARGET_64BIT"
---
> "!TARGET_64BIT
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7393c7466,7476
< (define_insn "mulditi3"
---
> (define_expand "mulditi3"
> [(parallel [(set (match_operand:TI 0 "register_operand" "")
> (mult:TI (sign_extend:TI
> (match_operand:DI 1 "nonimmediate_operand" ""))
> (sign_extend:TI
> (match_operand:DI 2 "register_operand" ""))))
> (clobber (reg:CC 17))])]
> "TARGET_64BIT"
> "")
>
> (define_insn "*mulditi3_insn"
7395c7478
< (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "%0"))
---
> (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7398c7481,7482
< "TARGET_64BIT"
---
> "TARGET_64BIT
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7404c7488,7498
< (define_insn "mulsidi3"
---
> (define_expand "mulsidi3"
> [(parallel [(set (match_operand:DI 0 "register_operand" "")
> (mult:DI (sign_extend:DI
> (match_operand:SI 1 "nonimmediate_operand" ""))
> (sign_extend:DI
> (match_operand:SI 2 "register_operand" ""))))
> (clobber (reg:CC 17))])]
> "!TARGET_64BIT"
> "")
>
> (define_insn "*mulsidi3_insn"
7406c7500
< (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
---
> (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7409c7503,7504
< "!TARGET_64BIT"
---
> "!TARGET_64BIT
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7414a7510,7523
> (define_expand "umuldi3_highpart"
> [(parallel [(set (match_operand:DI 0 "register_operand" "")
> (truncate:DI
> (lshiftrt:TI
> (mult:TI (zero_extend:TI
> (match_operand:DI 1 "nonimmediate_operand" ""))
> (zero_extend:TI
> (match_operand:DI 2 "register_operand" "")))
> (const_int 64))))
> (clobber (match_scratch:DI 3 ""))
> (clobber (reg:CC 17))])]
> "TARGET_64BIT"
> "")
>
7420c7529
< (match_operand:DI 1 "register_operand" "%a"))
---
> (match_operand:DI 1 "nonimmediate_operand" "%a"))
7424c7533
< (clobber (match_scratch:DI 3 "=a"))
---
> (clobber (match_scratch:DI 3 "=1"))
7426c7535,7536
< "TARGET_64BIT"
---
> "TARGET_64BIT
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7433c7543,7557
< (define_insn "umulsi3_highpart"
---
> (define_expand "umulsi3_highpart"
> [(parallel [(set (match_operand:SI 0 "register_operand" "")
> (truncate:SI
> (lshiftrt:DI
> (mult:DI (zero_extend:DI
> (match_operand:SI 1 "nonimmediate_operand" ""))
> (zero_extend:DI
> (match_operand:SI 2 "register_operand" "")))
> (const_int 32))))
> (clobber (match_scratch:SI 3 ""))
> (clobber (reg:CC 17))])]
> ""
> "")
>
> (define_insn "*umulsi3_highpart_insn"
7438c7562
< (match_operand:SI 1 "register_operand" "%a"))
---
> (match_operand:SI 1 "nonimmediate_operand" "%a"))
7442c7566
< (clobber (match_scratch:SI 3 "=a"))
---
> (clobber (match_scratch:SI 3 "=1"))
7444c7568
< ""
---
> "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7456c7580
< (match_operand:SI 1 "register_operand" "%a"))
---
> (match_operand:SI 1 "nonimmediate_operand" "%a"))
7460c7584
< (clobber (match_scratch:SI 3 "=a"))
---
> (clobber (match_scratch:SI 3 "=1"))
7462c7586,7587
< "TARGET_64BIT"
---
> "TARGET_64BIT
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7468a7594,7607
> (define_expand "smuldi3_highpart"
> [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
> (truncate:DI
> (lshiftrt:TI
> (mult:TI (sign_extend:TI
> (match_operand:DI 1 "nonimmediate_operand" ""))
> (sign_extend:TI
> (match_operand:DI 2 "register_operand" "")))
> (const_int 64))))
> (clobber (match_scratch:DI 3 ""))
> (clobber (reg:CC 17))])]
> "TARGET_64BIT"
> "")
>
7474c7613
< (match_operand:DI 1 "register_operand" "%a"))
---
> (match_operand:DI 1 "nonimmediate_operand" "%a"))
7478c7617
< (clobber (match_scratch:DI 3 "=a"))
---
> (clobber (match_scratch:DI 3 "=1"))
7480c7619,7620
< "TARGET_64BIT"
---
> "TARGET_64BIT
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7486c7626,7640
< (define_insn "smulsi3_highpart"
---
> (define_expand "smulsi3_highpart"
> [(parallel [(set (match_operand:SI 0 "register_operand" "")
> (truncate:SI
> (lshiftrt:DI
> (mult:DI (sign_extend:DI
> (match_operand:SI 1 "nonimmediate_operand" ""))
> (sign_extend:DI
> (match_operand:SI 2 "register_operand" "")))
> (const_int 32))))
> (clobber (match_scratch:SI 3 ""))
> (clobber (reg:CC 17))])]
> ""
> "")
>
> (define_insn "*smulsi3_highpart_insn"
7491c7645
< (match_operand:SI 1 "register_operand" "%a"))
---
> (match_operand:SI 1 "nonimmediate_operand" "%a"))
7495c7649
< (clobber (match_scratch:SI 3 "=a"))
---
> (clobber (match_scratch:SI 3 "=1"))
7497c7651
< ""
---
> "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7508c7662
< (match_operand:SI 1 "register_operand" "%a"))
---
> (match_operand:SI 1 "nonimmediate_operand" "%a"))
7512c7666
< (clobber (match_scratch:SI 3 "=a"))
---
> (clobber (match_scratch:SI 3 "=1"))
7514c7668,7669
< "TARGET_64BIT"
---
> "TARGET_64BIT
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13544c13699
< emit_call_insn (TARGET_80387
---
> emit_call_insn (TARGET_FLOAT_RETURNS_IN_80387
13859c14014
< [(match_operand:SF 1 "register_operand" "%0")
---
> [(match_operand:SF 1 "nonimmediate_operand" "%0")
13862c14017,14018
< && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
---
> && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13873c14029
< [(match_operand:SF 1 "register_operand" "%0,0")
---
> [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
13876c14032,14033
< && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
---
> && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13889c14046
< [(match_operand:SF 1 "register_operand" "%0")
---
> [(match_operand:SF 1 "nonimmediate_operand" "%0")
13891c14048,14049
< "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
---
> "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13899c14057
< [(match_operand:DF 1 "register_operand" "%0")
---
> [(match_operand:DF 1 "nonimmediate_operand" "%0")
13902c14060,14061
< && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
---
> && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13913c14072
< [(match_operand:DF 1 "register_operand" "%0,0")
---
> [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
13916c14075,14076
< && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
---
> && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13929c14089
< [(match_operand:DF 1 "register_operand" "%0")
---
> [(match_operand:DF 1 "nonimmediate_operand" "%0")
13932c14092,14093
< && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
---
> && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14566c14727
< "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387"
---
> "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14586c14747
< "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387"
---
> "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14633c14794
< "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387
---
> "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
15753,15754c15914,15915
< cmov%C1\t{%2, %0|%0, %2}
< cmov%c1\t{%3, %0|%0, %3}"
---
> cmov%O2%C1\t{%2, %0|%0, %2}
> cmov%O2%c1\t{%3, %0|%0, %3}"
15795,15796c15956,15957
< cmov%C1\t{%2, %0|%0, %2}
< cmov%c1\t{%3, %0|%0, %3}"
---
> cmov%O2%C1\t{%2, %0|%0, %2}
> cmov%O2%c1\t{%3, %0|%0, %3}"
15817,15818c15978,15979
< cmov%C1\t{%2, %0|%0, %2}
< cmov%c1\t{%3, %0|%0, %3}"
---
> cmov%O2%C1\t{%2, %0|%0, %2}
> cmov%O2%c1\t{%3, %0|%0, %3}"
15841,15842c16002,16003
< cmov%C1\t{%2, %0|%0, %2}
< cmov%c1\t{%3, %0|%0, %3}"
---
> cmov%O2%C1\t{%2, %0|%0, %2}
> cmov%O2%c1\t{%3, %0|%0, %3}"
15881,15882c16042,16043
< cmov%C1\t{%2, %0|%0, %2}
< cmov%c1\t{%3, %0|%0, %3}"
---
> cmov%O2%C1\t{%2, %0|%0, %2}
> cmov%O2%c1\t{%3, %0|%0, %3}"
15970c16131
< (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0")
---
> (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
15975c16136,16137
< "TARGET_SSE && !TARGET_IEEE_FP"
---
> "TARGET_SSE && !TARGET_IEEE_FP
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16052c16214
< (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0")
---
> (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16057c16219,16220
< "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
---
> "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16133c16296
< (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0")
---
> (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
16138c16301,16302
< "TARGET_SSE && !TARGET_IEEE_FP"
---
> "TARGET_SSE && !TARGET_IEEE_FP
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16213c16377
< (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0")
---
> (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16218c16382,16383
< "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
---
> "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17950c18115
< "TARGET_SSE || TARGET_3DNOW_A"
---
> "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
17954a18120,18128
> (define_insn "mmx_maskmovq_rex"
> [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
> (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
> (match_operand:V8QI 2 "register_operand" "y")] 32))]
> "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
> ;; @@@ check ordering of operands in intel/nonintel syntax
> "maskmovq\t{%2, %1|%1, %2}"
> [(set_attr "type" "sse")])
>
18234c18408
< (and:TI (match_operand:TI 1 "register_operand" "%0")
---
> (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18236c18410,18411
< "TARGET_SSE && !TARGET_SSE2"
---
> "TARGET_SSE && !TARGET_SSE2
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18242c18417
< (and:TI (match_operand:TI 1 "register_operand" "%0")
---
> (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18244c18419,18420
< "TARGET_SSE2"
---
> "TARGET_SSE2
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18314c18490
< (ior:TI (match_operand:TI 1 "register_operand" "%0")
---
> (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18316c18492,18493
< "TARGET_SSE && !TARGET_SSE2"
---
> "TARGET_SSE && !TARGET_SSE2
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18322c18499
< (ior:TI (match_operand:TI 1 "register_operand" "%0")
---
> (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18324c18501,18502
< "TARGET_SSE2"
---
> "TARGET_SSE2
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18362c18540
< (xor:TI (match_operand:TI 1 "register_operand" "%0")
---
> (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18364c18542,18543
< "TARGET_SSE && !TARGET_SSE2"
---
> "TARGET_SSE && !TARGET_SSE2
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18370c18549
< (xor:TI (match_operand:TI 1 "register_operand" "%0")
---
> (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18372c18551,18552
< "TARGET_SSE2"
---
> "TARGET_SSE2
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18842,18849c19022,19029
< (vec_const:V8QI (parallel [(const_int 1)
< (const_int 1)
< (const_int 1)
< (const_int 1)
< (const_int 1)
< (const_int 1)
< (const_int 1)
< (const_int 1)])))
---
> (const_vector:V8QI [(const_int 1)
> (const_int 1)
> (const_int 1)
> (const_int 1)
> (const_int 1)
> (const_int 1)
> (const_int 1)
> (const_int 1)]))
18861,18864c19041,19044
< (vec_const:V4HI (parallel [(const_int 1)
< (const_int 1)
< (const_int 1)
< (const_int 1)])))
---
> (const_vector:V4HI [(const_int 1)
> (const_int 1)
> (const_int 1)
> (const_int 1)]))
19578,19583c19758,19762
< (vec_const:V4SI
< (parallel [(const_int 32768)
< (const_int 32768)
< (const_int 32768)
< (const_int 32768)])))
< (const_int 16))))]
---
> (const_vector:V4SI [(const_int 32768)
> (const_int 32768)
> (const_int 32768)
> (const_int 32768)]))
> (const_int 16))))]
< ;; $FreeBSD: head/contrib/gcc/config/i386/i386.md 90286 2002-02-06 05:02:18Z obrien $
---
> ;; $FreeBSD: head/contrib/gcc/config/i386/i386.md 96294 2002-05-09 22:44:32Z obrien $
1737a1738,1742
> ; The first alternative is used only to compute proper length of instruction.
> ; Reload's algorithm does not take into account the cost of spill instructions
> ; needed to free register in given class, so avoid it from choosing the first
> ; alternative when eax is not available.
>
1739,1740c1744,1745
< [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!rm,!*Y,!rm,!*Y")
< (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,rm,*Y,*Y"))]
---
> [(set (match_operand:SI 0 "nonimmediate_operand" "=*?a,r,*?a,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
> (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,*y,rm,*Y,*Y"))]
1750a1756,1757
> if (get_attr_mode (insn) == DImode)
> return "movq\t{%1, %0|%0, %1}";
1763c1770
< (cond [(eq_attr "alternative" "4,5")
---
> (cond [(eq_attr "alternative" "4,5,6")
1765c1772
< (eq_attr "alternative" "6,7,8")
---
> (eq_attr "alternative" "7,8,9")
1772,1773c1779,1780
< (set_attr "modrm" "0,*,0,*,*,*,*,*,*")
< (set_attr "mode" "SI,SI,SI,SI,SI,SI,TI,SI,SI")])
---
> (set_attr "modrm" "0,*,0,*,*,*,*,*,*,*")
> (set_attr "mode" "SI,SI,SI,SI,SI,SI,DI,TI,SI,SI")])
1845a1853,1857
> ; The first alternative is used only to compute proper length of instruction.
> ; Reload's algorithm does not take into account the cost of spill instructions
> ; needed to free register in given class, so avoid it from choosing the first
> ; alternative when eax is not available.
>
1847c1859
< [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m")
---
> [(set (match_operand:HI 0 "nonimmediate_operand" "=*?a,r,r,*?a,r,m")
2465c2477
< [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,*Y,!*Y")
---
> [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
2718,2719c2730,2731
< [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m")
< (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf"))]
---
> [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
> (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf,rm,*y,*y"))]
2757c2769,2772
< return "pxor\t%0, %0";
---
> if (TARGET_SSE2)
> return "pxor\t%0, %0";
> else
> return "xorps\t%0, %0";
2766a2782,2788
> case 9:
> case 10:
> return "movd\t{%1, %0|%0, %1}";
>
> case 11:
> return "movq\t{%1, %0|%0, %1}";
>
2771,2772c2793,2794
< [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse")
< (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF")])
---
> [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse,mmx,mmx,mmx")
> (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF,SI,SI,DI")])
5132c5154
< ""
---
> "TARGET_80387 || TARGET_SSE2"
7335c7357,7365
< (define_insn "mulqi3"
---
> (define_expand "mulqi3"
> [(parallel [(set (match_operand:QI 0 "register_operand" "")
> (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
> (match_operand:QI 2 "register_operand" "")))
> (clobber (reg:CC 17))])]
> "TARGET_QIMODE_MATH"
> "")
>
> (define_insn "*mulqi3_1"
7337c7367
< (mult:QI (match_operand:QI 1 "register_operand" "%0")
---
> (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7340c7370,7371
< "TARGET_QIMODE_MATH"
---
> "TARGET_QIMODE_MATH
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7346c7377,7387
< (define_insn "umulqihi3"
---
> (define_expand "umulqihi3"
> [(parallel [(set (match_operand:HI 0 "register_operand" "")
> (mult:HI (zero_extend:HI
> (match_operand:QI 1 "nonimmediate_operand" ""))
> (zero_extend:HI
> (match_operand:QI 2 "register_operand" ""))))
> (clobber (reg:CC 17))])]
> "TARGET_QIMODE_MATH"
> "")
>
> (define_insn "*umulqihi3_1"
7348c7389
< (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
---
> (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7351c7392,7393
< "TARGET_QIMODE_MATH"
---
> "TARGET_QIMODE_MATH
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7357c7399,7407
< (define_insn "mulqihi3"
---
> (define_expand "mulqihi3"
> [(parallel [(set (match_operand:HI 0 "register_operand" "")
> (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
> (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
> (clobber (reg:CC 17))])]
> "TARGET_QIMODE_MATH"
> "")
>
> (define_insn "*mulqihi3_insn"
7359c7409
< (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
---
> (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7362c7412,7413
< "TARGET_QIMODE_MATH"
---
> "TARGET_QIMODE_MATH
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7368c7419,7429
< (define_insn "umulditi3"
---
> (define_expand "umulditi3"
> [(parallel [(set (match_operand:TI 0 "register_operand" "")
> (mult:TI (zero_extend:TI
> (match_operand:DI 1 "nonimmediate_operand" ""))
> (zero_extend:TI
> (match_operand:DI 2 "register_operand" ""))))
> (clobber (reg:CC 17))])]
> "TARGET_64BIT"
> "")
>
> (define_insn "*umulditi3_insn"
7370c7431
< (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "%0"))
---
> (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7373c7434,7435
< "TARGET_64BIT"
---
> "TARGET_64BIT
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7381c7443,7453
< (define_insn "umulsidi3"
---
> (define_expand "umulsidi3"
> [(parallel [(set (match_operand:DI 0 "register_operand" "")
> (mult:DI (zero_extend:DI
> (match_operand:SI 1 "nonimmediate_operand" ""))
> (zero_extend:DI
> (match_operand:SI 2 "register_operand" ""))))
> (clobber (reg:CC 17))])]
> "!TARGET_64BIT"
> "")
>
> (define_insn "*umulsidi3_insn"
7383c7455
< (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
---
> (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7386c7458,7459
< "!TARGET_64BIT"
---
> "!TARGET_64BIT
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7393c7466,7476
< (define_insn "mulditi3"
---
> (define_expand "mulditi3"
> [(parallel [(set (match_operand:TI 0 "register_operand" "")
> (mult:TI (sign_extend:TI
> (match_operand:DI 1 "nonimmediate_operand" ""))
> (sign_extend:TI
> (match_operand:DI 2 "register_operand" ""))))
> (clobber (reg:CC 17))])]
> "TARGET_64BIT"
> "")
>
> (define_insn "*mulditi3_insn"
7395c7478
< (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "%0"))
---
> (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7398c7481,7482
< "TARGET_64BIT"
---
> "TARGET_64BIT
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7404c7488,7498
< (define_insn "mulsidi3"
---
> (define_expand "mulsidi3"
> [(parallel [(set (match_operand:DI 0 "register_operand" "")
> (mult:DI (sign_extend:DI
> (match_operand:SI 1 "nonimmediate_operand" ""))
> (sign_extend:DI
> (match_operand:SI 2 "register_operand" ""))))
> (clobber (reg:CC 17))])]
> "!TARGET_64BIT"
> "")
>
> (define_insn "*mulsidi3_insn"
7406c7500
< (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
---
> (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7409c7503,7504
< "!TARGET_64BIT"
---
> "!TARGET_64BIT
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7414a7510,7523
> (define_expand "umuldi3_highpart"
> [(parallel [(set (match_operand:DI 0 "register_operand" "")
> (truncate:DI
> (lshiftrt:TI
> (mult:TI (zero_extend:TI
> (match_operand:DI 1 "nonimmediate_operand" ""))
> (zero_extend:TI
> (match_operand:DI 2 "register_operand" "")))
> (const_int 64))))
> (clobber (match_scratch:DI 3 ""))
> (clobber (reg:CC 17))])]
> "TARGET_64BIT"
> "")
>
7420c7529
< (match_operand:DI 1 "register_operand" "%a"))
---
> (match_operand:DI 1 "nonimmediate_operand" "%a"))
7424c7533
< (clobber (match_scratch:DI 3 "=a"))
---
> (clobber (match_scratch:DI 3 "=1"))
7426c7535,7536
< "TARGET_64BIT"
---
> "TARGET_64BIT
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7433c7543,7557
< (define_insn "umulsi3_highpart"
---
> (define_expand "umulsi3_highpart"
> [(parallel [(set (match_operand:SI 0 "register_operand" "")
> (truncate:SI
> (lshiftrt:DI
> (mult:DI (zero_extend:DI
> (match_operand:SI 1 "nonimmediate_operand" ""))
> (zero_extend:DI
> (match_operand:SI 2 "register_operand" "")))
> (const_int 32))))
> (clobber (match_scratch:SI 3 ""))
> (clobber (reg:CC 17))])]
> ""
> "")
>
> (define_insn "*umulsi3_highpart_insn"
7438c7562
< (match_operand:SI 1 "register_operand" "%a"))
---
> (match_operand:SI 1 "nonimmediate_operand" "%a"))
7442c7566
< (clobber (match_scratch:SI 3 "=a"))
---
> (clobber (match_scratch:SI 3 "=1"))
7444c7568
< ""
---
> "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7456c7580
< (match_operand:SI 1 "register_operand" "%a"))
---
> (match_operand:SI 1 "nonimmediate_operand" "%a"))
7460c7584
< (clobber (match_scratch:SI 3 "=a"))
---
> (clobber (match_scratch:SI 3 "=1"))
7462c7586,7587
< "TARGET_64BIT"
---
> "TARGET_64BIT
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7468a7594,7607
> (define_expand "smuldi3_highpart"
> [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
> (truncate:DI
> (lshiftrt:TI
> (mult:TI (sign_extend:TI
> (match_operand:DI 1 "nonimmediate_operand" ""))
> (sign_extend:TI
> (match_operand:DI 2 "register_operand" "")))
> (const_int 64))))
> (clobber (match_scratch:DI 3 ""))
> (clobber (reg:CC 17))])]
> "TARGET_64BIT"
> "")
>
7474c7613
< (match_operand:DI 1 "register_operand" "%a"))
---
> (match_operand:DI 1 "nonimmediate_operand" "%a"))
7478c7617
< (clobber (match_scratch:DI 3 "=a"))
---
> (clobber (match_scratch:DI 3 "=1"))
7480c7619,7620
< "TARGET_64BIT"
---
> "TARGET_64BIT
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7486c7626,7640
< (define_insn "smulsi3_highpart"
---
> (define_expand "smulsi3_highpart"
> [(parallel [(set (match_operand:SI 0 "register_operand" "")
> (truncate:SI
> (lshiftrt:DI
> (mult:DI (sign_extend:DI
> (match_operand:SI 1 "nonimmediate_operand" ""))
> (sign_extend:DI
> (match_operand:SI 2 "register_operand" "")))
> (const_int 32))))
> (clobber (match_scratch:SI 3 ""))
> (clobber (reg:CC 17))])]
> ""
> "")
>
> (define_insn "*smulsi3_highpart_insn"
7491c7645
< (match_operand:SI 1 "register_operand" "%a"))
---
> (match_operand:SI 1 "nonimmediate_operand" "%a"))
7495c7649
< (clobber (match_scratch:SI 3 "=a"))
---
> (clobber (match_scratch:SI 3 "=1"))
7497c7651
< ""
---
> "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7508c7662
< (match_operand:SI 1 "register_operand" "%a"))
---
> (match_operand:SI 1 "nonimmediate_operand" "%a"))
7512c7666
< (clobber (match_scratch:SI 3 "=a"))
---
> (clobber (match_scratch:SI 3 "=1"))
7514c7668,7669
< "TARGET_64BIT"
---
> "TARGET_64BIT
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13544c13699
< emit_call_insn (TARGET_80387
---
> emit_call_insn (TARGET_FLOAT_RETURNS_IN_80387
13859c14014
< [(match_operand:SF 1 "register_operand" "%0")
---
> [(match_operand:SF 1 "nonimmediate_operand" "%0")
13862c14017,14018
< && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
---
> && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13873c14029
< [(match_operand:SF 1 "register_operand" "%0,0")
---
> [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
13876c14032,14033
< && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
---
> && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13889c14046
< [(match_operand:SF 1 "register_operand" "%0")
---
> [(match_operand:SF 1 "nonimmediate_operand" "%0")
13891c14048,14049
< "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
---
> "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13899c14057
< [(match_operand:DF 1 "register_operand" "%0")
---
> [(match_operand:DF 1 "nonimmediate_operand" "%0")
13902c14060,14061
< && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
---
> && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13913c14072
< [(match_operand:DF 1 "register_operand" "%0,0")
---
> [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
13916c14075,14076
< && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
---
> && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13929c14089
< [(match_operand:DF 1 "register_operand" "%0")
---
> [(match_operand:DF 1 "nonimmediate_operand" "%0")
13932c14092,14093
< && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
---
> && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14566c14727
< "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387"
---
> "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14586c14747
< "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387"
---
> "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14633c14794
< "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387
---
> "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
15753,15754c15914,15915
< cmov%C1\t{%2, %0|%0, %2}
< cmov%c1\t{%3, %0|%0, %3}"
---
> cmov%O2%C1\t{%2, %0|%0, %2}
> cmov%O2%c1\t{%3, %0|%0, %3}"
15795,15796c15956,15957
< cmov%C1\t{%2, %0|%0, %2}
< cmov%c1\t{%3, %0|%0, %3}"
---
> cmov%O2%C1\t{%2, %0|%0, %2}
> cmov%O2%c1\t{%3, %0|%0, %3}"
15817,15818c15978,15979
< cmov%C1\t{%2, %0|%0, %2}
< cmov%c1\t{%3, %0|%0, %3}"
---
> cmov%O2%C1\t{%2, %0|%0, %2}
> cmov%O2%c1\t{%3, %0|%0, %3}"
15841,15842c16002,16003
< cmov%C1\t{%2, %0|%0, %2}
< cmov%c1\t{%3, %0|%0, %3}"
---
> cmov%O2%C1\t{%2, %0|%0, %2}
> cmov%O2%c1\t{%3, %0|%0, %3}"
15881,15882c16042,16043
< cmov%C1\t{%2, %0|%0, %2}
< cmov%c1\t{%3, %0|%0, %3}"
---
> cmov%O2%C1\t{%2, %0|%0, %2}
> cmov%O2%c1\t{%3, %0|%0, %3}"
15970c16131
< (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0")
---
> (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
15975c16136,16137
< "TARGET_SSE && !TARGET_IEEE_FP"
---
> "TARGET_SSE && !TARGET_IEEE_FP
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16052c16214
< (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0")
---
> (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16057c16219,16220
< "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
---
> "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16133c16296
< (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0")
---
> (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
16138c16301,16302
< "TARGET_SSE && !TARGET_IEEE_FP"
---
> "TARGET_SSE && !TARGET_IEEE_FP
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16213c16377
< (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0")
---
> (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16218c16382,16383
< "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
---
> "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17950c18115
< "TARGET_SSE || TARGET_3DNOW_A"
---
> "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
17954a18120,18128
> (define_insn "mmx_maskmovq_rex"
> [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
> (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
> (match_operand:V8QI 2 "register_operand" "y")] 32))]
> "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
> ;; @@@ check ordering of operands in intel/nonintel syntax
> "maskmovq\t{%2, %1|%1, %2}"
> [(set_attr "type" "sse")])
>
18234c18408
< (and:TI (match_operand:TI 1 "register_operand" "%0")
---
> (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18236c18410,18411
< "TARGET_SSE && !TARGET_SSE2"
---
> "TARGET_SSE && !TARGET_SSE2
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18242c18417
< (and:TI (match_operand:TI 1 "register_operand" "%0")
---
> (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18244c18419,18420
< "TARGET_SSE2"
---
> "TARGET_SSE2
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18314c18490
< (ior:TI (match_operand:TI 1 "register_operand" "%0")
---
> (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18316c18492,18493
< "TARGET_SSE && !TARGET_SSE2"
---
> "TARGET_SSE && !TARGET_SSE2
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18322c18499
< (ior:TI (match_operand:TI 1 "register_operand" "%0")
---
> (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18324c18501,18502
< "TARGET_SSE2"
---
> "TARGET_SSE2
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18362c18540
< (xor:TI (match_operand:TI 1 "register_operand" "%0")
---
> (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18364c18542,18543
< "TARGET_SSE && !TARGET_SSE2"
---
> "TARGET_SSE && !TARGET_SSE2
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18370c18549
< (xor:TI (match_operand:TI 1 "register_operand" "%0")
---
> (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18372c18551,18552
< "TARGET_SSE2"
---
> "TARGET_SSE2
> && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18842,18849c19022,19029
< (vec_const:V8QI (parallel [(const_int 1)
< (const_int 1)
< (const_int 1)
< (const_int 1)
< (const_int 1)
< (const_int 1)
< (const_int 1)
< (const_int 1)])))
---
> (const_vector:V8QI [(const_int 1)
> (const_int 1)
> (const_int 1)
> (const_int 1)
> (const_int 1)
> (const_int 1)
> (const_int 1)
> (const_int 1)]))
18861,18864c19041,19044
< (vec_const:V4HI (parallel [(const_int 1)
< (const_int 1)
< (const_int 1)
< (const_int 1)])))
---
> (const_vector:V4HI [(const_int 1)
> (const_int 1)
> (const_int 1)
> (const_int 1)]))
19578,19583c19758,19762
< (vec_const:V4SI
< (parallel [(const_int 32768)
< (const_int 32768)
< (const_int 32768)
< (const_int 32768)])))
< (const_int 16))))]
---
> (const_vector:V4SI [(const_int 32768)
> (const_int 32768)
> (const_int 32768)
> (const_int 32768)]))
> (const_int 16))))]