1;; GCC machine description for IA-32 and x86-64.
2;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3;; Free Software Foundation, Inc.
4;; Mostly by William Schelter.
5;; x86_64 support added by Jan Hubicka
6;;
7;; This file is part of GNU CC.
8;;
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108;; "reload_completed && TARGET_64BIT".
109
110
111;; Processor type. This attribute must exactly match the processor_type
112;; enumeration in i386.h.
113(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
114 (const (symbol_ref "ix86_cpu")))
115
116;; $FreeBSD: head/contrib/gcc/config/i386/i386.md 90286 2002-02-06 05:02:18Z obrien $
117
118;; A basic instruction type. Refinements due to arguments to be
119;; provided in other attributes.
120(define_attr "type"
121 "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx,fistp"
122 (const_string "other"))
123
124;; Main data type used by the insn
--- 1605 unchanged lines hidden (view full) ---
1730{
1731 operands[1] = constm1_rtx;
1732 return "or{l}\t{%1, %0|%0, %1}";
1733}
1734 [(set_attr "type" "alu1")
1735 (set_attr "mode" "SI")
1736 (set_attr "length_immediate" "1")])
1737
1738(define_insn "*movsi_1"
1739 [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!rm,!*Y,!rm,!*Y")
1740 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,rm,*Y,*Y"))]
1741 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1742{
1743 switch (get_attr_type (insn))
1744 {
1745 case TYPE_SSE:
1746 if (get_attr_mode (insn) == TImode)
1747 return "movdqa\t{%1, %0|%0, %1}";
1748 return "movd\t{%1, %0|%0, %1}";
1749
1750 case TYPE_MMX:
1751 return "movd\t{%1, %0|%0, %1}";
1752
1753 case TYPE_LEA:
1754 return "lea{l}\t{%1, %0|%0, %1}";
1755
1756 default:
1757 if (flag_pic && SYMBOLIC_CONST (operands[1]))
1758 abort();
1759 return "mov{l}\t{%1, %0|%0, %1}";
1760 }
1761}
1762 [(set (attr "type")
1763 (cond [(eq_attr "alternative" "4,5")
1764 (const_string "mmx")
1765 (eq_attr "alternative" "6,7,8")
1766 (const_string "sse")
1767 (and (ne (symbol_ref "flag_pic") (const_int 0))
1768 (match_operand:SI 1 "symbolic_operand" ""))
1769 (const_string "lea")
1770 ]
1771 (const_string "imov")))
1772 (set_attr "modrm" "0,*,0,*,*,*,*,*,*")
1773 (set_attr "mode" "SI,SI,SI,SI,SI,SI,TI,SI,SI")])
1774
1775;; Stores and loads of ax to arbitary constant address.
1776;; We fake an second form of instruction to force reload to load address
1777;; into register when rax is not available
1778(define_insn "*movabssi_1_rex64"
1779 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1780 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1781 "TARGET_64BIT"
--- 56 unchanged lines hidden (view full) ---
1838(define_insn "*pushhi2_rex64"
1839 [(set (match_operand:HI 0 "push_operand" "=X")
1840 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1841 "TARGET_64BIT"
1842 "push{q}\t%q1"
1843 [(set_attr "type" "push")
1844 (set_attr "mode" "QI")])
1845
1846(define_insn "*movhi_1"
1847 [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m")
1848 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1849 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1850{
1851 switch (get_attr_type (insn))
1852 {
1853 case TYPE_IMOVX:
1854 /* movzwl is faster than movw on p2 due to partial word stalls,
1855 though not as fast as an aligned movl. */
--- 601 unchanged lines hidden (view full) ---
2457 operands[1] = constm1_rtx;
2458 return "or{q}\t{%1, %0|%0, %1}";
2459}
2460 [(set_attr "type" "alu1")
2461 (set_attr "mode" "DI")
2462 (set_attr "length_immediate" "1")])
2463
2464(define_insn "*movdi_2"
2465 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,*Y,!*Y")
2466 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
2467 "!TARGET_64BIT
2468 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2469 "@
2470 #
2471 #
2472 movq\t{%1, %0|%0, %1}
2473 movq\t{%1, %0|%0, %1}
--- 236 unchanged lines hidden (view full) ---
2710(define_split
2711 [(set (match_operand:SF 0 "push_operand" "")
2712 (match_operand:SF 1 "register_operand" ""))]
2713 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2714 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2715 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2716
2717(define_insn "*movsf_1"
2718 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m")
2719 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf"))]
2720 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2721 && (reload_in_progress || reload_completed
2722 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2723 || GET_CODE (operands[1]) != CONST_DOUBLE
2724 || memory_operand (operands[0], SFmode))"
2725{
2726 switch (which_alternative)
2727 {
--- 21 unchanged lines hidden (view full) ---
2749 return "fld1";
2750 }
2751 abort();
2752
2753 case 3:
2754 case 4:
2755 return "mov{l}\t{%1, %0|%0, %1}";
2756 case 5:
2757 return "pxor\t%0, %0";
2758 case 6:
2759 if (TARGET_PARTIAL_REG_DEPENDENCY)
2760 return "movaps\t{%1, %0|%0, %1}";
2761 else
2762 return "movss\t{%1, %0|%0, %1}";
2763 case 7:
2764 case 8:
2765 return "movss\t{%1, %0|%0, %1}";
2766
2767 default:
2768 abort();
2769 }
2770}
2771 [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse")
2772 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF")])
2773
2774(define_insn "*swapsf"
2775 [(set (match_operand:SF 0 "register_operand" "+f")
2776 (match_operand:SF 1 "register_operand" "+f"))
2777 (set (match_dup 1)
2778 (match_dup 0))]
2779 "reload_completed || !TARGET_SSE"
2780{
--- 2343 unchanged lines hidden (view full) ---
5124 #"
5125 [(set_attr "type" "fmov,multi")
5126 (set_attr "mode" "DF")
5127 (set_attr "fp_int_src" "true")])
5128
5129(define_expand "floatsidf2"
5130 [(set (match_operand:DF 0 "register_operand" "")
5131 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
5132 ""
5133 "")
5134
5135(define_insn "*floatsidf2_i387"
5136 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
5137 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
5138 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5139 "@
5140 fild%z1\t%1
--- 2186 unchanged lines hidden (view full) ---
7327 "@
7328 imul{w}\t{%2, %1, %0|%0, %1, %2}
7329 imul{w}\t{%2, %1, %0|%0, %1, %2}
7330 imul{w}\t{%2, %0|%0, %2}"
7331 [(set_attr "type" "imul")
7332 (set_attr "prefix_0f" "0,0,1")
7333 (set_attr "mode" "HI")])
7334
7335(define_insn "mulqi3"
7336 [(set (match_operand:QI 0 "register_operand" "=a")
7337 (mult:QI (match_operand:QI 1 "register_operand" "%0")
7338 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7339 (clobber (reg:CC 17))]
7340 "TARGET_QIMODE_MATH"
7341 "mul{b}\t%2"
7342 [(set_attr "type" "imul")
7343 (set_attr "length_immediate" "0")
7344 (set_attr "mode" "QI")])
7345
7346(define_insn "umulqihi3"
7347 [(set (match_operand:HI 0 "register_operand" "=a")
7348 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7349 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7350 (clobber (reg:CC 17))]
7351 "TARGET_QIMODE_MATH"
7352 "mul{b}\t%2"
7353 [(set_attr "type" "imul")
7354 (set_attr "length_immediate" "0")
7355 (set_attr "mode" "QI")])
7356
7357(define_insn "mulqihi3"
7358 [(set (match_operand:HI 0 "register_operand" "=a")
7359 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7360 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7361 (clobber (reg:CC 17))]
7362 "TARGET_QIMODE_MATH"
7363 "imul{b}\t%2"
7364 [(set_attr "type" "imul")
7365 (set_attr "length_immediate" "0")
7366 (set_attr "mode" "QI")])
7367
7368(define_insn "umulditi3"
7369 [(set (match_operand:TI 0 "register_operand" "=A")
7370 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7371 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7372 (clobber (reg:CC 17))]
7373 "TARGET_64BIT"
7374 "mul{q}\t%2"
7375 [(set_attr "type" "imul")
7376 (set_attr "ppro_uops" "few")
7377 (set_attr "length_immediate" "0")
7378 (set_attr "mode" "DI")])
7379
7380;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7381(define_insn "umulsidi3"
7382 [(set (match_operand:DI 0 "register_operand" "=A")
7383 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7384 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7385 (clobber (reg:CC 17))]
7386 "!TARGET_64BIT"
7387 "mul{l}\t%2"
7388 [(set_attr "type" "imul")
7389 (set_attr "ppro_uops" "few")
7390 (set_attr "length_immediate" "0")
7391 (set_attr "mode" "SI")])
7392
7393(define_insn "mulditi3"
7394 [(set (match_operand:TI 0 "register_operand" "=A")
7395 (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7396 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7397 (clobber (reg:CC 17))]
7398 "TARGET_64BIT"
7399 "imul{q}\t%2"
7400 [(set_attr "type" "imul")
7401 (set_attr "length_immediate" "0")
7402 (set_attr "mode" "DI")])
7403
7404(define_insn "mulsidi3"
7405 [(set (match_operand:DI 0 "register_operand" "=A")
7406 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7407 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7408 (clobber (reg:CC 17))]
7409 "!TARGET_64BIT"
7410 "imul{l}\t%2"
7411 [(set_attr "type" "imul")
7412 (set_attr "length_immediate" "0")
7413 (set_attr "mode" "SI")])
7414
7415(define_insn "*umuldi3_highpart_rex64"
7416 [(set (match_operand:DI 0 "register_operand" "=d")
7417 (truncate:DI
7418 (lshiftrt:TI
7419 (mult:TI (zero_extend:TI
7420 (match_operand:DI 1 "register_operand" "%a"))
7421 (zero_extend:TI
7422 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7423 (const_int 64))))
7424 (clobber (match_scratch:DI 3 "=a"))
7425 (clobber (reg:CC 17))]
7426 "TARGET_64BIT"
7427 "mul{q}\t%2"
7428 [(set_attr "type" "imul")
7429 (set_attr "ppro_uops" "few")
7430 (set_attr "length_immediate" "0")
7431 (set_attr "mode" "DI")])
7432
7433(define_insn "umulsi3_highpart"
7434 [(set (match_operand:SI 0 "register_operand" "=d")
7435 (truncate:SI
7436 (lshiftrt:DI
7437 (mult:DI (zero_extend:DI
7438 (match_operand:SI 1 "register_operand" "%a"))
7439 (zero_extend:DI
7440 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7441 (const_int 32))))
7442 (clobber (match_scratch:SI 3 "=a"))
7443 (clobber (reg:CC 17))]
7444 ""
7445 "mul{l}\t%2"
7446 [(set_attr "type" "imul")
7447 (set_attr "ppro_uops" "few")
7448 (set_attr "length_immediate" "0")
7449 (set_attr "mode" "SI")])
7450
7451(define_insn "*umulsi3_highpart_zext"
7452 [(set (match_operand:DI 0 "register_operand" "=d")
7453 (zero_extend:DI (truncate:SI
7454 (lshiftrt:DI
7455 (mult:DI (zero_extend:DI
7456 (match_operand:SI 1 "register_operand" "%a"))
7457 (zero_extend:DI
7458 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7459 (const_int 32)))))
7460 (clobber (match_scratch:SI 3 "=a"))
7461 (clobber (reg:CC 17))]
7462 "TARGET_64BIT"
7463 "mul{l}\t%2"
7464 [(set_attr "type" "imul")
7465 (set_attr "ppro_uops" "few")
7466 (set_attr "length_immediate" "0")
7467 (set_attr "mode" "SI")])
7468
7469(define_insn "*smuldi3_highpart_rex64"
7470 [(set (match_operand:DI 0 "register_operand" "=d")
7471 (truncate:DI
7472 (lshiftrt:TI
7473 (mult:TI (sign_extend:TI
7474 (match_operand:DI 1 "register_operand" "%a"))
7475 (sign_extend:TI
7476 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7477 (const_int 64))))
7478 (clobber (match_scratch:DI 3 "=a"))
7479 (clobber (reg:CC 17))]
7480 "TARGET_64BIT"
7481 "imul{q}\t%2"
7482 [(set_attr "type" "imul")
7483 (set_attr "ppro_uops" "few")
7484 (set_attr "mode" "DI")])
7485
7486(define_insn "smulsi3_highpart"
7487 [(set (match_operand:SI 0 "register_operand" "=d")
7488 (truncate:SI
7489 (lshiftrt:DI
7490 (mult:DI (sign_extend:DI
7491 (match_operand:SI 1 "register_operand" "%a"))
7492 (sign_extend:DI
7493 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7494 (const_int 32))))
7495 (clobber (match_scratch:SI 3 "=a"))
7496 (clobber (reg:CC 17))]
7497 ""
7498 "imul{l}\t%2"
7499 [(set_attr "type" "imul")
7500 (set_attr "ppro_uops" "few")
7501 (set_attr "mode" "SI")])
7502
7503(define_insn "*smulsi3_highpart_zext"
7504 [(set (match_operand:DI 0 "register_operand" "=d")
7505 (zero_extend:DI (truncate:SI
7506 (lshiftrt:DI
7507 (mult:DI (sign_extend:DI
7508 (match_operand:SI 1 "register_operand" "%a"))
7509 (sign_extend:DI
7510 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7511 (const_int 32)))))
7512 (clobber (match_scratch:SI 3 "=a"))
7513 (clobber (reg:CC 17))]
7514 "TARGET_64BIT"
7515 "imul{l}\t%2"
7516 [(set_attr "type" "imul")
7517 (set_attr "ppro_uops" "few")
7518 (set_attr "mode" "SI")])
7519
7520;; The patterns that match these are at the end of this file.
7521
7522(define_expand "mulxf3"
--- 6013 unchanged lines hidden (view full) ---
13536{
13537 int i;
13538
13539 /* In order to give reg-stack an easier job in validating two
13540 coprocessor registers as containing a possible return value,
13541 simply pretend the untyped call returns a complex long double
13542 value. */
13543
13544 emit_call_insn (TARGET_80387
13545 ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG),
13546 operands[0], const0_rtx,
13547 GEN_INT (SSE_REGPARM_MAX - 1))
13548 : gen_call (operands[0], const0_rtx,
13549 GEN_INT (SSE_REGPARM_MAX - 1)));
13550
13551 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13552 {
--- 298 unchanged lines hidden (view full) ---
13851;; SImode if the target mode DFmode, but only SImode if the target mode
13852;; is SFmode.
13853
13854;; Gcc is slightly more smart about handling normal two address instructions
13855;; so use special patterns for add and mull.
13856(define_insn "*fop_sf_comm_nosse"
13857 [(set (match_operand:SF 0 "register_operand" "=f")
13858 (match_operator:SF 3 "binary_fp_operator"
13859 [(match_operand:SF 1 "register_operand" "%0")
13860 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
13861 "TARGET_80387 && !TARGET_SSE_MATH
13862 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13863 "* return output_387_binary_op (insn, operands);"
13864 [(set (attr "type")
13865 (if_then_else (match_operand:SF 3 "mult_operator" "")
13866 (const_string "fmul")
13867 (const_string "fop")))
13868 (set_attr "mode" "SF")])
13869
13870(define_insn "*fop_sf_comm"
13871 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
13872 (match_operator:SF 3 "binary_fp_operator"
13873 [(match_operand:SF 1 "register_operand" "%0,0")
13874 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
13875 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
13876 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13877 "* return output_387_binary_op (insn, operands);"
13878 [(set (attr "type")
13879 (if_then_else (eq_attr "alternative" "1")
13880 (const_string "sse")
13881 (if_then_else (match_operand:SF 3 "mult_operator" "")
13882 (const_string "fmul")
13883 (const_string "fop"))))
13884 (set_attr "mode" "SF")])
13885
13886(define_insn "*fop_sf_comm_sse"
13887 [(set (match_operand:SF 0 "register_operand" "=x")
13888 (match_operator:SF 3 "binary_fp_operator"
13889 [(match_operand:SF 1 "register_operand" "%0")
13890 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13891 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13892 "* return output_387_binary_op (insn, operands);"
13893 [(set_attr "type" "sse")
13894 (set_attr "mode" "SF")])
13895
13896(define_insn "*fop_df_comm_nosse"
13897 [(set (match_operand:DF 0 "register_operand" "=f")
13898 (match_operator:DF 3 "binary_fp_operator"
13899 [(match_operand:DF 1 "register_operand" "%0")
13900 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
13901 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
13902 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13903 "* return output_387_binary_op (insn, operands);"
13904 [(set (attr "type")
13905 (if_then_else (match_operand:SF 3 "mult_operator" "")
13906 (const_string "fmul")
13907 (const_string "fop")))
13908 (set_attr "mode" "DF")])
13909
13910(define_insn "*fop_df_comm"
13911 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
13912 (match_operator:DF 3 "binary_fp_operator"
13913 [(match_operand:DF 1 "register_operand" "%0,0")
13914 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
13915 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
13916 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13917 "* return output_387_binary_op (insn, operands);"
13918 [(set (attr "type")
13919 (if_then_else (eq_attr "alternative" "1")
13920 (const_string "sse")
13921 (if_then_else (match_operand:SF 3 "mult_operator" "")
13922 (const_string "fmul")
13923 (const_string "fop"))))
13924 (set_attr "mode" "DF")])
13925
13926(define_insn "*fop_df_comm_sse"
13927 [(set (match_operand:DF 0 "register_operand" "=Y")
13928 (match_operator:DF 3 "binary_fp_operator"
13929 [(match_operand:DF 1 "register_operand" "%0")
13930 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13931 "TARGET_SSE2 && TARGET_SSE_MATH
13932 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13933 "* return output_387_binary_op (insn, operands);"
13934 [(set_attr "type" "sse")
13935 (set_attr "mode" "DF")])
13936
13937(define_insn "*fop_xf_comm"
13938 [(set (match_operand:XF 0 "register_operand" "=f")
13939 (match_operator:XF 3 "binary_fp_operator"
13940 [(match_operand:XF 1 "register_operand" "%0")
--- 617 unchanged lines hidden (view full) ---
14558 [(set_attr "type" "fpspc")
14559 (set_attr "mode" "XF")
14560 (set_attr "athlon_decode" "direct")])
14561
14562(define_insn "*sqrtextenddfxf2"
14563 [(set (match_operand:XF 0 "register_operand" "=f")
14564 (sqrt:XF (float_extend:XF
14565 (match_operand:DF 1 "register_operand" "0"))))]
14566 "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387"
14567 "fsqrt"
14568 [(set_attr "type" "fpspc")
14569 (set_attr "mode" "XF")
14570 (set_attr "athlon_decode" "direct")])
14571
14572(define_insn "*sqrtextenddftf2"
14573 [(set (match_operand:TF 0 "register_operand" "=f")
14574 (sqrt:TF (float_extend:TF
14575 (match_operand:DF 1 "register_operand" "0"))))]
14576 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14577 "fsqrt"
14578 [(set_attr "type" "fpspc")
14579 (set_attr "mode" "XF")
14580 (set_attr "athlon_decode" "direct")])
14581
14582(define_insn "*sqrtextendsfxf2"
14583 [(set (match_operand:XF 0 "register_operand" "=f")
14584 (sqrt:XF (float_extend:XF
14585 (match_operand:SF 1 "register_operand" "0"))))]
14586 "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387"
14587 "fsqrt"
14588 [(set_attr "type" "fpspc")
14589 (set_attr "mode" "XF")
14590 (set_attr "athlon_decode" "direct")])
14591
14592(define_insn "*sqrtextendsftf2"
14593 [(set (match_operand:TF 0 "register_operand" "=f")
14594 (sqrt:TF (float_extend:TF
--- 30 unchanged lines hidden (view full) ---
14625 && flag_unsafe_math_optimizations"
14626 "fsin"
14627 [(set_attr "type" "fpspc")
14628 (set_attr "mode" "DF")])
14629
14630(define_insn "sinxf2"
14631 [(set (match_operand:XF 0 "register_operand" "=f")
14632 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
14633 "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387
14634 && flag_unsafe_math_optimizations"
14635 "fsin"
14636 [(set_attr "type" "fpspc")
14637 (set_attr "mode" "XF")])
14638
14639(define_insn "sintf2"
14640 [(set (match_operand:TF 0 "register_operand" "=f")
14641 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))]
--- 1103 unchanged lines hidden (view full) ---
15745 [(set (match_operand:DI 0 "register_operand" "=r,r")
15746 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
15747 [(reg 17) (const_int 0)])
15748 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
15749 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
15750 "TARGET_64BIT && TARGET_CMOVE
15751 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15752 "@
15753 cmov%C1\t{%2, %0|%0, %2}
15754 cmov%c1\t{%3, %0|%0, %3}"
15755 [(set_attr "type" "icmov")
15756 (set_attr "mode" "DI")])
15757
15758(define_expand "movsicc"
15759 [(set (match_operand:SI 0 "register_operand" "")
15760 (if_then_else:SI (match_operand 1 "comparison_operator" "")
15761 (match_operand:SI 2 "general_operand" "")
15762 (match_operand:SI 3 "general_operand" "")))]
--- 24 unchanged lines hidden (view full) ---
15787 [(set (match_operand:SI 0 "register_operand" "=r,r")
15788 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
15789 [(reg 17) (const_int 0)])
15790 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
15791 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
15792 "TARGET_CMOVE
15793 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15794 "@
15795 cmov%C1\t{%2, %0|%0, %2}
15796 cmov%c1\t{%3, %0|%0, %3}"
15797 [(set_attr "type" "icmov")
15798 (set_attr "mode" "SI")])
15799
15800(define_expand "movhicc"
15801 [(set (match_operand:HI 0 "register_operand" "")
15802 (if_then_else:HI (match_operand 1 "comparison_operator" "")
15803 (match_operand:HI 2 "nonimmediate_operand" "")
15804 (match_operand:HI 3 "nonimmediate_operand" "")))]
--- 4 unchanged lines hidden (view full) ---
15809 [(set (match_operand:HI 0 "register_operand" "=r,r")
15810 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
15811 [(reg 17) (const_int 0)])
15812 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
15813 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
15814 "TARGET_CMOVE
15815 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15816 "@
15817 cmov%C1\t{%2, %0|%0, %2}
15818 cmov%c1\t{%3, %0|%0, %3}"
15819 [(set_attr "type" "icmov")
15820 (set_attr "mode" "HI")])
15821
15822(define_expand "movsfcc"
15823 [(set (match_operand:SF 0 "register_operand" "")
15824 (if_then_else:SF (match_operand 1 "comparison_operator" "")
15825 (match_operand:SF 2 "register_operand" "")
15826 (match_operand:SF 3 "register_operand" "")))]
--- 6 unchanged lines hidden (view full) ---
15833 [(reg 17) (const_int 0)])
15834 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
15835 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
15836 "TARGET_CMOVE
15837 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15838 "@
15839 fcmov%F1\t{%2, %0|%0, %2}
15840 fcmov%f1\t{%3, %0|%0, %3}
15841 cmov%C1\t{%2, %0|%0, %2}
15842 cmov%c1\t{%3, %0|%0, %3}"
15843 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15844 (set_attr "mode" "SF,SF,SI,SI")])
15845
15846(define_expand "movdfcc"
15847 [(set (match_operand:DF 0 "register_operand" "")
15848 (if_then_else:DF (match_operand 1 "comparison_operator" "")
15849 (match_operand:DF 2 "register_operand" "")
15850 (match_operand:DF 3 "register_operand" "")))]
--- 22 unchanged lines hidden (view full) ---
15873 [(reg 17) (const_int 0)])
15874 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15875 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15876 "TARGET_64BIT && TARGET_CMOVE
15877 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15878 "@
15879 fcmov%F1\t{%2, %0|%0, %2}
15880 fcmov%f1\t{%3, %0|%0, %3}
15881 cmov%C1\t{%2, %0|%0, %2}
15882 cmov%c1\t{%3, %0|%0, %3}"
15883 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15884 (set_attr "mode" "DF")])
15885
15886(define_split
15887 [(set (match_operand:DF 0 "register_operand" "")
15888 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15889 [(match_operand 4 "" "") (const_int 0)])
15890 (match_operand:DF 2 "nonimmediate_operand" "")
--- 71 unchanged lines hidden (view full) ---
15962 (match_dup 1)
15963 (match_dup 2)))
15964 (clobber (reg:CC 17))]
15965 "TARGET_SSE && TARGET_IEEE_FP"
15966 "#")
15967
15968(define_insn "*minsf_nonieee"
15969 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
15970 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0")
15971 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
15972 (match_dup 1)
15973 (match_dup 2)))
15974 (clobber (reg:CC 17))]
15975 "TARGET_SSE && !TARGET_IEEE_FP"
15976 "#")
15977
15978(define_split
15979 [(set (match_operand:SF 0 "register_operand" "")
15980 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15981 (match_operand:SF 2 "nonimmediate_operand" ""))
15982 (match_operand:SF 3 "register_operand" "")
15983 (match_operand:SF 4 "nonimmediate_operand" "")))
--- 60 unchanged lines hidden (view full) ---
16044 (match_dup 1)
16045 (match_dup 2)))
16046 (clobber (reg:CC 17))]
16047 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
16048 "#")
16049
16050(define_insn "*mindf_nonieee"
16051 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16052 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0")
16053 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16054 (match_dup 1)
16055 (match_dup 2)))
16056 (clobber (reg:CC 17))]
16057 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
16058 "#")
16059
16060(define_split
16061 [(set (match_operand:DF 0 "register_operand" "")
16062 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16063 (match_operand:DF 2 "nonimmediate_operand" ""))
16064 (match_operand:DF 3 "register_operand" "")
16065 (match_operand:DF 4 "nonimmediate_operand" "")))
--- 59 unchanged lines hidden (view full) ---
16125 (match_dup 1)
16126 (match_dup 2)))
16127 (clobber (reg:CC 17))]
16128 "TARGET_SSE && TARGET_IEEE_FP"
16129 "#")
16130
16131(define_insn "*maxsf_nonieee"
16132 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16133 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0")
16134 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16135 (match_dup 1)
16136 (match_dup 2)))
16137 (clobber (reg:CC 17))]
16138 "TARGET_SSE && !TARGET_IEEE_FP"
16139 "#")
16140
16141(define_split
16142 [(set (match_operand:SF 0 "register_operand" "")
16143 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16144 (match_operand:SF 2 "nonimmediate_operand" ""))
16145 (match_operand:SF 3 "register_operand" "")
16146 (match_operand:SF 4 "nonimmediate_operand" "")))
--- 58 unchanged lines hidden (view full) ---
16205 (match_dup 1)
16206 (match_dup 2)))
16207 (clobber (reg:CC 17))]
16208 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
16209 "#")
16210
16211(define_insn "*maxdf_nonieee"
16212 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16213 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0")
16214 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16215 (match_dup 1)
16216 (match_dup 2)))
16217 (clobber (reg:CC 17))]
16218 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
16219 "#")
16220
16221(define_split
16222 [(set (match_operand:DF 0 "register_operand" "")
16223 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16224 (match_operand:DF 2 "nonimmediate_operand" ""))
16225 (match_operand:DF 3 "register_operand" "")
16226 (match_operand:DF 4 "nonimmediate_operand" "")))
--- 1715 unchanged lines hidden (view full) ---
17942 "TARGET_SSE || TARGET_3DNOW_A"
17943 "pmovmskb\t{%1, %0|%0, %1}"
17944 [(set_attr "type" "sse")])
17945
17946(define_insn "mmx_maskmovq"
17947 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
17948 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
17949 (match_operand:V8QI 2 "register_operand" "y")] 32))]
17950 "TARGET_SSE || TARGET_3DNOW_A"
17951 ;; @@@ check ordering of operands in intel/nonintel syntax
17952 "maskmovq\t{%2, %1|%1, %2}"
17953 [(set_attr "type" "sse")])
17954
17955(define_insn "sse_movntv4sf"
17956 [(set (match_operand:V4SF 0 "memory_operand" "=m")
17957 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
17958 "TARGET_SSE"
17959 "movntps\t{%1, %0|%0, %1}"
17960 [(set_attr "type" "sse")])
17961
17962(define_insn "sse_movntdi"
--- 263 unchanged lines hidden (view full) ---
18226 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18227 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18228 "TARGET_SSE"
18229 "andps\t{%2, %0|%0, %2}"
18230 [(set_attr "type" "sse")])
18231
18232(define_insn "sse_andti3"
18233 [(set (match_operand:TI 0 "register_operand" "=x")
18234 (and:TI (match_operand:TI 1 "register_operand" "%0")
18235 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18236 "TARGET_SSE && !TARGET_SSE2"
18237 "andps\t{%2, %0|%0, %2}"
18238 [(set_attr "type" "sse")])
18239
18240(define_insn "*sse_andti3_sse2"
18241 [(set (match_operand:TI 0 "register_operand" "=x")
18242 (and:TI (match_operand:TI 1 "register_operand" "%0")
18243 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18244 "TARGET_SSE2"
18245 "pand\t{%2, %0|%0, %2}"
18246 [(set_attr "type" "sse")])
18247
18248(define_insn "*sse_nandti3_df"
18249 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18250 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
18251 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18252 "TARGET_SSE2"
--- 53 unchanged lines hidden (view full) ---
18306 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18307 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18308 "TARGET_SSE"
18309 "orps\t{%2, %0|%0, %2}"
18310 [(set_attr "type" "sse")])
18311
18312(define_insn "sse_iorti3"
18313 [(set (match_operand:TI 0 "register_operand" "=x")
18314 (ior:TI (match_operand:TI 1 "register_operand" "%0")
18315 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18316 "TARGET_SSE && !TARGET_SSE2"
18317 "orps\t{%2, %0|%0, %2}"
18318 [(set_attr "type" "sse")])
18319
18320(define_insn "*sse_iorti3_sse2"
18321 [(set (match_operand:TI 0 "register_operand" "=x")
18322 (ior:TI (match_operand:TI 1 "register_operand" "%0")
18323 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18324 "TARGET_SSE2"
18325 "por\t{%2, %0|%0, %2}"
18326 [(set_attr "type" "sse")])
18327
18328(define_insn "*sse_xorti3_df_1"
18329 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18330 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18331 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18332 "TARGET_SSE2"
--- 21 unchanged lines hidden (view full) ---
18354 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18355 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18356 "TARGET_SSE"
18357 "xorps\t{%2, %0|%0, %2}"
18358 [(set_attr "type" "sse")])
18359
18360(define_insn "sse_xorti3"
18361 [(set (match_operand:TI 0 "register_operand" "=x")
18362 (xor:TI (match_operand:TI 1 "register_operand" "%0")
18363 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18364 "TARGET_SSE && !TARGET_SSE2"
18365 "xorps\t{%2, %0|%0, %2}"
18366 [(set_attr "type" "sse")])
18367
18368(define_insn "*sse_xorti3_sse2"
18369 [(set (match_operand:TI 0 "register_operand" "=x")
18370 (xor:TI (match_operand:TI 1 "register_operand" "%0")
18371 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18372 "TARGET_SSE2"
18373 "pxor\t{%2, %0|%0, %2}"
18374 [(set_attr "type" "sse")])
18375
18376;; Use xor, but don't show input operands so they aren't live before
18377;; this insn.
18378(define_insn "sse_clrv4sf"
18379 [(set (match_operand:V4SF 0 "register_operand" "=x")
18380 (unspec:V4SF [(const_int 0)] 45))]
--- 453 unchanged lines hidden (view full) ---
18834;; MMX unsigned averages/sum of absolute differences
18835
18836(define_insn "mmx_uavgv8qi3"
18837 [(set (match_operand:V8QI 0 "register_operand" "=y")
18838 (ashiftrt:V8QI
18839 (plus:V8QI (plus:V8QI
18840 (match_operand:V8QI 1 "register_operand" "0")
18841 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
18842 (vec_const:V8QI (parallel [(const_int 1)
18843 (const_int 1)
18844 (const_int 1)
18845 (const_int 1)
18846 (const_int 1)
18847 (const_int 1)
18848 (const_int 1)
18849 (const_int 1)])))
18850 (const_int 1)))]
18851 "TARGET_SSE || TARGET_3DNOW_A"
18852 "pavgb\t{%2, %0|%0, %2}"
18853 [(set_attr "type" "sse")])
18854
18855(define_insn "mmx_uavgv4hi3"
18856 [(set (match_operand:V4HI 0 "register_operand" "=y")
18857 (ashiftrt:V4HI
18858 (plus:V4HI (plus:V4HI
18859 (match_operand:V4HI 1 "register_operand" "0")
18860 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
18861 (vec_const:V4HI (parallel [(const_int 1)
18862 (const_int 1)
18863 (const_int 1)
18864 (const_int 1)])))
18865 (const_int 1)))]
18866 "TARGET_SSE || TARGET_3DNOW_A"
18867 "pavgw\t{%2, %0|%0, %2}"
18868 [(set_attr "type" "sse")])
18869
18870(define_insn "mmx_psadbw"
18871 [(set (match_operand:V8QI 0 "register_operand" "=y")
18872 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
--- 697 unchanged lines hidden (view full) ---
19570 (truncate:V4HI
19571 (lshiftrt:V4SI
19572 (plus:V4SI
19573 (mult:V4SI
19574 (sign_extend:V4SI
19575 (match_operand:V4HI 1 "register_operand" "0"))
19576 (sign_extend:V4SI
19577 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
19578 (vec_const:V4SI
19579 (parallel [(const_int 32768)
19580 (const_int 32768)
19581 (const_int 32768)
19582 (const_int 32768)])))
19583 (const_int 16))))]
19584 "TARGET_3DNOW"
19585 "pmulhrw\\t{%2, %0|%0, %2}"
19586 [(set_attr "type" "mmx")])
19587
19588(define_insn "pswapdv2si2"
19589 [(set (match_operand:V2SI 0 "register_operand" "=y")
19590 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
19591 (parallel [(const_int 1) (const_int 0)])))]
--- 66 unchanged lines hidden ---
2;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3;; Free Software Foundation, Inc.
4;; Mostly by William Schelter.
5;; x86_64 support added by Jan Hubicka
6;;
7;; This file is part of GNU CC.
8;;
--- 99 unchanged lines hidden (view full) ---
108;; "reload_completed && TARGET_64BIT".
109
110
111;; Processor type. This attribute must exactly match the processor_type
112;; enumeration in i386.h.
113(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
114 (const (symbol_ref "ix86_cpu")))
115
116;; $FreeBSD: head/contrib/gcc/config/i386/i386.md 90286 2002-02-06 05:02:18Z obrien $
117
118;; A basic instruction type. Refinements due to arguments to be
119;; provided in other attributes.
120(define_attr "type"
121 "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx,fistp"
122 (const_string "other"))
123
124;; Main data type used by the insn
--- 1605 unchanged lines hidden (view full) ---
1730{
1731 operands[1] = constm1_rtx;
1732 return "or{l}\t{%1, %0|%0, %1}";
1733}
1734 [(set_attr "type" "alu1")
1735 (set_attr "mode" "SI")
1736 (set_attr "length_immediate" "1")])
1737
1738(define_insn "*movsi_1"
1739 [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!rm,!*Y,!rm,!*Y")
1740 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,rm,*Y,*Y"))]
1741 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1742{
1743 switch (get_attr_type (insn))
1744 {
1745 case TYPE_SSE:
1746 if (get_attr_mode (insn) == TImode)
1747 return "movdqa\t{%1, %0|%0, %1}";
1748 return "movd\t{%1, %0|%0, %1}";
1749
1750 case TYPE_MMX:
1751 return "movd\t{%1, %0|%0, %1}";
1752
1753 case TYPE_LEA:
1754 return "lea{l}\t{%1, %0|%0, %1}";
1755
1756 default:
1757 if (flag_pic && SYMBOLIC_CONST (operands[1]))
1758 abort();
1759 return "mov{l}\t{%1, %0|%0, %1}";
1760 }
1761}
1762 [(set (attr "type")
1763 (cond [(eq_attr "alternative" "4,5")
1764 (const_string "mmx")
1765 (eq_attr "alternative" "6,7,8")
1766 (const_string "sse")
1767 (and (ne (symbol_ref "flag_pic") (const_int 0))
1768 (match_operand:SI 1 "symbolic_operand" ""))
1769 (const_string "lea")
1770 ]
1771 (const_string "imov")))
1772 (set_attr "modrm" "0,*,0,*,*,*,*,*,*")
1773 (set_attr "mode" "SI,SI,SI,SI,SI,SI,TI,SI,SI")])
1774
1775;; Stores and loads of ax to arbitary constant address.
1776;; We fake an second form of instruction to force reload to load address
1777;; into register when rax is not available
1778(define_insn "*movabssi_1_rex64"
1779 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1780 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1781 "TARGET_64BIT"
--- 56 unchanged lines hidden (view full) ---
1838(define_insn "*pushhi2_rex64"
1839 [(set (match_operand:HI 0 "push_operand" "=X")
1840 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1841 "TARGET_64BIT"
1842 "push{q}\t%q1"
1843 [(set_attr "type" "push")
1844 (set_attr "mode" "QI")])
1845
1846(define_insn "*movhi_1"
1847 [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m")
1848 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1849 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1850{
1851 switch (get_attr_type (insn))
1852 {
1853 case TYPE_IMOVX:
1854 /* movzwl is faster than movw on p2 due to partial word stalls,
1855 though not as fast as an aligned movl. */
--- 601 unchanged lines hidden (view full) ---
2457 operands[1] = constm1_rtx;
2458 return "or{q}\t{%1, %0|%0, %1}";
2459}
2460 [(set_attr "type" "alu1")
2461 (set_attr "mode" "DI")
2462 (set_attr "length_immediate" "1")])
2463
2464(define_insn "*movdi_2"
2465 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,*Y,!*Y")
2466 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
2467 "!TARGET_64BIT
2468 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2469 "@
2470 #
2471 #
2472 movq\t{%1, %0|%0, %1}
2473 movq\t{%1, %0|%0, %1}
--- 236 unchanged lines hidden (view full) ---
2710(define_split
2711 [(set (match_operand:SF 0 "push_operand" "")
2712 (match_operand:SF 1 "register_operand" ""))]
2713 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2714 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2715 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2716
2717(define_insn "*movsf_1"
2718 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m")
2719 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf"))]
2720 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2721 && (reload_in_progress || reload_completed
2722 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2723 || GET_CODE (operands[1]) != CONST_DOUBLE
2724 || memory_operand (operands[0], SFmode))"
2725{
2726 switch (which_alternative)
2727 {
--- 21 unchanged lines hidden (view full) ---
2749 return "fld1";
2750 }
2751 abort();
2752
2753 case 3:
2754 case 4:
2755 return "mov{l}\t{%1, %0|%0, %1}";
2756 case 5:
2757 return "pxor\t%0, %0";
2758 case 6:
2759 if (TARGET_PARTIAL_REG_DEPENDENCY)
2760 return "movaps\t{%1, %0|%0, %1}";
2761 else
2762 return "movss\t{%1, %0|%0, %1}";
2763 case 7:
2764 case 8:
2765 return "movss\t{%1, %0|%0, %1}";
2766
2767 default:
2768 abort();
2769 }
2770}
2771 [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse")
2772 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF")])
2773
2774(define_insn "*swapsf"
2775 [(set (match_operand:SF 0 "register_operand" "+f")
2776 (match_operand:SF 1 "register_operand" "+f"))
2777 (set (match_dup 1)
2778 (match_dup 0))]
2779 "reload_completed || !TARGET_SSE"
2780{
--- 2343 unchanged lines hidden (view full) ---
5124 #"
5125 [(set_attr "type" "fmov,multi")
5126 (set_attr "mode" "DF")
5127 (set_attr "fp_int_src" "true")])
5128
5129(define_expand "floatsidf2"
5130 [(set (match_operand:DF 0 "register_operand" "")
5131 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
5132 ""
5133 "")
5134
5135(define_insn "*floatsidf2_i387"
5136 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
5137 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
5138 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5139 "@
5140 fild%z1\t%1
--- 2186 unchanged lines hidden (view full) ---
7327 "@
7328 imul{w}\t{%2, %1, %0|%0, %1, %2}
7329 imul{w}\t{%2, %1, %0|%0, %1, %2}
7330 imul{w}\t{%2, %0|%0, %2}"
7331 [(set_attr "type" "imul")
7332 (set_attr "prefix_0f" "0,0,1")
7333 (set_attr "mode" "HI")])
7334
7335(define_insn "mulqi3"
7336 [(set (match_operand:QI 0 "register_operand" "=a")
7337 (mult:QI (match_operand:QI 1 "register_operand" "%0")
7338 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7339 (clobber (reg:CC 17))]
7340 "TARGET_QIMODE_MATH"
7341 "mul{b}\t%2"
7342 [(set_attr "type" "imul")
7343 (set_attr "length_immediate" "0")
7344 (set_attr "mode" "QI")])
7345
7346(define_insn "umulqihi3"
7347 [(set (match_operand:HI 0 "register_operand" "=a")
7348 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7349 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7350 (clobber (reg:CC 17))]
7351 "TARGET_QIMODE_MATH"
7352 "mul{b}\t%2"
7353 [(set_attr "type" "imul")
7354 (set_attr "length_immediate" "0")
7355 (set_attr "mode" "QI")])
7356
7357(define_insn "mulqihi3"
7358 [(set (match_operand:HI 0 "register_operand" "=a")
7359 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7360 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7361 (clobber (reg:CC 17))]
7362 "TARGET_QIMODE_MATH"
7363 "imul{b}\t%2"
7364 [(set_attr "type" "imul")
7365 (set_attr "length_immediate" "0")
7366 (set_attr "mode" "QI")])
7367
7368(define_insn "umulditi3"
7369 [(set (match_operand:TI 0 "register_operand" "=A")
7370 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7371 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7372 (clobber (reg:CC 17))]
7373 "TARGET_64BIT"
7374 "mul{q}\t%2"
7375 [(set_attr "type" "imul")
7376 (set_attr "ppro_uops" "few")
7377 (set_attr "length_immediate" "0")
7378 (set_attr "mode" "DI")])
7379
7380;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7381(define_insn "umulsidi3"
7382 [(set (match_operand:DI 0 "register_operand" "=A")
7383 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7384 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7385 (clobber (reg:CC 17))]
7386 "!TARGET_64BIT"
7387 "mul{l}\t%2"
7388 [(set_attr "type" "imul")
7389 (set_attr "ppro_uops" "few")
7390 (set_attr "length_immediate" "0")
7391 (set_attr "mode" "SI")])
7392
7393(define_insn "mulditi3"
7394 [(set (match_operand:TI 0 "register_operand" "=A")
7395 (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7396 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7397 (clobber (reg:CC 17))]
7398 "TARGET_64BIT"
7399 "imul{q}\t%2"
7400 [(set_attr "type" "imul")
7401 (set_attr "length_immediate" "0")
7402 (set_attr "mode" "DI")])
7403
7404(define_insn "mulsidi3"
7405 [(set (match_operand:DI 0 "register_operand" "=A")
7406 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7407 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7408 (clobber (reg:CC 17))]
7409 "!TARGET_64BIT"
7410 "imul{l}\t%2"
7411 [(set_attr "type" "imul")
7412 (set_attr "length_immediate" "0")
7413 (set_attr "mode" "SI")])
7414
7415(define_insn "*umuldi3_highpart_rex64"
7416 [(set (match_operand:DI 0 "register_operand" "=d")
7417 (truncate:DI
7418 (lshiftrt:TI
7419 (mult:TI (zero_extend:TI
7420 (match_operand:DI 1 "register_operand" "%a"))
7421 (zero_extend:TI
7422 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7423 (const_int 64))))
7424 (clobber (match_scratch:DI 3 "=a"))
7425 (clobber (reg:CC 17))]
7426 "TARGET_64BIT"
7427 "mul{q}\t%2"
7428 [(set_attr "type" "imul")
7429 (set_attr "ppro_uops" "few")
7430 (set_attr "length_immediate" "0")
7431 (set_attr "mode" "DI")])
7432
7433(define_insn "umulsi3_highpart"
7434 [(set (match_operand:SI 0 "register_operand" "=d")
7435 (truncate:SI
7436 (lshiftrt:DI
7437 (mult:DI (zero_extend:DI
7438 (match_operand:SI 1 "register_operand" "%a"))
7439 (zero_extend:DI
7440 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7441 (const_int 32))))
7442 (clobber (match_scratch:SI 3 "=a"))
7443 (clobber (reg:CC 17))]
7444 ""
7445 "mul{l}\t%2"
7446 [(set_attr "type" "imul")
7447 (set_attr "ppro_uops" "few")
7448 (set_attr "length_immediate" "0")
7449 (set_attr "mode" "SI")])
7450
7451(define_insn "*umulsi3_highpart_zext"
7452 [(set (match_operand:DI 0 "register_operand" "=d")
7453 (zero_extend:DI (truncate:SI
7454 (lshiftrt:DI
7455 (mult:DI (zero_extend:DI
7456 (match_operand:SI 1 "register_operand" "%a"))
7457 (zero_extend:DI
7458 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7459 (const_int 32)))))
7460 (clobber (match_scratch:SI 3 "=a"))
7461 (clobber (reg:CC 17))]
7462 "TARGET_64BIT"
7463 "mul{l}\t%2"
7464 [(set_attr "type" "imul")
7465 (set_attr "ppro_uops" "few")
7466 (set_attr "length_immediate" "0")
7467 (set_attr "mode" "SI")])
7468
7469(define_insn "*smuldi3_highpart_rex64"
7470 [(set (match_operand:DI 0 "register_operand" "=d")
7471 (truncate:DI
7472 (lshiftrt:TI
7473 (mult:TI (sign_extend:TI
7474 (match_operand:DI 1 "register_operand" "%a"))
7475 (sign_extend:TI
7476 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7477 (const_int 64))))
7478 (clobber (match_scratch:DI 3 "=a"))
7479 (clobber (reg:CC 17))]
7480 "TARGET_64BIT"
7481 "imul{q}\t%2"
7482 [(set_attr "type" "imul")
7483 (set_attr "ppro_uops" "few")
7484 (set_attr "mode" "DI")])
7485
7486(define_insn "smulsi3_highpart"
7487 [(set (match_operand:SI 0 "register_operand" "=d")
7488 (truncate:SI
7489 (lshiftrt:DI
7490 (mult:DI (sign_extend:DI
7491 (match_operand:SI 1 "register_operand" "%a"))
7492 (sign_extend:DI
7493 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7494 (const_int 32))))
7495 (clobber (match_scratch:SI 3 "=a"))
7496 (clobber (reg:CC 17))]
7497 ""
7498 "imul{l}\t%2"
7499 [(set_attr "type" "imul")
7500 (set_attr "ppro_uops" "few")
7501 (set_attr "mode" "SI")])
7502
7503(define_insn "*smulsi3_highpart_zext"
7504 [(set (match_operand:DI 0 "register_operand" "=d")
7505 (zero_extend:DI (truncate:SI
7506 (lshiftrt:DI
7507 (mult:DI (sign_extend:DI
7508 (match_operand:SI 1 "register_operand" "%a"))
7509 (sign_extend:DI
7510 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7511 (const_int 32)))))
7512 (clobber (match_scratch:SI 3 "=a"))
7513 (clobber (reg:CC 17))]
7514 "TARGET_64BIT"
7515 "imul{l}\t%2"
7516 [(set_attr "type" "imul")
7517 (set_attr "ppro_uops" "few")
7518 (set_attr "mode" "SI")])
7519
7520;; The patterns that match these are at the end of this file.
7521
7522(define_expand "mulxf3"
--- 6013 unchanged lines hidden (view full) ---
13536{
13537 int i;
13538
13539 /* In order to give reg-stack an easier job in validating two
13540 coprocessor registers as containing a possible return value,
13541 simply pretend the untyped call returns a complex long double
13542 value. */
13543
13544 emit_call_insn (TARGET_80387
13545 ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG),
13546 operands[0], const0_rtx,
13547 GEN_INT (SSE_REGPARM_MAX - 1))
13548 : gen_call (operands[0], const0_rtx,
13549 GEN_INT (SSE_REGPARM_MAX - 1)));
13550
13551 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13552 {
--- 298 unchanged lines hidden (view full) ---
13851;; SImode if the target mode DFmode, but only SImode if the target mode
13852;; is SFmode.
13853
13854;; Gcc is slightly more smart about handling normal two address instructions
13855;; so use special patterns for add and mull.
13856(define_insn "*fop_sf_comm_nosse"
13857 [(set (match_operand:SF 0 "register_operand" "=f")
13858 (match_operator:SF 3 "binary_fp_operator"
13859 [(match_operand:SF 1 "register_operand" "%0")
13860 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
13861 "TARGET_80387 && !TARGET_SSE_MATH
13862 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13863 "* return output_387_binary_op (insn, operands);"
13864 [(set (attr "type")
13865 (if_then_else (match_operand:SF 3 "mult_operator" "")
13866 (const_string "fmul")
13867 (const_string "fop")))
13868 (set_attr "mode" "SF")])
13869
13870(define_insn "*fop_sf_comm"
13871 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
13872 (match_operator:SF 3 "binary_fp_operator"
13873 [(match_operand:SF 1 "register_operand" "%0,0")
13874 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
13875 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
13876 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13877 "* return output_387_binary_op (insn, operands);"
13878 [(set (attr "type")
13879 (if_then_else (eq_attr "alternative" "1")
13880 (const_string "sse")
13881 (if_then_else (match_operand:SF 3 "mult_operator" "")
13882 (const_string "fmul")
13883 (const_string "fop"))))
13884 (set_attr "mode" "SF")])
13885
13886(define_insn "*fop_sf_comm_sse"
13887 [(set (match_operand:SF 0 "register_operand" "=x")
13888 (match_operator:SF 3 "binary_fp_operator"
13889 [(match_operand:SF 1 "register_operand" "%0")
13890 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13891 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13892 "* return output_387_binary_op (insn, operands);"
13893 [(set_attr "type" "sse")
13894 (set_attr "mode" "SF")])
13895
13896(define_insn "*fop_df_comm_nosse"
13897 [(set (match_operand:DF 0 "register_operand" "=f")
13898 (match_operator:DF 3 "binary_fp_operator"
13899 [(match_operand:DF 1 "register_operand" "%0")
13900 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
13901 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
13902 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13903 "* return output_387_binary_op (insn, operands);"
13904 [(set (attr "type")
13905 (if_then_else (match_operand:SF 3 "mult_operator" "")
13906 (const_string "fmul")
13907 (const_string "fop")))
13908 (set_attr "mode" "DF")])
13909
13910(define_insn "*fop_df_comm"
13911 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
13912 (match_operator:DF 3 "binary_fp_operator"
13913 [(match_operand:DF 1 "register_operand" "%0,0")
13914 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
13915 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
13916 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13917 "* return output_387_binary_op (insn, operands);"
13918 [(set (attr "type")
13919 (if_then_else (eq_attr "alternative" "1")
13920 (const_string "sse")
13921 (if_then_else (match_operand:SF 3 "mult_operator" "")
13922 (const_string "fmul")
13923 (const_string "fop"))))
13924 (set_attr "mode" "DF")])
13925
13926(define_insn "*fop_df_comm_sse"
13927 [(set (match_operand:DF 0 "register_operand" "=Y")
13928 (match_operator:DF 3 "binary_fp_operator"
13929 [(match_operand:DF 1 "register_operand" "%0")
13930 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13931 "TARGET_SSE2 && TARGET_SSE_MATH
13932 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13933 "* return output_387_binary_op (insn, operands);"
13934 [(set_attr "type" "sse")
13935 (set_attr "mode" "DF")])
13936
13937(define_insn "*fop_xf_comm"
13938 [(set (match_operand:XF 0 "register_operand" "=f")
13939 (match_operator:XF 3 "binary_fp_operator"
13940 [(match_operand:XF 1 "register_operand" "%0")
--- 617 unchanged lines hidden (view full) ---
14558 [(set_attr "type" "fpspc")
14559 (set_attr "mode" "XF")
14560 (set_attr "athlon_decode" "direct")])
14561
14562(define_insn "*sqrtextenddfxf2"
14563 [(set (match_operand:XF 0 "register_operand" "=f")
14564 (sqrt:XF (float_extend:XF
14565 (match_operand:DF 1 "register_operand" "0"))))]
14566 "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387"
14567 "fsqrt"
14568 [(set_attr "type" "fpspc")
14569 (set_attr "mode" "XF")
14570 (set_attr "athlon_decode" "direct")])
14571
14572(define_insn "*sqrtextenddftf2"
14573 [(set (match_operand:TF 0 "register_operand" "=f")
14574 (sqrt:TF (float_extend:TF
14575 (match_operand:DF 1 "register_operand" "0"))))]
14576 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14577 "fsqrt"
14578 [(set_attr "type" "fpspc")
14579 (set_attr "mode" "XF")
14580 (set_attr "athlon_decode" "direct")])
14581
14582(define_insn "*sqrtextendsfxf2"
14583 [(set (match_operand:XF 0 "register_operand" "=f")
14584 (sqrt:XF (float_extend:XF
14585 (match_operand:SF 1 "register_operand" "0"))))]
14586 "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387"
14587 "fsqrt"
14588 [(set_attr "type" "fpspc")
14589 (set_attr "mode" "XF")
14590 (set_attr "athlon_decode" "direct")])
14591
14592(define_insn "*sqrtextendsftf2"
14593 [(set (match_operand:TF 0 "register_operand" "=f")
14594 (sqrt:TF (float_extend:TF
--- 30 unchanged lines hidden (view full) ---
14625 && flag_unsafe_math_optimizations"
14626 "fsin"
14627 [(set_attr "type" "fpspc")
14628 (set_attr "mode" "DF")])
14629
14630(define_insn "sinxf2"
14631 [(set (match_operand:XF 0 "register_operand" "=f")
14632 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
14633 "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387
14634 && flag_unsafe_math_optimizations"
14635 "fsin"
14636 [(set_attr "type" "fpspc")
14637 (set_attr "mode" "XF")])
14638
14639(define_insn "sintf2"
14640 [(set (match_operand:TF 0 "register_operand" "=f")
14641 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))]
--- 1103 unchanged lines hidden (view full) ---
15745 [(set (match_operand:DI 0 "register_operand" "=r,r")
15746 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
15747 [(reg 17) (const_int 0)])
15748 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
15749 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
15750 "TARGET_64BIT && TARGET_CMOVE
15751 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15752 "@
15753 cmov%C1\t{%2, %0|%0, %2}
15754 cmov%c1\t{%3, %0|%0, %3}"
15755 [(set_attr "type" "icmov")
15756 (set_attr "mode" "DI")])
15757
15758(define_expand "movsicc"
15759 [(set (match_operand:SI 0 "register_operand" "")
15760 (if_then_else:SI (match_operand 1 "comparison_operator" "")
15761 (match_operand:SI 2 "general_operand" "")
15762 (match_operand:SI 3 "general_operand" "")))]
--- 24 unchanged lines hidden (view full) ---
15787 [(set (match_operand:SI 0 "register_operand" "=r,r")
15788 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
15789 [(reg 17) (const_int 0)])
15790 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
15791 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
15792 "TARGET_CMOVE
15793 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15794 "@
15795 cmov%C1\t{%2, %0|%0, %2}
15796 cmov%c1\t{%3, %0|%0, %3}"
15797 [(set_attr "type" "icmov")
15798 (set_attr "mode" "SI")])
15799
15800(define_expand "movhicc"
15801 [(set (match_operand:HI 0 "register_operand" "")
15802 (if_then_else:HI (match_operand 1 "comparison_operator" "")
15803 (match_operand:HI 2 "nonimmediate_operand" "")
15804 (match_operand:HI 3 "nonimmediate_operand" "")))]
--- 4 unchanged lines hidden (view full) ---
15809 [(set (match_operand:HI 0 "register_operand" "=r,r")
15810 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
15811 [(reg 17) (const_int 0)])
15812 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
15813 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
15814 "TARGET_CMOVE
15815 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15816 "@
15817 cmov%C1\t{%2, %0|%0, %2}
15818 cmov%c1\t{%3, %0|%0, %3}"
15819 [(set_attr "type" "icmov")
15820 (set_attr "mode" "HI")])
15821
15822(define_expand "movsfcc"
15823 [(set (match_operand:SF 0 "register_operand" "")
15824 (if_then_else:SF (match_operand 1 "comparison_operator" "")
15825 (match_operand:SF 2 "register_operand" "")
15826 (match_operand:SF 3 "register_operand" "")))]
--- 6 unchanged lines hidden (view full) ---
15833 [(reg 17) (const_int 0)])
15834 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
15835 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
15836 "TARGET_CMOVE
15837 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15838 "@
15839 fcmov%F1\t{%2, %0|%0, %2}
15840 fcmov%f1\t{%3, %0|%0, %3}
15841 cmov%C1\t{%2, %0|%0, %2}
15842 cmov%c1\t{%3, %0|%0, %3}"
15843 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15844 (set_attr "mode" "SF,SF,SI,SI")])
15845
15846(define_expand "movdfcc"
15847 [(set (match_operand:DF 0 "register_operand" "")
15848 (if_then_else:DF (match_operand 1 "comparison_operator" "")
15849 (match_operand:DF 2 "register_operand" "")
15850 (match_operand:DF 3 "register_operand" "")))]
--- 22 unchanged lines hidden (view full) ---
15873 [(reg 17) (const_int 0)])
15874 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15875 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15876 "TARGET_64BIT && TARGET_CMOVE
15877 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15878 "@
15879 fcmov%F1\t{%2, %0|%0, %2}
15880 fcmov%f1\t{%3, %0|%0, %3}
15881 cmov%C1\t{%2, %0|%0, %2}
15882 cmov%c1\t{%3, %0|%0, %3}"
15883 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15884 (set_attr "mode" "DF")])
15885
15886(define_split
15887 [(set (match_operand:DF 0 "register_operand" "")
15888 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15889 [(match_operand 4 "" "") (const_int 0)])
15890 (match_operand:DF 2 "nonimmediate_operand" "")
--- 71 unchanged lines hidden (view full) ---
15962 (match_dup 1)
15963 (match_dup 2)))
15964 (clobber (reg:CC 17))]
15965 "TARGET_SSE && TARGET_IEEE_FP"
15966 "#")
15967
15968(define_insn "*minsf_nonieee"
15969 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
15970 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0")
15971 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
15972 (match_dup 1)
15973 (match_dup 2)))
15974 (clobber (reg:CC 17))]
15975 "TARGET_SSE && !TARGET_IEEE_FP"
15976 "#")
15977
15978(define_split
15979 [(set (match_operand:SF 0 "register_operand" "")
15980 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15981 (match_operand:SF 2 "nonimmediate_operand" ""))
15982 (match_operand:SF 3 "register_operand" "")
15983 (match_operand:SF 4 "nonimmediate_operand" "")))
--- 60 unchanged lines hidden (view full) ---
16044 (match_dup 1)
16045 (match_dup 2)))
16046 (clobber (reg:CC 17))]
16047 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
16048 "#")
16049
16050(define_insn "*mindf_nonieee"
16051 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16052 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0")
16053 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16054 (match_dup 1)
16055 (match_dup 2)))
16056 (clobber (reg:CC 17))]
16057 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
16058 "#")
16059
16060(define_split
16061 [(set (match_operand:DF 0 "register_operand" "")
16062 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16063 (match_operand:DF 2 "nonimmediate_operand" ""))
16064 (match_operand:DF 3 "register_operand" "")
16065 (match_operand:DF 4 "nonimmediate_operand" "")))
--- 59 unchanged lines hidden (view full) ---
16125 (match_dup 1)
16126 (match_dup 2)))
16127 (clobber (reg:CC 17))]
16128 "TARGET_SSE && TARGET_IEEE_FP"
16129 "#")
16130
16131(define_insn "*maxsf_nonieee"
16132 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16133 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0")
16134 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16135 (match_dup 1)
16136 (match_dup 2)))
16137 (clobber (reg:CC 17))]
16138 "TARGET_SSE && !TARGET_IEEE_FP"
16139 "#")
16140
16141(define_split
16142 [(set (match_operand:SF 0 "register_operand" "")
16143 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16144 (match_operand:SF 2 "nonimmediate_operand" ""))
16145 (match_operand:SF 3 "register_operand" "")
16146 (match_operand:SF 4 "nonimmediate_operand" "")))
--- 58 unchanged lines hidden (view full) ---
16205 (match_dup 1)
16206 (match_dup 2)))
16207 (clobber (reg:CC 17))]
16208 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
16209 "#")
16210
16211(define_insn "*maxdf_nonieee"
16212 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16213 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0")
16214 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16215 (match_dup 1)
16216 (match_dup 2)))
16217 (clobber (reg:CC 17))]
16218 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
16219 "#")
16220
16221(define_split
16222 [(set (match_operand:DF 0 "register_operand" "")
16223 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16224 (match_operand:DF 2 "nonimmediate_operand" ""))
16225 (match_operand:DF 3 "register_operand" "")
16226 (match_operand:DF 4 "nonimmediate_operand" "")))
--- 1715 unchanged lines hidden (view full) ---
17942 "TARGET_SSE || TARGET_3DNOW_A"
17943 "pmovmskb\t{%1, %0|%0, %1}"
17944 [(set_attr "type" "sse")])
17945
17946(define_insn "mmx_maskmovq"
17947 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
17948 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
17949 (match_operand:V8QI 2 "register_operand" "y")] 32))]
17950 "TARGET_SSE || TARGET_3DNOW_A"
17951 ;; @@@ check ordering of operands in intel/nonintel syntax
17952 "maskmovq\t{%2, %1|%1, %2}"
17953 [(set_attr "type" "sse")])
17954
17955(define_insn "sse_movntv4sf"
17956 [(set (match_operand:V4SF 0 "memory_operand" "=m")
17957 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
17958 "TARGET_SSE"
17959 "movntps\t{%1, %0|%0, %1}"
17960 [(set_attr "type" "sse")])
17961
17962(define_insn "sse_movntdi"
--- 263 unchanged lines hidden (view full) ---
18226 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18227 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18228 "TARGET_SSE"
18229 "andps\t{%2, %0|%0, %2}"
18230 [(set_attr "type" "sse")])
18231
18232(define_insn "sse_andti3"
18233 [(set (match_operand:TI 0 "register_operand" "=x")
18234 (and:TI (match_operand:TI 1 "register_operand" "%0")
18235 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18236 "TARGET_SSE && !TARGET_SSE2"
18237 "andps\t{%2, %0|%0, %2}"
18238 [(set_attr "type" "sse")])
18239
18240(define_insn "*sse_andti3_sse2"
18241 [(set (match_operand:TI 0 "register_operand" "=x")
18242 (and:TI (match_operand:TI 1 "register_operand" "%0")
18243 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18244 "TARGET_SSE2"
18245 "pand\t{%2, %0|%0, %2}"
18246 [(set_attr "type" "sse")])
18247
18248(define_insn "*sse_nandti3_df"
18249 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18250 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
18251 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18252 "TARGET_SSE2"
--- 53 unchanged lines hidden (view full) ---
18306 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18307 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18308 "TARGET_SSE"
18309 "orps\t{%2, %0|%0, %2}"
18310 [(set_attr "type" "sse")])
18311
18312(define_insn "sse_iorti3"
18313 [(set (match_operand:TI 0 "register_operand" "=x")
18314 (ior:TI (match_operand:TI 1 "register_operand" "%0")
18315 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18316 "TARGET_SSE && !TARGET_SSE2"
18317 "orps\t{%2, %0|%0, %2}"
18318 [(set_attr "type" "sse")])
18319
18320(define_insn "*sse_iorti3_sse2"
18321 [(set (match_operand:TI 0 "register_operand" "=x")
18322 (ior:TI (match_operand:TI 1 "register_operand" "%0")
18323 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18324 "TARGET_SSE2"
18325 "por\t{%2, %0|%0, %2}"
18326 [(set_attr "type" "sse")])
18327
18328(define_insn "*sse_xorti3_df_1"
18329 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18330 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18331 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18332 "TARGET_SSE2"
--- 21 unchanged lines hidden (view full) ---
18354 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18355 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18356 "TARGET_SSE"
18357 "xorps\t{%2, %0|%0, %2}"
18358 [(set_attr "type" "sse")])
18359
18360(define_insn "sse_xorti3"
18361 [(set (match_operand:TI 0 "register_operand" "=x")
18362 (xor:TI (match_operand:TI 1 "register_operand" "%0")
18363 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18364 "TARGET_SSE && !TARGET_SSE2"
18365 "xorps\t{%2, %0|%0, %2}"
18366 [(set_attr "type" "sse")])
18367
18368(define_insn "*sse_xorti3_sse2"
18369 [(set (match_operand:TI 0 "register_operand" "=x")
18370 (xor:TI (match_operand:TI 1 "register_operand" "%0")
18371 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18372 "TARGET_SSE2"
18373 "pxor\t{%2, %0|%0, %2}"
18374 [(set_attr "type" "sse")])
18375
18376;; Use xor, but don't show input operands so they aren't live before
18377;; this insn.
18378(define_insn "sse_clrv4sf"
18379 [(set (match_operand:V4SF 0 "register_operand" "=x")
18380 (unspec:V4SF [(const_int 0)] 45))]
--- 453 unchanged lines hidden (view full) ---
18834;; MMX unsigned averages/sum of absolute differences
18835
18836(define_insn "mmx_uavgv8qi3"
18837 [(set (match_operand:V8QI 0 "register_operand" "=y")
18838 (ashiftrt:V8QI
18839 (plus:V8QI (plus:V8QI
18840 (match_operand:V8QI 1 "register_operand" "0")
18841 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
18842 (vec_const:V8QI (parallel [(const_int 1)
18843 (const_int 1)
18844 (const_int 1)
18845 (const_int 1)
18846 (const_int 1)
18847 (const_int 1)
18848 (const_int 1)
18849 (const_int 1)])))
18850 (const_int 1)))]
18851 "TARGET_SSE || TARGET_3DNOW_A"
18852 "pavgb\t{%2, %0|%0, %2}"
18853 [(set_attr "type" "sse")])
18854
18855(define_insn "mmx_uavgv4hi3"
18856 [(set (match_operand:V4HI 0 "register_operand" "=y")
18857 (ashiftrt:V4HI
18858 (plus:V4HI (plus:V4HI
18859 (match_operand:V4HI 1 "register_operand" "0")
18860 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
18861 (vec_const:V4HI (parallel [(const_int 1)
18862 (const_int 1)
18863 (const_int 1)
18864 (const_int 1)])))
18865 (const_int 1)))]
18866 "TARGET_SSE || TARGET_3DNOW_A"
18867 "pavgw\t{%2, %0|%0, %2}"
18868 [(set_attr "type" "sse")])
18869
18870(define_insn "mmx_psadbw"
18871 [(set (match_operand:V8QI 0 "register_operand" "=y")
18872 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
--- 697 unchanged lines hidden (view full) ---
19570 (truncate:V4HI
19571 (lshiftrt:V4SI
19572 (plus:V4SI
19573 (mult:V4SI
19574 (sign_extend:V4SI
19575 (match_operand:V4HI 1 "register_operand" "0"))
19576 (sign_extend:V4SI
19577 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
19578 (vec_const:V4SI
19579 (parallel [(const_int 32768)
19580 (const_int 32768)
19581 (const_int 32768)
19582 (const_int 32768)])))
19583 (const_int 16))))]
19584 "TARGET_3DNOW"
19585 "pmulhrw\\t{%2, %0|%0, %2}"
19586 [(set_attr "type" "mmx")])
19587
19588(define_insn "pswapdv2si2"
19589 [(set (match_operand:V2SI 0 "register_operand" "=y")
19590 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
19591 (parallel [(const_int 1) (const_int 0)])))]
--- 66 unchanged lines hidden ---