Deleted Added
sdiff udiff text old ( 218895 ) new ( 219374 )
full compact
i386.c (218895) i386.c (219374)
1/* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by

--- 5 unchanged lines hidden (view full) ---

14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING. If not, write to
19the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20Boston, MA 02110-1301, USA. */
21
1/* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by

--- 5 unchanged lines hidden (view full) ---

14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING. If not, write to
19the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20Boston, MA 02110-1301, USA. */
21
22/* $FreeBSD: head/contrib/gcc/config/i386/i386.c 218895 2011-02-20 22:25:23Z mm $ */
22/* $FreeBSD: head/contrib/gcc/config/i386/i386.c 219374 2011-03-07 14:48:22Z mm $ */
23
24#include "config.h"
25#include "system.h"
26#include "coretypes.h"
27#include "tm.h"
28#include "rtl.h"
29#include "tree.h"
30#include "tm_p.h"

--- 300 unchanged lines hidden (view full) ---

331 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
332 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
333 COSTS_N_INSNS (2), /* cost of FABS instruction. */
334 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
335 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
336};
337
338static const
23
24#include "config.h"
25#include "system.h"
26#include "coretypes.h"
27#include "tm.h"
28#include "rtl.h"
29#include "tree.h"
30#include "tm_p.h"

--- 300 unchanged lines hidden (view full) ---

331 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
332 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
333 COSTS_N_INSNS (2), /* cost of FABS instruction. */
334 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
335 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
336};
337
338static const
339struct processor_costs geode_cost = {
340 COSTS_N_INSNS (1), /* cost of an add instruction */
341 COSTS_N_INSNS (1), /* cost of a lea instruction */
342 COSTS_N_INSNS (2), /* variable shift costs */
343 COSTS_N_INSNS (1), /* constant shift costs */
344 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
345 COSTS_N_INSNS (4), /* HI */
346 COSTS_N_INSNS (7), /* SI */
347 COSTS_N_INSNS (7), /* DI */
348 COSTS_N_INSNS (7)}, /* other */
349 0, /* cost of multiply per each bit set */
350 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
351 COSTS_N_INSNS (23), /* HI */
352 COSTS_N_INSNS (39), /* SI */
353 COSTS_N_INSNS (39), /* DI */
354 COSTS_N_INSNS (39)}, /* other */
355 COSTS_N_INSNS (1), /* cost of movsx */
356 COSTS_N_INSNS (1), /* cost of movzx */
357 8, /* "large" insn */
358 4, /* MOVE_RATIO */
359 1, /* cost for loading QImode using movzbl */
360 {1, 1, 1}, /* cost of loading integer registers
361 in QImode, HImode and SImode.
362 Relative to reg-reg move (2). */
363 {1, 1, 1}, /* cost of storing integer registers */
364 1, /* cost of reg,reg fld/fst */
365 {1, 1, 1}, /* cost of loading fp registers
366 in SFmode, DFmode and XFmode */
367 {4, 6, 6}, /* cost of storing fp registers
368 in SFmode, DFmode and XFmode */
369
370 1, /* cost of moving MMX register */
371 {1, 1}, /* cost of loading MMX registers
372 in SImode and DImode */
373 {1, 1}, /* cost of storing MMX registers
374 in SImode and DImode */
375 1, /* cost of moving SSE register */
376 {1, 1, 1}, /* cost of loading SSE registers
377 in SImode, DImode and TImode */
378 {1, 1, 1}, /* cost of storing SSE registers
379 in SImode, DImode and TImode */
380 1, /* MMX or SSE register to integer */
381 32, /* size of prefetch block */
382 1, /* number of parallel prefetches */
383 1, /* Branch cost */
384 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
385 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
386 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
387 COSTS_N_INSNS (1), /* cost of FABS instruction. */
388 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
389 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
390};
391
392static const
339struct processor_costs k6_cost = {
340 COSTS_N_INSNS (1), /* cost of an add instruction */
341 COSTS_N_INSNS (2), /* cost of a lea instruction */
342 COSTS_N_INSNS (1), /* variable shift costs */
343 COSTS_N_INSNS (1), /* constant shift costs */
344 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
345 COSTS_N_INSNS (3), /* HI */
346 COSTS_N_INSNS (3), /* SI */

--- 248 unchanged lines hidden (view full) ---

595 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
596 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
597 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
598 COSTS_N_INSNS (3), /* cost of FABS instruction. */
599 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
600 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
601};
602
393struct processor_costs k6_cost = {
394 COSTS_N_INSNS (1), /* cost of an add instruction */
395 COSTS_N_INSNS (2), /* cost of a lea instruction */
396 COSTS_N_INSNS (1), /* variable shift costs */
397 COSTS_N_INSNS (1), /* constant shift costs */
398 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
399 COSTS_N_INSNS (3), /* HI */
400 COSTS_N_INSNS (3), /* SI */

--- 248 unchanged lines hidden (view full) ---

649 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
650 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
651 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
652 COSTS_N_INSNS (3), /* cost of FABS instruction. */
653 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
654 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
655};
656
657static const
658struct processor_costs core2_cost = {
659 COSTS_N_INSNS (1), /* cost of an add instruction */
660 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
661 COSTS_N_INSNS (1), /* variable shift costs */
662 COSTS_N_INSNS (1), /* constant shift costs */
663 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
664 COSTS_N_INSNS (3), /* HI */
665 COSTS_N_INSNS (3), /* SI */
666 COSTS_N_INSNS (3), /* DI */
667 COSTS_N_INSNS (3)}, /* other */
668 0, /* cost of multiply per each bit set */
669 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
670 COSTS_N_INSNS (22), /* HI */
671 COSTS_N_INSNS (22), /* SI */
672 COSTS_N_INSNS (22), /* DI */
673 COSTS_N_INSNS (22)}, /* other */
674 COSTS_N_INSNS (1), /* cost of movsx */
675 COSTS_N_INSNS (1), /* cost of movzx */
676 8, /* "large" insn */
677 16, /* MOVE_RATIO */
678 2, /* cost for loading QImode using movzbl */
679 {6, 6, 6}, /* cost of loading integer registers
680 in QImode, HImode and SImode.
681 Relative to reg-reg move (2). */
682 {4, 4, 4}, /* cost of storing integer registers */
683 2, /* cost of reg,reg fld/fst */
684 {6, 6, 6}, /* cost of loading fp registers
685 in SFmode, DFmode and XFmode */
686 {4, 4, 4}, /* cost of loading integer registers */
687 2, /* cost of moving MMX register */
688 {6, 6}, /* cost of loading MMX registers
689 in SImode and DImode */
690 {4, 4}, /* cost of storing MMX registers
691 in SImode and DImode */
692 2, /* cost of moving SSE register */
693 {6, 6, 6}, /* cost of loading SSE registers
694 in SImode, DImode and TImode */
695 {4, 4, 4}, /* cost of storing SSE registers
696 in SImode, DImode and TImode */
697 2, /* MMX or SSE register to integer */
698 128, /* size of prefetch block */
699 8, /* number of parallel prefetches */
700 3, /* Branch cost */
701 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
702 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
703 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
704 COSTS_N_INSNS (1), /* cost of FABS instruction. */
705 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
706 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
707};
708
603/* Generic64 should produce code tuned for Nocona and K8. */
604static const
605struct processor_costs generic64_cost = {
606 COSTS_N_INSNS (1), /* cost of an add instruction */
607 /* On all chips taken into consideration lea is 2 cycles and more. With
608 this cost however our current implementation of synth_mult results in
609 use of unnecessary temporary registers causing regression on several
610 SPECfp benchmarks. */

--- 105 unchanged lines hidden (view full) ---

716
717const struct processor_costs *ix86_cost = &pentium_cost;
718
719/* Processor feature/optimization bitmasks. */
720#define m_386 (1<<PROCESSOR_I386)
721#define m_486 (1<<PROCESSOR_I486)
722#define m_PENT (1<<PROCESSOR_PENTIUM)
723#define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
709/* Generic64 should produce code tuned for Nocona and K8. */
710static const
711struct processor_costs generic64_cost = {
712 COSTS_N_INSNS (1), /* cost of an add instruction */
713 /* On all chips taken into consideration lea is 2 cycles and more. With
714 this cost however our current implementation of synth_mult results in
715 use of unnecessary temporary registers causing regression on several
716 SPECfp benchmarks. */

--- 105 unchanged lines hidden (view full) ---

822
823const struct processor_costs *ix86_cost = &pentium_cost;
824
825/* Processor feature/optimization bitmasks. */
826#define m_386 (1<<PROCESSOR_I386)
827#define m_486 (1<<PROCESSOR_I486)
828#define m_PENT (1<<PROCESSOR_PENTIUM)
829#define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
830#define m_GEODE (1<<PROCESSOR_GEODE)
831#define m_K6_GEODE (m_K6 | m_GEODE)
724#define m_K6 (1<<PROCESSOR_K6)
725#define m_ATHLON (1<<PROCESSOR_ATHLON)
726#define m_PENT4 (1<<PROCESSOR_PENTIUM4)
727#define m_K8 (1<<PROCESSOR_K8)
728#define m_ATHLON_K8 (m_K8 | m_ATHLON)
729#define m_NOCONA (1<<PROCESSOR_NOCONA)
832#define m_K6 (1<<PROCESSOR_K6)
833#define m_ATHLON (1<<PROCESSOR_ATHLON)
834#define m_PENT4 (1<<PROCESSOR_PENTIUM4)
835#define m_K8 (1<<PROCESSOR_K8)
836#define m_ATHLON_K8 (m_K8 | m_ATHLON)
837#define m_NOCONA (1<<PROCESSOR_NOCONA)
838#define m_CORE2 (1<<PROCESSOR_CORE2)
730#define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
731#define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
732#define m_GENERIC (m_GENERIC32 | m_GENERIC64)
733
734/* Generic instruction choice should be common subset of supported CPUs
839#define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
840#define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
841#define m_GENERIC (m_GENERIC32 | m_GENERIC64)
842
843/* Generic instruction choice should be common subset of supported CPUs
735 (PPro/PENT4/NOCONA/Athlon/K8). */
844 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
736
737/* Leave is not affecting Nocona SPEC2000 results negatively, so enabling for
738 Generic64 seems like good code size tradeoff. We can't enable it for 32bit
739 generic because it is not working well with PPro base chips. */
845
846/* Leave is not affecting Nocona SPEC2000 results negatively, so enabling for
847 Generic64 seems like good code size tradeoff. We can't enable it for 32bit
848 generic because it is not working well with PPro base chips. */
740const int x86_use_leave = m_386 | m_K6 | m_ATHLON_K8 | m_GENERIC64;
741const int x86_push_memory = m_386 | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
849const int x86_use_leave = m_386 | m_K6_GEODE | m_ATHLON_K8 | m_CORE2 | m_GENERIC64;
850const int x86_push_memory = m_386 | m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
742const int x86_zero_extend_with_and = m_486 | m_PENT;
851const int x86_zero_extend_with_and = m_486 | m_PENT;
743const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_GENERIC /* m_386 | m_K6 */;
852const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */;
744const int x86_double_with_add = ~m_386;
745const int x86_use_bit_test = m_386;
853const int x86_double_with_add = ~m_386;
854const int x86_use_bit_test = m_386;
746const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6 | m_GENERIC;
747const int x86_cmove = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
855const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6 | m_CORE2 | m_GENERIC;
856const int x86_cmove = m_PPRO | m_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
748const int x86_3dnow_a = m_ATHLON_K8;
857const int x86_3dnow_a = m_ATHLON_K8;
749const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
858const int x86_deep_branch = m_PPRO | m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
750/* Branch hints were put in P4 based on simulation result. But
751 after P4 was made, no performance benefit was observed with
752 branch hints. It also increases the code size. As the result,
753 icc never generates branch hints. */
754const int x86_branch_hints = 0;
859/* Branch hints were put in P4 based on simulation result. But
860 after P4 was made, no performance benefit was observed with
861 branch hints. It also increases the code size. As the result,
862 icc never generates branch hints. */
863const int x86_branch_hints = 0;
755const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_GENERIC | m_ATHLON_K8 ? */
864const int x86_use_sahf = m_PPRO | m_K6_GEODE | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_GENERIC | m_ATHLON_K8 ? */
756/* We probably ought to watch for partial register stalls on Generic32
757 compilation setting as well. However in current implementation the
758 partial register stalls are not eliminated very well - they can
759 be introduced via subregs synthesized by combine and can happen
760 in caller/callee saving sequences.
761 Because this option pays back little on PPro based chips and is in conflict
762 with partial reg. dependencies used by Athlon/P4 based chips, it is better
763 to leave it off for generic32 for now. */
764const int x86_partial_reg_stall = m_PPRO;
865/* We probably ought to watch for partial register stalls on Generic32
866 compilation setting as well. However in current implementation the
867 partial register stalls are not eliminated very well - they can
868 be introduced via subregs synthesized by combine and can happen
869 in caller/callee saving sequences.
870 Because this option pays back little on PPro based chips and is in conflict
871 with partial reg. dependencies used by Athlon/P4 based chips, it is better
872 to leave it off for generic32 for now. */
873const int x86_partial_reg_stall = m_PPRO;
765const int x86_partial_flag_reg_stall = m_GENERIC;
766const int x86_use_himode_fiop = m_386 | m_486 | m_K6;
767const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_GENERIC);
874const int x86_partial_flag_reg_stall = m_CORE2 | m_GENERIC;
875const int x86_use_himode_fiop = m_386 | m_486 | m_K6_GEODE;
876const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_CORE2 | m_GENERIC);
768const int x86_use_mov0 = m_K6;
877const int x86_use_mov0 = m_K6;
769const int x86_use_cltd = ~(m_PENT | m_K6 | m_GENERIC);
878const int x86_use_cltd = ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC);
770const int x86_read_modify_write = ~m_PENT;
771const int x86_read_modify = ~(m_PENT | m_PPRO);
772const int x86_split_long_moves = m_PPRO;
879const int x86_read_modify_write = ~m_PENT;
880const int x86_read_modify = ~(m_PENT | m_PPRO);
881const int x86_split_long_moves = m_PPRO;
773const int x86_promote_QImode = m_K6 | m_PENT | m_386 | m_486 | m_ATHLON_K8 | m_GENERIC; /* m_PENT4 ? */
882const int x86_promote_QImode = m_K6_GEODE | m_PENT | m_386 | m_486 | m_ATHLON_K8 | m_CORE2 | m_GENERIC; /* m_PENT4 ? */
774const int x86_fast_prefix = ~(m_PENT | m_486 | m_386);
775const int x86_single_stringop = m_386 | m_PENT4 | m_NOCONA;
776const int x86_qimode_math = ~(0);
777const int x86_promote_qi_regs = 0;
778/* On PPro this flag is meant to avoid partial register stalls. Just like
779 the x86_partial_reg_stall this option might be considered for Generic32
780 if our scheme for avoiding partial stalls was more effective. */
781const int x86_himode_math = ~(m_PPRO);
782const int x86_promote_hi_regs = m_PPRO;
883const int x86_fast_prefix = ~(m_PENT | m_486 | m_386);
884const int x86_single_stringop = m_386 | m_PENT4 | m_NOCONA;
885const int x86_qimode_math = ~(0);
886const int x86_promote_qi_regs = 0;
887/* On PPro this flag is meant to avoid partial register stalls. Just like
888 the x86_partial_reg_stall this option might be considered for Generic32
889 if our scheme for avoiding partial stalls was more effective. */
890const int x86_himode_math = ~(m_PPRO);
891const int x86_promote_hi_regs = m_PPRO;
783const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_GENERIC;
784const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA | m_GENERIC;
785const int x86_add_esp_4 = m_ATHLON_K8 | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC;
786const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6 | m_386 | m_486 | m_PENT4 | m_NOCONA | m_GENERIC;
787const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC);
788const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
789const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
790const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC;
791const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO | m_GENERIC;
792const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO | m_GENERIC;
892const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
893const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
894const int x86_add_esp_4 = m_ATHLON_K8 | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
895const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6_GEODE | m_386 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
896const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_GEODE);
897const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
898const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
899const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
900const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC;
901const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC;
793const int x86_shift1 = ~m_486;
902const int x86_shift1 = ~m_486;
794const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
903const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
795/* In Generic model we have an conflict here in between PPro/Pentium4 based chips
796 that thread 128bit SSE registers as single units versus K8 based chips that
797 divide SSE registers to two 64bit halves.
798 x86_sse_partial_reg_dependency promote all store destinations to be 128bit
799 to allow register renaming on 128bit SSE units, but usually results in one
800 extra microop on 64bit SSE units. Experimental results shows that disabling
801 this option on P4 brings over 20% SPECfp regression, while enabling it on
802 K8 brings roughly 2.4% regression that can be partly masked by careful scheduling
803 of moves. */
904/* In Generic model we have an conflict here in between PPro/Pentium4 based chips
905 that thread 128bit SSE registers as single units versus K8 based chips that
906 divide SSE registers to two 64bit halves.
907 x86_sse_partial_reg_dependency promote all store destinations to be 128bit
908 to allow register renaming on 128bit SSE units, but usually results in one
909 extra microop on 64bit SSE units. Experimental results shows that disabling
910 this option on P4 brings over 20% SPECfp regression, while enabling it on
911 K8 brings roughly 2.4% regression that can be partly masked by careful scheduling
912 of moves. */
804const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC;
913const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
805/* Set for machines where the type and dependencies are resolved on SSE
806 register parts instead of whole registers, so we may maintain just
807 lower part of scalar values in proper format leaving the upper part
808 undefined. */
809const int x86_sse_split_regs = m_ATHLON_K8;
810const int x86_sse_typeless_stores = m_ATHLON_K8;
811const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
812const int x86_use_ffreep = m_ATHLON_K8;
914/* Set for machines where the type and dependencies are resolved on SSE
915 register parts instead of whole registers, so we may maintain just
916 lower part of scalar values in proper format leaving the upper part
917 undefined. */
918const int x86_sse_split_regs = m_ATHLON_K8;
919const int x86_sse_typeless_stores = m_ATHLON_K8;
920const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
921const int x86_use_ffreep = m_ATHLON_K8;
813const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6;
814const int x86_use_incdec = ~(m_PENT4 | m_NOCONA | m_GENERIC);
922const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6_GEODE | m_CORE2;
923const int x86_use_incdec = ~(m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC);
815
816/* ??? Allowing interunit moves makes it all too easy for the compiler to put
817 integer data in xmm registers. Which results in pretty abysmal code. */
818const int x86_inter_unit_moves = 0 /* ~(m_ATHLON_K8) */;
819
924
925/* ??? Allowing interunit moves makes it all too easy for the compiler to put
926 integer data in xmm registers. Which results in pretty abysmal code. */
927const int x86_inter_unit_moves = 0 /* ~(m_ATHLON_K8) */;
928
820const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC32;
929const int x86_ext_80387_constants = m_K6_GEODE | m_ATHLON | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC32;
821/* Some CPU cores are not able to predict more than 4 branch instructions in
822 the 16 byte window. */
930/* Some CPU cores are not able to predict more than 4 branch instructions in
931 the 16 byte window. */
823const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
824const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6 | m_PENT | m_GENERIC;
932const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
933const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC;
825const int x86_use_bt = m_ATHLON_K8;
826/* Compare and exchange was added for 80486. */
827const int x86_cmpxchg = ~m_386;
828/* Compare and exchange 8 bytes was added for pentium. */
829const int x86_cmpxchg8b = ~(m_386 | m_486);
830/* Compare and exchange 16 bytes was added for nocona. */
831const int x86_cmpxchg16b = m_NOCONA;
832/* Exchange and add was added for 80486. */
833const int x86_xadd = ~m_386;
934const int x86_use_bt = m_ATHLON_K8;
935/* Compare and exchange was added for 80486. */
936const int x86_cmpxchg = ~m_386;
937/* Compare and exchange 8 bytes was added for pentium. */
938const int x86_cmpxchg8b = ~(m_386 | m_486);
939/* Compare and exchange 16 bytes was added for nocona. */
940const int x86_cmpxchg16b = m_NOCONA;
941/* Exchange and add was added for 80486. */
942const int x86_xadd = ~m_386;
834const int x86_pad_returns = m_ATHLON_K8 | m_GENERIC;
943const int x86_pad_returns = m_ATHLON_K8 | m_CORE2 | m_GENERIC;
835
836/* In case the average insn count for single function invocation is
837 lower than this constant, emit fast (but longer) prologue and
838 epilogue code. */
839#define FAST_PROLOGUE_INSN_COUNT 20
840
841/* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
842static const char *const qi_reg_name[] = QI_REGISTER_NAMES;

--- 607 unchanged lines hidden (view full) ---

1450 const int align_func;
1451 }
1452 const processor_target_table[PROCESSOR_max] =
1453 {
1454 {&i386_cost, 0, 0, 4, 3, 4, 3, 4},
1455 {&i486_cost, 0, 0, 16, 15, 16, 15, 16},
1456 {&pentium_cost, 0, 0, 16, 7, 16, 7, 16},
1457 {&pentiumpro_cost, 0, 0, 16, 15, 16, 7, 16},
944
945/* In case the average insn count for single function invocation is
946 lower than this constant, emit fast (but longer) prologue and
947 epilogue code. */
948#define FAST_PROLOGUE_INSN_COUNT 20
949
950/* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
951static const char *const qi_reg_name[] = QI_REGISTER_NAMES;

--- 607 unchanged lines hidden (view full) ---

1559 const int align_func;
1560 }
1561 const processor_target_table[PROCESSOR_max] =
1562 {
1563 {&i386_cost, 0, 0, 4, 3, 4, 3, 4},
1564 {&i486_cost, 0, 0, 16, 15, 16, 15, 16},
1565 {&pentium_cost, 0, 0, 16, 7, 16, 7, 16},
1566 {&pentiumpro_cost, 0, 0, 16, 15, 16, 7, 16},
1567 {&geode_cost, 0, 0, 0, 0, 0, 0, 0},
1458 {&k6_cost, 0, 0, 32, 7, 32, 7, 32},
1459 {&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
1460 {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
1461 {&k8_cost, 0, 0, 16, 7, 16, 7, 16},
1462 {&nocona_cost, 0, 0, 0, 0, 0, 0, 0},
1568 {&k6_cost, 0, 0, 32, 7, 32, 7, 32},
1569 {&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
1570 {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
1571 {&k8_cost, 0, 0, 16, 7, 16, 7, 16},
1572 {&nocona_cost, 0, 0, 0, 0, 0, 0, 0},
1573 {&core2_cost, 0, 0, 16, 7, 16, 7, 16},
1463 {&generic32_cost, 0, 0, 16, 7, 16, 7, 16},
1464 {&generic64_cost, 0, 0, 16, 7, 16, 7, 16}
1465 };
1466
1467 static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
1468 static struct pta
1469 {
1470 const char *const name; /* processor name or nickname. */

--- 30 unchanged lines hidden (view full) ---

1501 {"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1502 | PTA_MMX | PTA_PREFETCH_SSE},
1503 {"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1504 | PTA_MMX | PTA_PREFETCH_SSE},
1505 {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
1506 | PTA_MMX | PTA_PREFETCH_SSE},
1507 {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
1508 | PTA_MMX | PTA_PREFETCH_SSE},
1574 {&generic32_cost, 0, 0, 16, 7, 16, 7, 16},
1575 {&generic64_cost, 0, 0, 16, 7, 16, 7, 16}
1576 };
1577
1578 static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
1579 static struct pta
1580 {
1581 const char *const name; /* processor name or nickname. */

--- 30 unchanged lines hidden (view full) ---

1612 {"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1613 | PTA_MMX | PTA_PREFETCH_SSE},
1614 {"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1615 | PTA_MMX | PTA_PREFETCH_SSE},
1616 {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
1617 | PTA_MMX | PTA_PREFETCH_SSE},
1618 {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
1619 | PTA_MMX | PTA_PREFETCH_SSE},
1620 {"core2", PROCESSOR_CORE2, PTA_SSE | PTA_SSE2 | PTA_SSE3
1621 | PTA_64BIT | PTA_MMX
1622 | PTA_PREFETCH_SSE},
1623 {"geode", PROCESSOR_GEODE, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1624 | PTA_3DNOW_A},
1509 {"k6", PROCESSOR_K6, PTA_MMX},
1510 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1511 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1512 {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1513 | PTA_3DNOW_A},
1514 {"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
1515 | PTA_3DNOW | PTA_3DNOW_A},
1516 {"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW

--- 12184 unchanged lines hidden (view full) ---

13701 case PROCESSOR_PENTIUM4:
13702 case PROCESSOR_ATHLON:
13703 case PROCESSOR_K8:
13704 case PROCESSOR_NOCONA:
13705 case PROCESSOR_GENERIC32:
13706 case PROCESSOR_GENERIC64:
13707 return 3;
13708
1625 {"k6", PROCESSOR_K6, PTA_MMX},
1626 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1627 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1628 {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1629 | PTA_3DNOW_A},
1630 {"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
1631 | PTA_3DNOW | PTA_3DNOW_A},
1632 {"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW

--- 12184 unchanged lines hidden (view full) ---

13817 case PROCESSOR_PENTIUM4:
13818 case PROCESSOR_ATHLON:
13819 case PROCESSOR_K8:
13820 case PROCESSOR_NOCONA:
13821 case PROCESSOR_GENERIC32:
13822 case PROCESSOR_GENERIC64:
13823 return 3;
13824
13825 case PROCESSOR_CORE2:
13826 return 4;
13827
13709 default:
13710 return 1;
13711 }
13712}
13713
13714/* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
13715 by DEP_INSN and nothing set by DEP_INSN. */
13716

--- 5464 unchanged lines hidden --- 		13828 default:
13829 return 1;
13830 }
13831}
13832
13833/* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
13834 by DEP_INSN and nothing set by DEP_INSN. */
13835

--- 5464 unchanged lines hidden ---