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combine.c (18334) combine.c (50397)
1/* Optimize by combining instructions for GNU compiler.
1/* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92, 93, 94, 1995 Free Software Foundation, Inc.
2 Copyright (C) 1987, 88, 92-98, 1999 Free Software Foundation, Inc.
3
4This file is part of GNU CC.
5
6GNU CC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2, or (at your option)
9any later version.
10

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76
77#include "config.h"
78#ifdef __STDC__
79#include <stdarg.h>
80#else
81#include <varargs.h>
82#endif
83
3
4This file is part of GNU CC.
5
6GNU CC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2, or (at your option)
9any later version.
10

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76
77#include "config.h"
78#ifdef __STDC__
79#include <stdarg.h>
80#else
81#include <varargs.h>
82#endif
83
84/* Must precede rtl.h for FFS. */
85#include <stdio.h>
84/* stdio.h must precede rtl.h for FFS. */
85#include "system.h"
86
87#include "rtl.h"
88#include "flags.h"
89#include "regs.h"
90#include "hard-reg-set.h"
86
87#include "rtl.h"
88#include "flags.h"
89#include "regs.h"
90#include "hard-reg-set.h"
91#include "expr.h"
92#include "basic-block.h"
93#include "insn-config.h"
91#include "basic-block.h"
92#include "insn-config.h"
93/* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
94#include "expr.h"
94#include "insn-flags.h"
95#include "insn-codes.h"
96#include "insn-attr.h"
97#include "recog.h"
98#include "real.h"
95#include "insn-flags.h"
96#include "insn-codes.h"
97#include "insn-attr.h"
98#include "recog.h"
99#include "real.h"
100#include "toplev.h"
99
100/* It is not safe to use ordinary gen_lowpart in combine.
101 Use gen_lowpart_for_combine instead. See comments there. */
102#define gen_lowpart dont_use_gen_lowpart_you_dummy
103
104/* Number of attempts to combine instructions in this function. */
105
106static int combine_attempts;

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135 proves to be a bad idea because it makes it hard to compare
136 the dumps produced by earlier passes with those from later passes. */
137
138static int *uid_cuid;
139static int max_uid_cuid;
140
141/* Get the cuid of an insn. */
142
101
102/* It is not safe to use ordinary gen_lowpart in combine.
103 Use gen_lowpart_for_combine instead. See comments there. */
104#define gen_lowpart dont_use_gen_lowpart_you_dummy
105
106/* Number of attempts to combine instructions in this function. */
107
108static int combine_attempts;

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137 proves to be a bad idea because it makes it hard to compare
138 the dumps produced by earlier passes with those from later passes. */
139
140static int *uid_cuid;
141static int max_uid_cuid;
142
143/* Get the cuid of an insn. */
144
143#define INSN_CUID(INSN) (INSN_UID (INSN) > max_uid_cuid \
144 ? (abort(), 0) \
145 : uid_cuid[INSN_UID (INSN)])
145#define INSN_CUID(INSN) \
146(INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
146
147/* Maximum register number, which is the size of the tables below. */
148
149static int combine_max_regno;
150
151/* Record last point of death of (hard or pseudo) register n. */
152
153static rtx *reg_last_death;

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194static HARD_REG_SET newpat_used_regs;
195
196/* This is an insn to which a LOG_LINKS entry has been added. If this
197 insn is the earlier than I2 or I3, combine should rescan starting at
198 that location. */
199
200static rtx added_links_insn;
201
147
148/* Maximum register number, which is the size of the tables below. */
149
150static int combine_max_regno;
151
152/* Record last point of death of (hard or pseudo) register n. */
153
154static rtx *reg_last_death;

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195static HARD_REG_SET newpat_used_regs;
196
197/* This is an insn to which a LOG_LINKS entry has been added. If this
198 insn is the earlier than I2 or I3, combine should rescan starting at
199 that location. */
200
201static rtx added_links_insn;
202
202/* This is the value of undobuf.num_undo when we started processing this
203 substitution. This will prevent gen_rtx_combine from re-used a piece
204 from the previous expression. Doing so can produce circular rtl
205 structures. */
206
207static int previous_num_undos;
208
209/* Basic block number of the block in which we are performing combines. */
210static int this_basic_block;
211
212/* The next group of arrays allows the recording of the last value assigned
213 to (hard or pseudo) register n. We use this information to see if a
214 operation being processed is redundant given a prior operation performed
215 on the register. For example, an `and' with a constant is redundant if
216 all the zero bits are already known to be turned off.

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248
249 If an expression is found in the table containing a register which may
250 not validly appear in an expression, the register is replaced by
251 something that won't match, (clobber (const_int 0)).
252
253 reg_last_set_invalid[i] is set non-zero when register I is being assigned
254 to and reg_last_set_table_tick[i] == label_tick. */
255
203/* Basic block number of the block in which we are performing combines. */
204static int this_basic_block;
205
206/* The next group of arrays allows the recording of the last value assigned
207 to (hard or pseudo) register n. We use this information to see if a
208 operation being processed is redundant given a prior operation performed
209 on the register. For example, an `and' with a constant is redundant if
210 all the zero bits are already known to be turned off.

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242
243 If an expression is found in the table containing a register which may
244 not validly appear in an expression, the register is replaced by
245 something that won't match, (clobber (const_int 0)).
246
247 reg_last_set_invalid[i] is set non-zero when register I is being assigned
248 to and reg_last_set_table_tick[i] == label_tick. */
249
256/* Record last value assigned to (hard or pseudo) register n. */
250/* Record last value assigned to (hard or pseudo) register n. */
257
258static rtx *reg_last_set_value;
259
260/* Record the value of label_tick when the value for register n is placed in
261 reg_last_set_value[n]. */
262
263static int *reg_last_set_label;
264
265/* Record the value of label_tick when an expression involving register n
251
252static rtx *reg_last_set_value;
253
254/* Record the value of label_tick when the value for register n is placed in
255 reg_last_set_value[n]. */
256
257static int *reg_last_set_label;
258
259/* Record the value of label_tick when an expression involving register n
266 is placed in reg_last_set_value. */
260 is placed in reg_last_set_value. */
267
268static int *reg_last_set_table_tick;
269
270/* Set non-zero if references to register n in expressions should not be
271 used. */
272
273static char *reg_last_set_invalid;
274
261
262static int *reg_last_set_table_tick;
263
264/* Set non-zero if references to register n in expressions should not be
265 used. */
266
267static char *reg_last_set_invalid;
268
275/* Incremented for each label. */
269/* Incremented for each label. */
276
277static int label_tick;
278
279/* Some registers that are set more than once and used in more than one
280 basic block are nevertheless always set in similar ways. For example,
281 a QImode register may be loaded from memory in two places on a machine
282 where byte loads zero extend.
283

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315static char *reg_last_set_sign_bit_copies;
316
317/* Record one modification to rtl structure
318 to be undone by storing old_contents into *where.
319 is_int is 1 if the contents are an int. */
320
321struct undo
322{
270
271static int label_tick;
272
273/* Some registers that are set more than once and used in more than one
274 basic block are nevertheless always set in similar ways. For example,
275 a QImode register may be loaded from memory in two places on a machine
276 where byte loads zero extend.
277

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309static char *reg_last_set_sign_bit_copies;
310
311/* Record one modification to rtl structure
312 to be undone by storing old_contents into *where.
313 is_int is 1 if the contents are an int. */
314
315struct undo
316{
317 struct undo *next;
323 int is_int;
324 union {rtx r; int i;} old_contents;
325 union {rtx *r; int *i;} where;
326};
327
328/* Record a bunch of changes to be undone, up to MAX_UNDO of them.
329 num_undo says how many are currently recorded.
330
331 storage is nonzero if we must undo the allocation of new storage.
332 The value of storage is what to pass to obfree.
333
334 other_insn is nonzero if we have modified some other insn in the process
318 int is_int;
319 union {rtx r; int i;} old_contents;
320 union {rtx *r; int *i;} where;
321};
322
323/* Record a bunch of changes to be undone, up to MAX_UNDO of them.
324 num_undo says how many are currently recorded.
325
326 storage is nonzero if we must undo the allocation of new storage.
327 The value of storage is what to pass to obfree.
328
329 other_insn is nonzero if we have modified some other insn in the process
335 of working on subst_insn. It must be verified too. */
330 of working on subst_insn. It must be verified too.
336
331
337#define MAX_UNDO 50
332 previous_undos is the value of undobuf.undos when we started processing
333 this substitution. This will prevent gen_rtx_combine from re-used a piece
334 from the previous expression. Doing so can produce circular rtl
335 structures. */
338
339struct undobuf
340{
336
337struct undobuf
338{
341 int num_undo;
342 char *storage;
339 char *storage;
343 struct undo undo[MAX_UNDO];
340 struct undo *undos;
341 struct undo *frees;
342 struct undo *previous_undos;
344 rtx other_insn;
345};
346
347static struct undobuf undobuf;
348
349/* Substitute NEWVAL, an rtx expression, into INTO, a place in some
350 insn. The substitution can be undone by undo_all. If INTO is already
351 set to NEWVAL, do not record this change. Because computing NEWVAL might
352 also call SUBST, we have to compute it before we put anything into
353 the undo table. */
354
355#define SUBST(INTO, NEWVAL) \
343 rtx other_insn;
344};
345
346static struct undobuf undobuf;
347
348/* Substitute NEWVAL, an rtx expression, into INTO, a place in some
349 insn. The substitution can be undone by undo_all. If INTO is already
350 set to NEWVAL, do not record this change. Because computing NEWVAL might
351 also call SUBST, we have to compute it before we put anything into
352 the undo table. */
353
354#define SUBST(INTO, NEWVAL) \
356 do { rtx _new = (NEWVAL); \
357 if (undobuf.num_undo < MAX_UNDO) \
358 { \
359 undobuf.undo[undobuf.num_undo].is_int = 0; \
360 undobuf.undo[undobuf.num_undo].where.r = &INTO; \
361 undobuf.undo[undobuf.num_undo].old_contents.r = INTO; \
362 INTO = _new; \
363 if (undobuf.undo[undobuf.num_undo].old_contents.r != INTO) \
364 undobuf.num_undo++; \
365 } \
355 do { rtx _new = (NEWVAL); \
356 struct undo *_buf; \
357 \
358 if (undobuf.frees) \
359 _buf = undobuf.frees, undobuf.frees = _buf->next; \
360 else \
361 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
362 \
363 _buf->is_int = 0; \
364 _buf->where.r = &INTO; \
365 _buf->old_contents.r = INTO; \
366 INTO = _new; \
367 if (_buf->old_contents.r == INTO) \
368 _buf->next = undobuf.frees, undobuf.frees = _buf; \
369 else \
370 _buf->next = undobuf.undos, undobuf.undos = _buf; \
366 } while (0)
367
371 } while (0)
372
368/* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
369 expression.
370 Note that substitution for the value of a CONST_INT is not safe. */
373/* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
374 for the value of a HOST_WIDE_INT value (including CONST_INT) is
375 not safe. */
371
372#define SUBST_INT(INTO, NEWVAL) \
376
377#define SUBST_INT(INTO, NEWVAL) \
373 do { if (undobuf.num_undo < MAX_UNDO) \
374{ \
375 undobuf.undo[undobuf.num_undo].is_int = 1; \
376 undobuf.undo[undobuf.num_undo].where.i = (int *) &INTO; \
377 undobuf.undo[undobuf.num_undo].old_contents.i = INTO; \
378 INTO = NEWVAL; \
379 if (undobuf.undo[undobuf.num_undo].old_contents.i != INTO) \
380 undobuf.num_undo++; \
381 } \
378 do { struct undo *_buf; \
379 \
380 if (undobuf.frees) \
381 _buf = undobuf.frees, undobuf.frees = _buf->next; \
382 else \
383 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
384 \
385 _buf->is_int = 1; \
386 _buf->where.i = (int *) &INTO; \
387 _buf->old_contents.i = INTO; \
388 INTO = NEWVAL; \
389 if (_buf->old_contents.i == INTO) \
390 _buf->next = undobuf.frees, undobuf.frees = _buf; \
391 else \
392 _buf->next = undobuf.undos, undobuf.undos = _buf; \
382 } while (0)
383
384/* Number of times the pseudo being substituted for
385 was found and replaced. */
386
387static int n_occurrences;
388
393 } while (0)
394
395/* Number of times the pseudo being substituted for
396 was found and replaced. */
397
398static int n_occurrences;
399
389static void init_reg_last_arrays PROTO(());
390static void setup_incoming_promotions PROTO(());
400static void init_reg_last_arrays PROTO((void));
401static void setup_incoming_promotions PROTO((void));
391static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
392static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
402static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
403static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
404static int sets_function_arg_p PROTO((rtx));
393static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
394static rtx try_combine PROTO((rtx, rtx, rtx));
395static void undo_all PROTO((void));
396static rtx *find_split_point PROTO((rtx *, rtx));
397static rtx subst PROTO((rtx, rtx, rtx, int, int));
398static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
399static rtx simplify_if_then_else PROTO((rtx));
400static rtx simplify_set PROTO((rtx));

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405 int, int, int));
406static rtx extract_left_shift PROTO((rtx, int));
407static rtx make_compound_operation PROTO((rtx, enum rtx_code));
408static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
409static rtx force_to_mode PROTO((rtx, enum machine_mode,
410 unsigned HOST_WIDE_INT, rtx, int));
411static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
412static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
405static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
406static rtx try_combine PROTO((rtx, rtx, rtx));
407static void undo_all PROTO((void));
408static rtx *find_split_point PROTO((rtx *, rtx));
409static rtx subst PROTO((rtx, rtx, rtx, int, int));
410static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
411static rtx simplify_if_then_else PROTO((rtx));
412static rtx simplify_set PROTO((rtx));

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417 int, int, int));
418static rtx extract_left_shift PROTO((rtx, int));
419static rtx make_compound_operation PROTO((rtx, enum rtx_code));
420static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
421static rtx force_to_mode PROTO((rtx, enum machine_mode,
422 unsigned HOST_WIDE_INT, rtx, int));
423static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
424static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
425static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
413static rtx make_field_assignment PROTO((rtx));
414static rtx apply_distributive_law PROTO((rtx));
415static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
416 unsigned HOST_WIDE_INT));
417static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
418static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
419static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
420 enum rtx_code, HOST_WIDE_INT,

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430static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
431 enum machine_mode, rtx));
432static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
433static int reversible_comparison_p PROTO((rtx));
434static void update_table_tick PROTO((rtx));
435static void record_value_for_reg PROTO((rtx, rtx, rtx));
436static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
437static void record_dead_and_set_regs PROTO((rtx));
426static rtx make_field_assignment PROTO((rtx));
427static rtx apply_distributive_law PROTO((rtx));
428static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
429 unsigned HOST_WIDE_INT));
430static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
431static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
432static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
433 enum rtx_code, HOST_WIDE_INT,

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443static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
444 enum machine_mode, rtx));
445static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
446static int reversible_comparison_p PROTO((rtx));
447static void update_table_tick PROTO((rtx));
448static void record_value_for_reg PROTO((rtx, rtx, rtx));
449static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
450static void record_dead_and_set_regs PROTO((rtx));
438static int get_last_value_validate PROTO((rtx *, int, int));
451static int get_last_value_validate PROTO((rtx *, rtx, int, int));
439static rtx get_last_value PROTO((rtx));
440static int use_crosses_set_p PROTO((rtx, int));
441static void reg_dead_at_p_1 PROTO((rtx, rtx));
442static int reg_dead_at_p PROTO((rtx, rtx));
452static rtx get_last_value PROTO((rtx));
453static int use_crosses_set_p PROTO((rtx, int));
454static void reg_dead_at_p_1 PROTO((rtx, rtx));
455static int reg_dead_at_p PROTO((rtx, rtx));
443static void move_deaths PROTO((rtx, int, rtx, rtx *));
456static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
444static int reg_bitfield_target_p PROTO((rtx, rtx));
445static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
446static void distribute_links PROTO((rtx));
447static void mark_used_regs_combine PROTO((rtx));
457static int reg_bitfield_target_p PROTO((rtx, rtx));
458static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
459static void distribute_links PROTO((rtx));
460static void mark_used_regs_combine PROTO((rtx));
461static int insn_cuid PROTO((rtx));
448
449/* Main entry point for combiner. F is the first insn of the function.
450 NREGS is the first unused pseudo-reg number. */
451
452void
453combine_instructions (f, nregs)
454 rtx f;
455 int nregs;
456{
462
463/* Main entry point for combiner. F is the first insn of the function.
464 NREGS is the first unused pseudo-reg number. */
465
466void
467combine_instructions (f, nregs)
468 rtx f;
469 int nregs;
470{
457 register rtx insn, next, prev;
471 register rtx insn, next;
472#ifdef HAVE_cc0
473 register rtx prev;
474#endif
458 register int i;
459 register rtx links, nextlinks;
460
461 combine_attempts = 0;
462 combine_merges = 0;
463 combine_extras = 0;
464 combine_successes = 0;
475 register int i;
476 register rtx links, nextlinks;
477
478 combine_attempts = 0;
479 combine_merges = 0;
480 combine_extras = 0;
481 combine_successes = 0;
465 undobuf.num_undo = previous_num_undos = 0;
482 undobuf.undos = undobuf.previous_undos = 0;
466
467 combine_max_regno = nregs;
468
469 reg_nonzero_bits
470 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
471 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
472
473 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));

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530 uid_cuid[INSN_UID (insn)] = ++i;
531 subst_low_cuid = i;
532 subst_insn = insn;
533
534 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
535 {
536 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
537 record_dead_and_set_regs (insn);
483
484 combine_max_regno = nregs;
485
486 reg_nonzero_bits
487 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
488 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
489
490 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));

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547 uid_cuid[INSN_UID (insn)] = ++i;
548 subst_low_cuid = i;
549 subst_insn = insn;
550
551 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
552 {
553 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
554 record_dead_and_set_regs (insn);
555
556#ifdef AUTO_INC_DEC
557 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
558 if (REG_NOTE_KIND (links) == REG_INC)
559 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
560#endif
538 }
539
540 if (GET_CODE (insn) == CODE_LABEL)
541 label_tick++;
542 }
543
544 nonzero_sign_valid = 1;
545

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689 rtx reg;
690 enum machine_mode mode;
691 int unsignedp;
692 rtx first = get_insns ();
693
694 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
695 if (FUNCTION_ARG_REGNO_P (regno)
696 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
561 }
562
563 if (GET_CODE (insn) == CODE_LABEL)
564 label_tick++;
565 }
566
567 nonzero_sign_valid = 1;
568

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712 rtx reg;
713 enum machine_mode mode;
714 int unsignedp;
715 rtx first = get_insns ();
716
717 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
718 if (FUNCTION_ARG_REGNO_P (regno)
719 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
697 record_value_for_reg (reg, first,
698 gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
699 GET_MODE (reg),
700 gen_rtx (CLOBBER, mode, const0_rtx)));
720 {
721 record_value_for_reg
722 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
723 : SIGN_EXTEND),
724 GET_MODE (reg),
725 gen_rtx_CLOBBER (mode, const0_rtx)));
726 }
701#endif
702}
703
727#endif
728}
729
704/* Called via note_stores. If X is a pseudo that is used in more than
705 one basic block, is narrower that HOST_BITS_PER_WIDE_INT, and is being
706 set, record what bits are known zero. If we are clobbering X,
707 ignore this "set" because the clobbered value won't be used.
730/* Called via note_stores. If X is a pseudo that is narrower than
731 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
708
709 If we are setting only a portion of X and we can't figure out what
710 portion, assume all bits will be used since we don't know what will
711 be happening.
712
713 Similarly, set how many bits of X are known to be copies of the sign bit
714 at all locations in the function. This is the smallest number implied
715 by any set of X. */
716
717static void
718set_nonzero_bits_and_sign_copies (x, set)
719 rtx x;
720 rtx set;
721{
722 int num;
723
724 if (GET_CODE (x) == REG
725 && REGNO (x) >= FIRST_PSEUDO_REGISTER
732
733 If we are setting only a portion of X and we can't figure out what
734 portion, assume all bits will be used since we don't know what will
735 be happening.
736
737 Similarly, set how many bits of X are known to be copies of the sign bit
738 at all locations in the function. This is the smallest number implied
739 by any set of X. */
740
741static void
742set_nonzero_bits_and_sign_copies (x, set)
743 rtx x;
744 rtx set;
745{
746 int num;
747
748 if (GET_CODE (x) == REG
749 && REGNO (x) >= FIRST_PSEUDO_REGISTER
726 && reg_n_sets[REGNO (x)] > 1
727 && reg_basic_block[REGNO (x)] < 0
728 /* If this register is undefined at the start of the file, we can't
729 say what its contents were. */
750 /* If this register is undefined at the start of the file, we can't
751 say what its contents were. */
730 && ! (basic_block_live_at_start[0][REGNO (x) / REGSET_ELT_BITS]
731 & ((REGSET_ELT_TYPE) 1 << (REGNO (x) % REGSET_ELT_BITS)))
752 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], REGNO (x))
732 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
733 {
753 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
754 {
734 if (GET_CODE (set) == CLOBBER)
755 if (set == 0 || GET_CODE (set) == CLOBBER)
735 {
736 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
756 {
757 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
737 reg_sign_bit_copies[REGNO (x)] = 0;
758 reg_sign_bit_copies[REGNO (x)] = 1;
738 return;
739 }
740
741 /* If this is a complex assignment, see if we can convert it into a
742 simple assignment. */
743 set = expand_field_assignment (set);
744
745 /* If this is a simple assignment, or we have a paradoxical SUBREG,

--- 33 unchanged lines hidden (view full) ---

779 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
780 if (reg_sign_bit_copies[REGNO (x)] == 0
781 || reg_sign_bit_copies[REGNO (x)] > num)
782 reg_sign_bit_copies[REGNO (x)] = num;
783 }
784 else
785 {
786 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
759 return;
760 }
761
762 /* If this is a complex assignment, see if we can convert it into a
763 simple assignment. */
764 set = expand_field_assignment (set);
765
766 /* If this is a simple assignment, or we have a paradoxical SUBREG,

--- 33 unchanged lines hidden (view full) ---

800 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
801 if (reg_sign_bit_copies[REGNO (x)] == 0
802 || reg_sign_bit_copies[REGNO (x)] > num)
803 reg_sign_bit_copies[REGNO (x)] = num;
804 }
805 else
806 {
807 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
787 reg_sign_bit_copies[REGNO (x)] = 0;
808 reg_sign_bit_copies[REGNO (x)] = 1;
788 }
789 }
790}
791
792/* See if INSN can be combined into I3. PRED and SUCC are optionally
793 insns that were previously combined into I3 or that will be combined
794 into the merger of INSN and I3.
795

--- 7 unchanged lines hidden (view full) ---

803can_combine_p (insn, i3, pred, succ, pdest, psrc)
804 rtx insn;
805 rtx i3;
806 rtx pred, succ;
807 rtx *pdest, *psrc;
808{
809 int i;
810 rtx set = 0, src, dest;
809 }
810 }
811}
812
813/* See if INSN can be combined into I3. PRED and SUCC are optionally
814 insns that were previously combined into I3 or that will be combined
815 into the merger of INSN and I3.
816

--- 7 unchanged lines hidden (view full) ---

824can_combine_p (insn, i3, pred, succ, pdest, psrc)
825 rtx insn;
826 rtx i3;
827 rtx pred, succ;
828 rtx *pdest, *psrc;
829{
830 int i;
831 rtx set = 0, src, dest;
811 rtx p, link;
832 rtx p;
833#ifdef AUTO_INC_DEC
834 rtx link;
835#endif
812 int all_adjacent = (succ ? (next_active_insn (insn) == succ
813 && next_active_insn (succ) == i3)
814 : next_active_insn (insn) == i3);
815
816 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
817 or a PARALLEL consisting of such a SET and CLOBBERs.
818
819 If INSN has CLOBBER parallel parts, ignore them for our processing.

--- 14 unchanged lines hidden (view full) ---

834 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
835 {
836 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
837 {
838 rtx elt = XVECEXP (PATTERN (insn), 0, i);
839
840 switch (GET_CODE (elt))
841 {
836 int all_adjacent = (succ ? (next_active_insn (insn) == succ
837 && next_active_insn (succ) == i3)
838 : next_active_insn (insn) == i3);
839
840 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
841 or a PARALLEL consisting of such a SET and CLOBBERs.
842
843 If INSN has CLOBBER parallel parts, ignore them for our processing.

--- 14 unchanged lines hidden (view full) ---

858 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
859 {
860 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
861 {
862 rtx elt = XVECEXP (PATTERN (insn), 0, i);
863
864 switch (GET_CODE (elt))
865 {
866 /* This is important to combine floating point insns
867 for the SH4 port. */
868 case USE:
869 /* Combining an isolated USE doesn't make sense.
870 We depend here on combinable_i3_pat to reject them. */
871 /* The code below this loop only verifies that the inputs of
872 the SET in INSN do not change. We call reg_set_between_p
873 to verify that the REG in the USE does not change betweeen
874 I3 and INSN.
875 If the USE in INSN was for a pseudo register, the matching
876 insn pattern will likely match any register; combining this
877 with any other USE would only be safe if we knew that the
878 used registers have identical values, or if there was
879 something to tell them apart, e.g. different modes. For
880 now, we forgo such compilcated tests and simply disallow
881 combining of USES of pseudo registers with any other USE. */
882 if (GET_CODE (XEXP (elt, 0)) == REG
883 && GET_CODE (PATTERN (i3)) == PARALLEL)
884 {
885 rtx i3pat = PATTERN (i3);
886 int i = XVECLEN (i3pat, 0) - 1;
887 int regno = REGNO (XEXP (elt, 0));
888 do
889 {
890 rtx i3elt = XVECEXP (i3pat, 0, i);
891 if (GET_CODE (i3elt) == USE
892 && GET_CODE (XEXP (i3elt, 0)) == REG
893 && (REGNO (XEXP (i3elt, 0)) == regno
894 ? reg_set_between_p (XEXP (elt, 0),
895 PREV_INSN (insn), i3)
896 : regno >= FIRST_PSEUDO_REGISTER))
897 return 0;
898 }
899 while (--i >= 0);
900 }
901 break;
902
842 /* We can ignore CLOBBERs. */
843 case CLOBBER:
844 break;
845
846 case SET:
847 /* Ignore SETs whose result isn't used but not those that
848 have side-effects. */
849 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))

--- 84 unchanged lines hidden (view full) ---

934 {
935 /* If register alignment is being enforced for multi-word items in all
936 cases except for parameters, it is possible to have a register copy
937 insn referencing a hard register that is not allowed to contain the
938 mode being copied and which would not be valid as an operand of most
939 insns. Eliminate this problem by not combining with such an insn.
940
941 Also, on some machines we don't want to extend the life of a hard
903 /* We can ignore CLOBBERs. */
904 case CLOBBER:
905 break;
906
907 case SET:
908 /* Ignore SETs whose result isn't used but not those that
909 have side-effects. */
910 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))

--- 84 unchanged lines hidden (view full) ---

995 {
996 /* If register alignment is being enforced for multi-word items in all
997 cases except for parameters, it is possible to have a register copy
998 insn referencing a hard register that is not allowed to contain the
999 mode being copied and which would not be valid as an operand of most
1000 insns. Eliminate this problem by not combining with such an insn.
1001
1002 Also, on some machines we don't want to extend the life of a hard
942 register. */
1003 register.
943
1004
1005 This is the same test done in can_combine except that we don't test
1006 if SRC is a CALL operation to permit a hard register with
1007 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1008 into account. */
1009
944 if (GET_CODE (src) == REG
945 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
946 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
947 /* Don't extend the life of a hard register unless it is
948 user variable (if we have few registers) or it can't
949 fit into the desired register (meaning something special
1010 if (GET_CODE (src) == REG
1011 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1012 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1013 /* Don't extend the life of a hard register unless it is
1014 user variable (if we have few registers) or it can't
1015 fit into the desired register (meaning something special
950 is going on). */
1016 is going on).
1017 Also avoid substituting a return register into I3, because
1018 reload can't handle a conflict with constraints of other
1019 inputs. */
951 || (REGNO (src) < FIRST_PSEUDO_REGISTER
952 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
1020 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1021 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
953#ifdef SMALL_REGISTER_CLASSES
954 || ! REG_USERVAR_P (src)
955#endif
956 ))))
1022 || (SMALL_REGISTER_CLASSES
1023 && ((! all_adjacent && ! REG_USERVAR_P (src))
1024 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
1025 && ! REG_USERVAR_P (src))))))))
957 return 0;
958 }
959 else if (GET_CODE (dest) != CC0)
960 return 0;
961
962 /* Don't substitute for a register intended as a clobberable operand.
963 Similarly, don't substitute an expression containing a register that
964 will be clobbered in I3. */
965 if (GET_CODE (PATTERN (i3)) == PARALLEL)
966 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
967 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
968 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
969 src)
970 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
971 return 0;
972
973 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1026 return 0;
1027 }
1028 else if (GET_CODE (dest) != CC0)
1029 return 0;
1030
1031 /* Don't substitute for a register intended as a clobberable operand.
1032 Similarly, don't substitute an expression containing a register that
1033 will be clobbered in I3. */
1034 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1035 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1036 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1037 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1038 src)
1039 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1040 return 0;
1041
1042 /* If INSN contains anything volatile, or is an `asm' (whether volatile
974 or not), reject, unless nothing volatile comes between it and I3,
975 with the exception of SUCC. */
1043 or not), reject, unless nothing volatile comes between it and I3 */
976
977 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1044
1045 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
978 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
979 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
980 && p != succ && volatile_refs_p (PATTERN (p)))
981 return 0;
1046 {
1047 /* Make sure succ doesn't contain a volatile reference. */
1048 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1049 return 0;
1050
1051 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1052 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1053 && p != succ && volatile_refs_p (PATTERN (p)))
1054 return 0;
1055 }
982
1056
1057 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1058 to be an explicit register variable, and was chosen for a reason. */
1059
1060 if (GET_CODE (src) == ASM_OPERANDS
1061 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1062 return 0;
1063
983 /* If there are any volatile insns between INSN and I3, reject, because
984 they might affect machine state. */
985
986 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
987 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
988 && p != succ && volatile_insn_p (PATTERN (p)))
989 return 0;
990

--- 32 unchanged lines hidden (view full) ---

1023 to be allowed. */
1024
1025 *pdest = dest;
1026 *psrc = src;
1027
1028 return 1;
1029}
1030
1064 /* If there are any volatile insns between INSN and I3, reject, because
1065 they might affect machine state. */
1066
1067 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1068 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1069 && p != succ && volatile_insn_p (PATTERN (p)))
1070 return 0;
1071

--- 32 unchanged lines hidden (view full) ---

1104 to be allowed. */
1105
1106 *pdest = dest;
1107 *psrc = src;
1108
1109 return 1;
1110}
1111
1112/* Check if PAT is an insn - or a part of it - used to set up an
1113 argument for a function in a hard register. */
1114
1115static int
1116sets_function_arg_p (pat)
1117 rtx pat;
1118{
1119 int i;
1120 rtx inner_dest;
1121
1122 switch (GET_CODE (pat))
1123 {
1124 case INSN:
1125 return sets_function_arg_p (PATTERN (pat));
1126
1127 case PARALLEL:
1128 for (i = XVECLEN (pat, 0); --i >= 0;)
1129 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1130 return 1;
1131
1132 break;
1133
1134 case SET:
1135 inner_dest = SET_DEST (pat);
1136 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1137 || GET_CODE (inner_dest) == SUBREG
1138 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1139 inner_dest = XEXP (inner_dest, 0);
1140
1141 return (GET_CODE (inner_dest) == REG
1142 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1143 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1144
1145 default:
1146 break;
1147 }
1148
1149 return 0;
1150}
1151
1031/* LOC is the location within I3 that contains its pattern or the component
1032 of a PARALLEL of the pattern. We validate that it is valid for combining.
1033
1034 One problem is if I3 modifies its output, as opposed to replacing it
1035 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1036 so would produce an insn that is not equivalent to the original insns.
1037
1038 Consider:

--- 12 unchanged lines hidden (view full) ---

1051 We can also run into a problem if I2 sets a register that I1
1052 uses and I1 gets directly substituted into I3 (not via I2). In that
1053 case, we would be getting the wrong value of I2DEST into I3, so we
1054 must reject the combination. This case occurs when I2 and I1 both
1055 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1056 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1057 of a SET must prevent combination from occurring.
1058
1152/* LOC is the location within I3 that contains its pattern or the component
1153 of a PARALLEL of the pattern. We validate that it is valid for combining.
1154
1155 One problem is if I3 modifies its output, as opposed to replacing it
1156 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1157 so would produce an insn that is not equivalent to the original insns.
1158
1159 Consider:

--- 12 unchanged lines hidden (view full) ---

1172 We can also run into a problem if I2 sets a register that I1
1173 uses and I1 gets directly substituted into I3 (not via I2). In that
1174 case, we would be getting the wrong value of I2DEST into I3, so we
1175 must reject the combination. This case occurs when I2 and I1 both
1176 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1177 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1178 of a SET must prevent combination from occurring.
1179
1059 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
1180 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1060 if the destination of a SET is a hard register that isn't a user
1061 variable.
1062
1063 Before doing the above check, we first try to expand a field assignment
1064 into a set of logical operations.
1065
1066 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1067 we place a register that is both set and used within I3. If more than one

--- 12 unchanged lines hidden (view full) ---

1080{
1081 rtx x = *loc;
1082
1083 if (GET_CODE (x) == SET)
1084 {
1085 rtx set = expand_field_assignment (x);
1086 rtx dest = SET_DEST (set);
1087 rtx src = SET_SRC (set);
1181 if the destination of a SET is a hard register that isn't a user
1182 variable.
1183
1184 Before doing the above check, we first try to expand a field assignment
1185 into a set of logical operations.
1186
1187 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1188 we place a register that is both set and used within I3. If more than one

--- 12 unchanged lines hidden (view full) ---

1201{
1202 rtx x = *loc;
1203
1204 if (GET_CODE (x) == SET)
1205 {
1206 rtx set = expand_field_assignment (x);
1207 rtx dest = SET_DEST (set);
1208 rtx src = SET_SRC (set);
1088 rtx inner_dest = dest, inner_src = src;
1209 rtx inner_dest = dest;
1210
1211#if 0
1212 rtx inner_src = src;
1213#endif
1089
1090 SUBST (*loc, set);
1091
1092 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1093 || GET_CODE (inner_dest) == SUBREG
1094 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1095 inner_dest = XEXP (inner_dest, 0);
1096

--- 21 unchanged lines hidden (view full) ---

1118 return 0;
1119#endif
1120
1121 /* Check for the case where I3 modifies its output, as
1122 discussed above. */
1123 if ((inner_dest != dest
1124 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1125 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1214
1215 SUBST (*loc, set);
1216
1217 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1218 || GET_CODE (inner_dest) == SUBREG
1219 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1220 inner_dest = XEXP (inner_dest, 0);
1221

--- 21 unchanged lines hidden (view full) ---

1243 return 0;
1244#endif
1245
1246 /* Check for the case where I3 modifies its output, as
1247 discussed above. */
1248 if ((inner_dest != dest
1249 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1250 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1251
1126 /* This is the same test done in can_combine_p except that we
1127 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1252 /* This is the same test done in can_combine_p except that we
1253 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1128 CALL operation. */
1254 CALL operation. Moreover, we can't test all_adjacent; we don't
1255 have to, since this instruction will stay in place, thus we are
1256 not considering increasing the lifetime of INNER_DEST.
1257
1258 Also, if this insn sets a function argument, combining it with
1259 something that might need a spill could clobber a previous
1260 function argument; the all_adjacent test in can_combine_p also
1261 checks this; here, we do a more specific test for this case. */
1262
1129 || (GET_CODE (inner_dest) == REG
1130 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1131 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1132 GET_MODE (inner_dest))
1263 || (GET_CODE (inner_dest) == REG
1264 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1265 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1266 GET_MODE (inner_dest))
1133#ifdef SMALL_REGISTER_CLASSES
1134 || (GET_CODE (src) != CALL && ! REG_USERVAR_P (inner_dest))
1135#endif
1136 ))
1267 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1268 && ! REG_USERVAR_P (inner_dest)
1269 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1270 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1271 && i3 != 0
1272 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1137 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1138 return 0;
1139
1140 /* If DEST is used in I3, it is being killed in this insn,
1141 so record that for later.
1142 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1143 STACK_POINTER_REGNUM, since these are always considered to be
1144 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */

--- 90 unchanged lines hidden (view full) ---

1235 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1236 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1237 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1238 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1239 return 0;
1240
1241 combine_attempts++;
1242
1273 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1274 return 0;
1275
1276 /* If DEST is used in I3, it is being killed in this insn,
1277 so record that for later.
1278 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1279 STACK_POINTER_REGNUM, since these are always considered to be
1280 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */

--- 90 unchanged lines hidden (view full) ---

1371 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1372 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1373 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1374 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1375 return 0;
1376
1377 combine_attempts++;
1378
1243 undobuf.num_undo = previous_num_undos = 0;
1379 undobuf.undos = undobuf.previous_undos = 0;
1244 undobuf.other_insn = 0;
1245
1246 /* Save the current high-water-mark so we can free storage if we didn't
1247 accept this combination. */
1248 undobuf.storage = (char *) oballoc (0);
1249
1250 /* Reset the hard register usage information. */
1251 CLEAR_HARD_REG_SET (newpat_used_regs);

--- 16 unchanged lines hidden (view full) ---

1268 We make very conservative checks below and only try to handle the
1269 most common cases of this. For example, we only handle the case
1270 where I2 and I3 are adjacent to avoid making difficult register
1271 usage tests. */
1272
1273 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1274 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1275 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1380 undobuf.other_insn = 0;
1381
1382 /* Save the current high-water-mark so we can free storage if we didn't
1383 accept this combination. */
1384 undobuf.storage = (char *) oballoc (0);
1385
1386 /* Reset the hard register usage information. */
1387 CLEAR_HARD_REG_SET (newpat_used_regs);

--- 16 unchanged lines hidden (view full) ---

1404 We make very conservative checks below and only try to handle the
1405 most common cases of this. For example, we only handle the case
1406 where I2 and I3 are adjacent to avoid making difficult register
1407 usage tests. */
1408
1409 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1410 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1411 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1276#ifdef SMALL_REGISTER_CLASSES
1277 && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1278 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1279 || REG_USERVAR_P (SET_DEST (PATTERN (i3))))
1280#endif
1412 && (! SMALL_REGISTER_CLASSES
1413 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1414 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1415 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1281 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1282 && GET_CODE (PATTERN (i2)) == PARALLEL
1283 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1284 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1285 below would need to check what is inside (and reg_overlap_mentioned_p
1286 doesn't support those codes anyway). Don't allow those destinations;
1287 the resulting insn isn't likely to be recognized anyway. */
1288 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT

--- 10 unchanged lines hidden (view full) ---

1299 (parallel [(set (mem (reg 69)) ...)
1300 (set (reg 69) ...)])
1301 which is not well-defined as to order of actions.
1302 (Besides, reload can't handle output reloads for this.)
1303
1304 The problem can also happen if the dest of I3 is a memory ref,
1305 if another dest in I2 is an indirect memory ref. */
1306 for (i = 0; i < XVECLEN (p2, 0); i++)
1416 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1417 && GET_CODE (PATTERN (i2)) == PARALLEL
1418 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1419 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1420 below would need to check what is inside (and reg_overlap_mentioned_p
1421 doesn't support those codes anyway). Don't allow those destinations;
1422 the resulting insn isn't likely to be recognized anyway. */
1423 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT

--- 10 unchanged lines hidden (view full) ---

1434 (parallel [(set (mem (reg 69)) ...)
1435 (set (reg 69) ...)])
1436 which is not well-defined as to order of actions.
1437 (Besides, reload can't handle output reloads for this.)
1438
1439 The problem can also happen if the dest of I3 is a memory ref,
1440 if another dest in I2 is an indirect memory ref. */
1441 for (i = 0; i < XVECLEN (p2, 0); i++)
1307 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
1442 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1443 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1308 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1309 SET_DEST (XVECEXP (p2, 0, i))))
1310 break;
1311
1312 if (i == XVECLEN (p2, 0))
1313 for (i = 0; i < XVECLEN (p2, 0); i++)
1314 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1315 {

--- 50 unchanged lines hidden (view full) ---

1366 if (i == 1)
1367 {
1368 /* We make I1 with the same INSN_UID as I2. This gives it
1369 the same INSN_CUID for value tracking. Our fake I1 will
1370 never appear in the insn stream so giving it the same INSN_UID
1371 as I2 will not cause a problem. */
1372
1373 subst_prev_insn = i1
1444 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1445 SET_DEST (XVECEXP (p2, 0, i))))
1446 break;
1447
1448 if (i == XVECLEN (p2, 0))
1449 for (i = 0; i < XVECLEN (p2, 0); i++)
1450 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1451 {

--- 50 unchanged lines hidden (view full) ---

1502 if (i == 1)
1503 {
1504 /* We make I1 with the same INSN_UID as I2. This gives it
1505 the same INSN_CUID for value tracking. Our fake I1 will
1506 never appear in the insn stream so giving it the same INSN_UID
1507 as I2 will not cause a problem. */
1508
1509 subst_prev_insn = i1
1374 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1375 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1510 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1511 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1512 NULL_RTX);
1376
1377 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1378 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1379 SET_DEST (PATTERN (i1)));
1380 }
1381 }
1382#endif
1383

--- 80 unchanged lines hidden (view full) ---

1464 /* If the set in I2 needs to be kept around, we must make a copy of
1465 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1466 PATTERN (I2), we are only substituting for the original I1DEST, not into
1467 an already-substituted copy. This also prevents making self-referential
1468 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1469 I2DEST. */
1470
1471 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1513
1514 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1515 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1516 SET_DEST (PATTERN (i1)));
1517 }
1518 }
1519#endif
1520

--- 80 unchanged lines hidden (view full) ---

1601 /* If the set in I2 needs to be kept around, we must make a copy of
1602 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1603 PATTERN (I2), we are only substituting for the original I1DEST, not into
1604 an already-substituted copy. This also prevents making self-referential
1605 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1606 I2DEST. */
1607
1608 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1472 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1609 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1473 : PATTERN (i2));
1474
1475 if (added_sets_2)
1476 i2pat = copy_rtx (i2pat);
1477
1478 combine_merges++;
1479
1480 /* Substitute in the latest insn for the regs set by the earlier ones. */

--- 27 unchanged lines hidden (view full) ---

1508 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1509 }
1510 else
1511 {
1512 subst_low_cuid = INSN_CUID (i2);
1513 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1514 }
1515
1610 : PATTERN (i2));
1611
1612 if (added_sets_2)
1613 i2pat = copy_rtx (i2pat);
1614
1615 combine_merges++;
1616
1617 /* Substitute in the latest insn for the regs set by the earlier ones. */

--- 27 unchanged lines hidden (view full) ---

1645 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1646 }
1647 else
1648 {
1649 subst_low_cuid = INSN_CUID (i2);
1650 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1651 }
1652
1516 previous_num_undos = undobuf.num_undo;
1653 undobuf.previous_undos = undobuf.undos;
1517 }
1518
1519#ifndef HAVE_cc0
1520 /* Many machines that don't use CC0 have insns that can both perform an
1521 arithmetic operation and set the condition code. These operations will
1522 be represented as a PARALLEL with the first element of the vector
1523 being a COMPARE of an arithmetic operation with the constant zero.
1524 The second element of the vector will set some pseudo to the result
1525 of the same arithmetic operation. If we simplify the COMPARE, we won't
1526 match such a pattern and so will generate an extra insn. Here we test
1527 for this case, where both the comparison and the operation result are
1528 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1529 I2SRC. Later we will make the PARALLEL that contains I2. */
1530
1531 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1532 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1533 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1534 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1535 {
1654 }
1655
1656#ifndef HAVE_cc0
1657 /* Many machines that don't use CC0 have insns that can both perform an
1658 arithmetic operation and set the condition code. These operations will
1659 be represented as a PARALLEL with the first element of the vector
1660 being a COMPARE of an arithmetic operation with the constant zero.
1661 The second element of the vector will set some pseudo to the result
1662 of the same arithmetic operation. If we simplify the COMPARE, we won't
1663 match such a pattern and so will generate an extra insn. Here we test
1664 for this case, where both the comparison and the operation result are
1665 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1666 I2SRC. Later we will make the PARALLEL that contains I2. */
1667
1668 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1669 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1670 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1671 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1672 {
1673#ifdef EXTRA_CC_MODES
1536 rtx *cc_use;
1537 enum machine_mode compare_mode;
1674 rtx *cc_use;
1675 enum machine_mode compare_mode;
1676#endif
1538
1539 newpat = PATTERN (i3);
1540 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1541
1542 i2_is_used = 1;
1543
1544#ifdef EXTRA_CC_MODES
1545 /* See if a COMPARE with the operand we substituted in should be done

--- 4 unchanged lines hidden (view full) ---

1550 if (undobuf.other_insn == 0
1551 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1552 &undobuf.other_insn))
1553 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1554 i2src, const0_rtx))
1555 != GET_MODE (SET_DEST (newpat))))
1556 {
1557 int regno = REGNO (SET_DEST (newpat));
1677
1678 newpat = PATTERN (i3);
1679 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1680
1681 i2_is_used = 1;
1682
1683#ifdef EXTRA_CC_MODES
1684 /* See if a COMPARE with the operand we substituted in should be done

--- 4 unchanged lines hidden (view full) ---

1689 if (undobuf.other_insn == 0
1690 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1691 &undobuf.other_insn))
1692 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1693 i2src, const0_rtx))
1694 != GET_MODE (SET_DEST (newpat))))
1695 {
1696 int regno = REGNO (SET_DEST (newpat));
1558 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1697 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1559
1560 if (regno < FIRST_PSEUDO_REGISTER
1698
1699 if (regno < FIRST_PSEUDO_REGISTER
1561 || (reg_n_sets[regno] == 1 && ! added_sets_2
1700 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1562 && ! REG_USERVAR_P (SET_DEST (newpat))))
1563 {
1564 if (regno >= FIRST_PSEUDO_REGISTER)
1565 SUBST (regno_reg_rtx[regno], new_dest);
1566
1567 SUBST (SET_DEST (newpat), new_dest);
1568 SUBST (XEXP (*cc_use, 0), new_dest);
1569 SUBST (SET_SRC (newpat),

--- 12 unchanged lines hidden (view full) ---

1582
1583 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1584 need to make a unique copy of I2SRC each time we substitute it
1585 to avoid self-referential rtl. */
1586
1587 subst_low_cuid = INSN_CUID (i2);
1588 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1589 ! i1_feeds_i3 && i1dest_in_i1src);
1701 && ! REG_USERVAR_P (SET_DEST (newpat))))
1702 {
1703 if (regno >= FIRST_PSEUDO_REGISTER)
1704 SUBST (regno_reg_rtx[regno], new_dest);
1705
1706 SUBST (SET_DEST (newpat), new_dest);
1707 SUBST (XEXP (*cc_use, 0), new_dest);
1708 SUBST (SET_SRC (newpat),

--- 12 unchanged lines hidden (view full) ---

1721
1722 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1723 need to make a unique copy of I2SRC each time we substitute it
1724 to avoid self-referential rtl. */
1725
1726 subst_low_cuid = INSN_CUID (i2);
1727 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1728 ! i1_feeds_i3 && i1dest_in_i1src);
1590 previous_num_undos = undobuf.num_undo;
1729 undobuf.previous_undos = undobuf.undos;
1591
1592 /* Record whether i2's body now appears within i3's body. */
1593 i2_is_used = n_occurrences;
1594 }
1595
1596 /* If we already got a failure, don't try to do more. Otherwise,
1597 try to substitute in I1 if we have it. */
1598
1599 if (i1 && GET_CODE (newpat) != CLOBBER)
1600 {
1601 /* Before we can do this substitution, we must redo the test done
1602 above (see detailed comments there) that ensures that I1DEST
1730
1731 /* Record whether i2's body now appears within i3's body. */
1732 i2_is_used = n_occurrences;
1733 }
1734
1735 /* If we already got a failure, don't try to do more. Otherwise,
1736 try to substitute in I1 if we have it. */
1737
1738 if (i1 && GET_CODE (newpat) != CLOBBER)
1739 {
1740 /* Before we can do this substitution, we must redo the test done
1741 above (see detailed comments there) that ensures that I1DEST
1603 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1742 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1604
1605 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1606 0, NULL_PTR))
1607 {
1608 undo_all ();
1609 return 0;
1610 }
1611
1612 n_occurrences = 0;
1613 subst_low_cuid = INSN_CUID (i1);
1614 newpat = subst (newpat, i1dest, i1src, 0, 0);
1743
1744 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1745 0, NULL_PTR))
1746 {
1747 undo_all ();
1748 return 0;
1749 }
1750
1751 n_occurrences = 0;
1752 subst_low_cuid = INSN_CUID (i1);
1753 newpat = subst (newpat, i1dest, i1src, 0, 0);
1615 previous_num_undos = undobuf.num_undo;
1754 undobuf.previous_undos = undobuf.undos;
1616 }
1617
1618 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1619 to count all the ways that I2SRC and I1SRC can be used. */
1620 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1621 && i2_is_used + added_sets_2 > 1)
1622 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1623 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)

--- 20 unchanged lines hidden (view full) ---

1644 if (added_sets_1 || added_sets_2)
1645 {
1646 combine_extras++;
1647
1648 if (GET_CODE (newpat) == PARALLEL)
1649 {
1650 rtvec old = XVEC (newpat, 0);
1651 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1755 }
1756
1757 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1758 to count all the ways that I2SRC and I1SRC can be used. */
1759 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1760 && i2_is_used + added_sets_2 > 1)
1761 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1762 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)

--- 20 unchanged lines hidden (view full) ---

1783 if (added_sets_1 || added_sets_2)
1784 {
1785 combine_extras++;
1786
1787 if (GET_CODE (newpat) == PARALLEL)
1788 {
1789 rtvec old = XVEC (newpat, 0);
1790 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1652 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1653 bcopy ((char *) &old->elem[0], (char *) &XVECEXP (newpat, 0, 0),
1791 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1792 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1654 sizeof (old->elem[0]) * old->num_elem);
1655 }
1656 else
1657 {
1658 rtx old = newpat;
1659 total_sets = 1 + added_sets_1 + added_sets_2;
1793 sizeof (old->elem[0]) * old->num_elem);
1794 }
1795 else
1796 {
1797 rtx old = newpat;
1798 total_sets = 1 + added_sets_1 + added_sets_2;
1660 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1799 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1661 XVECEXP (newpat, 0, 0) = old;
1662 }
1663
1664 if (added_sets_1)
1665 XVECEXP (newpat, 0, --total_sets)
1666 = (GET_CODE (PATTERN (i1)) == PARALLEL
1800 XVECEXP (newpat, 0, 0) = old;
1801 }
1802
1803 if (added_sets_1)
1804 XVECEXP (newpat, 0, --total_sets)
1805 = (GET_CODE (PATTERN (i1)) == PARALLEL
1667 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1806 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
1668
1669 if (added_sets_2)
1670 {
1671 /* If there is no I1, use I2's body as is. We used to also not do
1672 the subst call below if I2 was substituted into I3,
1673 but that could lose a simplification. */
1674 if (i1 == 0)
1675 XVECEXP (newpat, 0, --total_sets) = i2pat;

--- 80 unchanged lines hidden (view full) ---

1756 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1757 {
1758 /* If I2DEST is a hard register or the only use of a pseudo,
1759 we can change its mode. */
1760 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1761 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1762 && GET_CODE (i2dest) == REG
1763 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1807
1808 if (added_sets_2)
1809 {
1810 /* If there is no I1, use I2's body as is. We used to also not do
1811 the subst call below if I2 was substituted into I3,
1812 but that could lose a simplification. */
1813 if (i1 == 0)
1814 XVECEXP (newpat, 0, --total_sets) = i2pat;

--- 80 unchanged lines hidden (view full) ---

1895 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1896 {
1897 /* If I2DEST is a hard register or the only use of a pseudo,
1898 we can change its mode. */
1899 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1900 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1901 && GET_CODE (i2dest) == REG
1902 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1764 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1903 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1765 && ! REG_USERVAR_P (i2dest))))
1904 && ! REG_USERVAR_P (i2dest))))
1766 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1905 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
1767 REGNO (i2dest));
1768
1906 REGNO (i2dest));
1907
1769 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1770 gen_rtvec (2, newpat,
1771 gen_rtx (CLOBBER,
1772 VOIDmode,
1773 ni2dest))),
1774 i3);
1908 m_split = split_insns
1909 (gen_rtx_PARALLEL (VOIDmode,
1910 gen_rtvec (2, newpat,
1911 gen_rtx_CLOBBER (VOIDmode,
1912 ni2dest))),
1913 i3);
1775 }
1776
1777 if (m_split && GET_CODE (m_split) == SEQUENCE
1778 && XVECLEN (m_split, 0) == 2
1779 && (next_real_insn (i2) == i3
1780 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1781 INSN_CUID (i2))))
1782 {

--- 10 unchanged lines hidden (view full) ---

1793
1794 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1795 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1796
1797 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1798 &i2_scratches);
1799
1800 /* If I2 or I3 has multiple SETs, we won't know how to track
1914 }
1915
1916 if (m_split && GET_CODE (m_split) == SEQUENCE
1917 && XVECLEN (m_split, 0) == 2
1918 && (next_real_insn (i2) == i3
1919 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1920 INSN_CUID (i2))))
1921 {

--- 10 unchanged lines hidden (view full) ---

1932
1933 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1934 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1935
1936 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1937 &i2_scratches);
1938
1939 /* If I2 or I3 has multiple SETs, we won't know how to track
1801 register status, so don't use these insns. */
1940 register status, so don't use these insns. If I2's destination
1941 is used between I2 and I3, we also can't use these insns. */
1802
1942
1803 if (i2_code_number >= 0 && i2set && i3set)
1943 if (i2_code_number >= 0 && i2set && i3set
1944 && (next_real_insn (i2) == i3
1945 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1804 insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1805 &i3_scratches);
1806 if (insn_code_number >= 0)
1807 newpat = newi3pat;
1808
1809 /* It is possible that both insns now set the destination of I3.
1810 If so, we must show an extra use of it. */
1811
1946 insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1947 &i3_scratches);
1948 if (insn_code_number >= 0)
1949 newpat = newi3pat;
1950
1951 /* It is possible that both insns now set the destination of I3.
1952 If so, we must show an extra use of it. */
1953
1812 if (insn_code_number >= 0 && GET_CODE (SET_DEST (i3set)) == REG
1813 && GET_CODE (SET_DEST (i2set)) == REG
1814 && REGNO (SET_DEST (i3set)) == REGNO (SET_DEST (i2set)))
1815 reg_n_sets[REGNO (SET_DEST (i2set))]++;
1954 if (insn_code_number >= 0)
1955 {
1956 rtx new_i3_dest = SET_DEST (i3set);
1957 rtx new_i2_dest = SET_DEST (i2set);
1958
1959 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1960 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1961 || GET_CODE (new_i3_dest) == SUBREG)
1962 new_i3_dest = XEXP (new_i3_dest, 0);
1963
1964 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1965 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1966 || GET_CODE (new_i2_dest) == SUBREG)
1967 new_i2_dest = XEXP (new_i2_dest, 0);
1968
1969 if (GET_CODE (new_i3_dest) == REG
1970 && GET_CODE (new_i2_dest) == REG
1971 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
1972 REG_N_SETS (REGNO (new_i2_dest))++;
1973 }
1816 }
1817
1818 /* If we can split it and use I2DEST, go ahead and see if that
1819 helps things be recognized. Verify that none of the registers
1820 are set between I2 and I3. */
1821 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1822#ifdef HAVE_cc0
1823 && GET_CODE (i2dest) == REG
1824#endif
1825 /* We need I2DEST in the proper mode. If it is a hard register
1826 or the only use of a pseudo, we can change its mode. */
1827 && (GET_MODE (*split) == GET_MODE (i2dest)
1828 || GET_MODE (*split) == VOIDmode
1829 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1974 }
1975
1976 /* If we can split it and use I2DEST, go ahead and see if that
1977 helps things be recognized. Verify that none of the registers
1978 are set between I2 and I3. */
1979 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1980#ifdef HAVE_cc0
1981 && GET_CODE (i2dest) == REG
1982#endif
1983 /* We need I2DEST in the proper mode. If it is a hard register
1984 or the only use of a pseudo, we can change its mode. */
1985 && (GET_MODE (*split) == GET_MODE (i2dest)
1986 || GET_MODE (*split) == VOIDmode
1987 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1830 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1988 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1831 && ! REG_USERVAR_P (i2dest)))
1832 && (next_real_insn (i2) == i3
1833 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1834 /* We can't overwrite I2DEST if its value is still used by
1835 NEWPAT. */
1836 && ! reg_referenced_p (i2dest, newpat))
1837 {
1838 rtx newdest = i2dest;
1839 enum rtx_code split_code = GET_CODE (*split);
1840 enum machine_mode split_mode = GET_MODE (*split);
1841
1842 /* Get NEWDEST as a register in the proper mode. We have already
1843 validated that we can do this. */
1844 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
1845 {
1989 && ! REG_USERVAR_P (i2dest)))
1990 && (next_real_insn (i2) == i3
1991 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1992 /* We can't overwrite I2DEST if its value is still used by
1993 NEWPAT. */
1994 && ! reg_referenced_p (i2dest, newpat))
1995 {
1996 rtx newdest = i2dest;
1997 enum rtx_code split_code = GET_CODE (*split);
1998 enum machine_mode split_mode = GET_MODE (*split);
1999
2000 /* Get NEWDEST as a register in the proper mode. We have already
2001 validated that we can do this. */
2002 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2003 {
1846 newdest = gen_rtx (REG, split_mode, REGNO (i2dest));
2004 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
1847
1848 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1849 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1850 }
1851
1852 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1853 an ASHIFT. This can occur if it was inside a PLUS and hence
1854 appeared to be a memory address. This is a kludge. */

--- 96 unchanged lines hidden (view full) ---

1951 to I3. No other part of combine.c makes such a transformation.
1952
1953 The new I3 will have a destination that was previously the
1954 destination of I1 or I2 and which was used in i2 or I3. Call
1955 distribute_links to make a LOG_LINK from the next use of
1956 that destination. */
1957
1958 PATTERN (i3) = newpat;
2005
2006 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2007 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2008 }
2009
2010 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2011 an ASHIFT. This can occur if it was inside a PLUS and hence
2012 appeared to be a memory address. This is a kludge. */

--- 96 unchanged lines hidden (view full) ---

2109 to I3. No other part of combine.c makes such a transformation.
2110
2111 The new I3 will have a destination that was previously the
2112 destination of I1 or I2 and which was used in i2 or I3. Call
2113 distribute_links to make a LOG_LINK from the next use of
2114 that destination. */
2115
2116 PATTERN (i3) = newpat;
1959 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
2117 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
1960
1961 /* I3 now uses what used to be its destination and which is
1962 now I2's destination. That means we need a LOG_LINK from
1963 I3 to I2. But we used to have one, so we still will.
1964
1965 However, some later insn might be using I2's dest and have
1966 a LOG_LINK pointing at I3. We must remove this link.
1967 The simplest way to remove the link is to point it at I1,

--- 37 unchanged lines hidden (view full) ---

2005 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2006 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2007 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2008 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2009 XVECEXP (newpat, 0, 0))
2010 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2011 XVECEXP (newpat, 0, 1)))
2012 {
2118
2119 /* I3 now uses what used to be its destination and which is
2120 now I2's destination. That means we need a LOG_LINK from
2121 I3 to I2. But we used to have one, so we still will.
2122
2123 However, some later insn might be using I2's dest and have
2124 a LOG_LINK pointing at I3. We must remove this link.
2125 The simplest way to remove the link is to point it at I1,

--- 37 unchanged lines hidden (view full) ---

2163 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2164 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2165 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2166 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2167 XVECEXP (newpat, 0, 0))
2168 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2169 XVECEXP (newpat, 0, 1)))
2170 {
2013 newi2pat = XVECEXP (newpat, 0, 1);
2014 newpat = XVECEXP (newpat, 0, 0);
2171 /* Normally, it doesn't matter which of the two is done first,
2172 but it does if one references cc0. In that case, it has to
2173 be first. */
2174#ifdef HAVE_cc0
2175 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2176 {
2177 newi2pat = XVECEXP (newpat, 0, 0);
2178 newpat = XVECEXP (newpat, 0, 1);
2179 }
2180 else
2181#endif
2182 {
2183 newi2pat = XVECEXP (newpat, 0, 1);
2184 newpat = XVECEXP (newpat, 0, 0);
2185 }
2015
2016 i2_code_number
2017 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2018
2019 if (i2_code_number >= 0)
2020 insn_code_number
2021 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2022 }

--- 35 unchanged lines hidden (view full) ---

2058 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2059 {
2060 next = XEXP (note, 1);
2061
2062 if (REG_NOTE_KIND (note) == REG_UNUSED
2063 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2064 {
2065 if (GET_CODE (XEXP (note, 0)) == REG)
2186
2187 i2_code_number
2188 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2189
2190 if (i2_code_number >= 0)
2191 insn_code_number
2192 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2193 }

--- 35 unchanged lines hidden (view full) ---

2229 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2230 {
2231 next = XEXP (note, 1);
2232
2233 if (REG_NOTE_KIND (note) == REG_UNUSED
2234 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2235 {
2236 if (GET_CODE (XEXP (note, 0)) == REG)
2066 reg_n_deaths[REGNO (XEXP (note, 0))]--;
2237 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2067
2068 remove_note (undobuf.other_insn, note);
2069 }
2070 }
2071
2072 for (note = new_other_notes; note; note = XEXP (note, 1))
2073 if (GET_CODE (XEXP (note, 0)) == REG)
2238
2239 remove_note (undobuf.other_insn, note);
2240 }
2241 }
2242
2243 for (note = new_other_notes; note; note = XEXP (note, 1))
2244 if (GET_CODE (XEXP (note, 0)) == REG)
2074 reg_n_deaths[REGNO (XEXP (note, 0))]++;
2245 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2075
2076 distribute_notes (new_other_notes, undobuf.other_insn,
2077 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2078 }
2079
2080 /* We now know that we can do this combination. Merge the insns and
2081 update the status of registers and LOG_LINKS. */
2082
2083 {
2084 rtx i3notes, i2notes, i1notes = 0;
2085 rtx i3links, i2links, i1links = 0;
2086 rtx midnotes = 0;
2087 register int regno;
2246
2247 distribute_notes (new_other_notes, undobuf.other_insn,
2248 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2249 }
2250
2251 /* We now know that we can do this combination. Merge the insns and
2252 update the status of registers and LOG_LINKS. */
2253
2254 {
2255 rtx i3notes, i2notes, i1notes = 0;
2256 rtx i3links, i2links, i1links = 0;
2257 rtx midnotes = 0;
2258 register int regno;
2088 /* Compute which registers we expect to eliminate. */
2089 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
2259 /* Compute which registers we expect to eliminate. newi2pat may be setting
2260 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2261 same as i3dest, in which case newi2pat may be setting i1dest. */
2262 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2263 || i2dest_in_i2src || i2dest_in_i1src
2090 ? 0 : i2dest);
2264 ? 0 : i2dest);
2091 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
2265 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2266 || (newi2pat && reg_set_p (i1dest, newi2pat))
2267 ? 0 : i1dest);
2092
2093 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2094 clear them. */
2095 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2096 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2097 if (i1)
2098 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2099

--- 81 unchanged lines hidden (view full) ---

2181 LOG_LINKS (i1) = 0;
2182 REG_NOTES (i1) = 0;
2183 PUT_CODE (i1, NOTE);
2184 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2185 NOTE_SOURCE_FILE (i1) = 0;
2186 }
2187
2188 /* Get death notes for everything that is now used in either I3 or
2268
2269 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2270 clear them. */
2271 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2272 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2273 if (i1)
2274 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2275

--- 81 unchanged lines hidden (view full) ---

2357 LOG_LINKS (i1) = 0;
2358 REG_NOTES (i1) = 0;
2359 PUT_CODE (i1, NOTE);
2360 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2361 NOTE_SOURCE_FILE (i1) = 0;
2362 }
2363
2364 /* Get death notes for everything that is now used in either I3 or
2189 I2 and used to die in a previous insn. */
2365 I2 and used to die in a previous insn. If we built two new
2366 patterns, move from I1 to I2 then I2 to I3 so that we get the
2367 proper movement on registers that I2 modifies. */
2190
2368
2191 move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes);
2192 if (newi2pat)
2369 if (newi2pat)
2193 move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes);
2370 {
2371 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2372 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2373 }
2374 else
2375 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2376 i3, &midnotes);
2194
2195 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2196 if (i3notes)
2197 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2198 elim_i2, elim_i1);
2199 if (i2notes)
2200 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2201 elim_i2, elim_i1);

--- 8 unchanged lines hidden (view full) ---

2210 know these are REG_UNUSED and want them to go to the desired insn,
2211 so we always pass it as i3. We have not counted the notes in
2212 reg_n_deaths yet, so we need to do so now. */
2213
2214 if (newi2pat && new_i2_notes)
2215 {
2216 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2217 if (GET_CODE (XEXP (temp, 0)) == REG)
2377
2378 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2379 if (i3notes)
2380 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2381 elim_i2, elim_i1);
2382 if (i2notes)
2383 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2384 elim_i2, elim_i1);

--- 8 unchanged lines hidden (view full) ---

2393 know these are REG_UNUSED and want them to go to the desired insn,
2394 so we always pass it as i3. We have not counted the notes in
2395 reg_n_deaths yet, so we need to do so now. */
2396
2397 if (newi2pat && new_i2_notes)
2398 {
2399 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2400 if (GET_CODE (XEXP (temp, 0)) == REG)
2218 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2401 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2219
2220 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2221 }
2222
2223 if (new_i3_notes)
2224 {
2225 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2226 if (GET_CODE (XEXP (temp, 0)) == REG)
2402
2403 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2404 }
2405
2406 if (new_i3_notes)
2407 {
2408 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2409 if (GET_CODE (XEXP (temp, 0)) == REG)
2227 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2410 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2228
2229 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2230 }
2231
2232 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2411
2412 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2413 }
2414
2415 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2233 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
2416 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2417 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2418 in that case, it might delete I2. Similarly for I2 and I1.
2234 Show an additional death due to the REG_DEAD note we make here. If
2235 we discard it in distribute_notes, we will decrement it again. */
2236
2237 if (i3dest_killed)
2238 {
2239 if (GET_CODE (i3dest_killed) == REG)
2419 Show an additional death due to the REG_DEAD note we make here. If
2420 we discard it in distribute_notes, we will decrement it again. */
2421
2422 if (i3dest_killed)
2423 {
2424 if (GET_CODE (i3dest_killed) == REG)
2240 reg_n_deaths[REGNO (i3dest_killed)]++;
2425 REG_N_DEATHS (REGNO (i3dest_killed))++;
2241
2426
2242 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2243 NULL_RTX),
2244 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2245 NULL_RTX, NULL_RTX);
2427 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2428 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2429 NULL_RTX),
2430 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2431 else
2432 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2433 NULL_RTX),
2434 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2435 elim_i2, elim_i1);
2246 }
2247
2436 }
2437
2248 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
2249 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
2250 we passed I3 in that case, it might delete I2. */
2251
2252 if (i2dest_in_i2src)
2253 {
2254 if (GET_CODE (i2dest) == REG)
2438 if (i2dest_in_i2src)
2439 {
2440 if (GET_CODE (i2dest) == REG)
2255 reg_n_deaths[REGNO (i2dest)]++;
2441 REG_N_DEATHS (REGNO (i2dest))++;
2256
2257 if (newi2pat && reg_set_p (i2dest, newi2pat))
2442
2443 if (newi2pat && reg_set_p (i2dest, newi2pat))
2258 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2444 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2259 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2260 else
2445 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2446 else
2261 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2447 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2262 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2263 NULL_RTX, NULL_RTX);
2264 }
2265
2266 if (i1dest_in_i1src)
2267 {
2268 if (GET_CODE (i1dest) == REG)
2448 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2449 NULL_RTX, NULL_RTX);
2450 }
2451
2452 if (i1dest_in_i1src)
2453 {
2454 if (GET_CODE (i1dest) == REG)
2269 reg_n_deaths[REGNO (i1dest)]++;
2455 REG_N_DEATHS (REGNO (i1dest))++;
2270
2271 if (newi2pat && reg_set_p (i1dest, newi2pat))
2456
2457 if (newi2pat && reg_set_p (i1dest, newi2pat))
2272 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2458 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2273 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2274 else
2459 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2460 else
2275 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2461 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2276 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2277 NULL_RTX, NULL_RTX);
2278 }
2279
2280 distribute_links (i3links);
2281 distribute_links (i2links);
2282 distribute_links (i1links);
2283

--- 14 unchanged lines hidden (view full) ---

2298 if ((set = single_set (XEXP (link, 0))) != 0
2299 && rtx_equal_p (i2dest, SET_DEST (set)))
2300 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2301
2302 record_value_for_reg (i2dest, i2_insn, i2_val);
2303
2304 /* If the reg formerly set in I2 died only once and that was in I3,
2305 zero its use count so it won't make `reload' do any work. */
2462 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2463 NULL_RTX, NULL_RTX);
2464 }
2465
2466 distribute_links (i3links);
2467 distribute_links (i2links);
2468 distribute_links (i1links);
2469

--- 14 unchanged lines hidden (view full) ---

2484 if ((set = single_set (XEXP (link, 0))) != 0
2485 && rtx_equal_p (i2dest, SET_DEST (set)))
2486 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2487
2488 record_value_for_reg (i2dest, i2_insn, i2_val);
2489
2490 /* If the reg formerly set in I2 died only once and that was in I3,
2491 zero its use count so it won't make `reload' do any work. */
2306 if (! added_sets_2 && newi2pat == 0 && ! i2dest_in_i2src)
2492 if (! added_sets_2
2493 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2494 && ! i2dest_in_i2src)
2307 {
2308 regno = REGNO (i2dest);
2495 {
2496 regno = REGNO (i2dest);
2309 reg_n_sets[regno]--;
2310 if (reg_n_sets[regno] == 0
2311 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2312 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2313 reg_n_refs[regno] = 0;
2497 REG_N_SETS (regno)--;
2498 if (REG_N_SETS (regno) == 0
2499 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2500 REG_N_REFS (regno) = 0;
2314 }
2315 }
2316
2317 if (i1 && GET_CODE (i1dest) == REG)
2318 {
2319 rtx link;
2320 rtx i1_insn = 0, i1_val = 0, set;
2321
2322 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2323 if ((set = single_set (XEXP (link, 0))) != 0
2324 && rtx_equal_p (i1dest, SET_DEST (set)))
2325 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2326
2327 record_value_for_reg (i1dest, i1_insn, i1_val);
2328
2329 regno = REGNO (i1dest);
2330 if (! added_sets_1 && ! i1dest_in_i1src)
2331 {
2501 }
2502 }
2503
2504 if (i1 && GET_CODE (i1dest) == REG)
2505 {
2506 rtx link;
2507 rtx i1_insn = 0, i1_val = 0, set;
2508
2509 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2510 if ((set = single_set (XEXP (link, 0))) != 0
2511 && rtx_equal_p (i1dest, SET_DEST (set)))
2512 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2513
2514 record_value_for_reg (i1dest, i1_insn, i1_val);
2515
2516 regno = REGNO (i1dest);
2517 if (! added_sets_1 && ! i1dest_in_i1src)
2518 {
2332 reg_n_sets[regno]--;
2333 if (reg_n_sets[regno] == 0
2334 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2335 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2336 reg_n_refs[regno] = 0;
2519 REG_N_SETS (regno)--;
2520 if (REG_N_SETS (regno) == 0
2521 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2522 REG_N_REFS (regno) = 0;
2337 }
2338 }
2339
2340 /* Update reg_nonzero_bits et al for any changes that may have been made
2341 to this insn. */
2342
2343 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2344 if (newi2pat)

--- 29 unchanged lines hidden (view full) ---

2374 return newi2pat ? i2 : i3;
2375}
2376
2377/* Undo all the modifications recorded in undobuf. */
2378
2379static void
2380undo_all ()
2381{
2523 }
2524 }
2525
2526 /* Update reg_nonzero_bits et al for any changes that may have been made
2527 to this insn. */
2528
2529 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2530 if (newi2pat)

--- 29 unchanged lines hidden (view full) ---

2560 return newi2pat ? i2 : i3;
2561}
2562
2563/* Undo all the modifications recorded in undobuf. */
2564
2565static void
2566undo_all ()
2567{
2382 register int i;
2383 if (undobuf.num_undo > MAX_UNDO)
2384 undobuf.num_undo = MAX_UNDO;
2385 for (i = undobuf.num_undo - 1; i >= 0; i--)
2568 struct undo *undo, *next;
2569
2570 for (undo = undobuf.undos; undo; undo = next)
2386 {
2571 {
2387 if (undobuf.undo[i].is_int)
2388 *undobuf.undo[i].where.i = undobuf.undo[i].old_contents.i;
2572 next = undo->next;
2573 if (undo->is_int)
2574 *undo->where.i = undo->old_contents.i;
2389 else
2575 else
2390 *undobuf.undo[i].where.r = undobuf.undo[i].old_contents.r;
2391
2576 *undo->where.r = undo->old_contents.r;
2577
2578 undo->next = undobuf.frees;
2579 undobuf.frees = undo;
2392 }
2393
2394 obfree (undobuf.storage);
2580 }
2581
2582 obfree (undobuf.storage);
2395 undobuf.num_undo = 0;
2583 undobuf.undos = undobuf.previous_undos = 0;
2396
2397 /* Clear this here, so that subsequent get_last_value calls are not
2398 affected. */
2399 subst_prev_insn = NULL_RTX;
2400}
2401
2402/* Find the innermost point within the rtx at LOC, possibly LOC itself,
2403 where we have an arithmetic expression and return that point. LOC will

--- 45 unchanged lines hidden (view full) ---

2449 the machine-specific way to split large constants. We use
2450 the first pseudo-reg (one of the virtual regs) as a placeholder;
2451 it will not remain in the result. */
2452 if (GET_CODE (XEXP (x, 0)) == PLUS
2453 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2454 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2455 {
2456 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2584
2585 /* Clear this here, so that subsequent get_last_value calls are not
2586 affected. */
2587 subst_prev_insn = NULL_RTX;
2588}
2589
2590/* Find the innermost point within the rtx at LOC, possibly LOC itself,
2591 where we have an arithmetic expression and return that point. LOC will

--- 45 unchanged lines hidden (view full) ---

2637 the machine-specific way to split large constants. We use
2638 the first pseudo-reg (one of the virtual regs) as a placeholder;
2639 it will not remain in the result. */
2640 if (GET_CODE (XEXP (x, 0)) == PLUS
2641 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2642 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2643 {
2644 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2457 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2645 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2458 subst_insn);
2459
2460 /* This should have produced two insns, each of which sets our
2461 placeholder. If the source of the second is a valid address,
2462 we can make put both sources together and make a split point
2463 in the middle. */
2464
2465 if (seq && XVECLEN (seq, 0) == 2

--- 60 unchanged lines hidden (view full) ---

2526 return &SET_SRC (x);
2527#endif
2528
2529 /* See if we can split SET_SRC as it stands. */
2530 split = find_split_point (&SET_SRC (x), insn);
2531 if (split && split != &SET_SRC (x))
2532 return split;
2533
2646 subst_insn);
2647
2648 /* This should have produced two insns, each of which sets our
2649 placeholder. If the source of the second is a valid address,
2650 we can make put both sources together and make a split point
2651 in the middle. */
2652
2653 if (seq && XVECLEN (seq, 0) == 2

--- 60 unchanged lines hidden (view full) ---

2714 return &SET_SRC (x);
2715#endif
2716
2717 /* See if we can split SET_SRC as it stands. */
2718 split = find_split_point (&SET_SRC (x), insn);
2719 if (split && split != &SET_SRC (x))
2720 return split;
2721
2722 /* See if we can split SET_DEST as it stands. */
2723 split = find_split_point (&SET_DEST (x), insn);
2724 if (split && split != &SET_DEST (x))
2725 return split;
2726
2534 /* See if this is a bitfield assignment with everything constant. If
2535 so, this is an IOR of an AND, so split it into that. */
2536 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2537 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2538 <= HOST_BITS_PER_WIDE_INT)
2539 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2540 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2541 && GET_CODE (SET_SRC (x)) == CONST_INT

--- 50 unchanged lines hidden (view full) ---

2592 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2593 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2594 && GET_CODE (SET_DEST (x)) == REG
2595 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2596 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2597 && XEXP (*split, 0) == SET_DEST (x)
2598 && XEXP (*split, 1) == const0_rtx)
2599 {
2727 /* See if this is a bitfield assignment with everything constant. If
2728 so, this is an IOR of an AND, so split it into that. */
2729 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2730 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2731 <= HOST_BITS_PER_WIDE_INT)
2732 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2733 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2734 && GET_CODE (SET_SRC (x)) == CONST_INT

--- 50 unchanged lines hidden (view full) ---

2785 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2786 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2787 && GET_CODE (SET_DEST (x)) == REG
2788 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2789 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2790 && XEXP (*split, 0) == SET_DEST (x)
2791 && XEXP (*split, 1) == const0_rtx)
2792 {
2793 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2794 XEXP (SET_SRC (x), 0),
2795 pos, NULL_RTX, 1, 1, 0, 0);
2796 if (extraction != 0)
2797 {
2798 SUBST (SET_SRC (x), extraction);
2799 return find_split_point (loc, insn);
2800 }
2801 }
2802 break;
2803
2804 case NE:
2805 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2806 is known to be on, this can be converted into a NEG of a shift. */
2807 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2808 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
2809 && 1 <= (pos = exact_log2
2810 (nonzero_bits (XEXP (SET_SRC (x), 0),
2811 GET_MODE (XEXP (SET_SRC (x), 0))))))
2812 {
2813 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2814
2600 SUBST (SET_SRC (x),
2815 SUBST (SET_SRC (x),
2601 make_extraction (GET_MODE (SET_DEST (x)),
2602 XEXP (SET_SRC (x), 0),
2603 pos, NULL_RTX, 1, 1, 0, 0));
2604 return find_split_point (loc, insn);
2816 gen_rtx_combine (NEG, mode,
2817 gen_rtx_combine (LSHIFTRT, mode,
2818 XEXP (SET_SRC (x), 0),
2819 GEN_INT (pos))));
2820
2821 split = find_split_point (&SET_SRC (x), insn);
2822 if (split && split != &SET_SRC (x))
2823 return split;
2605 }
2606 break;
2607
2608 case SIGN_EXTEND:
2609 inner = XEXP (SET_SRC (x), 0);
2824 }
2825 break;
2826
2827 case SIGN_EXTEND:
2828 inner = XEXP (SET_SRC (x), 0);
2829
2830 /* We can't optimize if either mode is a partial integer
2831 mode as we don't know how many bits are significant
2832 in those modes. */
2833 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2834 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2835 break;
2836
2610 pos = 0;
2611 len = GET_MODE_BITSIZE (GET_MODE (inner));
2612 unsignedp = 0;
2613 break;
2614
2615 case SIGN_EXTRACT:
2616 case ZERO_EXTRACT:
2617 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2618 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2619 {
2620 inner = XEXP (SET_SRC (x), 0);
2621 len = INTVAL (XEXP (SET_SRC (x), 1));
2622 pos = INTVAL (XEXP (SET_SRC (x), 2));
2623
2624 if (BITS_BIG_ENDIAN)
2625 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2626 unsignedp = (code == ZERO_EXTRACT);
2627 }
2628 break;
2837 pos = 0;
2838 len = GET_MODE_BITSIZE (GET_MODE (inner));
2839 unsignedp = 0;
2840 break;
2841
2842 case SIGN_EXTRACT:
2843 case ZERO_EXTRACT:
2844 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2845 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2846 {
2847 inner = XEXP (SET_SRC (x), 0);
2848 len = INTVAL (XEXP (SET_SRC (x), 1));
2849 pos = INTVAL (XEXP (SET_SRC (x), 2));
2850
2851 if (BITS_BIG_ENDIAN)
2852 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2853 unsignedp = (code == ZERO_EXTRACT);
2854 }
2855 break;
2856
2857 default:
2858 break;
2629 }
2630
2631 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2632 {
2633 enum machine_mode mode = GET_MODE (SET_SRC (x));
2634
2635 /* For unsigned, we have a choice of a shift followed by an
2636 AND or two shifts. Use two shifts for field sizes where the

--- 80 unchanged lines hidden (view full) ---

2717 other operand first. */
2718 if (GET_CODE (XEXP (x, 1)) == NOT)
2719 {
2720 rtx tem = XEXP (x, 0);
2721 SUBST (XEXP (x, 0), XEXP (x, 1));
2722 SUBST (XEXP (x, 1), tem);
2723 }
2724 break;
2859 }
2860
2861 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2862 {
2863 enum machine_mode mode = GET_MODE (SET_SRC (x));
2864
2865 /* For unsigned, we have a choice of a shift followed by an
2866 AND or two shifts. Use two shifts for field sizes where the

--- 80 unchanged lines hidden (view full) ---

2947 other operand first. */
2948 if (GET_CODE (XEXP (x, 1)) == NOT)
2949 {
2950 rtx tem = XEXP (x, 0);
2951 SUBST (XEXP (x, 0), XEXP (x, 1));
2952 SUBST (XEXP (x, 1), tem);
2953 }
2954 break;
2955
2956 default:
2957 break;
2725 }
2726
2727 /* Otherwise, select our actions depending on our rtx class. */
2728 switch (GET_RTX_CLASS (code))
2729 {
2730 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2731 case '3':
2732 split = find_split_point (&XEXP (x, 2), insn);
2733 if (split)
2734 return split;
2958 }
2959
2960 /* Otherwise, select our actions depending on our rtx class. */
2961 switch (GET_RTX_CLASS (code))
2962 {
2963 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2964 case '3':
2965 split = find_split_point (&XEXP (x, 2), insn);
2966 if (split)
2967 return split;
2735 /* ... fall through ... */
2968 /* ... fall through ... */
2736 case '2':
2737 case 'c':
2738 case '<':
2739 split = find_split_point (&XEXP (x, 1), insn);
2740 if (split)
2741 return split;
2969 case '2':
2970 case 'c':
2971 case '<':
2972 split = find_split_point (&XEXP (x, 1), insn);
2973 if (split)
2974 return split;
2742 /* ... fall through ... */
2975 /* ... fall through ... */
2743 case '1':
2744 /* Some machines have (and (shift ...) ...) insns. If X is not
2745 an AND, but XEXP (X, 0) is, use it as our split point. */
2746 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2747 return &XEXP (x, 0);
2748
2749 split = find_split_point (&XEXP (x, 0), insn);
2750 if (split)

--- 55 unchanged lines hidden (view full) ---

2806 not have been seen as equal above. However, flow.c will make a
2807 LOG_LINKS entry for that case. If we do nothing, we will try to
2808 rerecognize our original insn and, when it succeeds, we will
2809 delete the feeding insn, which is incorrect.
2810
2811 So force this insn not to match in this (rare) case. */
2812 if (! in_dest && code == REG && GET_CODE (from) == REG
2813 && REGNO (x) == REGNO (from))
2976 case '1':
2977 /* Some machines have (and (shift ...) ...) insns. If X is not
2978 an AND, but XEXP (X, 0) is, use it as our split point. */
2979 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2980 return &XEXP (x, 0);
2981
2982 split = find_split_point (&XEXP (x, 0), insn);
2983 if (split)

--- 55 unchanged lines hidden (view full) ---

3039 not have been seen as equal above. However, flow.c will make a
3040 LOG_LINKS entry for that case. If we do nothing, we will try to
3041 rerecognize our original insn and, when it succeeds, we will
3042 delete the feeding insn, which is incorrect.
3043
3044 So force this insn not to match in this (rare) case. */
3045 if (! in_dest && code == REG && GET_CODE (from) == REG
3046 && REGNO (x) == REGNO (from))
2814 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
3047 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
2815
2816 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2817 of which may contain things that can be combined. */
2818 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2819 return x;
2820
2821 /* It is possible to have a subexpression appear twice in the insn.
2822 Suppose that FROM is a register that appears within TO.
2823 Then, after that subexpression has been scanned once by `subst',
2824 the second time it is scanned, TO may be found. If we were
2825 to scan TO here, we would find FROM within it and create a
2826 self-referent rtl structure which is completely wrong. */
2827 if (COMBINE_RTX_EQUAL_P (x, to))
2828 return to;
2829
3048
3049 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3050 of which may contain things that can be combined. */
3051 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3052 return x;
3053
3054 /* It is possible to have a subexpression appear twice in the insn.
3055 Suppose that FROM is a register that appears within TO.
3056 Then, after that subexpression has been scanned once by `subst',
3057 the second time it is scanned, TO may be found. If we were
3058 to scan TO here, we would find FROM within it and create a
3059 self-referent rtl structure which is completely wrong. */
3060 if (COMBINE_RTX_EQUAL_P (x, to))
3061 return to;
3062
2830 len = GET_RTX_LENGTH (code);
2831 fmt = GET_RTX_FORMAT (code);
3063 /* Parallel asm_operands need special attention because all of the
3064 inputs are shared across the arms. Furthermore, unsharing the
3065 rtl results in recognition failures. Failure to handle this case
3066 specially can result in circular rtl.
2832
3067
2833 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2834 set up to skip this common case. All other cases where we want to
2835 suppress replacing something inside a SET_SRC are handled via the
2836 IN_DEST operand. */
2837 if (code == SET
2838 && (GET_CODE (SET_DEST (x)) == REG
2839 || GET_CODE (SET_DEST (x)) == CC0
2840 || GET_CODE (SET_DEST (x)) == PC))
2841 fmt = "ie";
3068 Solve this by doing a normal pass across the first entry of the
3069 parallel, and only processing the SET_DESTs of the subsequent
3070 entries. Ug. */
2842
3071
2843 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2844 if (fmt[0] == 'e')
2845 op0_mode = GET_MODE (XEXP (x, 0));
2846
2847 for (i = 0; i < len; i++)
3072 if (code == PARALLEL
3073 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3074 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
2848 {
3075 {
2849 if (fmt[i] == 'E')
3076 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3077
3078 /* If this substitution failed, this whole thing fails. */
3079 if (GET_CODE (new) == CLOBBER
3080 && XEXP (new, 0) == const0_rtx)
3081 return new;
3082
3083 SUBST (XVECEXP (x, 0, 0), new);
3084
3085 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
2850 {
3086 {
2851 register int j;
2852 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3087 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3088
3089 if (GET_CODE (dest) != REG
3090 && GET_CODE (dest) != CC0
3091 && GET_CODE (dest) != PC)
2853 {
3092 {
2854 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2855 {
2856 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2857 n_occurrences++;
2858 }
2859 else
2860 {
2861 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
3093 new = subst (dest, from, to, 0, unique_copy);
2862
3094
2863 /* If this substitution failed, this whole thing fails. */
2864 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2865 return new;
2866 }
3095 /* If this substitution failed, this whole thing fails. */
3096 if (GET_CODE (new) == CLOBBER
3097 && XEXP (new, 0) == const0_rtx)
3098 return new;
2867
3099
2868 SUBST (XVECEXP (x, i, j), new);
3100 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
2869 }
2870 }
3101 }
3102 }
2871 else if (fmt[i] == 'e')
3103 }
3104 else
3105 {
3106 len = GET_RTX_LENGTH (code);
3107 fmt = GET_RTX_FORMAT (code);
3108
3109 /* We don't need to process a SET_DEST that is a register, CC0,
3110 or PC, so set up to skip this common case. All other cases
3111 where we want to suppress replacing something inside a
3112 SET_SRC are handled via the IN_DEST operand. */
3113 if (code == SET
3114 && (GET_CODE (SET_DEST (x)) == REG
3115 || GET_CODE (SET_DEST (x)) == CC0
3116 || GET_CODE (SET_DEST (x)) == PC))
3117 fmt = "ie";
3118
3119 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3120 constant. */
3121 if (fmt[0] == 'e')
3122 op0_mode = GET_MODE (XEXP (x, 0));
3123
3124 for (i = 0; i < len; i++)
2872 {
3125 {
2873 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3126 if (fmt[i] == 'E')
2874 {
3127 {
2875 /* In general, don't install a subreg involving two modes not
2876 tieable. It can worsen register allocation, and can even
2877 make invalid reload insns, since the reg inside may need to
2878 be copied from in the outside mode, and that may be invalid
2879 if it is an fp reg copied in integer mode.
3128 register int j;
3129 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3130 {
3131 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3132 {
3133 new = (unique_copy && n_occurrences
3134 ? copy_rtx (to) : to);
3135 n_occurrences++;
3136 }
3137 else
3138 {
3139 new = subst (XVECEXP (x, i, j), from, to, 0,
3140 unique_copy);
2880
3141
2881 We allow two exceptions to this: It is valid if it is inside
2882 another SUBREG and the mode of that SUBREG and the mode of
2883 the inside of TO is tieable and it is valid if X is a SET
2884 that copies FROM to CC0. */
2885 if (GET_CODE (to) == SUBREG
2886 && ! MODES_TIEABLE_P (GET_MODE (to),
2887 GET_MODE (SUBREG_REG (to)))
2888 && ! (code == SUBREG
2889 && MODES_TIEABLE_P (GET_MODE (x),
2890 GET_MODE (SUBREG_REG (to))))
3142 /* If this substitution failed, this whole thing
3143 fails. */
3144 if (GET_CODE (new) == CLOBBER
3145 && XEXP (new, 0) == const0_rtx)
3146 return new;
3147 }
3148
3149 SUBST (XVECEXP (x, i, j), new);
3150 }
3151 }
3152 else if (fmt[i] == 'e')
3153 {
3154 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3155 {
3156 /* In general, don't install a subreg involving two
3157 modes not tieable. It can worsen register
3158 allocation, and can even make invalid reload
3159 insns, since the reg inside may need to be copied
3160 from in the outside mode, and that may be invalid
3161 if it is an fp reg copied in integer mode.
3162
3163 We allow two exceptions to this: It is valid if
3164 it is inside another SUBREG and the mode of that
3165 SUBREG and the mode of the inside of TO is
3166 tieable and it is valid if X is a SET that copies
3167 FROM to CC0. */
3168
3169 if (GET_CODE (to) == SUBREG
3170 && ! MODES_TIEABLE_P (GET_MODE (to),
3171 GET_MODE (SUBREG_REG (to)))
3172 && ! (code == SUBREG
3173 && MODES_TIEABLE_P (GET_MODE (x),
3174 GET_MODE (SUBREG_REG (to))))
2891#ifdef HAVE_cc0
3175#ifdef HAVE_cc0
2892 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3176 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
2893#endif
3177#endif
2894 )
2895 return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
3178 )
3179 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
2896
3180
2897 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2898 n_occurrences++;
2899 }
2900 else
2901 /* If we are in a SET_DEST, suppress most cases unless we
2902 have gone inside a MEM, in which case we want to
2903 simplify the address. We assume here that things that
2904 are actually part of the destination have their inner
2905 parts in the first expression. This is true for SUBREG,
2906 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2907 things aside from REG and MEM that should appear in a
2908 SET_DEST. */
2909 new = subst (XEXP (x, i), from, to,
2910 (((in_dest
2911 && (code == SUBREG || code == STRICT_LOW_PART
2912 || code == ZERO_EXTRACT))
2913 || code == SET)
2914 && i == 0), unique_copy);
3181 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3182 n_occurrences++;
3183 }
3184 else
3185 /* If we are in a SET_DEST, suppress most cases unless we
3186 have gone inside a MEM, in which case we want to
3187 simplify the address. We assume here that things that
3188 are actually part of the destination have their inner
3189 parts in the first expression. This is true for SUBREG,
3190 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3191 things aside from REG and MEM that should appear in a
3192 SET_DEST. */
3193 new = subst (XEXP (x, i), from, to,
3194 (((in_dest
3195 && (code == SUBREG || code == STRICT_LOW_PART
3196 || code == ZERO_EXTRACT))
3197 || code == SET)
3198 && i == 0), unique_copy);
2915
3199
2916 /* If we found that we will have to reject this combination,
2917 indicate that by returning the CLOBBER ourselves, rather than
2918 an expression containing it. This will speed things up as
2919 well as prevent accidents where two CLOBBERs are considered
2920 to be equal, thus producing an incorrect simplification. */
3200 /* If we found that we will have to reject this combination,
3201 indicate that by returning the CLOBBER ourselves, rather than
3202 an expression containing it. This will speed things up as
3203 well as prevent accidents where two CLOBBERs are considered
3204 to be equal, thus producing an incorrect simplification. */
2921
3205
2922 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2923 return new;
3206 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3207 return new;
2924
3208
2925 SUBST (XEXP (x, i), new);
3209 SUBST (XEXP (x, i), new);
3210 }
2926 }
2927 }
2928
2929 /* Try to simplify X. If the simplification changed the code, it is likely
2930 that further simplification will help, so loop, but limit the number
2931 of repetitions that will be performed. */
2932
2933 for (i = 0; i < 4; i++)

--- 113 unchanged lines hidden (view full) ---

3047 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3048 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3049 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3050 == 'o'))))))
3051 {
3052 rtx cond, true, false;
3053
3054 cond = if_then_else_cond (x, &true, &false);
3211 }
3212 }
3213
3214 /* Try to simplify X. If the simplification changed the code, it is likely
3215 that further simplification will help, so loop, but limit the number
3216 of repetitions that will be performed. */
3217
3218 for (i = 0; i < 4; i++)

--- 113 unchanged lines hidden (view full) ---

3332 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3333 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3334 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3335 == 'o'))))))
3336 {
3337 rtx cond, true, false;
3338
3339 cond = if_then_else_cond (x, &true, &false);
3055 if (cond != 0)
3340 if (cond != 0
3341 /* If everything is a comparison, what we have is highly unlikely
3342 to be simpler, so don't use it. */
3343 && ! (GET_RTX_CLASS (code) == '<'
3344 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3345 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3056 {
3057 rtx cop1 = const0_rtx;
3058 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3059
3060 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3061 return x;
3062
3063 /* Simplify the alternative arms; this may collapse the true and

--- 20 unchanged lines hidden (view full) ---

3084 gen_binary (cond_code, mode, cond, cop1));
3085 else if (GET_CODE (false) == CONST_INT
3086 && INTVAL (false) == - STORE_FLAG_VALUE
3087 && true == const0_rtx)
3088 x = gen_unary (NEG, mode, mode,
3089 gen_binary (reverse_condition (cond_code),
3090 mode, cond, cop1));
3091 else
3346 {
3347 rtx cop1 = const0_rtx;
3348 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3349
3350 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3351 return x;
3352
3353 /* Simplify the alternative arms; this may collapse the true and

--- 20 unchanged lines hidden (view full) ---

3374 gen_binary (cond_code, mode, cond, cop1));
3375 else if (GET_CODE (false) == CONST_INT
3376 && INTVAL (false) == - STORE_FLAG_VALUE
3377 && true == const0_rtx)
3378 x = gen_unary (NEG, mode, mode,
3379 gen_binary (reverse_condition (cond_code),
3380 mode, cond, cop1));
3381 else
3092 return gen_rtx (IF_THEN_ELSE, mode,
3093 gen_binary (cond_code, VOIDmode, cond, cop1),
3094 true, false);
3382 return gen_rtx_IF_THEN_ELSE (mode,
3383 gen_binary (cond_code, VOIDmode,
3384 cond, cop1),
3385 true, false);
3095
3096 code = GET_CODE (x);
3097 op0_mode = VOIDmode;
3098 }
3099 }
3100
3101 /* Try to fold this expression in case we have constants that weren't
3102 present before. */

--- 99 unchanged lines hidden (view full) ---

3202 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3203 {
3204 rtx inner = SUBREG_REG (x);
3205 int endian_offset = 0;
3206 /* Don't change the mode of the MEM
3207 if that would change the meaning of the address. */
3208 if (MEM_VOLATILE_P (SUBREG_REG (x))
3209 || mode_dependent_address_p (XEXP (inner, 0)))
3386
3387 code = GET_CODE (x);
3388 op0_mode = VOIDmode;
3389 }
3390 }
3391
3392 /* Try to fold this expression in case we have constants that weren't
3393 present before. */

--- 99 unchanged lines hidden (view full) ---

3493 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3494 {
3495 rtx inner = SUBREG_REG (x);
3496 int endian_offset = 0;
3497 /* Don't change the mode of the MEM
3498 if that would change the meaning of the address. */
3499 if (MEM_VOLATILE_P (SUBREG_REG (x))
3500 || mode_dependent_address_p (XEXP (inner, 0)))
3210 return gen_rtx (CLOBBER, mode, const0_rtx);
3501 return gen_rtx_CLOBBER (mode, const0_rtx);
3211
3212 if (BYTES_BIG_ENDIAN)
3213 {
3214 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3215 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3216 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3217 endian_offset -= (UNITS_PER_WORD
3218 - GET_MODE_SIZE (GET_MODE (inner)));
3219 }
3220 /* Note if the plus_constant doesn't make a valid address
3221 then this combination won't be accepted. */
3502
3503 if (BYTES_BIG_ENDIAN)
3504 {
3505 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3506 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3507 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3508 endian_offset -= (UNITS_PER_WORD
3509 - GET_MODE_SIZE (GET_MODE (inner)));
3510 }
3511 /* Note if the plus_constant doesn't make a valid address
3512 then this combination won't be accepted. */
3222 x = gen_rtx (MEM, mode,
3223 plus_constant (XEXP (inner, 0),
3224 (SUBREG_WORD (x) * UNITS_PER_WORD
3225 + endian_offset)));
3513 x = gen_rtx_MEM (mode,
3514 plus_constant (XEXP (inner, 0),
3515 (SUBREG_WORD (x) * UNITS_PER_WORD
3516 + endian_offset)));
3226 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3227 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3228 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3229 return x;
3230 }
3231
3232 /* If we are in a SET_DEST, these other cases can't apply. */
3233 if (in_dest)

--- 25 unchanged lines hidden (view full) ---

3259#endif
3260#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3261 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3262#endif
3263 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3264 {
3265 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3266 mode))
3517 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3518 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3519 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3520 return x;
3521 }
3522
3523 /* If we are in a SET_DEST, these other cases can't apply. */
3524 if (in_dest)

--- 25 unchanged lines hidden (view full) ---

3550#endif
3551#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3552 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3553#endif
3554 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3555 {
3556 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3557 mode))
3267 return gen_rtx (REG, mode,
3268 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3558 return gen_rtx_REG (mode,
3559 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3269 else
3560 else
3270 return gen_rtx (CLOBBER, mode, const0_rtx);
3561 return gen_rtx_CLOBBER (mode, const0_rtx);
3271 }
3272
3273 /* For a constant, try to pick up the part we want. Handle a full
3274 word and low-order part. Only do this if we are narrowing
3275 the constant; if it is being widened, we have no idea what
3276 the extra bits will have been set to. */
3277
3278 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3279 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3562 }
3563
3564 /* For a constant, try to pick up the part we want. Handle a full
3565 word and low-order part. Only do this if we are narrowing
3566 the constant; if it is being widened, we have no idea what
3567 the extra bits will have been set to. */
3568
3569 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3570 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3280 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
3571 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3281 && GET_MODE_CLASS (mode) == MODE_INT)
3282 {
3283 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3284 0, op0_mode);
3285 if (temp)
3286 return temp;
3287 }
3288
3289 /* If we want a subreg of a constant, at offset 0,
3290 take the low bits. On a little-endian machine, that's
3291 always valid. On a big-endian machine, it's valid
3572 && GET_MODE_CLASS (mode) == MODE_INT)
3573 {
3574 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3575 0, op0_mode);
3576 if (temp)
3577 return temp;
3578 }
3579
3580 /* If we want a subreg of a constant, at offset 0,
3581 take the low bits. On a little-endian machine, that's
3582 always valid. On a big-endian machine, it's valid
3292 only if the constant's mode fits in one word. */
3293 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
3294 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode)
3583 only if the constant's mode fits in one word. Note that we
3584 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3585 if (CONSTANT_P (SUBREG_REG (x))
3586 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3587 || ! WORDS_BIG_ENDIAN)
3588 ? SUBREG_WORD (x) == 0
3589 : (SUBREG_WORD (x)
3590 == ((GET_MODE_SIZE (op0_mode)
3591 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3592 / UNITS_PER_WORD)))
3593 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3295 && (! WORDS_BIG_ENDIAN
3296 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3297 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3298
3299 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3300 since we are saying that the high bits don't matter. */
3301 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3302 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))

--- 25 unchanged lines hidden (view full) ---

3328 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3329
3330 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3331 other than 1, but that is not valid. We could do a similar
3332 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3333 but this doesn't seem common enough to bother with. */
3334 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3335 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3594 && (! WORDS_BIG_ENDIAN
3595 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3596 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3597
3598 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3599 since we are saying that the high bits don't matter. */
3600 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3601 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))

--- 25 unchanged lines hidden (view full) ---

3627 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3628
3629 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3630 other than 1, but that is not valid. We could do a similar
3631 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3632 but this doesn't seem common enough to bother with. */
3633 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3634 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3336 return gen_rtx (ROTATE, mode, gen_unary (NOT, mode, mode, const1_rtx),
3337 XEXP (XEXP (x, 0), 1));
3635 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3636 XEXP (XEXP (x, 0), 1));
3338
3339 if (GET_CODE (XEXP (x, 0)) == SUBREG
3340 && subreg_lowpart_p (XEXP (x, 0))
3341 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3342 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3343 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3344 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3345 {
3346 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3347
3637
3638 if (GET_CODE (XEXP (x, 0)) == SUBREG
3639 && subreg_lowpart_p (XEXP (x, 0))
3640 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3641 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3642 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3643 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3644 {
3645 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3646
3348 x = gen_rtx (ROTATE, inner_mode,
3349 gen_unary (NOT, inner_mode, inner_mode, const1_rtx),
3350 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3647 x = gen_rtx_ROTATE (inner_mode,
3648 gen_unary (NOT, inner_mode, inner_mode,
3649 const1_rtx),
3650 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3351 return gen_lowpart_for_combine (mode, x);
3352 }
3353
3651 return gen_lowpart_for_combine (mode, x);
3652 }
3653
3354#if STORE_FLAG_VALUE == -1
3355 /* (not (comparison foo bar)) can be done by reversing the comparison
3356 code if valid. */
3357 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3654 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3655 reversing the comparison code if valid. */
3656 if (STORE_FLAG_VALUE == -1
3657 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3358 && reversible_comparison_p (XEXP (x, 0)))
3359 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3360 mode, XEXP (XEXP (x, 0), 0),
3361 XEXP (XEXP (x, 0), 1));
3362
3363 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3658 && reversible_comparison_p (XEXP (x, 0)))
3659 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3660 mode, XEXP (XEXP (x, 0), 0),
3661 XEXP (XEXP (x, 0), 1));
3662
3663 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3364 is (lt foo (const_int 0)), so we can perform the above
3365 simplification. */
3664 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3665 perform the above simplification. */
3366
3666
3367 if (XEXP (x, 1) == const1_rtx
3667 if (STORE_FLAG_VALUE == -1
3668 && XEXP (x, 1) == const1_rtx
3368 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3369 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3370 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3371 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3669 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3670 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3671 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3672 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3372#endif
3373
3374 /* Apply De Morgan's laws to reduce number of patterns for machines
3375 with negating logical insns (and-not, nand, etc.). If result has
3376 only one NOT, put it first, since that is how the patterns are
3377 coded. */
3378
3379 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3380 {

--- 31 unchanged lines hidden (view full) ---

3412
3413 /* Similarly, (neg (not X)) is (plus X 1). */
3414 if (GET_CODE (XEXP (x, 0)) == NOT)
3415 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3416
3417 /* (neg (minus X Y)) can become (minus Y X). */
3418 if (GET_CODE (XEXP (x, 0)) == MINUS
3419 && (! FLOAT_MODE_P (mode)
3673
3674 /* Apply De Morgan's laws to reduce number of patterns for machines
3675 with negating logical insns (and-not, nand, etc.). If result has
3676 only one NOT, put it first, since that is how the patterns are
3677 coded. */
3678
3679 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3680 {

--- 31 unchanged lines hidden (view full) ---

3712
3713 /* Similarly, (neg (not X)) is (plus X 1). */
3714 if (GET_CODE (XEXP (x, 0)) == NOT)
3715 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3716
3717 /* (neg (minus X Y)) can become (minus Y X). */
3718 if (GET_CODE (XEXP (x, 0)) == MINUS
3719 && (! FLOAT_MODE_P (mode)
3420 /* x-y != -(y-x) with IEEE floating point. */
3720 /* x-y != -(y-x) with IEEE floating point. */
3421 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3422 || flag_fast_math))
3423 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3424 XEXP (XEXP (x, 0), 0));
3425
3721 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3722 || flag_fast_math))
3723 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3724 XEXP (XEXP (x, 0), 0));
3725
3426 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3726 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3427 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3428 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3429 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3430
3431 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3432 if we can then eliminate the NEG (e.g.,
3433 if the operand is a constant). */
3434

--- 44 unchanged lines hidden (view full) ---

3479 if (GET_CODE (temp1) != ASHIFTRT
3480 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3481 || XEXP (XEXP (temp1, 0), 0) != temp)
3482 return temp1;
3483 }
3484 break;
3485
3486 case TRUNCATE:
3727 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3728 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3729 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3730
3731 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3732 if we can then eliminate the NEG (e.g.,
3733 if the operand is a constant). */
3734

--- 44 unchanged lines hidden (view full) ---

3779 if (GET_CODE (temp1) != ASHIFTRT
3780 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3781 || XEXP (XEXP (temp1, 0), 0) != temp)
3782 return temp1;
3783 }
3784 break;
3785
3786 case TRUNCATE:
3487 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3787 /* We can't handle truncation to a partial integer mode here
3788 because we don't know the real bitsize of the partial
3789 integer mode. */
3790 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3791 break;
3792
3793 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3794 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3795 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3488 SUBST (XEXP (x, 0),
3489 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3490 GET_MODE_MASK (mode), NULL_RTX, 0));
3796 SUBST (XEXP (x, 0),
3797 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3798 GET_MODE_MASK (mode), NULL_RTX, 0));
3799
3800 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3801 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3802 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3803 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3804 return XEXP (XEXP (x, 0), 0);
3805
3806 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3807 (OP:SI foo:SI) if OP is NEG or ABS. */
3808 if ((GET_CODE (XEXP (x, 0)) == ABS
3809 || GET_CODE (XEXP (x, 0)) == NEG)
3810 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3811 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3812 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3813 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3814 XEXP (XEXP (XEXP (x, 0), 0), 0));
3815
3816 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3817 (truncate:SI x). */
3818 if (GET_CODE (XEXP (x, 0)) == SUBREG
3819 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3820 && subreg_lowpart_p (XEXP (x, 0)))
3821 return SUBREG_REG (XEXP (x, 0));
3822
3823 /* If we know that the value is already truncated, we can
3824 replace the TRUNCATE with a SUBREG. */
3825 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3826 >= GET_MODE_BITSIZE (mode) + 1)
3827 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3828
3829 /* A truncate of a comparison can be replaced with a subreg if
3830 STORE_FLAG_VALUE permits. This is like the previous test,
3831 but it works even if the comparison is done in a mode larger
3832 than HOST_BITS_PER_WIDE_INT. */
3833 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3834 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3835 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3836 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3837
3838 /* Similarly, a truncate of a register whose value is a
3839 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3840 permits. */
3841 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3842 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3843 && (temp = get_last_value (XEXP (x, 0)))
3844 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3845 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3846
3491 break;
3492
3493 case FLOAT_TRUNCATE:
3494 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3495 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3496 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3497 return XEXP (XEXP (x, 0), 0);
3498

--- 123 unchanged lines hidden (view full) ---

3622
3623 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3624 && (nonzero_bits (XEXP (x, 0), mode)
3625 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3626 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3627 break;
3628
3629 case MINUS:
3847 break;
3848
3849 case FLOAT_TRUNCATE:
3850 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3851 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3852 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3853 return XEXP (XEXP (x, 0), 0);
3854

--- 123 unchanged lines hidden (view full) ---

3978
3979 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3980 && (nonzero_bits (XEXP (x, 0), mode)
3981 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3982 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3983 break;
3984
3985 case MINUS:
3630#if STORE_FLAG_VALUE == 1
3631 /* (minus 1 (comparison foo bar)) can be done by reversing the comparison
3632 code if valid. */
3633 if (XEXP (x, 0) == const1_rtx
3986 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3987 by reversing the comparison code if valid. */
3988 if (STORE_FLAG_VALUE == 1
3989 && XEXP (x, 0) == const1_rtx
3634 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3635 && reversible_comparison_p (XEXP (x, 1)))
3636 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3637 mode, XEXP (XEXP (x, 1), 0),
3638 XEXP (XEXP (x, 1), 1));
3990 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3991 && reversible_comparison_p (XEXP (x, 1)))
3992 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3993 mode, XEXP (XEXP (x, 1), 0),
3994 XEXP (XEXP (x, 1), 1));
3639#endif
3640
3641 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3642 (and <foo> (const_int pow2-1)) */
3643 if (GET_CODE (XEXP (x, 1)) == AND
3644 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3645 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3646 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3647 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),

--- 57 unchanged lines hidden (view full) ---

3705 enum rtx_code new_code;
3706
3707 if (GET_CODE (op0) == COMPARE)
3708 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3709
3710 /* Simplify our comparison, if possible. */
3711 new_code = simplify_comparison (code, &op0, &op1);
3712
3995
3996 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3997 (and <foo> (const_int pow2-1)) */
3998 if (GET_CODE (XEXP (x, 1)) == AND
3999 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4000 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4001 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4002 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),

--- 57 unchanged lines hidden (view full) ---

4060 enum rtx_code new_code;
4061
4062 if (GET_CODE (op0) == COMPARE)
4063 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4064
4065 /* Simplify our comparison, if possible. */
4066 new_code = simplify_comparison (code, &op0, &op1);
4067
3713#if STORE_FLAG_VALUE == 1
3714 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3715 if only the low-order bit is possibly nonzero in X (such as when
3716 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
3717 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
3718 known to be either 0 or -1, NE becomes a NEG and EQ becomes
3719 (plus X 1).
3720
3721 Remove any ZERO_EXTRACT we made when thinking this was a
3722 comparison. It may now be simpler to use, e.g., an AND. If a
3723 ZERO_EXTRACT is indeed appropriate, it will be placed back by
3724 the call to make_compound_operation in the SET case. */
3725
4068 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4069 if only the low-order bit is possibly nonzero in X (such as when
4070 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4071 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4072 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4073 (plus X 1).
4074
4075 Remove any ZERO_EXTRACT we made when thinking this was a
4076 comparison. It may now be simpler to use, e.g., an AND. If a
4077 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4078 the call to make_compound_operation in the SET case. */
4079
3726 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3727 && op1 == const0_rtx
3728 && nonzero_bits (op0, mode) == 1)
4080 if (STORE_FLAG_VALUE == 1
4081 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4082 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
3729 return gen_lowpart_for_combine (mode,
3730 expand_compound_operation (op0));
3731
4083 return gen_lowpart_for_combine (mode,
4084 expand_compound_operation (op0));
4085
3732 else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4086 else if (STORE_FLAG_VALUE == 1
4087 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3733 && op1 == const0_rtx
3734 && (num_sign_bit_copies (op0, mode)
3735 == GET_MODE_BITSIZE (mode)))
3736 {
3737 op0 = expand_compound_operation (op0);
3738 return gen_unary (NEG, mode, mode,
3739 gen_lowpart_for_combine (mode, op0));
3740 }
3741
4088 && op1 == const0_rtx
4089 && (num_sign_bit_copies (op0, mode)
4090 == GET_MODE_BITSIZE (mode)))
4091 {
4092 op0 = expand_compound_operation (op0);
4093 return gen_unary (NEG, mode, mode,
4094 gen_lowpart_for_combine (mode, op0));
4095 }
4096
3742 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4097 else if (STORE_FLAG_VALUE == 1
4098 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3743 && op1 == const0_rtx
3744 && nonzero_bits (op0, mode) == 1)
3745 {
3746 op0 = expand_compound_operation (op0);
3747 return gen_binary (XOR, mode,
3748 gen_lowpart_for_combine (mode, op0),
3749 const1_rtx);
3750 }
3751
4099 && op1 == const0_rtx
4100 && nonzero_bits (op0, mode) == 1)
4101 {
4102 op0 = expand_compound_operation (op0);
4103 return gen_binary (XOR, mode,
4104 gen_lowpart_for_combine (mode, op0),
4105 const1_rtx);
4106 }
4107
3752 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4108 else if (STORE_FLAG_VALUE == 1
4109 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3753 && op1 == const0_rtx
3754 && (num_sign_bit_copies (op0, mode)
3755 == GET_MODE_BITSIZE (mode)))
3756 {
3757 op0 = expand_compound_operation (op0);
3758 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
3759 }
4110 && op1 == const0_rtx
4111 && (num_sign_bit_copies (op0, mode)
4112 == GET_MODE_BITSIZE (mode)))
4113 {
4114 op0 = expand_compound_operation (op0);
4115 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4116 }
3760#endif
3761
4117
3762#if STORE_FLAG_VALUE == -1
3763 /* If STORE_FLAG_VALUE is -1, we have cases similar to
3764 those above. */
4118 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4119 those above. */
3765 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4120 if (STORE_FLAG_VALUE == -1
4121 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3766 && op1 == const0_rtx
3767 && (num_sign_bit_copies (op0, mode)
3768 == GET_MODE_BITSIZE (mode)))
3769 return gen_lowpart_for_combine (mode,
3770 expand_compound_operation (op0));
3771
4122 && op1 == const0_rtx
4123 && (num_sign_bit_copies (op0, mode)
4124 == GET_MODE_BITSIZE (mode)))
4125 return gen_lowpart_for_combine (mode,
4126 expand_compound_operation (op0));
4127
3772 else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4128 else if (STORE_FLAG_VALUE == -1
4129 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3773 && op1 == const0_rtx
3774 && nonzero_bits (op0, mode) == 1)
3775 {
3776 op0 = expand_compound_operation (op0);
3777 return gen_unary (NEG, mode, mode,
3778 gen_lowpart_for_combine (mode, op0));
3779 }
3780
4130 && op1 == const0_rtx
4131 && nonzero_bits (op0, mode) == 1)
4132 {
4133 op0 = expand_compound_operation (op0);
4134 return gen_unary (NEG, mode, mode,
4135 gen_lowpart_for_combine (mode, op0));
4136 }
4137
3781 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4138 else if (STORE_FLAG_VALUE == -1
4139 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3782 && op1 == const0_rtx
3783 && (num_sign_bit_copies (op0, mode)
3784 == GET_MODE_BITSIZE (mode)))
3785 {
3786 op0 = expand_compound_operation (op0);
3787 return gen_unary (NOT, mode, mode,
3788 gen_lowpart_for_combine (mode, op0));
3789 }
3790
3791 /* If X is 0/1, (eq X 0) is X-1. */
4140 && op1 == const0_rtx
4141 && (num_sign_bit_copies (op0, mode)
4142 == GET_MODE_BITSIZE (mode)))
4143 {
4144 op0 = expand_compound_operation (op0);
4145 return gen_unary (NOT, mode, mode,
4146 gen_lowpart_for_combine (mode, op0));
4147 }
4148
4149 /* If X is 0/1, (eq X 0) is X-1. */
3792 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4150 else if (STORE_FLAG_VALUE == -1
4151 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3793 && op1 == const0_rtx
3794 && nonzero_bits (op0, mode) == 1)
3795 {
3796 op0 = expand_compound_operation (op0);
3797 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
3798 }
4152 && op1 == const0_rtx
4153 && nonzero_bits (op0, mode) == 1)
4154 {
4155 op0 = expand_compound_operation (op0);
4156 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4157 }
3799#endif
3800
3801 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3802 one bit that might be nonzero, we can convert (ne x 0) to
3803 (ashift x c) where C puts the bit in the sign bit. Remove any
3804 AND with STORE_FLAG_VALUE when we are done, since we are only
3805 going to test the sign bit. */
3806 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3807 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4158
4159 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4160 one bit that might be nonzero, we can convert (ne x 0) to
4161 (ashift x c) where C puts the bit in the sign bit. Remove any
4162 AND with STORE_FLAG_VALUE when we are done, since we are only
4163 going to test the sign bit. */
4164 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4165 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3808 && (STORE_FLAG_VALUE
4166 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
3809 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3810 && op1 == const0_rtx
3811 && mode == GET_MODE (op0)
3812 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
3813 {
3814 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3815 expand_compound_operation (op0),
3816 GET_MODE_BITSIZE (mode) - 1 - i);

--- 16 unchanged lines hidden (view full) ---

3833
3834 case IF_THEN_ELSE:
3835 return simplify_if_then_else (x);
3836
3837 case ZERO_EXTRACT:
3838 case SIGN_EXTRACT:
3839 case ZERO_EXTEND:
3840 case SIGN_EXTEND:
4167 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4168 && op1 == const0_rtx
4169 && mode == GET_MODE (op0)
4170 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4171 {
4172 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4173 expand_compound_operation (op0),
4174 GET_MODE_BITSIZE (mode) - 1 - i);

--- 16 unchanged lines hidden (view full) ---

4191
4192 case IF_THEN_ELSE:
4193 return simplify_if_then_else (x);
4194
4195 case ZERO_EXTRACT:
4196 case SIGN_EXTRACT:
4197 case ZERO_EXTEND:
4198 case SIGN_EXTEND:
3841 /* If we are processing SET_DEST, we are done. */
4199 /* If we are processing SET_DEST, we are done. */
3842 if (in_dest)
3843 return x;
3844
3845 return expand_compound_operation (x);
3846
3847 case SET:
3848 return simplify_set (x);
3849
3850 case AND:
3851 case IOR:
3852 case XOR:
3853 return simplify_logical (x, last);
3854
4200 if (in_dest)
4201 return x;
4202
4203 return expand_compound_operation (x);
4204
4205 case SET:
4206 return simplify_set (x);
4207
4208 case AND:
4209 case IOR:
4210 case XOR:
4211 return simplify_logical (x, last);
4212
3855 case ABS:
4213 case ABS:
3856 /* (abs (neg <foo>)) -> (abs <foo>) */
3857 if (GET_CODE (XEXP (x, 0)) == NEG)
3858 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3859
4214 /* (abs (neg <foo>)) -> (abs <foo>) */
4215 if (GET_CODE (XEXP (x, 0)) == NEG)
4216 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4217
4218 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4219 do nothing. */
4220 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4221 break;
4222
3860 /* If operand is something known to be positive, ignore the ABS. */
3861 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
3862 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
3863 <= HOST_BITS_PER_WIDE_INT)
3864 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3865 & ((HOST_WIDE_INT) 1
3866 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
3867 == 0)))

--- 35 unchanged lines hidden (view full) ---

3903 force_to_mode (XEXP (x, 1), GET_MODE (x),
3904 ((HOST_WIDE_INT) 1
3905 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
3906 - 1,
3907 NULL_RTX, 0));
3908#endif
3909
3910 break;
4223 /* If operand is something known to be positive, ignore the ABS. */
4224 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4225 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4226 <= HOST_BITS_PER_WIDE_INT)
4227 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4228 & ((HOST_WIDE_INT) 1
4229 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4230 == 0)))

--- 35 unchanged lines hidden (view full) ---

4266 force_to_mode (XEXP (x, 1), GET_MODE (x),
4267 ((HOST_WIDE_INT) 1
4268 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4269 - 1,
4270 NULL_RTX, 0));
4271#endif
4272
4273 break;
4274
4275 default:
4276 break;
3911 }
3912
3913 return x;
3914}
3915
3916/* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
3917
3918static rtx

--- 4 unchanged lines hidden (view full) ---

3923 rtx cond = XEXP (x, 0);
3924 rtx true = XEXP (x, 1);
3925 rtx false = XEXP (x, 2);
3926 enum rtx_code true_code = GET_CODE (cond);
3927 int comparison_p = GET_RTX_CLASS (true_code) == '<';
3928 rtx temp;
3929 int i;
3930
4277 }
4278
4279 return x;
4280}
4281
4282/* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4283
4284static rtx

--- 4 unchanged lines hidden (view full) ---

4289 rtx cond = XEXP (x, 0);
4290 rtx true = XEXP (x, 1);
4291 rtx false = XEXP (x, 2);
4292 enum rtx_code true_code = GET_CODE (cond);
4293 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4294 rtx temp;
4295 int i;
4296
3931 /* Simplify storing of the truth value. */
4297 /* Simplify storing of the truth value. */
3932 if (comparison_p && true == const_true_rtx && false == const0_rtx)
3933 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
3934
4298 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4299 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4300
3935 /* Also when the truth value has to be reversed. */
4301 /* Also when the truth value has to be reversed. */
3936 if (comparison_p && reversible_comparison_p (cond)
3937 && true == const0_rtx && false == const_true_rtx)
3938 return gen_binary (reverse_condition (true_code),
3939 mode, XEXP (cond, 0), XEXP (cond, 1));
3940
3941 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
3942 in it is being compared against certain values. Get the true and false
3943 comparisons and see if that says anything about the value of each arm. */

--- 69 unchanged lines hidden (view full) ---

4013 SUBST (XEXP (x, 0),
4014 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4015 XEXP (cond, 1)));
4016
4017 SUBST (XEXP (x, 1), false);
4018 SUBST (XEXP (x, 2), true);
4019
4020 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4302 if (comparison_p && reversible_comparison_p (cond)
4303 && true == const0_rtx && false == const_true_rtx)
4304 return gen_binary (reverse_condition (true_code),
4305 mode, XEXP (cond, 0), XEXP (cond, 1));
4306
4307 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4308 in it is being compared against certain values. Get the true and false
4309 comparisons and see if that says anything about the value of each arm. */

--- 69 unchanged lines hidden (view full) ---

4379 SUBST (XEXP (x, 0),
4380 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4381 XEXP (cond, 1)));
4382
4383 SUBST (XEXP (x, 1), false);
4384 SUBST (XEXP (x, 2), true);
4385
4386 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4387
4388 /* It is possible that the conditional has been simplified out. */
4389 true_code = GET_CODE (cond);
4390 comparison_p = GET_RTX_CLASS (true_code) == '<';
4021 }
4022
4023 /* If the two arms are identical, we don't need the comparison. */
4024
4025 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4026 return true;
4027
4391 }
4392
4393 /* If the two arms are identical, we don't need the comparison. */
4394
4395 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4396 return true;
4397
4398 /* Convert a == b ? b : a to "a". */
4399 if (true_code == EQ && ! side_effects_p (cond)
4400 && rtx_equal_p (XEXP (cond, 0), false)
4401 && rtx_equal_p (XEXP (cond, 1), true))
4402 return false;
4403 else if (true_code == NE && ! side_effects_p (cond)
4404 && rtx_equal_p (XEXP (cond, 0), true)
4405 && rtx_equal_p (XEXP (cond, 1), false))
4406 return true;
4407
4028 /* Look for cases where we have (abs x) or (neg (abs X)). */
4029
4030 if (GET_MODE_CLASS (mode) == MODE_INT
4031 && GET_CODE (false) == NEG
4032 && rtx_equal_p (true, XEXP (false, 0))
4033 && comparison_p
4034 && rtx_equal_p (true, XEXP (cond, 0))
4035 && ! side_effects_p (true))
4036 switch (true_code)
4037 {
4038 case GT:
4039 case GE:
4040 return gen_unary (ABS, mode, mode, true);
4041 case LT:
4042 case LE:
4043 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4408 /* Look for cases where we have (abs x) or (neg (abs X)). */
4409
4410 if (GET_MODE_CLASS (mode) == MODE_INT
4411 && GET_CODE (false) == NEG
4412 && rtx_equal_p (true, XEXP (false, 0))
4413 && comparison_p
4414 && rtx_equal_p (true, XEXP (cond, 0))
4415 && ! side_effects_p (true))
4416 switch (true_code)
4417 {
4418 case GT:
4419 case GE:
4420 return gen_unary (ABS, mode, mode, true);
4421 case LT:
4422 case LE:
4423 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4424 default:
4425 break;
4044 }
4045
4046 /* Look for MIN or MAX. */
4047
4048 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4049 && comparison_p
4050 && rtx_equal_p (XEXP (cond, 0), true)
4051 && rtx_equal_p (XEXP (cond, 1), false)

--- 7 unchanged lines hidden (view full) ---

4059 case LT:
4060 return gen_binary (SMIN, mode, true, false);
4061 case GEU:
4062 case GTU:
4063 return gen_binary (UMAX, mode, true, false);
4064 case LEU:
4065 case LTU:
4066 return gen_binary (UMIN, mode, true, false);
4426 }
4427
4428 /* Look for MIN or MAX. */
4429
4430 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4431 && comparison_p
4432 && rtx_equal_p (XEXP (cond, 0), true)
4433 && rtx_equal_p (XEXP (cond, 1), false)

--- 7 unchanged lines hidden (view full) ---

4441 case LT:
4442 return gen_binary (SMIN, mode, true, false);
4443 case GEU:
4444 case GTU:
4445 return gen_binary (UMAX, mode, true, false);
4446 case LEU:
4447 case LTU:
4448 return gen_binary (UMIN, mode, true, false);
4449 default:
4450 break;
4067 }
4068
4451 }
4452
4069#if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
4070
4071 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4072 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4073 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4074 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4075 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4453 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4454 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4455 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4456 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4457 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4076 neither of the above, but it isn't worth checking for. */
4458 neither 1 or -1, but it isn't worth checking for. */
4077
4459
4078 if (comparison_p && mode != VOIDmode && ! side_effects_p (x))
4460 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4461 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4079 {
4080 rtx t = make_compound_operation (true, SET);
4081 rtx f = make_compound_operation (false, SET);
4082 rtx cond_op0 = XEXP (cond, 0);
4083 rtx cond_op1 = XEXP (cond, 1);
4084 enum rtx_code op, extend_op = NIL;
4085 enum machine_mode m = mode;
4086 rtx z = 0, c1;
4087
4088 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4089 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4090 || GET_CODE (t) == ASHIFT
4091 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4092 && rtx_equal_p (XEXP (t, 0), f))
4093 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4094
4095 /* If an identity-zero op is commutative, check whether there
4462 {
4463 rtx t = make_compound_operation (true, SET);
4464 rtx f = make_compound_operation (false, SET);
4465 rtx cond_op0 = XEXP (cond, 0);
4466 rtx cond_op1 = XEXP (cond, 1);
4467 enum rtx_code op, extend_op = NIL;
4468 enum machine_mode m = mode;
4469 rtx z = 0, c1;
4470
4471 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4472 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4473 || GET_CODE (t) == ASHIFT
4474 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4475 && rtx_equal_p (XEXP (t, 0), f))
4476 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4477
4478 /* If an identity-zero op is commutative, check whether there
4096 would be a match if we swapped the operands. */
4479 would be a match if we swapped the operands. */
4097 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4098 || GET_CODE (t) == XOR)
4099 && rtx_equal_p (XEXP (t, 1), f))
4100 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4101 else if (GET_CODE (t) == SIGN_EXTEND
4102 && (GET_CODE (XEXP (t, 0)) == PLUS
4103 || GET_CODE (XEXP (t, 0)) == MINUS
4104 || GET_CODE (XEXP (t, 0)) == IOR

--- 74 unchanged lines hidden (view full) ---

4179 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4180
4181 if (extend_op != NIL)
4182 temp = gen_unary (extend_op, mode, m, temp);
4183
4184 return temp;
4185 }
4186 }
4480 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4481 || GET_CODE (t) == XOR)
4482 && rtx_equal_p (XEXP (t, 1), f))
4483 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4484 else if (GET_CODE (t) == SIGN_EXTEND
4485 && (GET_CODE (XEXP (t, 0)) == PLUS
4486 || GET_CODE (XEXP (t, 0)) == MINUS
4487 || GET_CODE (XEXP (t, 0)) == IOR

--- 74 unchanged lines hidden (view full) ---

4562 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4563
4564 if (extend_op != NIL)
4565 temp = gen_unary (extend_op, mode, m, temp);
4566
4567 return temp;
4568 }
4569 }
4187#endif
4188
4189 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4190 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4191 negation of a single bit, we can convert this operation to a shift. We
4192 can actually do this more generally, but it doesn't seem worth it. */
4193
4194 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4195 && false == const0_rtx && GET_CODE (true) == CONST_INT

--- 70 unchanged lines hidden (view full) ---

4266 /* If the mode changed, we have to change SET_DEST, the mode in the
4267 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4268 a hard register, just build new versions with the proper mode. If it
4269 is a pseudo, we lose unless it is only time we set the pseudo, in
4270 which case we can safely change its mode. */
4271 if (compare_mode != GET_MODE (dest))
4272 {
4273 int regno = REGNO (dest);
4570
4571 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4572 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4573 negation of a single bit, we can convert this operation to a shift. We
4574 can actually do this more generally, but it doesn't seem worth it. */
4575
4576 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4577 && false == const0_rtx && GET_CODE (true) == CONST_INT

--- 70 unchanged lines hidden (view full) ---

4648 /* If the mode changed, we have to change SET_DEST, the mode in the
4649 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4650 a hard register, just build new versions with the proper mode. If it
4651 is a pseudo, we lose unless it is only time we set the pseudo, in
4652 which case we can safely change its mode. */
4653 if (compare_mode != GET_MODE (dest))
4654 {
4655 int regno = REGNO (dest);
4274 rtx new_dest = gen_rtx (REG, compare_mode, regno);
4656 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4275
4276 if (regno < FIRST_PSEUDO_REGISTER
4657
4658 if (regno < FIRST_PSEUDO_REGISTER
4277 || (reg_n_sets[regno] == 1 && ! REG_USERVAR_P (dest)))
4659 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4278 {
4279 if (regno >= FIRST_PSEUDO_REGISTER)
4280 SUBST (regno_reg_rtx[regno], new_dest);
4281
4282 SUBST (SET_DEST (x), new_dest);
4283 SUBST (XEXP (*cc_use, 0), new_dest);
4284 other_changed = 1;
4285

--- 79 unchanged lines hidden (view full) ---

4365 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4366 and X being a REG or (subreg (reg)), we may be able to convert this to
4367 (set (subreg:m2 x) (op)).
4368
4369 We can always do this if M1 is narrower than M2 because that means that
4370 we only care about the low bits of the result.
4371
4372 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4660 {
4661 if (regno >= FIRST_PSEUDO_REGISTER)
4662 SUBST (regno_reg_rtx[regno], new_dest);
4663
4664 SUBST (SET_DEST (x), new_dest);
4665 SUBST (XEXP (*cc_use, 0), new_dest);
4666 other_changed = 1;
4667

--- 79 unchanged lines hidden (view full) ---

4747 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4748 and X being a REG or (subreg (reg)), we may be able to convert this to
4749 (set (subreg:m2 x) (op)).
4750
4751 We can always do this if M1 is narrower than M2 because that means that
4752 we only care about the low bits of the result.
4753
4754 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4373 perform a narrower operation that requested since the high-order bits will
4755 perform a narrower operation than requested since the high-order bits will
4374 be undefined. On machine where it is defined, this transformation is safe
4375 as long as M1 and M2 have the same number of words. */
4376
4377 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4378 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4379 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4380 / UNITS_PER_WORD)
4381 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))

--- 20 unchanged lines hidden (view full) ---

4402 SUBST (SET_SRC (x), SUBREG_REG (src));
4403
4404 src = SET_SRC (x), dest = SET_DEST (x);
4405 }
4406
4407#ifdef LOAD_EXTEND_OP
4408 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4409 would require a paradoxical subreg. Replace the subreg with a
4756 be undefined. On machine where it is defined, this transformation is safe
4757 as long as M1 and M2 have the same number of words. */
4758
4759 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4760 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4761 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4762 / UNITS_PER_WORD)
4763 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))

--- 20 unchanged lines hidden (view full) ---

4784 SUBST (SET_SRC (x), SUBREG_REG (src));
4785
4786 src = SET_SRC (x), dest = SET_DEST (x);
4787 }
4788
4789#ifdef LOAD_EXTEND_OP
4790 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4791 would require a paradoxical subreg. Replace the subreg with a
4410 zero_extend to avoid the reload that would otherwise be required. */
4792 zero_extend to avoid the reload that would otherwise be required. */
4411
4412 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4413 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4414 && SUBREG_WORD (src) == 0
4415 && (GET_MODE_SIZE (GET_MODE (src))
4416 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4417 && GET_CODE (SUBREG_REG (src)) == MEM)
4418 {

--- 111 unchanged lines hidden (view full) ---

4530 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4531
4532 if (GET_CODE (op1) == CONST_INT)
4533 {
4534 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4535
4536 /* If we have (ior (and (X C1) C2)) and the next restart would be
4537 the last, simplify this by making C1 as small as possible
4793
4794 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4795 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4796 && SUBREG_WORD (src) == 0
4797 && (GET_MODE_SIZE (GET_MODE (src))
4798 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4799 && GET_CODE (SUBREG_REG (src)) == MEM)
4800 {

--- 111 unchanged lines hidden (view full) ---

4912 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4913
4914 if (GET_CODE (op1) == CONST_INT)
4915 {
4916 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4917
4918 /* If we have (ior (and (X C1) C2)) and the next restart would be
4919 the last, simplify this by making C1 as small as possible
4538 and then exit. */
4920 and then exit. */
4539 if (last
4540 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4541 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4542 && GET_CODE (op1) == CONST_INT)
4543 return gen_binary (IOR, mode,
4544 gen_binary (AND, mode, XEXP (op0, 0),
4545 GEN_INT (INTVAL (XEXP (op0, 1))
4546 & ~ INTVAL (op1))), op1);

--- 106 unchanged lines hidden (view full) ---

4653
4654 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4655 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4656 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4657 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4658 && GET_CODE (XEXP (op1, 1)) == CONST_INT
4659 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
4660 == GET_MODE_BITSIZE (mode)))
4921 if (last
4922 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4923 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4924 && GET_CODE (op1) == CONST_INT)
4925 return gen_binary (IOR, mode,
4926 gen_binary (AND, mode, XEXP (op0, 0),
4927 GEN_INT (INTVAL (XEXP (op0, 1))
4928 & ~ INTVAL (op1))), op1);

--- 106 unchanged lines hidden (view full) ---

5035
5036 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5037 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5038 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5039 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5040 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5041 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5042 == GET_MODE_BITSIZE (mode)))
4661 return gen_rtx (ROTATE, mode, XEXP (op0, 0),
4662 (GET_CODE (op0) == ASHIFT
4663 ? XEXP (op0, 1) : XEXP (op1, 1)));
5043 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5044 (GET_CODE (op0) == ASHIFT
5045 ? XEXP (op0, 1) : XEXP (op1, 1)));
4664
4665 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4666 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
4667 does not affect any of the bits in OP1, it can really be done
4668 as a PLUS and we can associate. We do this by seeing if OP1
4669 can be safely shifted left C bits. */
4670 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
4671 && GET_CODE (XEXP (op0, 0)) == PLUS

--- 48 unchanged lines hidden (view full) ---

4720
4721 else if (GET_CODE (op0) == AND
4722 && rtx_equal_p (XEXP (op0, 0), op1)
4723 && ! side_effects_p (op1))
4724 return gen_binary (AND, mode,
4725 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
4726 op1);
4727
5046
5047 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5048 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5049 does not affect any of the bits in OP1, it can really be done
5050 as a PLUS and we can associate. We do this by seeing if OP1
5051 can be safely shifted left C bits. */
5052 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5053 && GET_CODE (XEXP (op0, 0)) == PLUS

--- 48 unchanged lines hidden (view full) ---

5102
5103 else if (GET_CODE (op0) == AND
5104 && rtx_equal_p (XEXP (op0, 0), op1)
5105 && ! side_effects_p (op1))
5106 return gen_binary (AND, mode,
5107 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5108 op1);
5109
4728#if STORE_FLAG_VALUE == 1
4729 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5110 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4730 comparison. */
4731 if (op1 == const1_rtx
5111 comparison if STORE_FLAG_VALUE is 1. */
5112 if (STORE_FLAG_VALUE == 1
5113 && op1 == const1_rtx
4732 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4733 && reversible_comparison_p (op0))
4734 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4735 mode, XEXP (op0, 0), XEXP (op0, 1));
4736
4737 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4738 is (lt foo (const_int 0)), so we can perform the above
5114 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5115 && reversible_comparison_p (op0))
5116 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5117 mode, XEXP (op0, 0), XEXP (op0, 1));
5118
5119 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5120 is (lt foo (const_int 0)), so we can perform the above
4739 simplification. */
5121 simplification if STORE_FLAG_VALUE is 1. */
4740
5122
4741 if (op1 == const1_rtx
5123 if (STORE_FLAG_VALUE == 1
5124 && op1 == const1_rtx
4742 && GET_CODE (op0) == LSHIFTRT
4743 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4744 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
4745 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5125 && GET_CODE (op0) == LSHIFTRT
5126 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5127 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5128 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
4746#endif
4747
4748 /* (xor (comparison foo bar) (const_int sign-bit))
4749 when STORE_FLAG_VALUE is the sign bit. */
4750 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5129
5130 /* (xor (comparison foo bar) (const_int sign-bit))
5131 when STORE_FLAG_VALUE is the sign bit. */
5132 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4751 && (STORE_FLAG_VALUE
5133 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4752 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4753 && op1 == const_true_rtx
4754 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4755 && reversible_comparison_p (op0))
4756 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4757 mode, XEXP (op0, 0), XEXP (op0, 1));
4758 break;
5134 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5135 && op1 == const_true_rtx
5136 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5137 && reversible_comparison_p (op0))
5138 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5139 mode, XEXP (op0, 0), XEXP (op0, 1));
5140 break;
5141
5142 default:
5143 abort ();
4759 }
4760
4761 return x;
4762}
4763
4764/* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4765 operations" because they can be replaced with two more basic operations.
4766 ZERO_EXTEND is also considered "compound" because it can be replaced with

--- 67 unchanged lines hidden (view full) ---

4834
4835 len = INTVAL (XEXP (x, 1));
4836 pos = INTVAL (XEXP (x, 2));
4837
4838 /* If this goes outside the object being extracted, replace the object
4839 with a (use (mem ...)) construct that only combine understands
4840 and is used only for this purpose. */
4841 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5144 }
5145
5146 return x;
5147}
5148
5149/* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5150 operations" because they can be replaced with two more basic operations.
5151 ZERO_EXTEND is also considered "compound" because it can be replaced with

--- 67 unchanged lines hidden (view full) ---

5219
5220 len = INTVAL (XEXP (x, 1));
5221 pos = INTVAL (XEXP (x, 2));
5222
5223 /* If this goes outside the object being extracted, replace the object
5224 with a (use (mem ...)) construct that only combine understands
5225 and is used only for this purpose. */
5226 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4842 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
5227 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
4843
4844 if (BITS_BIG_ENDIAN)
4845 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
4846
4847 break;
4848
4849 default:
4850 return x;
4851 }
4852
5228
5229 if (BITS_BIG_ENDIAN)
5230 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5231
5232 break;
5233
5234 default:
5235 return x;
5236 }
5237
5238 /* We can optimize some special cases of ZERO_EXTEND. */
5239 if (GET_CODE (x) == ZERO_EXTEND)
5240 {
5241 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5242 know that the last value didn't have any inappropriate bits
5243 set. */
5244 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5245 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5246 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5247 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5248 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5249 return XEXP (XEXP (x, 0), 0);
5250
5251 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5252 if (GET_CODE (XEXP (x, 0)) == SUBREG
5253 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5254 && subreg_lowpart_p (XEXP (x, 0))
5255 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5256 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5257 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5258 return SUBREG_REG (XEXP (x, 0));
5259
5260 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5261 is a comparison and STORE_FLAG_VALUE permits. This is like
5262 the first case, but it works even when GET_MODE (x) is larger
5263 than HOST_WIDE_INT. */
5264 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5265 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5266 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5267 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5268 <= HOST_BITS_PER_WIDE_INT)
5269 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5270 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5271 return XEXP (XEXP (x, 0), 0);
5272
5273 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5274 if (GET_CODE (XEXP (x, 0)) == SUBREG
5275 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5276 && subreg_lowpart_p (XEXP (x, 0))
5277 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5278 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5279 <= HOST_BITS_PER_WIDE_INT)
5280 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5281 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5282 return SUBREG_REG (XEXP (x, 0));
5283
5284 /* If sign extension is cheaper than zero extension, then use it
5285 if we know that no extraneous bits are set, and that the high
5286 bit is not set. */
5287 if (flag_expensive_optimizations
5288 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5289 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5290 & ~ (((unsigned HOST_WIDE_INT)
5291 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5292 >> 1))
5293 == 0))
5294 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5295 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5296 <= HOST_BITS_PER_WIDE_INT)
5297 && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5298 & ~ (((unsigned HOST_WIDE_INT)
5299 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5300 >> 1))
5301 == 0))))
5302 {
5303 rtx temp = gen_rtx_SIGN_EXTEND (GET_MODE (x), XEXP (x, 0));
5304
5305 if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5306 return expand_compound_operation (temp);
5307 }
5308 }
5309
4853 /* If we reach here, we want to return a pair of shifts. The inner
4854 shift is a left shift of BITSIZE - POS - LEN bits. The outer
4855 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
4856 logical depending on the value of UNSIGNEDP.
4857
4858 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
4859 converted into an AND of a shift.
4860

--- 41 unchanged lines hidden (view full) ---

4902 We half-heartedly support variable positions, but do not at all
4903 support variable lengths. */
4904
4905static rtx
4906expand_field_assignment (x)
4907 rtx x;
4908{
4909 rtx inner;
5310 /* If we reach here, we want to return a pair of shifts. The inner
5311 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5312 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5313 logical depending on the value of UNSIGNEDP.
5314
5315 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5316 converted into an AND of a shift.
5317

--- 41 unchanged lines hidden (view full) ---

5359 We half-heartedly support variable positions, but do not at all
5360 support variable lengths. */
5361
5362static rtx
5363expand_field_assignment (x)
5364 rtx x;
5365{
5366 rtx inner;
4910 rtx pos; /* Always counts from low bit. */
5367 rtx pos; /* Always counts from low bit. */
4911 int len;
4912 rtx mask;
4913 enum machine_mode compute_mode;
4914
4915 /* Loop until we find something we can't simplify. */
4916 while (1)
4917 {
4918 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
4919 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
4920 {
4921 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
4922 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5368 int len;
5369 rtx mask;
5370 enum machine_mode compute_mode;
5371
5372 /* Loop until we find something we can't simplify. */
5373 while (1)
5374 {
5375 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5376 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5377 {
5378 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5379 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4923 pos = const0_rtx;
5380 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
4924 }
4925 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4926 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
4927 {
4928 inner = XEXP (SET_DEST (x), 0);
4929 len = INTVAL (XEXP (SET_DEST (x), 1));
4930 pos = XEXP (SET_DEST (x), 2);
4931
4932 /* If the position is constant and spans the width of INNER,
4933 surround INNER with a USE to indicate this. */
4934 if (GET_CODE (pos) == CONST_INT
4935 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5381 }
5382 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5383 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5384 {
5385 inner = XEXP (SET_DEST (x), 0);
5386 len = INTVAL (XEXP (SET_DEST (x), 1));
5387 pos = XEXP (SET_DEST (x), 2);
5388
5389 /* If the position is constant and spans the width of INNER,
5390 surround INNER with a USE to indicate this. */
5391 if (GET_CODE (pos) == CONST_INT
5392 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
4936 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
5393 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
4937
4938 if (BITS_BIG_ENDIAN)
4939 {
4940 if (GET_CODE (pos) == CONST_INT)
4941 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
4942 - INTVAL (pos));
4943 else if (GET_CODE (pos) == MINUS
4944 && GET_CODE (XEXP (pos, 1)) == CONST_INT

--- 12 unchanged lines hidden (view full) ---

4957 /* A SUBREG between two modes that occupy the same numbers of words
4958 can be done by moving the SUBREG to the source. */
4959 else if (GET_CODE (SET_DEST (x)) == SUBREG
4960 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
4961 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
4962 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
4963 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
4964 {
5394
5395 if (BITS_BIG_ENDIAN)
5396 {
5397 if (GET_CODE (pos) == CONST_INT)
5398 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5399 - INTVAL (pos));
5400 else if (GET_CODE (pos) == MINUS
5401 && GET_CODE (XEXP (pos, 1)) == CONST_INT

--- 12 unchanged lines hidden (view full) ---

5414 /* A SUBREG between two modes that occupy the same numbers of words
5415 can be done by moving the SUBREG to the source. */
5416 else if (GET_CODE (SET_DEST (x)) == SUBREG
5417 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5418 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5419 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5420 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5421 {
4965 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
4966 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
4967 SET_SRC (x)));
5422 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5423 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5424 SET_SRC (x)));
4968 continue;
4969 }
4970 else
4971 break;
4972
4973 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4974 inner = SUBREG_REG (inner);
4975
4976 compute_mode = GET_MODE (inner);
4977
4978 /* Compute a mask of LEN bits, if we can do this on the host machine. */
4979 if (len < HOST_BITS_PER_WIDE_INT)
4980 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
4981 else
4982 break;
4983
4984 /* Now compute the equivalent expression. Make a copy of INNER
4985 for the SET_DEST in case it is a MEM into which we will substitute;
4986 we don't want shared RTL in that case. */
5425 continue;
5426 }
5427 else
5428 break;
5429
5430 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5431 inner = SUBREG_REG (inner);
5432
5433 compute_mode = GET_MODE (inner);
5434
5435 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5436 if (len < HOST_BITS_PER_WIDE_INT)
5437 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5438 else
5439 break;
5440
5441 /* Now compute the equivalent expression. Make a copy of INNER
5442 for the SET_DEST in case it is a MEM into which we will substitute;
5443 we don't want shared RTL in that case. */
4987 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
4988 gen_binary (IOR, compute_mode,
4989 gen_binary (AND, compute_mode,
4990 gen_unary (NOT, compute_mode,
4991 compute_mode,
4992 gen_binary (ASHIFT,
4993 compute_mode,
4994 mask, pos)),
4995 inner),
4996 gen_binary (ASHIFT, compute_mode,
4997 gen_binary (AND, compute_mode,
4998 gen_lowpart_for_combine
4999 (compute_mode,
5000 SET_SRC (x)),
5001 mask),
5002 pos)));
5444 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5445 gen_binary (IOR, compute_mode,
5446 gen_binary (AND, compute_mode,
5447 gen_unary (NOT, compute_mode,
5448 compute_mode,
5449 gen_binary (ASHIFT,
5450 compute_mode,
5451 mask, pos)),
5452 inner),
5453 gen_binary (ASHIFT, compute_mode,
5454 gen_binary (AND, compute_mode,
5455 gen_lowpart_for_combine
5456 (compute_mode,
5457 SET_SRC (x)),
5458 mask),
5459 pos)));
5003 }
5004
5005 return x;
5006}
5007
5008/* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5009 it is an RTX that represents a variable starting position; otherwise,
5010 POS is the (constant) starting bit position (counted from the LSB).

--- 11 unchanged lines hidden (view full) ---

5022 IN_DEST is non-zero if this is a reference in the destination of a
5023 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5024 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5025 be used.
5026
5027 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5028 ZERO_EXTRACT should be built even for bits starting at bit 0.
5029
5460 }
5461
5462 return x;
5463}
5464
5465/* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5466 it is an RTX that represents a variable starting position; otherwise,
5467 POS is the (constant) starting bit position (counted from the LSB).

--- 11 unchanged lines hidden (view full) ---

5479 IN_DEST is non-zero if this is a reference in the destination of a
5480 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5481 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5482 be used.
5483
5484 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5485 ZERO_EXTRACT should be built even for bits starting at bit 0.
5486
5030 MODE is the desired mode of the result (if IN_DEST == 0). */
5487 MODE is the desired mode of the result (if IN_DEST == 0).
5031
5488
5489 The result is an RTX for the extraction or NULL_RTX if the target
5490 can't handle it. */
5491
5032static rtx
5033make_extraction (mode, inner, pos, pos_rtx, len,
5034 unsignedp, in_dest, in_compare)
5035 enum machine_mode mode;
5036 rtx inner;
5037 int pos;
5038 rtx pos_rtx;
5039 int len;
5040 int unsignedp;
5041 int in_dest, in_compare;
5042{
5043 /* This mode describes the size of the storage area
5044 to fetch the overall value from. Within that, we
5045 ignore the POS lowest bits, etc. */
5046 enum machine_mode is_mode = GET_MODE (inner);
5047 enum machine_mode inner_mode;
5492static rtx
5493make_extraction (mode, inner, pos, pos_rtx, len,
5494 unsignedp, in_dest, in_compare)
5495 enum machine_mode mode;
5496 rtx inner;
5497 int pos;
5498 rtx pos_rtx;
5499 int len;
5500 int unsignedp;
5501 int in_dest, in_compare;
5502{
5503 /* This mode describes the size of the storage area
5504 to fetch the overall value from. Within that, we
5505 ignore the POS lowest bits, etc. */
5506 enum machine_mode is_mode = GET_MODE (inner);
5507 enum machine_mode inner_mode;
5048 enum machine_mode wanted_mem_mode = byte_mode;
5508 enum machine_mode wanted_inner_mode = byte_mode;
5509 enum machine_mode wanted_inner_reg_mode = word_mode;
5049 enum machine_mode pos_mode = word_mode;
5050 enum machine_mode extraction_mode = word_mode;
5051 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5052 int spans_byte = 0;
5053 rtx new = 0;
5054 rtx orig_pos_rtx = pos_rtx;
5055 int orig_pos;
5056

--- 30 unchanged lines hidden (view full) ---

5087 boundary and we can change the mode of the memory reference. However,
5088 we cannot directly access the MEM if we have a USE and the underlying
5089 MEM is not TMODE. This combination means that MEM was being used in a
5090 context where bits outside its mode were being referenced; that is only
5091 valid in bit-field insns. */
5092
5093 if (tmode != BLKmode
5094 && ! (spans_byte && inner_mode != tmode)
5510 enum machine_mode pos_mode = word_mode;
5511 enum machine_mode extraction_mode = word_mode;
5512 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5513 int spans_byte = 0;
5514 rtx new = 0;
5515 rtx orig_pos_rtx = pos_rtx;
5516 int orig_pos;
5517

--- 30 unchanged lines hidden (view full) ---

5548 boundary and we can change the mode of the memory reference. However,
5549 we cannot directly access the MEM if we have a USE and the underlying
5550 MEM is not TMODE. This combination means that MEM was being used in a
5551 context where bits outside its mode were being referenced; that is only
5552 valid in bit-field insns. */
5553
5554 if (tmode != BLKmode
5555 && ! (spans_byte && inner_mode != tmode)
5095 && ((pos_rtx == 0 && pos == 0 && GET_CODE (inner) != MEM
5556 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5557 && GET_CODE (inner) != MEM
5096 && (! in_dest
5097 || (GET_CODE (inner) == REG
5098 && (movstrict_optab->handlers[(int) tmode].insn_code
5099 != CODE_FOR_nothing))))
5100 || (GET_CODE (inner) == MEM && pos_rtx == 0
5101 && (pos
5102 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5103 : BITS_PER_UNIT)) == 0
5104 /* We can't do this if we are widening INNER_MODE (it
5105 may not be aligned, for one thing). */
5106 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5107 && (inner_mode == tmode
5108 || (! mode_dependent_address_p (XEXP (inner, 0))
5109 && ! MEM_VOLATILE_P (inner))))))
5110 {
5111 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5112 field. If the original and current mode are the same, we need not
5113 adjust the offset. Otherwise, we do if bytes big endian.
5114
5558 && (! in_dest
5559 || (GET_CODE (inner) == REG
5560 && (movstrict_optab->handlers[(int) tmode].insn_code
5561 != CODE_FOR_nothing))))
5562 || (GET_CODE (inner) == MEM && pos_rtx == 0
5563 && (pos
5564 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5565 : BITS_PER_UNIT)) == 0
5566 /* We can't do this if we are widening INNER_MODE (it
5567 may not be aligned, for one thing). */
5568 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5569 && (inner_mode == tmode
5570 || (! mode_dependent_address_p (XEXP (inner, 0))
5571 && ! MEM_VOLATILE_P (inner))))))
5572 {
5573 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5574 field. If the original and current mode are the same, we need not
5575 adjust the offset. Otherwise, we do if bytes big endian.
5576
5115 If INNER is not a MEM, get a piece consisting of the just the field
5116 of interest (in this case POS must be 0). */
5577 If INNER is not a MEM, get a piece consisting of just the field
5578 of interest (in this case POS % BITS_PER_WORD must be 0). */
5117
5118 if (GET_CODE (inner) == MEM)
5119 {
5120 int offset;
5121 /* POS counts from lsb, but make OFFSET count in memory order. */
5122 if (BYTES_BIG_ENDIAN)
5123 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5124 else
5125 offset = pos / BITS_PER_UNIT;
5126
5579
5580 if (GET_CODE (inner) == MEM)
5581 {
5582 int offset;
5583 /* POS counts from lsb, but make OFFSET count in memory order. */
5584 if (BYTES_BIG_ENDIAN)
5585 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5586 else
5587 offset = pos / BITS_PER_UNIT;
5588
5127 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
5589 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
5128 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5129 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5130 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5131 }
5132 else if (GET_CODE (inner) == REG)
5133 {
5134 /* We can't call gen_lowpart_for_combine here since we always want
5135 a SUBREG and it would sometimes return a new hard register. */
5136 if (tmode != inner_mode)
5590 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5591 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5592 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5593 }
5594 else if (GET_CODE (inner) == REG)
5595 {
5596 /* We can't call gen_lowpart_for_combine here since we always want
5597 a SUBREG and it would sometimes return a new hard register. */
5598 if (tmode != inner_mode)
5137 new = gen_rtx (SUBREG, tmode, inner,
5138 (WORDS_BIG_ENDIAN
5139 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5140 ? ((GET_MODE_SIZE (inner_mode)
5141 - GET_MODE_SIZE (tmode))
5142 / UNITS_PER_WORD)
5143 : 0));
5599 new = gen_rtx_SUBREG (tmode, inner,
5600 (WORDS_BIG_ENDIAN
5601 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5602 ? (((GET_MODE_SIZE (inner_mode)
5603 - GET_MODE_SIZE (tmode))
5604 / UNITS_PER_WORD)
5605 - pos / BITS_PER_WORD)
5606 : pos / BITS_PER_WORD));
5144 else
5145 new = inner;
5146 }
5147 else
5148 new = force_to_mode (inner, tmode,
5149 len >= HOST_BITS_PER_WIDE_INT
5150 ? GET_MODE_MASK (tmode)
5151 : ((HOST_WIDE_INT) 1 << len) - 1,
5152 NULL_RTX, 0);
5153
5154 /* If this extraction is going into the destination of a SET,
5155 make a STRICT_LOW_PART unless we made a MEM. */
5156
5157 if (in_dest)
5158 return (GET_CODE (new) == MEM ? new
5159 : (GET_CODE (new) != SUBREG
5607 else
5608 new = inner;
5609 }
5610 else
5611 new = force_to_mode (inner, tmode,
5612 len >= HOST_BITS_PER_WIDE_INT
5613 ? GET_MODE_MASK (tmode)
5614 : ((HOST_WIDE_INT) 1 << len) - 1,
5615 NULL_RTX, 0);
5616
5617 /* If this extraction is going into the destination of a SET,
5618 make a STRICT_LOW_PART unless we made a MEM. */
5619
5620 if (in_dest)
5621 return (GET_CODE (new) == MEM ? new
5622 : (GET_CODE (new) != SUBREG
5160 ? gen_rtx (CLOBBER, tmode, const0_rtx)
5623 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5161 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5162
5163 /* Otherwise, sign- or zero-extend unless we already are in the
5164 proper mode. */
5165
5166 return (mode == tmode ? new
5167 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5168 mode, new));

--- 11 unchanged lines hidden (view full) ---

5180 is not 1. In all other cases, we would only be going outside
5181 out object in cases when an original shift would have been
5182 undefined. */
5183 if (! spans_byte
5184 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5185 || (pos_rtx != 0 && len != 1)))
5186 return 0;
5187
5624 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5625
5626 /* Otherwise, sign- or zero-extend unless we already are in the
5627 proper mode. */
5628
5629 return (mode == tmode ? new
5630 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5631 mode, new));

--- 11 unchanged lines hidden (view full) ---

5643 is not 1. In all other cases, we would only be going outside
5644 out object in cases when an original shift would have been
5645 undefined. */
5646 if (! spans_byte
5647 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5648 || (pos_rtx != 0 && len != 1)))
5649 return 0;
5650
5188 /* Get the mode to use should INNER be a MEM, the mode for the position,
5651 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5189 and the mode for the result. */
5190#ifdef HAVE_insv
5191 if (in_dest)
5192 {
5652 and the mode for the result. */
5653#ifdef HAVE_insv
5654 if (in_dest)
5655 {
5193 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5656 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5194 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5195 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5196 }
5197#endif
5198
5199#ifdef HAVE_extzv
5200 if (! in_dest && unsignedp)
5201 {
5657 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5658 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5659 }
5660#endif
5661
5662#ifdef HAVE_extzv
5663 if (! in_dest && unsignedp)
5664 {
5202 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5665 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5203 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5204 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5205 }
5206#endif
5207
5208#ifdef HAVE_extv
5209 if (! in_dest && ! unsignedp)
5210 {
5666 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5667 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5668 }
5669#endif
5670
5671#ifdef HAVE_extv
5672 if (! in_dest && ! unsignedp)
5673 {
5211 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5674 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5212 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5213 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5214 }
5215#endif
5216
5217 /* Never narrow an object, since that might not be safe. */
5218
5219 if (mode != VOIDmode
5220 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5221 extraction_mode = mode;
5222
5223 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5224 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5225 pos_mode = GET_MODE (pos_rtx);
5226
5675 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5676 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5677 }
5678#endif
5679
5680 /* Never narrow an object, since that might not be safe. */
5681
5682 if (mode != VOIDmode
5683 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5684 extraction_mode = mode;
5685
5686 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5687 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5688 pos_mode = GET_MODE (pos_rtx);
5689
5227 /* If this is not from memory or we have to change the mode of memory and
5228 cannot, the desired mode is EXTRACTION_MODE. */
5229 if (GET_CODE (inner) != MEM
5230 || (inner_mode != wanted_mem_mode
5231 && (mode_dependent_address_p (XEXP (inner, 0))
5232 || MEM_VOLATILE_P (inner))))
5233 wanted_mem_mode = extraction_mode;
5690 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5691 if we have to change the mode of memory and cannot, the desired mode is
5692 EXTRACTION_MODE. */
5693 if (GET_CODE (inner) != MEM)
5694 wanted_inner_mode = wanted_inner_reg_mode;
5695 else if (inner_mode != wanted_inner_mode
5696 && (mode_dependent_address_p (XEXP (inner, 0))
5697 || MEM_VOLATILE_P (inner)))
5698 wanted_inner_mode = extraction_mode;
5234
5235 orig_pos = pos;
5236
5237 if (BITS_BIG_ENDIAN)
5238 {
5699
5700 orig_pos = pos;
5701
5702 if (BITS_BIG_ENDIAN)
5703 {
5239 /* If position is constant, compute new position. Otherwise,
5240 build subtraction. */
5704 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5705 BITS_BIG_ENDIAN style. If position is constant, compute new
5706 position. Otherwise, build subtraction.
5707 Note that POS is relative to the mode of the original argument.
5708 If it's a MEM we need to recompute POS relative to that.
5709 However, if we're extracting from (or inserting into) a register,
5710 we want to recompute POS relative to wanted_inner_mode. */
5711 int width = (GET_CODE (inner) == MEM
5712 ? GET_MODE_BITSIZE (is_mode)
5713 : GET_MODE_BITSIZE (wanted_inner_mode));
5714
5241 if (pos_rtx == 0)
5715 if (pos_rtx == 0)
5242 pos = (MAX (GET_MODE_BITSIZE (is_mode),
5243 GET_MODE_BITSIZE (wanted_mem_mode))
5244 - len - pos);
5716 pos = width - len - pos;
5245 else
5246 pos_rtx
5247 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5717 else
5718 pos_rtx
5719 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5248 GEN_INT (MAX (GET_MODE_BITSIZE (is_mode),
5249 GET_MODE_BITSIZE (wanted_mem_mode))
5250 - len),
5251 pos_rtx);
5720 GEN_INT (width - len), pos_rtx);
5721 /* POS may be less than 0 now, but we check for that below.
5722 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5252 }
5253
5254 /* If INNER has a wider mode, make it smaller. If this is a constant
5255 extract, try to adjust the byte to point to the byte containing
5256 the value. */
5723 }
5724
5725 /* If INNER has a wider mode, make it smaller. If this is a constant
5726 extract, try to adjust the byte to point to the byte containing
5727 the value. */
5257 if (wanted_mem_mode != VOIDmode
5258 && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode)
5728 if (wanted_inner_mode != VOIDmode
5729 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5259 && ((GET_CODE (inner) == MEM
5730 && ((GET_CODE (inner) == MEM
5260 && (inner_mode == wanted_mem_mode
5731 && (inner_mode == wanted_inner_mode
5261 || (! mode_dependent_address_p (XEXP (inner, 0))
5262 && ! MEM_VOLATILE_P (inner))))))
5263 {
5264 int offset = 0;
5265
5266 /* The computations below will be correct if the machine is big
5267 endian in both bits and bytes or little endian in bits and bytes.
5268 If it is mixed, we must adjust. */
5269
5270 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5732 || (! mode_dependent_address_p (XEXP (inner, 0))
5733 && ! MEM_VOLATILE_P (inner))))))
5734 {
5735 int offset = 0;
5736
5737 /* The computations below will be correct if the machine is big
5738 endian in both bits and bytes or little endian in bits and bytes.
5739 If it is mixed, we must adjust. */
5740
5741 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5271 adjust OFFSET to compensate. */
5742 adjust OFFSET to compensate. */
5272 if (BYTES_BIG_ENDIAN
5273 && ! spans_byte
5274 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5275 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5276
5277 /* If this is a constant position, we can move to the desired byte. */
5278 if (pos_rtx == 0)
5279 {
5280 offset += pos / BITS_PER_UNIT;
5743 if (BYTES_BIG_ENDIAN
5744 && ! spans_byte
5745 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5746 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5747
5748 /* If this is a constant position, we can move to the desired byte. */
5749 if (pos_rtx == 0)
5750 {
5751 offset += pos / BITS_PER_UNIT;
5281 pos %= GET_MODE_BITSIZE (wanted_mem_mode);
5752 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5282 }
5283
5284 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5285 && ! spans_byte
5753 }
5754
5755 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5756 && ! spans_byte
5286 && is_mode != wanted_mem_mode)
5757 && is_mode != wanted_inner_mode)
5287 offset = (GET_MODE_SIZE (is_mode)
5758 offset = (GET_MODE_SIZE (is_mode)
5288 - GET_MODE_SIZE (wanted_mem_mode) - offset);
5759 - GET_MODE_SIZE (wanted_inner_mode) - offset);
5289
5760
5290 if (offset != 0 || inner_mode != wanted_mem_mode)
5761 if (offset != 0 || inner_mode != wanted_inner_mode)
5291 {
5762 {
5292 rtx newmem = gen_rtx (MEM, wanted_mem_mode,
5293 plus_constant (XEXP (inner, 0), offset));
5763 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
5764 plus_constant (XEXP (inner, 0), offset));
5294 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5295 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5296 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5297 inner = newmem;
5298 }
5299 }
5300
5765 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5766 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5767 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5768 inner = newmem;
5769 }
5770 }
5771
5301 /* If INNER is not memory, we can always get it into the proper mode. */
5772 /* If INNER is not memory, we can always get it into the proper mode. If we
5773 are changing its mode, POS must be a constant and smaller than the size
5774 of the new mode. */
5302 else if (GET_CODE (inner) != MEM)
5775 else if (GET_CODE (inner) != MEM)
5303 inner = force_to_mode (inner, extraction_mode,
5304 pos_rtx || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5305 ? GET_MODE_MASK (extraction_mode)
5306 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5307 NULL_RTX, 0);
5776 {
5777 if (GET_MODE (inner) != wanted_inner_mode
5778 && (pos_rtx != 0
5779 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5780 return 0;
5308
5781
5782 inner = force_to_mode (inner, wanted_inner_mode,
5783 pos_rtx
5784 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5785 ? GET_MODE_MASK (wanted_inner_mode)
5786 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5787 NULL_RTX, 0);
5788 }
5789
5309 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5310 have to zero extend. Otherwise, we can just use a SUBREG. */
5311 if (pos_rtx != 0
5312 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5313 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5314 else if (pos_rtx != 0
5315 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5316 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5317
5318 /* Make POS_RTX unless we already have it and it is correct. If we don't
5319 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5790 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5791 have to zero extend. Otherwise, we can just use a SUBREG. */
5792 if (pos_rtx != 0
5793 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5794 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5795 else if (pos_rtx != 0
5796 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5797 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5798
5799 /* Make POS_RTX unless we already have it and it is correct. If we don't
5800 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5320 be a CONST_INT. */
5801 be a CONST_INT. */
5321 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5322 pos_rtx = orig_pos_rtx;
5323
5324 else if (pos_rtx == 0)
5325 pos_rtx = GEN_INT (pos);
5326
5327 /* Make the required operation. See if we can use existing rtx. */
5328 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,

--- 33 unchanged lines hidden (view full) ---

5362 return gen_unary (code, mode, mode, tem);
5363
5364 break;
5365
5366 case PLUS: case IOR: case XOR: case AND:
5367 /* If we can safely shift this constant and we find the inner shift,
5368 make a new operation. */
5369 if (GET_CODE (XEXP (x,1)) == CONST_INT
5802 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5803 pos_rtx = orig_pos_rtx;
5804
5805 else if (pos_rtx == 0)
5806 pos_rtx = GEN_INT (pos);
5807
5808 /* Make the required operation. See if we can use existing rtx. */
5809 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,

--- 33 unchanged lines hidden (view full) ---

5843 return gen_unary (code, mode, mode, tem);
5844
5845 break;
5846
5847 case PLUS: case IOR: case XOR: case AND:
5848 /* If we can safely shift this constant and we find the inner shift,
5849 make a new operation. */
5850 if (GET_CODE (XEXP (x,1)) == CONST_INT
5370 && (INTVAL (XEXP (x, 1)) & (((HOST_WIDE_INT) 1 << count)) - 1) == 0
5851 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
5371 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5372 return gen_binary (code, mode, tem,
5373 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5374
5375 break;
5852 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5853 return gen_binary (code, mode, tem,
5854 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5855
5856 break;
5857
5858 default:
5859 break;
5376 }
5377
5378 return 0;
5379}
5380
5381/* Look at the expression rooted at X. Look for expressions
5382 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5383 Form these expressions.

--- 87 unchanged lines hidden (view full) ---

5471 else if ((GET_CODE (XEXP (x, 0)) == XOR
5472 || GET_CODE (XEXP (x, 0)) == IOR)
5473 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5474 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5475 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5476 {
5477 /* Apply the distributive law, and then try to make extractions. */
5478 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5860 }
5861
5862 return 0;
5863}
5864
5865/* Look at the expression rooted at X. Look for expressions
5866 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5867 Form these expressions.

--- 87 unchanged lines hidden (view full) ---

5955 else if ((GET_CODE (XEXP (x, 0)) == XOR
5956 || GET_CODE (XEXP (x, 0)) == IOR)
5957 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5958 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5959 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5960 {
5961 /* Apply the distributive law, and then try to make extractions. */
5962 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5479 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 0),
5480 XEXP (x, 1)),
5481 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 1),
5482 XEXP (x, 1)));
5963 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
5964 XEXP (x, 1)),
5965 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
5966 XEXP (x, 1)));
5483 new = make_compound_operation (new, in_code);
5484 }
5485
5486 /* If we are have (and (rotate X C) M) and C is larger than the number
5487 of bits in M, this is an extraction. */
5488
5489 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5490 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT

--- 61 unchanged lines hidden (view full) ---

5552 {
5553 new = gen_rtx_combine (ASHIFTRT, mode,
5554 make_compound_operation (XEXP (x, 0),
5555 next_code),
5556 XEXP (x, 1));
5557 break;
5558 }
5559
5967 new = make_compound_operation (new, in_code);
5968 }
5969
5970 /* If we are have (and (rotate X C) M) and C is larger than the number
5971 of bits in M, this is an extraction. */
5972
5973 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5974 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT

--- 61 unchanged lines hidden (view full) ---

6036 {
6037 new = gen_rtx_combine (ASHIFTRT, mode,
6038 make_compound_operation (XEXP (x, 0),
6039 next_code),
6040 XEXP (x, 1));
6041 break;
6042 }
6043
5560 /* ... fall through ... */
6044 /* ... fall through ... */
5561
5562 case ASHIFTRT:
5563 lhs = XEXP (x, 0);
5564 rhs = XEXP (x, 1);
5565
5566 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5567 this is a SIGN_EXTRACT. */
5568 if (GET_CODE (rhs) == CONST_INT

--- 40 unchanged lines hidden (view full) ---

5609
5610 /* If we have something other than a SUBREG, we might have
5611 done an expansion, so rerun outselves. */
5612 if (GET_CODE (newer) != SUBREG)
5613 newer = make_compound_operation (newer, in_code);
5614
5615 return newer;
5616 }
6045
6046 case ASHIFTRT:
6047 lhs = XEXP (x, 0);
6048 rhs = XEXP (x, 1);
6049
6050 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6051 this is a SIGN_EXTRACT. */
6052 if (GET_CODE (rhs) == CONST_INT

--- 40 unchanged lines hidden (view full) ---

6093
6094 /* If we have something other than a SUBREG, we might have
6095 done an expansion, so rerun outselves. */
6096 if (GET_CODE (newer) != SUBREG)
6097 newer = make_compound_operation (newer, in_code);
6098
6099 return newer;
6100 }
6101
6102 /* If this is a paradoxical subreg, and the new code is a sign or
6103 zero extension, omit the subreg and widen the extension. If it
6104 is a regular subreg, we can still get rid of the subreg by not
6105 widening so much, or in fact removing the extension entirely. */
6106 if ((GET_CODE (tem) == SIGN_EXTEND
6107 || GET_CODE (tem) == ZERO_EXTEND)
6108 && subreg_lowpart_p (x))
6109 {
6110 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6111 || (GET_MODE_SIZE (mode) >
6112 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6113 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6114 else
6115 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6116 return tem;
6117 }
6118 break;
6119
6120 default:
6121 break;
5617 }
5618
5619 if (new)
5620 {
5621 x = gen_lowpart_for_combine (mode, new);
5622 code = GET_CODE (x);
5623 }
5624

--- 62 unchanged lines hidden (view full) ---

5687 int just_select;
5688{
5689 enum rtx_code code = GET_CODE (x);
5690 int next_select = just_select || code == XOR || code == NOT || code == NEG;
5691 enum machine_mode op_mode;
5692 unsigned HOST_WIDE_INT fuller_mask, nonzero;
5693 rtx op0, op1, temp;
5694
6122 }
6123
6124 if (new)
6125 {
6126 x = gen_lowpart_for_combine (mode, new);
6127 code = GET_CODE (x);
6128 }
6129

--- 62 unchanged lines hidden (view full) ---

6192 int just_select;
6193{
6194 enum rtx_code code = GET_CODE (x);
6195 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6196 enum machine_mode op_mode;
6197 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6198 rtx op0, op1, temp;
6199
5695 /* If this is a CALL, don't do anything. Some of the code below
5696 will do the wrong thing since the mode of a CALL is VOIDmode. */
5697 if (code == CALL)
6200 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6201 code below will do the wrong thing since the mode of such an
6202 expression is VOIDmode.
6203
6204 Also do nothing if X is a CLOBBER; this can happen if X was
6205 the return value from a call to gen_lowpart_for_combine. */
6206 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
5698 return x;
5699
5700 /* We want to perform the operation is its present mode unless we know
5701 that the operation is valid in MODE, in which case we do the operation
5702 in MODE. */
5703 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
5704 && code_to_optab[(int) code] != 0
5705 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code

--- 53 unchanged lines hidden (view full) ---

5759 MASK are already known to be zero in X, we need not do anything. */
5760 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
5761 return x;
5762
5763 switch (code)
5764 {
5765 case CLOBBER:
5766 /* If X is a (clobber (const_int)), return it since we know we are
6207 return x;
6208
6209 /* We want to perform the operation is its present mode unless we know
6210 that the operation is valid in MODE, in which case we do the operation
6211 in MODE. */
6212 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6213 && code_to_optab[(int) code] != 0
6214 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code

--- 53 unchanged lines hidden (view full) ---

6268 MASK are already known to be zero in X, we need not do anything. */
6269 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6270 return x;
6271
6272 switch (code)
6273 {
6274 case CLOBBER:
6275 /* If X is a (clobber (const_int)), return it since we know we are
5767 generating something that won't match. */
6276 generating something that won't match. */
5768 return x;
5769
5770 case USE:
5771 /* X is a (use (mem ..)) that was made from a bit-field extraction that
5772 spanned the boundary of the MEM. If we are now masking so it is
5773 within that boundary, we don't need the USE any more. */
5774 if (! BITS_BIG_ENDIAN
5775 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)

--- 89 unchanged lines hidden (view full) ---

5865 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
5866 number, sign extend it. */
5867
5868 if (width < HOST_BITS_PER_WIDE_INT
5869 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
5870 smask |= (HOST_WIDE_INT) -1 << width;
5871
5872 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6277 return x;
6278
6279 case USE:
6280 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6281 spanned the boundary of the MEM. If we are now masking so it is
6282 within that boundary, we don't need the USE any more. */
6283 if (! BITS_BIG_ENDIAN
6284 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)

--- 89 unchanged lines hidden (view full) ---

6374 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6375 number, sign extend it. */
6376
6377 if (width < HOST_BITS_PER_WIDE_INT
6378 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6379 smask |= (HOST_WIDE_INT) -1 << width;
6380
6381 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5873 && exact_log2 (- smask) >= 0
5874 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
5875 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
5876 return force_to_mode (plus_constant (XEXP (x, 0),
5877 INTVAL (XEXP (x, 1)) & mask),
5878 mode, mask, reg, next_select);
6382 && exact_log2 (- smask) >= 0)
6383 {
6384#ifdef STACK_BIAS
6385 if (STACK_BIAS
6386 && (XEXP (x, 0) == stack_pointer_rtx
6387 || XEXP (x, 0) == frame_pointer_rtx))
6388 {
6389 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6390 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6391
6392 sp_mask &= ~ (sp_alignment - 1);
6393 if ((sp_mask & ~ mask) == 0
6394 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ mask) != 0)
6395 return force_to_mode (plus_constant (XEXP (x, 0),
6396 ((INTVAL (XEXP (x, 1)) -
6397 STACK_BIAS) & mask)
6398 + STACK_BIAS),
6399 mode, mask, reg, next_select);
6400 }
6401#endif
6402 if ((nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
6403 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
6404 return force_to_mode (plus_constant (XEXP (x, 0),
6405 INTVAL (XEXP (x, 1)) & mask),
6406 mode, mask, reg, next_select);
6407 }
5879 }
5880
6408 }
6409
5881 /* ... fall through ... */
6410 /* ... fall through ... */
5882
5883 case MINUS:
5884 case MULT:
5885 /* For PLUS, MINUS and MULT, we need any bits less significant than the
5886 most significant bit in MASK since carries from those bits will
5887 affect the bits we are interested in. */
5888 mask = fuller_mask;
5889 goto binop;

--- 9 unchanged lines hidden (view full) ---

5899 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5900 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5901 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5902 && GET_CODE (XEXP (x, 1)) == CONST_INT
5903 && ((INTVAL (XEXP (XEXP (x, 0), 1))
5904 + floor_log2 (INTVAL (XEXP (x, 1))))
5905 < GET_MODE_BITSIZE (GET_MODE (x)))
5906 && (INTVAL (XEXP (x, 1))
6411
6412 case MINUS:
6413 case MULT:
6414 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6415 most significant bit in MASK since carries from those bits will
6416 affect the bits we are interested in. */
6417 mask = fuller_mask;
6418 goto binop;

--- 9 unchanged lines hidden (view full) ---

6428 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6429 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6430 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6431 && GET_CODE (XEXP (x, 1)) == CONST_INT
6432 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6433 + floor_log2 (INTVAL (XEXP (x, 1))))
6434 < GET_MODE_BITSIZE (GET_MODE (x)))
6435 && (INTVAL (XEXP (x, 1))
5907 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x)) == 0))
6436 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
5908 {
5909 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
5910 << INTVAL (XEXP (XEXP (x, 0), 1)));
5911 temp = gen_binary (GET_CODE (x), GET_MODE (x),
5912 XEXP (XEXP (x, 0), 0), temp);
6437 {
6438 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6439 << INTVAL (XEXP (XEXP (x, 0), 1)));
6440 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6441 XEXP (XEXP (x, 0), 0), temp);
5913 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (x, 1));
6442 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6443 XEXP (XEXP (x, 0), 1));
5914 return force_to_mode (x, mode, mask, reg, next_select);
5915 }
5916
5917 binop:
5918 /* For most binary operations, just propagate into the operation and
5919 change the mode if we have an operation of that mode. */
5920
5921 op0 = gen_lowpart_for_combine (op_mode,

--- 114 unchanged lines hidden (view full) ---

6036 int i = -1;
6037
6038 /* If the considered data is wider then HOST_WIDE_INT, we can't
6039 represent a mask for all its bits in a single scalar.
6040 But we only care about the lower bits, so calculate these. */
6041
6042 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6043 {
6444 return force_to_mode (x, mode, mask, reg, next_select);
6445 }
6446
6447 binop:
6448 /* For most binary operations, just propagate into the operation and
6449 change the mode if we have an operation of that mode. */
6450
6451 op0 = gen_lowpart_for_combine (op_mode,

--- 114 unchanged lines hidden (view full) ---

6566 int i = -1;
6567
6568 /* If the considered data is wider then HOST_WIDE_INT, we can't
6569 represent a mask for all its bits in a single scalar.
6570 But we only care about the lower bits, so calculate these. */
6571
6572 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6573 {
6044 nonzero = ~(HOST_WIDE_INT)0;
6574 nonzero = ~ (HOST_WIDE_INT) 0;
6045
6046 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6047 is the number of bits a full-width mask would have set.
6048 We need only shift if these are fewer than nonzero can
6049 hold. If not, we must keep all bits set in nonzero. */
6050
6051 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6052 < HOST_BITS_PER_WIDE_INT)

--- 87 unchanged lines hidden (view full) ---

6140 {
6141 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6142 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6143 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6144
6145 return force_to_mode (x, mode, mask, reg, next_select);
6146 }
6147
6575
6576 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6577 is the number of bits a full-width mask would have set.
6578 We need only shift if these are fewer than nonzero can
6579 hold. If not, we must keep all bits set in nonzero. */
6580
6581 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6582 < HOST_BITS_PER_WIDE_INT)

--- 87 unchanged lines hidden (view full) ---

6670 {
6671 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6672 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6673 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6674
6675 return force_to_mode (x, mode, mask, reg, next_select);
6676 }
6677
6678 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6679 use the full mask inside the NOT. */
6680 mask = fuller_mask;
6681
6148 unop:
6149 op0 = gen_lowpart_for_combine (op_mode,
6150 force_to_mode (XEXP (x, 0), mode, mask,
6151 reg, next_select));
6152 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6153 x = gen_unary (code, op_mode, op_mode, op0);
6154 break;
6155
6156 case NE:
6157 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6682 unop:
6683 op0 = gen_lowpart_for_combine (op_mode,
6684 force_to_mode (XEXP (x, 0), mode, mask,
6685 reg, next_select));
6686 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6687 x = gen_unary (code, op_mode, op_mode, op0);
6688 break;
6689
6690 case NE:
6691 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6158 in STORE_FLAG_VALUE and FOO has no bits that might be nonzero not
6159 in CONST. */
6160 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 0) == const0_rtx
6161 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0)
6692 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6693 which is equal to STORE_FLAG_VALUE. */
6694 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6695 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6696 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
6162 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6163
6164 break;
6165
6166 case IF_THEN_ELSE:
6167 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6168 written in a narrower mode. We play it safe and do not do so. */
6169
6170 SUBST (XEXP (x, 1),
6171 gen_lowpart_for_combine (GET_MODE (x),
6172 force_to_mode (XEXP (x, 1), mode,
6173 mask, reg, next_select)));
6174 SUBST (XEXP (x, 2),
6175 gen_lowpart_for_combine (GET_MODE (x),
6176 force_to_mode (XEXP (x, 2), mode,
6177 mask, reg,next_select)));
6178 break;
6697 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6698
6699 break;
6700
6701 case IF_THEN_ELSE:
6702 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6703 written in a narrower mode. We play it safe and do not do so. */
6704
6705 SUBST (XEXP (x, 1),
6706 gen_lowpart_for_combine (GET_MODE (x),
6707 force_to_mode (XEXP (x, 1), mode,
6708 mask, reg, next_select)));
6709 SUBST (XEXP (x, 2),
6710 gen_lowpart_for_combine (GET_MODE (x),
6711 force_to_mode (XEXP (x, 2), mode,
6712 mask, reg,next_select)));
6713 break;
6714
6715 default:
6716 break;
6179 }
6180
6181 /* Ensure we return a value of the proper mode. */
6182 return gen_lowpart_for_combine (mode, x);
6183}
6184
6185/* Return nonzero if X is an expression that has one of two values depending on
6186 whether some other value is zero or nonzero. In that case, we return the

--- 35 unchanged lines hidden (view full) ---

6222 || GET_RTX_CLASS (code) == '<')
6223 {
6224 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6225 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6226
6227 if ((cond0 != 0 || cond1 != 0)
6228 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6229 {
6717 }
6718
6719 /* Ensure we return a value of the proper mode. */
6720 return gen_lowpart_for_combine (mode, x);
6721}
6722
6723/* Return nonzero if X is an expression that has one of two values depending on
6724 whether some other value is zero or nonzero. In that case, we return the

--- 35 unchanged lines hidden (view full) ---

6760 || GET_RTX_CLASS (code) == '<')
6761 {
6762 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6763 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6764
6765 if ((cond0 != 0 || cond1 != 0)
6766 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6767 {
6768 /* If if_then_else_cond returned zero, then true/false are the
6769 same rtl. We must copy one of them to prevent invalid rtl
6770 sharing. */
6771 if (cond0 == 0)
6772 true0 = copy_rtx (true0);
6773 else if (cond1 == 0)
6774 true1 = copy_rtx (true1);
6775
6230 *ptrue = gen_binary (code, mode, true0, true1);
6231 *pfalse = gen_binary (code, mode, false0, false1);
6232 return cond0 ? cond0 : cond1;
6233 }
6234
6776 *ptrue = gen_binary (code, mode, true0, true1);
6777 *pfalse = gen_binary (code, mode, false0, false1);
6778 return cond0 ? cond0 : cond1;
6779 }
6780
6235#if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
6236
6237 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6781 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6238 operands is zero when the other is non-zero, and vice-versa. */
6782 operands is zero when the other is non-zero, and vice-versa,
6783 and STORE_FLAG_VALUE is 1 or -1. */
6239
6784
6240 if ((code == PLUS || code == IOR || code == XOR || code == MINUS
6785 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6786 && (code == PLUS || code == IOR || code == XOR || code == MINUS
6241 || code == UMAX)
6242 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6243 {
6244 rtx op0 = XEXP (XEXP (x, 0), 1);
6245 rtx op1 = XEXP (XEXP (x, 1), 1);
6246
6247 cond0 = XEXP (XEXP (x, 0), 0);
6248 cond1 = XEXP (XEXP (x, 1), 0);

--- 16 unchanged lines hidden (view full) ---

6265 ? gen_unary (NEG, mode, mode, op1) : op1),
6266 const_true_rtx);
6267 return cond0;
6268 }
6269 }
6270
6271 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6272 is always zero. */
6787 || code == UMAX)
6788 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6789 {
6790 rtx op0 = XEXP (XEXP (x, 0), 1);
6791 rtx op1 = XEXP (XEXP (x, 1), 1);
6792
6793 cond0 = XEXP (XEXP (x, 0), 0);
6794 cond1 = XEXP (XEXP (x, 1), 0);

--- 16 unchanged lines hidden (view full) ---

6811 ? gen_unary (NEG, mode, mode, op1) : op1),
6812 const_true_rtx);
6813 return cond0;
6814 }
6815 }
6816
6817 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6818 is always zero. */
6273 if ((code == MULT || code == AND || code == UMIN)
6819 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6820 && (code == MULT || code == AND || code == UMIN)
6274 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6275 {
6276 cond0 = XEXP (XEXP (x, 0), 0);
6277 cond1 = XEXP (XEXP (x, 1), 0);
6278
6279 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6280 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6281 && reversible_comparison_p (cond1)

--- 5 unchanged lines hidden (view full) ---

6287 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6288 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6289 && ! side_effects_p (x))
6290 {
6291 *ptrue = *pfalse = const0_rtx;
6292 return cond0;
6293 }
6294 }
6821 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6822 {
6823 cond0 = XEXP (XEXP (x, 0), 0);
6824 cond1 = XEXP (XEXP (x, 1), 0);
6825
6826 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6827 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6828 && reversible_comparison_p (cond1)

--- 5 unchanged lines hidden (view full) ---

6834 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6835 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6836 && ! side_effects_p (x))
6837 {
6838 *ptrue = *pfalse = const0_rtx;
6839 return cond0;
6840 }
6841 }
6295#endif
6296 }
6297
6298 else if (code == IF_THEN_ELSE)
6299 {
6300 /* If we have IF_THEN_ELSE already, extract the condition and
6301 canonicalize it if it is NE or EQ. */
6302 cond0 = XEXP (x, 0);
6303 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);

--- 81 unchanged lines hidden (view full) ---

6385 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6386 switch (cond)
6387 {
6388 case GE: case GT: case EQ:
6389 return XEXP (x, 0);
6390 case LT: case LE:
6391 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6392 XEXP (x, 0));
6842 }
6843
6844 else if (code == IF_THEN_ELSE)
6845 {
6846 /* If we have IF_THEN_ELSE already, extract the condition and
6847 canonicalize it if it is NE or EQ. */
6848 cond0 = XEXP (x, 0);
6849 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);

--- 81 unchanged lines hidden (view full) ---

6931 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6932 switch (cond)
6933 {
6934 case GE: case GT: case EQ:
6935 return XEXP (x, 0);
6936 case LT: case LE:
6937 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6938 XEXP (x, 0));
6939 default:
6940 break;
6393 }
6394
6395 /* The only other cases we handle are MIN, MAX, and comparisons if the
6396 operands are the same as REG and VAL. */
6397
6398 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6399 {
6400 if (rtx_equal_p (XEXP (x, 0), val))

--- 20 unchanged lines hidden (view full) ---

6421 case GE: case GT:
6422 return unsignedp ? x : XEXP (x, 1);
6423 case LE: case LT:
6424 return unsignedp ? x : XEXP (x, 0);
6425 case GEU: case GTU:
6426 return unsignedp ? XEXP (x, 1) : x;
6427 case LEU: case LTU:
6428 return unsignedp ? XEXP (x, 0) : x;
6941 }
6942
6943 /* The only other cases we handle are MIN, MAX, and comparisons if the
6944 operands are the same as REG and VAL. */
6945
6946 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6947 {
6948 if (rtx_equal_p (XEXP (x, 0), val))

--- 20 unchanged lines hidden (view full) ---

6969 case GE: case GT:
6970 return unsignedp ? x : XEXP (x, 1);
6971 case LE: case LT:
6972 return unsignedp ? x : XEXP (x, 0);
6973 case GEU: case GTU:
6974 return unsignedp ? XEXP (x, 1) : x;
6975 case LEU: case LTU:
6976 return unsignedp ? XEXP (x, 0) : x;
6977 default:
6978 break;
6429 }
6430 }
6431 }
6432 }
6433
6434 fmt = GET_RTX_FORMAT (code);
6435 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6436 {
6437 if (fmt[i] == 'e')
6438 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6439 else if (fmt[i] == 'E')
6440 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6441 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6442 cond, reg, val));
6443 }
6444
6445 return x;
6446}
6447
6979 }
6980 }
6981 }
6982 }
6983
6984 fmt = GET_RTX_FORMAT (code);
6985 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6986 {
6987 if (fmt[i] == 'e')
6988 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6989 else if (fmt[i] == 'E')
6990 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6991 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6992 cond, reg, val));
6993 }
6994
6995 return x;
6996}
6997
6998/* See if X and Y are equal for the purposes of seeing if we can rewrite an
6999 assignment as a field assignment. */
7000
7001static int
7002rtx_equal_for_field_assignment_p (x, y)
7003 rtx x;
7004 rtx y;
7005{
7006 if (x == y || rtx_equal_p (x, y))
7007 return 1;
7008
7009 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7010 return 0;
7011
7012 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7013 Note that all SUBREGs of MEM are paradoxical; otherwise they
7014 would have been rewritten. */
7015 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7016 && GET_CODE (SUBREG_REG (y)) == MEM
7017 && rtx_equal_p (SUBREG_REG (y),
7018 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7019 return 1;
7020
7021 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7022 && GET_CODE (SUBREG_REG (x)) == MEM
7023 && rtx_equal_p (SUBREG_REG (x),
7024 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7025 return 1;
7026
7027 /* We used to see if get_last_value of X and Y were the same but that's
7028 not correct. In one direction, we'll cause the assignment to have
7029 the wrong destination and in the case, we'll import a register into this
7030 insn that might have already have been dead. So fail if none of the
7031 above cases are true. */
7032 return 0;
7033}
7034
6448/* See if X, a SET operation, can be rewritten as a bit-field assignment.
6449 Return that assignment if so.
6450
6451 We only handle the most common cases. */
6452
6453static rtx
6454make_field_assignment (x)
6455 rtx x;
6456{
6457 rtx dest = SET_DEST (x);
6458 rtx src = SET_SRC (x);
6459 rtx assign;
7035/* See if X, a SET operation, can be rewritten as a bit-field assignment.
7036 Return that assignment if so.
7037
7038 We only handle the most common cases. */
7039
7040static rtx
7041make_field_assignment (x)
7042 rtx x;
7043{
7044 rtx dest = SET_DEST (x);
7045 rtx src = SET_SRC (x);
7046 rtx assign;
7047 rtx rhs, lhs;
6460 HOST_WIDE_INT c1;
6461 int pos, len;
6462 rtx other;
6463 enum machine_mode mode;
6464
6465 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6466 a clear of a one-bit field. We will have changed it to
6467 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
6468 for a SUBREG. */
6469
6470 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
6471 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
6472 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7048 HOST_WIDE_INT c1;
7049 int pos, len;
7050 rtx other;
7051 enum machine_mode mode;
7052
7053 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7054 a clear of a one-bit field. We will have changed it to
7055 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7056 for a SUBREG. */
7057
7058 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7059 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7060 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
6473 && (rtx_equal_p (dest, XEXP (src, 1))
6474 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
6475 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
7061 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6476 {
6477 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6478 1, 1, 1, 0);
7062 {
7063 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7064 1, 1, 1, 0);
6479 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
7065 if (assign != 0)
7066 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7067 return x;
6480 }
6481
6482 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
6483 && subreg_lowpart_p (XEXP (src, 0))
6484 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
6485 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
6486 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
6487 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7068 }
7069
7070 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7071 && subreg_lowpart_p (XEXP (src, 0))
7072 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7073 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7074 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7075 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
6488 && (rtx_equal_p (dest, XEXP (src, 1))
6489 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
6490 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
7076 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6491 {
6492 assign = make_extraction (VOIDmode, dest, 0,
6493 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
6494 1, 1, 1, 0);
7077 {
7078 assign = make_extraction (VOIDmode, dest, 0,
7079 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7080 1, 1, 1, 0);
6495 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
7081 if (assign != 0)
7082 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7083 return x;
6496 }
6497
7084 }
7085
6498 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
7086 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
6499 one-bit field. */
6500 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
6501 && XEXP (XEXP (src, 0), 0) == const1_rtx
7087 one-bit field. */
7088 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7089 && XEXP (XEXP (src, 0), 0) == const1_rtx
6502 && (rtx_equal_p (dest, XEXP (src, 1))
6503 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
6504 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
7090 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6505 {
6506 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6507 1, 1, 1, 0);
7091 {
7092 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7093 1, 1, 1, 0);
6508 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
7094 if (assign != 0)
7095 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7096 return x;
6509 }
6510
6511 /* The other case we handle is assignments into a constant-position
7097 }
7098
7099 /* The other case we handle is assignments into a constant-position
6512 field. They look like (ior (and DEST C1) OTHER). If C1 represents
7100 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
6513 a mask that has all one bits except for a group of zero bits and
6514 OTHER is known to have zeros where C1 has ones, this is such an
6515 assignment. Compute the position and length from C1. Shift OTHER
6516 to the appropriate position, force it to the required mode, and
6517 make the extraction. Check for the AND in both operands. */
6518
7101 a mask that has all one bits except for a group of zero bits and
7102 OTHER is known to have zeros where C1 has ones, this is such an
7103 assignment. Compute the position and length from C1. Shift OTHER
7104 to the appropriate position, force it to the required mode, and
7105 make the extraction. Check for the AND in both operands. */
7106
6519 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND
6520 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
6521 && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest)
6522 || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest))
6523 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest)))
6524 c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1);
6525 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND
6526 && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT
6527 && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest)
6528 || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest))
6529 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)),
6530 dest)))
6531 c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0);
7107 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7108 return x;
7109
7110 rhs = expand_compound_operation (XEXP (src, 0));
7111 lhs = expand_compound_operation (XEXP (src, 1));
7112
7113 if (GET_CODE (rhs) == AND
7114 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7115 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7116 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7117 else if (GET_CODE (lhs) == AND
7118 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7119 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7120 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
6532 else
6533 return x;
6534
7121 else
7122 return x;
7123
6535 pos = get_pos_from_mask (c1 ^ GET_MODE_MASK (GET_MODE (dest)), &len);
7124 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
6536 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7125 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
6537 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
6538 && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
7126 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7127 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
6539 return x;
6540
6541 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7128 return x;
7129
7130 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7131 if (assign == 0)
7132 return x;
6542
6543 /* The mode to use for the source is the mode of the assignment, or of
6544 what is inside a possible STRICT_LOW_PART. */
6545 mode = (GET_CODE (assign) == STRICT_LOW_PART
6546 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
6547
6548 /* Shift OTHER right POS places and make it the source, restricting it
6549 to the proper length and mode. */

--- 29 unchanged lines hidden (view full) ---

6579
6580 /* The outer operation can only be one of the following: */
6581 if (code != IOR && code != AND && code != XOR
6582 && code != PLUS && code != MINUS)
6583 return x;
6584
6585 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
6586
7133
7134 /* The mode to use for the source is the mode of the assignment, or of
7135 what is inside a possible STRICT_LOW_PART. */
7136 mode = (GET_CODE (assign) == STRICT_LOW_PART
7137 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7138
7139 /* Shift OTHER right POS places and make it the source, restricting it
7140 to the proper length and mode. */

--- 29 unchanged lines hidden (view full) ---

7170
7171 /* The outer operation can only be one of the following: */
7172 if (code != IOR && code != AND && code != XOR
7173 && code != PLUS && code != MINUS)
7174 return x;
7175
7176 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7177
6587 /* If either operand is a primitive we can't do anything, so get out fast. */
7178 /* If either operand is a primitive we can't do anything, so get out
7179 fast. */
6588 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
6589 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
6590 return x;
6591
6592 lhs = expand_compound_operation (lhs);
6593 rhs = expand_compound_operation (rhs);
6594 inner_code = GET_CODE (lhs);
6595 if (inner_code != GET_CODE (rhs))

--- 168 unchanged lines hidden (view full) ---

6764 if we already had one (just check for the simplest cases). */
6765 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
6766 && GET_MODE (XEXP (x, 0)) == mode
6767 && SUBREG_REG (XEXP (x, 0)) == varop)
6768 varop = XEXP (x, 0);
6769 else
6770 varop = gen_lowpart_for_combine (mode, varop);
6771
7180 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7181 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7182 return x;
7183
7184 lhs = expand_compound_operation (lhs);
7185 rhs = expand_compound_operation (rhs);
7186 inner_code = GET_CODE (lhs);
7187 if (inner_code != GET_CODE (rhs))

--- 168 unchanged lines hidden (view full) ---

7356 if we already had one (just check for the simplest cases). */
7357 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7358 && GET_MODE (XEXP (x, 0)) == mode
7359 && SUBREG_REG (XEXP (x, 0)) == varop)
7360 varop = XEXP (x, 0);
7361 else
7362 varop = gen_lowpart_for_combine (mode, varop);
7363
6772 /* If we can't make the SUBREG, try to return what we were given. */
7364 /* If we can't make the SUBREG, try to return what we were given. */
6773 if (GET_CODE (varop) == CLOBBER)
6774 return x ? x : varop;
6775
6776 /* If we are only masking insignificant bits, return VAROP. */
6777 if (constop == nonzero)
6778 x = varop;
6779
6780 /* Otherwise, return an AND. See how much, if any, of X we can use. */

--- 7 unchanged lines hidden (view full) ---

6788 SUBST (XEXP (x, 1), GEN_INT (constop));
6789
6790 SUBST (XEXP (x, 0), varop);
6791 }
6792
6793 return x;
6794}
6795
7365 if (GET_CODE (varop) == CLOBBER)
7366 return x ? x : varop;
7367
7368 /* If we are only masking insignificant bits, return VAROP. */
7369 if (constop == nonzero)
7370 x = varop;
7371
7372 /* Otherwise, return an AND. See how much, if any, of X we can use. */

--- 7 unchanged lines hidden (view full) ---

7380 SUBST (XEXP (x, 1), GEN_INT (constop));
7381
7382 SUBST (XEXP (x, 0), varop);
7383 }
7384
7385 return x;
7386}
7387
7388/* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7389 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7390 is less useful. We can't allow both, because that results in exponential
7391 run time recursion. There is a nullstone testcase that triggered
7392 this. This macro avoids accidental uses of num_sign_bit_copies. */
7393#define num_sign_bit_copies()
7394
6796/* Given an expression, X, compute which bits in X can be non-zero.
6797 We don't care about bits outside of those defined in MODE.
6798
6799 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
6800 a shift, AND, or zero_extract, we can do better. */
6801
6802static unsigned HOST_WIDE_INT
6803nonzero_bits (x, mode)

--- 55 unchanged lines hidden (view full) ---

6859#endif
6860
6861#ifdef STACK_BOUNDARY
6862 /* If this is the stack pointer, we may know something about its
6863 alignment. If PUSH_ROUNDING is defined, it is possible for the
6864 stack to be momentarily aligned only to that amount, so we pick
6865 the least alignment. */
6866
7395/* Given an expression, X, compute which bits in X can be non-zero.
7396 We don't care about bits outside of those defined in MODE.
7397
7398 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7399 a shift, AND, or zero_extract, we can do better. */
7400
7401static unsigned HOST_WIDE_INT
7402nonzero_bits (x, mode)

--- 55 unchanged lines hidden (view full) ---

7458#endif
7459
7460#ifdef STACK_BOUNDARY
7461 /* If this is the stack pointer, we may know something about its
7462 alignment. If PUSH_ROUNDING is defined, it is possible for the
7463 stack to be momentarily aligned only to that amount, so we pick
7464 the least alignment. */
7465
6867 if (x == stack_pointer_rtx)
7466 /* We can't check for arg_pointer_rtx here, because it is not
7467 guaranteed to have as much alignment as the stack pointer.
7468 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7469 alignment but the argument pointer has only 64 bit alignment. */
7470
7471 if ((x == frame_pointer_rtx
7472 || x == stack_pointer_rtx
7473 || x == hard_frame_pointer_rtx
7474 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7475 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7476#ifdef STACK_BIAS
7477 && !STACK_BIAS
7478#endif
7479 )
6868 {
6869 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6870
6871#ifdef PUSH_ROUNDING
7480 {
7481 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7482
7483#ifdef PUSH_ROUNDING
6872 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7484 if (REGNO (x) == STACK_POINTER_REGNUM)
7485 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
6873#endif
6874
6875 /* We must return here, otherwise we may get a worse result from
6876 one of the choices below. There is nothing useful below as
6877 far as the stack pointer is concerned. */
6878 return nonzero &= ~ (sp_alignment - 1);
6879 }
6880#endif
6881
6882 /* If X is a register whose nonzero bits value is current, use it.
6883 Otherwise, if X is a register whose value we can find, use that
6884 value. Otherwise, use the previously-computed global nonzero bits
6885 for this register. */
6886
6887 if (reg_last_set_value[REGNO (x)] != 0
6888 && reg_last_set_mode[REGNO (x)] == mode
7486#endif
7487
7488 /* We must return here, otherwise we may get a worse result from
7489 one of the choices below. There is nothing useful below as
7490 far as the stack pointer is concerned. */
7491 return nonzero &= ~ (sp_alignment - 1);
7492 }
7493#endif
7494
7495 /* If X is a register whose nonzero bits value is current, use it.
7496 Otherwise, if X is a register whose value we can find, use that
7497 value. Otherwise, use the previously-computed global nonzero bits
7498 for this register. */
7499
7500 if (reg_last_set_value[REGNO (x)] != 0
7501 && reg_last_set_mode[REGNO (x)] == mode
6889 && (reg_n_sets[REGNO (x)] == 1
7502 && (REG_N_SETS (REGNO (x)) == 1
6890 || reg_last_set_label[REGNO (x)] == label_tick)
6891 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
6892 return reg_last_set_nonzero_bits[REGNO (x)];
6893
6894 tem = get_last_value (x);
6895
6896 if (tem)
6897 {

--- 55 unchanged lines hidden (view full) ---

6953 now done above. */
6954
6955 if (GET_MODE_CLASS (mode) == MODE_INT
6956 && mode_width <= HOST_BITS_PER_WIDE_INT)
6957 nonzero = STORE_FLAG_VALUE;
6958 break;
6959
6960 case NEG:
7503 || reg_last_set_label[REGNO (x)] == label_tick)
7504 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7505 return reg_last_set_nonzero_bits[REGNO (x)];
7506
7507 tem = get_last_value (x);
7508
7509 if (tem)
7510 {

--- 55 unchanged lines hidden (view full) ---

7566 now done above. */
7567
7568 if (GET_MODE_CLASS (mode) == MODE_INT
7569 && mode_width <= HOST_BITS_PER_WIDE_INT)
7570 nonzero = STORE_FLAG_VALUE;
7571 break;
7572
7573 case NEG:
7574#if 0
7575 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7576 and num_sign_bit_copies. */
6961 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6962 == GET_MODE_BITSIZE (GET_MODE (x)))
6963 nonzero = 1;
7577 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7578 == GET_MODE_BITSIZE (GET_MODE (x)))
7579 nonzero = 1;
7580#endif
6964
6965 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
6966 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
6967 break;
6968
6969 case ABS:
7581
7582 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7583 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7584 break;
7585
7586 case ABS:
7587#if 0
7588 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7589 and num_sign_bit_copies. */
6970 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6971 == GET_MODE_BITSIZE (GET_MODE (x)))
6972 nonzero = 1;
7590 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7591 == GET_MODE_BITSIZE (GET_MODE (x)))
7592 nonzero = 1;
7593#endif
6973 break;
6974
6975 case TRUNCATE:
6976 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
6977 break;
6978
6979 case ZERO_EXTEND:
6980 nonzero &= nonzero_bits (XEXP (x, 0), mode);

--- 4 unchanged lines hidden (view full) ---

6985 case SIGN_EXTEND:
6986 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
6987 Otherwise, show all the bits in the outer mode but not the inner
6988 may be non-zero. */
6989 inner_nz = nonzero_bits (XEXP (x, 0), mode);
6990 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6991 {
6992 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7594 break;
7595
7596 case TRUNCATE:
7597 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7598 break;
7599
7600 case ZERO_EXTEND:
7601 nonzero &= nonzero_bits (XEXP (x, 0), mode);

--- 4 unchanged lines hidden (view full) ---

7606 case SIGN_EXTEND:
7607 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7608 Otherwise, show all the bits in the outer mode but not the inner
7609 may be non-zero. */
7610 inner_nz = nonzero_bits (XEXP (x, 0), mode);
7611 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7612 {
7613 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6993 if (inner_nz &
6994 (((HOST_WIDE_INT) 1
6995 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7614 if (inner_nz
7615 & (((HOST_WIDE_INT) 1
7616 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
6996 inner_nz |= (GET_MODE_MASK (mode)
6997 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
6998 }
6999
7000 nonzero &= inner_nz;
7001 break;
7002
7003 case AND:

--- 27 unchanged lines hidden (view full) ---

7031 HOST_WIDE_INT op1_maybe_minusp
7032 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7033 int result_width = mode_width;
7034 int result_low = 0;
7035
7036 switch (code)
7037 {
7038 case PLUS:
7617 inner_nz |= (GET_MODE_MASK (mode)
7618 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7619 }
7620
7621 nonzero &= inner_nz;
7622 break;
7623
7624 case AND:

--- 27 unchanged lines hidden (view full) ---

7652 HOST_WIDE_INT op1_maybe_minusp
7653 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7654 int result_width = mode_width;
7655 int result_low = 0;
7656
7657 switch (code)
7658 {
7659 case PLUS:
7660#ifdef STACK_BIAS
7661 if (STACK_BIAS
7662 && (XEXP (x, 0) == stack_pointer_rtx
7663 || XEXP (x, 0) == frame_pointer_rtx)
7664 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7665 {
7666 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7667
7668 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
7669 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
7670 width0 = floor_log2 (nz0) + 1;
7671 width1 = floor_log2 (nz1) + 1;
7672 low0 = floor_log2 (nz0 & -nz0);
7673 low1 = floor_log2 (nz1 & -nz1);
7674 }
7675#endif
7039 result_width = MAX (width0, width1) + 1;
7040 result_low = MIN (low0, low1);
7041 break;
7042 case MINUS:
7043 result_low = MIN (low0, low1);
7044 break;
7045 case MULT:
7046 result_width = width0 + width1;

--- 10 unchanged lines hidden (view full) ---

7057 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7058 result_width = MIN (width0, width1);
7059 result_low = MIN (low0, low1);
7060 break;
7061 case UMOD:
7062 result_width = MIN (width0, width1);
7063 result_low = MIN (low0, low1);
7064 break;
7676 result_width = MAX (width0, width1) + 1;
7677 result_low = MIN (low0, low1);
7678 break;
7679 case MINUS:
7680 result_low = MIN (low0, low1);
7681 break;
7682 case MULT:
7683 result_width = width0 + width1;

--- 10 unchanged lines hidden (view full) ---

7694 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7695 result_width = MIN (width0, width1);
7696 result_low = MIN (low0, low1);
7697 break;
7698 case UMOD:
7699 result_width = MIN (width0, width1);
7700 result_low = MIN (low0, low1);
7701 break;
7702 default:
7703 abort ();
7065 }
7066
7067 if (result_width < mode_width)
7068 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7069
7070 if (result_low > 0)
7071 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7072 }

--- 18 unchanged lines hidden (view full) ---

7091 machines, we can compute this from which bits of the inner
7092 object might be nonzero. */
7093 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7094 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7095 <= HOST_BITS_PER_WIDE_INT))
7096 {
7097 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7098
7704 }
7705
7706 if (result_width < mode_width)
7707 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7708
7709 if (result_low > 0)
7710 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7711 }

--- 18 unchanged lines hidden (view full) ---

7730 machines, we can compute this from which bits of the inner
7731 object might be nonzero. */
7732 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7733 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7734 <= HOST_BITS_PER_WIDE_INT))
7735 {
7736 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7737
7099#ifndef WORD_REGISTER_OPERATIONS
7100 /* On many CISC machines, accessing an object in a wider mode
7101 causes the high-order bits to become undefined. So they are
7102 not known to be zero. */
7103 if (GET_MODE_SIZE (GET_MODE (x))
7104 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7105 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7106 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7738#if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
7739 /* If this is a typical RISC machine, we only have to worry
7740 about the way loads are extended. */
7741 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
7742 ? (nonzero
7743 & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1)))
7744 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
7107#endif
7745#endif
7746 {
7747 /* On many CISC machines, accessing an object in a wider mode
7748 causes the high-order bits to become undefined. So they are
7749 not known to be zero. */
7750 if (GET_MODE_SIZE (GET_MODE (x))
7751 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7752 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7753 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7754 }
7108 }
7109 break;
7110
7111 case ASHIFTRT:
7112 case LSHIFTRT:
7113 case ASHIFT:
7114 case ROTATE:
7115 /* The nonzero bits are in two classes: any bits within MODE

--- 43 unchanged lines hidden (view full) ---

7159 /* This is at most the number of bits in the mode. */
7160 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7161 break;
7162
7163 case IF_THEN_ELSE:
7164 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7165 | nonzero_bits (XEXP (x, 2), mode));
7166 break;
7755 }
7756 break;
7757
7758 case ASHIFTRT:
7759 case LSHIFTRT:
7760 case ASHIFT:
7761 case ROTATE:
7762 /* The nonzero bits are in two classes: any bits within MODE

--- 43 unchanged lines hidden (view full) ---

7806 /* This is at most the number of bits in the mode. */
7807 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7808 break;
7809
7810 case IF_THEN_ELSE:
7811 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7812 | nonzero_bits (XEXP (x, 2), mode));
7813 break;
7814
7815 default:
7816 break;
7167 }
7168
7169 return nonzero;
7170}
7817 }
7818
7819 return nonzero;
7820}
7821
7822/* See the macro definition above. */
7823#undef num_sign_bit_copies
7171
7172/* Return the number of bits at the high-order end of X that are known to
7173 be equal to the sign bit. X will be used in mode MODE; if MODE is
7174 VOIDmode, X will be used in its own mode. The returned value will always
7175 be between 1 and the number of bits in MODE. */
7176
7177static int
7178num_sign_bit_copies (x, mode)

--- 13 unchanged lines hidden (view full) ---

7192 if (mode == VOIDmode)
7193 mode = GET_MODE (x);
7194
7195 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7196 return 1;
7197
7198 bitwidth = GET_MODE_BITSIZE (mode);
7199
7824
7825/* Return the number of bits at the high-order end of X that are known to
7826 be equal to the sign bit. X will be used in mode MODE; if MODE is
7827 VOIDmode, X will be used in its own mode. The returned value will always
7828 be between 1 and the number of bits in MODE. */
7829
7830static int
7831num_sign_bit_copies (x, mode)

--- 13 unchanged lines hidden (view full) ---

7845 if (mode == VOIDmode)
7846 mode = GET_MODE (x);
7847
7848 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7849 return 1;
7850
7851 bitwidth = GET_MODE_BITSIZE (mode);
7852
7200 /* For a smaller object, just ignore the high bits. */
7853 /* For a smaller object, just ignore the high bits. */
7201 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7202 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7203 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7204
7854 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7855 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7856 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7857
7858 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7859 {
7205#ifndef WORD_REGISTER_OPERATIONS
7206 /* If this machine does not do all register operations on the entire
7207 register and MODE is wider than the mode of X, we can say nothing
7208 at all about the high-order bits. */
7860#ifndef WORD_REGISTER_OPERATIONS
7861 /* If this machine does not do all register operations on the entire
7862 register and MODE is wider than the mode of X, we can say nothing
7863 at all about the high-order bits. */
7209 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7210 return 1;
7864 return 1;
7865#else
7866 /* Likewise on machines that do, if the mode of the object is smaller
7867 than a word and loads of that size don't sign extend, we can say
7868 nothing about the high order bits. */
7869 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
7870#ifdef LOAD_EXTEND_OP
7871 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
7211#endif
7872#endif
7873 )
7874 return 1;
7875#endif
7876 }
7212
7213 switch (code)
7214 {
7215 case REG:
7216
7217#ifdef POINTERS_EXTEND_UNSIGNED
7218 /* If pointers extend signed and this is a pointer in Pmode, say that
7219 all the bits above ptr_mode are known to be sign bit copies. */
7220 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7221 && REGNO_POINTER_FLAG (REGNO (x)))
7222 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7223#endif
7224
7225 if (reg_last_set_value[REGNO (x)] != 0
7226 && reg_last_set_mode[REGNO (x)] == mode
7877
7878 switch (code)
7879 {
7880 case REG:
7881
7882#ifdef POINTERS_EXTEND_UNSIGNED
7883 /* If pointers extend signed and this is a pointer in Pmode, say that
7884 all the bits above ptr_mode are known to be sign bit copies. */
7885 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7886 && REGNO_POINTER_FLAG (REGNO (x)))
7887 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7888#endif
7889
7890 if (reg_last_set_value[REGNO (x)] != 0
7891 && reg_last_set_mode[REGNO (x)] == mode
7227 && (reg_n_sets[REGNO (x)] == 1
7892 && (REG_N_SETS (REGNO (x)) == 1
7228 || reg_last_set_label[REGNO (x)] == label_tick)
7229 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7230 return reg_last_set_sign_bit_copies[REGNO (x)];
7231
7232 tem = get_last_value (x);
7233 if (tem != 0)
7234 return num_sign_bit_copies (tem, mode);
7235

--- 23 unchanged lines hidden (view full) ---

7259 /* If this is a SUBREG for a promoted object that is sign-extended
7260 and we are looking at it in a wider mode, we know that at least the
7261 high-order bits are known to be sign bit copies. */
7262
7263 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7264 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7265 num_sign_bit_copies (SUBREG_REG (x), mode));
7266
7893 || reg_last_set_label[REGNO (x)] == label_tick)
7894 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7895 return reg_last_set_sign_bit_copies[REGNO (x)];
7896
7897 tem = get_last_value (x);
7898 if (tem != 0)
7899 return num_sign_bit_copies (tem, mode);
7900

--- 23 unchanged lines hidden (view full) ---

7924 /* If this is a SUBREG for a promoted object that is sign-extended
7925 and we are looking at it in a wider mode, we know that at least the
7926 high-order bits are known to be sign bit copies. */
7927
7928 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7929 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7930 num_sign_bit_copies (SUBREG_REG (x), mode));
7931
7267 /* For a smaller object, just ignore the high bits. */
7932 /* For a smaller object, just ignore the high bits. */
7268 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7269 {
7270 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7271 return MAX (1, (num0
7272 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7273 - bitwidth)));
7274 }
7275

--- 22 unchanged lines hidden (view full) ---

7298 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7299 break;
7300
7301 case SIGN_EXTEND:
7302 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7303 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7304
7305 case TRUNCATE:
7933 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7934 {
7935 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7936 return MAX (1, (num0
7937 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7938 - bitwidth)));
7939 }
7940

--- 22 unchanged lines hidden (view full) ---

7963 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7964 break;
7965
7966 case SIGN_EXTEND:
7967 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7968 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7969
7970 case TRUNCATE:
7306 /* For a smaller object, just ignore the high bits. */
7971 /* For a smaller object, just ignore the high bits. */
7307 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7308 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7309 - bitwidth)));
7310
7311 case NOT:
7312 return num_sign_bit_copies (XEXP (x, 0), mode);
7313
7314 case ROTATE: case ROTATERT:

--- 9 unchanged lines hidden (view full) ---

7324 }
7325 break;
7326
7327 case NEG:
7328 /* In general, this subtracts one sign bit copy. But if the value
7329 is known to be positive, the number of sign bit copies is the
7330 same as that of the input. Finally, if the input has just one bit
7331 that might be nonzero, all the bits are copies of the sign bit. */
7972 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7973 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7974 - bitwidth)));
7975
7976 case NOT:
7977 return num_sign_bit_copies (XEXP (x, 0), mode);
7978
7979 case ROTATE: case ROTATERT:

--- 9 unchanged lines hidden (view full) ---

7989 }
7990 break;
7991
7992 case NEG:
7993 /* In general, this subtracts one sign bit copy. But if the value
7994 is known to be positive, the number of sign bit copies is the
7995 same as that of the input. Finally, if the input has just one bit
7996 that might be nonzero, all the bits are copies of the sign bit. */
7997 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7998 if (bitwidth > HOST_BITS_PER_WIDE_INT)
7999 return num0 > 1 ? num0 - 1 : 1;
8000
7332 nonzero = nonzero_bits (XEXP (x, 0), mode);
7333 if (nonzero == 1)
7334 return bitwidth;
7335
8001 nonzero = nonzero_bits (XEXP (x, 0), mode);
8002 if (nonzero == 1)
8003 return bitwidth;
8004
7336 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7337 if (num0 > 1
8005 if (num0 > 1
7338 && bitwidth <= HOST_BITS_PER_WIDE_INT
7339 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
7340 num0--;
7341
7342 return num0;
7343
7344 case IOR: case AND: case XOR:
7345 case SMIN: case SMAX: case UMIN: case UMAX:
7346 /* Logical operations will preserve the number of sign-bit copies.

--- 27 unchanged lines hidden (view full) ---

7374 to be positive, we must allow for an additional bit since negating
7375 a negative number can remove one sign bit copy. */
7376
7377 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7378 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7379
7380 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
7381 if (result > 0
8006 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8007 num0--;
8008
8009 return num0;
8010
8011 case IOR: case AND: case XOR:
8012 case SMIN: case SMAX: case UMIN: case UMAX:
8013 /* Logical operations will preserve the number of sign-bit copies.

--- 27 unchanged lines hidden (view full) ---

8041 to be positive, we must allow for an additional bit since negating
8042 a negative number can remove one sign bit copy. */
8043
8044 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8045 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8046
8047 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8048 if (result > 0
7382 && bitwidth <= HOST_BITS_PER_WIDE_INT
7383 && ((nonzero_bits (XEXP (x, 0), mode)
7384 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7385 && (nonzero_bits (XEXP (x, 1), mode)
7386 & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) != 0))
8049 && (bitwidth > HOST_BITS_PER_WIDE_INT
8050 || (((nonzero_bits (XEXP (x, 0), mode)
8051 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8052 && ((nonzero_bits (XEXP (x, 1), mode)
8053 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
7387 result--;
7388
7389 return MAX (1, result);
7390
7391 case UDIV:
8054 result--;
8055
8056 return MAX (1, result);
8057
8058 case UDIV:
7392 /* The result must be <= the first operand. */
7393 return num_sign_bit_copies (XEXP (x, 0), mode);
7394
8059 /* The result must be <= the first operand. If the first operand
8060 has the high bit set, we know nothing about the number of sign
8061 bit copies. */
8062 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8063 return 1;
8064 else if ((nonzero_bits (XEXP (x, 0), mode)
8065 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8066 return 1;
8067 else
8068 return num_sign_bit_copies (XEXP (x, 0), mode);
8069
7395 case UMOD:
7396 /* The result must be <= the scond operand. */
7397 return num_sign_bit_copies (XEXP (x, 1), mode);
7398
7399 case DIV:
7400 /* Similar to unsigned division, except that we have to worry about
7401 the case where the divisor is negative, in which case we have
7402 to add 1. */
7403 result = num_sign_bit_copies (XEXP (x, 0), mode);
7404 if (result > 1
8070 case UMOD:
8071 /* The result must be <= the scond operand. */
8072 return num_sign_bit_copies (XEXP (x, 1), mode);
8073
8074 case DIV:
8075 /* Similar to unsigned division, except that we have to worry about
8076 the case where the divisor is negative, in which case we have
8077 to add 1. */
8078 result = num_sign_bit_copies (XEXP (x, 0), mode);
8079 if (result > 1
7405 && bitwidth <= HOST_BITS_PER_WIDE_INT
7406 && (nonzero_bits (XEXP (x, 1), mode)
7407 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7408 result --;
8080 && (bitwidth > HOST_BITS_PER_WIDE_INT
8081 || (nonzero_bits (XEXP (x, 1), mode)
8082 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8083 result--;
7409
7410 return result;
7411
7412 case MOD:
7413 result = num_sign_bit_copies (XEXP (x, 1), mode);
7414 if (result > 1
8084
8085 return result;
8086
8087 case MOD:
8088 result = num_sign_bit_copies (XEXP (x, 1), mode);
8089 if (result > 1
7415 && bitwidth <= HOST_BITS_PER_WIDE_INT
7416 && (nonzero_bits (XEXP (x, 1), mode)
7417 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7418 result --;
8090 && (bitwidth > HOST_BITS_PER_WIDE_INT
8091 || (nonzero_bits (XEXP (x, 1), mode)
8092 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8093 result--;
7419
7420 return result;
7421
7422 case ASHIFTRT:
7423 /* Shifts by a constant add to the number of bits equal to the
7424 sign bit. */
7425 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7426 if (GET_CODE (XEXP (x, 1)) == CONST_INT

--- 12 unchanged lines hidden (view full) ---

7439 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7440 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
7441
7442 case IF_THEN_ELSE:
7443 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
7444 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
7445 return MIN (num0, num1);
7446
8094
8095 return result;
8096
8097 case ASHIFTRT:
8098 /* Shifts by a constant add to the number of bits equal to the
8099 sign bit. */
8100 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8101 if (GET_CODE (XEXP (x, 1)) == CONST_INT

--- 12 unchanged lines hidden (view full) ---

8114 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8115 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8116
8117 case IF_THEN_ELSE:
8118 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8119 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8120 return MIN (num0, num1);
8121
7447#if STORE_FLAG_VALUE == -1
7448 case EQ: case NE: case GE: case GT: case LE: case LT:
7449 case GEU: case GTU: case LEU: case LTU:
8122 case EQ: case NE: case GE: case GT: case LE: case LT:
8123 case GEU: case GTU: case LEU: case LTU:
7450 return bitwidth;
7451#endif
8124 if (STORE_FLAG_VALUE == -1)
8125 return bitwidth;
8126 break;
8127
8128 default:
8129 break;
7452 }
7453
7454 /* If we haven't been able to figure it out by one of the above rules,
7455 see if some of the high-order bits are known to be zero. If so,
7456 count those bits and return one less than that amount. If we can't
7457 safely compute the mask for this mode, always return BITWIDTH. */
7458
7459 if (bitwidth > HOST_BITS_PER_WIDE_INT)

--- 95 unchanged lines hidden (view full) ---

7555 const0 ^= const1;
7556 break;
7557 case PLUS:
7558 const0 += const1;
7559 break;
7560 case NEG:
7561 op0 = NIL;
7562 break;
8130 }
8131
8132 /* If we haven't been able to figure it out by one of the above rules,
8133 see if some of the high-order bits are known to be zero. If so,
8134 count those bits and return one less than that amount. If we can't
8135 safely compute the mask for this mode, always return BITWIDTH. */
8136
8137 if (bitwidth > HOST_BITS_PER_WIDE_INT)

--- 95 unchanged lines hidden (view full) ---

8233 const0 ^= const1;
8234 break;
8235 case PLUS:
8236 const0 += const1;
8237 break;
8238 case NEG:
8239 op0 = NIL;
8240 break;
8241 default:
8242 break;
7563 }
7564 }
7565
7566 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
7567 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
7568 return 0;
7569
7570 /* If the two constants aren't the same, we can't do anything. The

--- 5 unchanged lines hidden (view full) ---

7576 switch (op0)
7577 {
7578 case IOR:
7579 if (op1 == AND)
7580 /* (a & b) | b == b */
7581 op0 = SET;
7582 else /* op1 == XOR */
7583 /* (a ^ b) | b == a | b */
8243 }
8244 }
8245
8246 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8247 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8248 return 0;
8249
8250 /* If the two constants aren't the same, we can't do anything. The

--- 5 unchanged lines hidden (view full) ---

8256 switch (op0)
8257 {
8258 case IOR:
8259 if (op1 == AND)
8260 /* (a & b) | b == b */
8261 op0 = SET;
8262 else /* op1 == XOR */
8263 /* (a ^ b) | b == a | b */
7584 ;
8264 {;}
7585 break;
7586
7587 case XOR:
7588 if (op1 == AND)
7589 /* (a & b) ^ b == (~a) & b */
7590 op0 = AND, *pcomp_p = 1;
7591 else /* op1 == IOR */
7592 /* (a | b) ^ b == a & ~b */
7593 op0 = AND, *pconst0 = ~ const0;
7594 break;
7595
7596 case AND:
7597 if (op1 == IOR)
7598 /* (a | b) & b == b */
7599 op0 = SET;
7600 else /* op1 == XOR */
7601 /* (a ^ b) & b) == (~a) & b */
7602 *pcomp_p = 1;
7603 break;
8265 break;
8266
8267 case XOR:
8268 if (op1 == AND)
8269 /* (a & b) ^ b == (~a) & b */
8270 op0 = AND, *pcomp_p = 1;
8271 else /* op1 == IOR */
8272 /* (a | b) ^ b == a & ~b */
8273 op0 = AND, *pconst0 = ~ const0;
8274 break;
8275
8276 case AND:
8277 if (op1 == IOR)
8278 /* (a | b) & b == b */
8279 op0 = SET;
8280 else /* op1 == XOR */
8281 /* (a ^ b) & b) == (~a) & b */
8282 *pcomp_p = 1;
8283 break;
8284 default:
8285 break;
7604 }
7605
7606 /* Check for NO-OP cases. */
7607 const0 &= GET_MODE_MASK (mode);
7608 if (const0 == 0
7609 && (op0 == IOR || op0 == XOR || op0 == PLUS))
7610 op0 = NIL;
7611 else if (const0 == 0 && op0 == AND)

--- 52 unchanged lines hidden (view full) ---

7664 /* If we were given an invalid count, don't do anything except exactly
7665 what was requested. */
7666
7667 if (count < 0 || count > GET_MODE_BITSIZE (mode))
7668 {
7669 if (x)
7670 return x;
7671
8286 }
8287
8288 /* Check for NO-OP cases. */
8289 const0 &= GET_MODE_MASK (mode);
8290 if (const0 == 0
8291 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8292 op0 = NIL;
8293 else if (const0 == 0 && op0 == AND)

--- 52 unchanged lines hidden (view full) ---

8346 /* If we were given an invalid count, don't do anything except exactly
8347 what was requested. */
8348
8349 if (count < 0 || count > GET_MODE_BITSIZE (mode))
8350 {
8351 if (x)
8352 return x;
8353
7672 return gen_rtx (code, mode, varop, GEN_INT (count));
8354 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (count));
7673 }
7674
7675 /* Unless one of the branches of the `if' in this loop does a `continue',
7676 we will `break' the loop after the `if'. */
7677
7678 while (count != 0)
7679 {
7680 /* If we have an operand of (clobber (const_int 0)), just return that

--- 8 unchanged lines hidden (view full) ---

7689
7690 /* Convert ROTATERT to ROTATE. */
7691 if (code == ROTATERT)
7692 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
7693
7694 /* We need to determine what mode we will do the shift in. If the
7695 shift is a right shift or a ROTATE, we must always do it in the mode
7696 it was originally done in. Otherwise, we can do it in MODE, the
8355 }
8356
8357 /* Unless one of the branches of the `if' in this loop does a `continue',
8358 we will `break' the loop after the `if'. */
8359
8360 while (count != 0)
8361 {
8362 /* If we have an operand of (clobber (const_int 0)), just return that

--- 8 unchanged lines hidden (view full) ---

8371
8372 /* Convert ROTATERT to ROTATE. */
8373 if (code == ROTATERT)
8374 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8375
8376 /* We need to determine what mode we will do the shift in. If the
8377 shift is a right shift or a ROTATE, we must always do it in the mode
8378 it was originally done in. Otherwise, we can do it in MODE, the
7697 widest mode encountered. */
8379 widest mode encountered. */
7698 shift_mode
7699 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
7700 ? result_mode : mode);
7701
7702 /* Handle cases where the count is greater than the size of the mode
7703 minus 1. For ASHIFT, use the size minus one as the count (this can
7704 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
7705 take the count modulo the size. For other shifts, the result is

--- 16 unchanged lines hidden (view full) ---

7722 varop = const0_rtx;
7723 count = 0;
7724 break;
7725 }
7726 }
7727
7728 /* Negative counts are invalid and should not have been made (a
7729 programmer-specified negative count should have been handled
8380 shift_mode
8381 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8382 ? result_mode : mode);
8383
8384 /* Handle cases where the count is greater than the size of the mode
8385 minus 1. For ASHIFT, use the size minus one as the count (this can
8386 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8387 take the count modulo the size. For other shifts, the result is

--- 16 unchanged lines hidden (view full) ---

8404 varop = const0_rtx;
8405 count = 0;
8406 break;
8407 }
8408 }
8409
8410 /* Negative counts are invalid and should not have been made (a
8411 programmer-specified negative count should have been handled
7730 above). */
8412 above). */
7731 else if (count < 0)
7732 abort ();
7733
7734 /* An arithmetic right shift of a quantity known to be -1 or 0
7735 is a no-op. */
7736 if (code == ASHIFTRT
7737 && (num_sign_bit_copies (varop, shift_mode)
7738 == GET_MODE_BITSIZE (shift_mode)))

--- 43 unchanged lines hidden (view full) ---

7782 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
7783 if ((code == ASHIFTRT || code == LSHIFTRT)
7784 && ! mode_dependent_address_p (XEXP (varop, 0))
7785 && ! MEM_VOLATILE_P (varop)
7786 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
7787 MODE_INT, 1)) != BLKmode)
7788 {
7789 if (BYTES_BIG_ENDIAN)
8413 else if (count < 0)
8414 abort ();
8415
8416 /* An arithmetic right shift of a quantity known to be -1 or 0
8417 is a no-op. */
8418 if (code == ASHIFTRT
8419 && (num_sign_bit_copies (varop, shift_mode)
8420 == GET_MODE_BITSIZE (shift_mode)))

--- 43 unchanged lines hidden (view full) ---

8464 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8465 if ((code == ASHIFTRT || code == LSHIFTRT)
8466 && ! mode_dependent_address_p (XEXP (varop, 0))
8467 && ! MEM_VOLATILE_P (varop)
8468 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8469 MODE_INT, 1)) != BLKmode)
8470 {
8471 if (BYTES_BIG_ENDIAN)
7790 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
8472 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
7791 else
8473 else
7792 new = gen_rtx (MEM, tmode,
7793 plus_constant (XEXP (varop, 0),
7794 count / BITS_PER_UNIT));
8474 new = gen_rtx_MEM (tmode,
8475 plus_constant (XEXP (varop, 0),
8476 count / BITS_PER_UNIT));
7795 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
7796 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
7797 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
7798 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
7799 : ZERO_EXTEND, mode, new);
7800 count = 0;
7801 continue;
7802 }

--- 72 unchanged lines hidden (view full) ---

7875 /* If we are extracting just the sign bit of an arithmetic right
7876 shift, that shift is not needed. */
7877 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
7878 {
7879 varop = XEXP (varop, 0);
7880 continue;
7881 }
7882
8477 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8478 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
8479 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
8480 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8481 : ZERO_EXTEND, mode, new);
8482 count = 0;
8483 continue;
8484 }

--- 72 unchanged lines hidden (view full) ---

8557 /* If we are extracting just the sign bit of an arithmetic right
8558 shift, that shift is not needed. */
8559 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8560 {
8561 varop = XEXP (varop, 0);
8562 continue;
8563 }
8564
7883 /* ... fall through ... */
8565 /* ... fall through ... */
7884
7885 case LSHIFTRT:
7886 case ASHIFT:
7887 case ROTATE:
7888 /* Here we have two nested shifts. The result is usually the
7889 AND of a new shift with a mask. We compute the result below. */
7890 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7891 && INTVAL (XEXP (varop, 1)) >= 0

--- 319 unchanged lines hidden (view full) ---

8211 case MINUS:
8212 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8213 with C the size of VAROP - 1 and the shift is logical if
8214 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8215 we have a (gt X 0) operation. If the shift is arithmetic with
8216 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8217 we have a (neg (gt X 0)) operation. */
8218
8566
8567 case LSHIFTRT:
8568 case ASHIFT:
8569 case ROTATE:
8570 /* Here we have two nested shifts. The result is usually the
8571 AND of a new shift with a mask. We compute the result below. */
8572 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8573 && INTVAL (XEXP (varop, 1)) >= 0

--- 319 unchanged lines hidden (view full) ---

8893 case MINUS:
8894 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8895 with C the size of VAROP - 1 and the shift is logical if
8896 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8897 we have a (gt X 0) operation. If the shift is arithmetic with
8898 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8899 we have a (neg (gt X 0)) operation. */
8900
8219 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8901 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8902 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8220 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8903 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8221 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8222 && (code == LSHIFTRT || code == ASHIFTRT)
8223 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8224 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8225 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8226 {
8227 count = 0;
8228 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8229 const0_rtx);
8230
8231 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8232 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8233
8234 continue;
8235 }
8236 break;
8904 && (code == LSHIFTRT || code == ASHIFTRT)
8905 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8906 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8907 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8908 {
8909 count = 0;
8910 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8911 const0_rtx);
8912
8913 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8914 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8915
8916 continue;
8917 }
8918 break;
8919
8920 case TRUNCATE:
8921 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
8922 if the truncate does not affect the value. */
8923 if (code == LSHIFTRT
8924 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
8925 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8926 && (INTVAL (XEXP (XEXP (varop, 0), 1))
8927 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
8928 - GET_MODE_BITSIZE (GET_MODE (varop)))))
8929 {
8930 rtx varop_inner = XEXP (varop, 0);
8931
8932 varop_inner = gen_rtx_combine (LSHIFTRT,
8933 GET_MODE (varop_inner),
8934 XEXP (varop_inner, 0),
8935 GEN_INT (count + INTVAL (XEXP (varop_inner, 1))));
8936 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
8937 varop_inner);
8938 count = 0;
8939 continue;
8940 }
8941 break;
8942
8943 default:
8944 break;
8237 }
8238
8239 break;
8240 }
8241
8242 /* We need to determine what mode to do the shift in. If the shift is
8243 a right shift or ROTATE, we must always do it in the mode it was
8244 originally done in. Otherwise, we can do it in MODE, the widest mode

--- 21 unchanged lines hidden (view full) ---

8266
8267 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8268 && GET_MODE (XEXP (x, 0)) == shift_mode
8269 && SUBREG_REG (XEXP (x, 0)) == varop)
8270 varop = XEXP (x, 0);
8271 else if (GET_MODE (varop) != shift_mode)
8272 varop = gen_lowpart_for_combine (shift_mode, varop);
8273
8945 }
8946
8947 break;
8948 }
8949
8950 /* We need to determine what mode to do the shift in. If the shift is
8951 a right shift or ROTATE, we must always do it in the mode it was
8952 originally done in. Otherwise, we can do it in MODE, the widest mode

--- 21 unchanged lines hidden (view full) ---

8974
8975 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8976 && GET_MODE (XEXP (x, 0)) == shift_mode
8977 && SUBREG_REG (XEXP (x, 0)) == varop)
8978 varop = XEXP (x, 0);
8979 else if (GET_MODE (varop) != shift_mode)
8980 varop = gen_lowpart_for_combine (shift_mode, varop);
8981
8274 /* If we can't make the SUBREG, try to return what we were given. */
8982 /* If we can't make the SUBREG, try to return what we were given. */
8275 if (GET_CODE (varop) == CLOBBER)
8276 return x ? x : varop;
8277
8278 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8279 if (new != 0)
8280 x = new;
8281 else
8282 {

--- 133 unchanged lines hidden (view full) ---

8416
8417 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8418 }
8419
8420 /* If we had any clobbers to add, make a new pattern than contains
8421 them. Then check to make sure that all of them are dead. */
8422 if (num_clobbers_to_add)
8423 {
8983 if (GET_CODE (varop) == CLOBBER)
8984 return x ? x : varop;
8985
8986 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8987 if (new != 0)
8988 x = new;
8989 else
8990 {

--- 133 unchanged lines hidden (view full) ---

9124
9125 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9126 }
9127
9128 /* If we had any clobbers to add, make a new pattern than contains
9129 them. Then check to make sure that all of them are dead. */
9130 if (num_clobbers_to_add)
9131 {
8424 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
8425 gen_rtvec (GET_CODE (pat) == PARALLEL
8426 ? XVECLEN (pat, 0) + num_clobbers_to_add
8427 : num_clobbers_to_add + 1));
9132 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9133 gen_rtvec (GET_CODE (pat) == PARALLEL
9134 ? XVECLEN (pat, 0) + num_clobbers_to_add
9135 : num_clobbers_to_add + 1));
8428
8429 if (GET_CODE (pat) == PARALLEL)
8430 for (i = 0; i < XVECLEN (pat, 0); i++)
8431 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
8432 else
8433 XVECEXP (newpat, 0, 0) = pat;
8434
8435 add_clobbers (newpat, insn_code_number);
8436
8437 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
8438 i < XVECLEN (newpat, 0); i++)
8439 {
8440 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
8441 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
8442 return -1;
8443 else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
8444 (*padded_scratches)++;
9136
9137 if (GET_CODE (pat) == PARALLEL)
9138 for (i = 0; i < XVECLEN (pat, 0); i++)
9139 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9140 else
9141 XVECEXP (newpat, 0, 0) = pat;
9142
9143 add_clobbers (newpat, insn_code_number);
9144
9145 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9146 i < XVECLEN (newpat, 0); i++)
9147 {
9148 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9149 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9150 return -1;
9151 else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
9152 (*padded_scratches)++;
8445 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
8446 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9153 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9154 XEXP (XVECEXP (newpat, 0, i), 0), notes);
8447 }
8448 pat = newpat;
8449 }
8450
8451 *pnewpat = pat;
8452 *pnotes = notes;
8453
8454 return insn_code_number;

--- 23 unchanged lines hidden (view full) ---

8478 /* We can only support MODE being wider than a word if X is a
8479 constant integer or has a mode the same size. */
8480
8481 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8482 && ! ((GET_MODE (x) == VOIDmode
8483 && (GET_CODE (x) == CONST_INT
8484 || GET_CODE (x) == CONST_DOUBLE))
8485 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9155 }
9156 pat = newpat;
9157 }
9158
9159 *pnewpat = pat;
9160 *pnotes = notes;
9161
9162 return insn_code_number;

--- 23 unchanged lines hidden (view full) ---

9186 /* We can only support MODE being wider than a word if X is a
9187 constant integer or has a mode the same size. */
9188
9189 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9190 && ! ((GET_MODE (x) == VOIDmode
9191 && (GET_CODE (x) == CONST_INT
9192 || GET_CODE (x) == CONST_DOUBLE))
9193 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
8486 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
9194 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
8487
8488 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
8489 won't know what to do. So we will strip off the SUBREG here and
8490 process normally. */
8491 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
8492 {
8493 x = SUBREG_REG (x);
8494 if (GET_MODE (x) == mode)
8495 return x;
8496 }
8497
8498 result = gen_lowpart_common (mode, x);
8499 if (result != 0
8500 && GET_CODE (result) == SUBREG
8501 && GET_CODE (SUBREG_REG (result)) == REG
8502 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
8503 && (GET_MODE_SIZE (GET_MODE (result))
8504 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
9195
9196 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9197 won't know what to do. So we will strip off the SUBREG here and
9198 process normally. */
9199 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9200 {
9201 x = SUBREG_REG (x);
9202 if (GET_MODE (x) == mode)
9203 return x;
9204 }
9205
9206 result = gen_lowpart_common (mode, x);
9207 if (result != 0
9208 && GET_CODE (result) == SUBREG
9209 && GET_CODE (SUBREG_REG (result)) == REG
9210 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9211 && (GET_MODE_SIZE (GET_MODE (result))
9212 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
8505 reg_changes_size[REGNO (SUBREG_REG (result))] = 1;
9213 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
8506
8507 if (result)
8508 return result;
8509
8510 if (GET_CODE (x) == MEM)
8511 {
8512 register int offset = 0;
8513 rtx new;
8514
8515 /* Refuse to work on a volatile memory ref or one with a mode-dependent
8516 address. */
8517 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9214
9215 if (result)
9216 return result;
9217
9218 if (GET_CODE (x) == MEM)
9219 {
9220 register int offset = 0;
9221 rtx new;
9222
9223 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9224 address. */
9225 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
8518 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
9226 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
8519
8520 /* If we want to refer to something bigger than the original memref,
8521 generate a perverse subreg instead. That will force a reload
8522 of the original memref X. */
8523 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9227
9228 /* If we want to refer to something bigger than the original memref,
9229 generate a perverse subreg instead. That will force a reload
9230 of the original memref X. */
9231 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
8524 return gen_rtx (SUBREG, mode, x, 0);
9232 return gen_rtx_SUBREG (mode, x, 0);
8525
8526 if (WORDS_BIG_ENDIAN)
8527 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
8528 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
8529 if (BYTES_BIG_ENDIAN)
8530 {
8531 /* Adjust the address so that the address-after-the-data is
8532 unchanged. */
8533 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
8534 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
8535 }
9233
9234 if (WORDS_BIG_ENDIAN)
9235 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9236 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9237 if (BYTES_BIG_ENDIAN)
9238 {
9239 /* Adjust the address so that the address-after-the-data is
9240 unchanged. */
9241 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9242 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9243 }
8536 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
9244 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
8537 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
8538 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
8539 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
8540 return new;
8541 }
8542
8543 /* If X is a comparison operator, rewrite it in a new mode. This
8544 probably won't match, but may allow further simplifications. */

--- 6 unchanged lines hidden (view full) ---

8551 else
8552 {
8553 int word = 0;
8554
8555 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
8556 word = ((GET_MODE_SIZE (GET_MODE (x))
8557 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
8558 / UNITS_PER_WORD);
9245 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
9246 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
9247 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
9248 return new;
9249 }
9250
9251 /* If X is a comparison operator, rewrite it in a new mode. This
9252 probably won't match, but may allow further simplifications. */

--- 6 unchanged lines hidden (view full) ---

9259 else
9260 {
9261 int word = 0;
9262
9263 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9264 word = ((GET_MODE_SIZE (GET_MODE (x))
9265 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9266 / UNITS_PER_WORD);
8559 return gen_rtx (SUBREG, mode, x, word);
9267 return gen_rtx_SUBREG (mode, x, word);
8560 }
8561}
8562
8563/* Make an rtx expression. This is a subset of gen_rtx and only supports
8564 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
8565
8566 If the identical expression was previously in the insn (in the undobuf),
8567 it will be returned. Only if it is not found will a new expression

--- 5 unchanged lines hidden (view full) ---

8573{
8574#ifndef __STDC__
8575 enum rtx_code code;
8576 enum machine_mode mode;
8577#endif
8578 va_list p;
8579 int n_args;
8580 rtx args[3];
9268 }
9269}
9270
9271/* Make an rtx expression. This is a subset of gen_rtx and only supports
9272 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9273
9274 If the identical expression was previously in the insn (in the undobuf),
9275 it will be returned. Only if it is not found will a new expression

--- 5 unchanged lines hidden (view full) ---

9281{
9282#ifndef __STDC__
9283 enum rtx_code code;
9284 enum machine_mode mode;
9285#endif
9286 va_list p;
9287 int n_args;
9288 rtx args[3];
8581 int i, j;
9289 int j;
8582 char *fmt;
8583 rtx rt;
9290 char *fmt;
9291 rtx rt;
9292 struct undo *undo;
8584
8585 VA_START (p, mode);
8586
8587#ifndef __STDC__
8588 code = va_arg (p, enum rtx_code);
8589 mode = va_arg (p, enum machine_mode);
8590#endif
8591

--- 10 unchanged lines hidden (view full) ---

8602 abort ();
8603
8604 args[j] = va_arg (p, rtx);
8605 }
8606
8607 /* See if this is in undobuf. Be sure we don't use objects that came
8608 from another insn; this could produce circular rtl structures. */
8609
9293
9294 VA_START (p, mode);
9295
9296#ifndef __STDC__
9297 code = va_arg (p, enum rtx_code);
9298 mode = va_arg (p, enum machine_mode);
9299#endif
9300

--- 10 unchanged lines hidden (view full) ---

9311 abort ();
9312
9313 args[j] = va_arg (p, rtx);
9314 }
9315
9316 /* See if this is in undobuf. Be sure we don't use objects that came
9317 from another insn; this could produce circular rtl structures. */
9318
8610 for (i = previous_num_undos; i < undobuf.num_undo; i++)
8611 if (!undobuf.undo[i].is_int
8612 && GET_CODE (undobuf.undo[i].old_contents.r) == code
8613 && GET_MODE (undobuf.undo[i].old_contents.r) == mode)
9319 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9320 if (!undo->is_int
9321 && GET_CODE (undo->old_contents.r) == code
9322 && GET_MODE (undo->old_contents.r) == mode)
8614 {
8615 for (j = 0; j < n_args; j++)
9323 {
9324 for (j = 0; j < n_args; j++)
8616 if (XEXP (undobuf.undo[i].old_contents.r, j) != args[j])
9325 if (XEXP (undo->old_contents.r, j) != args[j])
8617 break;
8618
8619 if (j == n_args)
9326 break;
9327
9328 if (j == n_args)
8620 return undobuf.undo[i].old_contents.r;
9329 return undo->old_contents.r;
8621 }
8622
8623 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
8624 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
8625 rt = rtx_alloc (code);
8626 PUT_MODE (rt, mode);
8627 XEXP (rt, 0) = args[0];
8628 if (n_args > 1)

--- 22 unchanged lines hidden (view full) ---

8651 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
8652 tem = op0, op0 = op1, op1 = tem;
8653
8654 if (GET_RTX_CLASS (code) == '<')
8655 {
8656 enum machine_mode op_mode = GET_MODE (op0);
8657
8658 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9330 }
9331
9332 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9333 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9334 rt = rtx_alloc (code);
9335 PUT_MODE (rt, mode);
9336 XEXP (rt, 0) = args[0];
9337 if (n_args > 1)

--- 22 unchanged lines hidden (view full) ---

9360 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9361 tem = op0, op0 = op1, op1 = tem;
9362
9363 if (GET_RTX_CLASS (code) == '<')
9364 {
9365 enum machine_mode op_mode = GET_MODE (op0);
9366
9367 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
8659 just (REL_OP X Y). */
9368 just (REL_OP X Y). */
8660 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
8661 {
8662 op1 = XEXP (op0, 1);
8663 op0 = XEXP (op0, 0);
8664 op_mode = GET_MODE (op0);
8665 }
8666
8667 if (op_mode == VOIDmode)

--- 11 unchanged lines hidden (view full) ---

8679 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
8680 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
8681 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
8682 || (GET_CODE (op0) == SUBREG
8683 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
8684 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
8685 return gen_rtx_combine (code, mode, op1, op0);
8686
9369 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9370 {
9371 op1 = XEXP (op0, 1);
9372 op0 = XEXP (op0, 0);
9373 op_mode = GET_MODE (op0);
9374 }
9375
9376 if (op_mode == VOIDmode)

--- 11 unchanged lines hidden (view full) ---

9388 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9389 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9390 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9391 || (GET_CODE (op0) == SUBREG
9392 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9393 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9394 return gen_rtx_combine (code, mode, op1, op0);
9395
9396 /* If we are turning off bits already known off in OP0, we need not do
9397 an AND. */
9398 else if (code == AND && GET_CODE (op1) == CONST_INT
9399 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9400 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9401 return op0;
9402
8687 return gen_rtx_combine (code, mode, op0, op1);
8688}
8689
8690static rtx
8691gen_unary (code, mode, op0_mode, op0)
8692 enum rtx_code code;
8693 enum machine_mode mode, op0_mode;
8694 rtx op0;

--- 116 unchanged lines hidden (view full) ---

8811 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
8812 int changed = 0;
8813
8814 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
8815 && (GET_MODE_SIZE (GET_MODE (inner_op0))
8816 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
8817 && (GET_MODE (SUBREG_REG (inner_op0))
8818 == GET_MODE (SUBREG_REG (inner_op1)))
9403 return gen_rtx_combine (code, mode, op0, op1);
9404}
9405
9406static rtx
9407gen_unary (code, mode, op0_mode, op0)
9408 enum rtx_code code;
9409 enum machine_mode mode, op0_mode;
9410 rtx op0;

--- 116 unchanged lines hidden (view full) ---

9527 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9528 int changed = 0;
9529
9530 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9531 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9532 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9533 && (GET_MODE (SUBREG_REG (inner_op0))
9534 == GET_MODE (SUBREG_REG (inner_op1)))
8819 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9535 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
8820 <= HOST_BITS_PER_WIDE_INT)
9536 <= HOST_BITS_PER_WIDE_INT)
8821 && (0 == (~c0) & nonzero_bits (SUBREG_REG (inner_op0),
8822 GET_MODE (SUBREG_REG (op0))))
8823 && (0 == (~c1) & nonzero_bits (SUBREG_REG (inner_op1),
8824 GET_MODE (SUBREG_REG (inner_op1)))))
9537 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9538 GET_MODE (SUBREG_REG (inner_op0)))))
9539 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9540 GET_MODE (SUBREG_REG (inner_op1))))))
8825 {
8826 op0 = SUBREG_REG (inner_op0);
8827 op1 = SUBREG_REG (inner_op1);
8828
8829 /* The resulting comparison is always unsigned since we masked
9541 {
9542 op0 = SUBREG_REG (inner_op0);
9543 op1 = SUBREG_REG (inner_op1);
9544
9545 /* The resulting comparison is always unsigned since we masked
8830 off the original sign bit. */
9546 off the original sign bit. */
8831 code = unsigned_condition (code);
8832
8833 changed = 1;
8834 }
8835
8836 else if (c0 == c1)
8837 for (tmode = GET_CLASS_NARROWEST_MODE
8838 (GET_MODE_CLASS (GET_MODE (op0)));

--- 19 unchanged lines hidden (view full) ---

8858 && (code == EQ || code == NE)))
8859 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
8860
8861 else
8862 break;
8863 }
8864
8865 /* If the first operand is a constant, swap the operands and adjust the
9547 code = unsigned_condition (code);
9548
9549 changed = 1;
9550 }
9551
9552 else if (c0 == c1)
9553 for (tmode = GET_CLASS_NARROWEST_MODE
9554 (GET_MODE_CLASS (GET_MODE (op0)));

--- 19 unchanged lines hidden (view full) ---

9574 && (code == EQ || code == NE)))
9575 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9576
9577 else
9578 break;
9579 }
9580
9581 /* If the first operand is a constant, swap the operands and adjust the
8866 comparison code appropriately. */
8867 if (CONSTANT_P (op0))
9582 comparison code appropriately, but don't do this if the second operand
9583 is already a constant integer. */
9584 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
8868 {
8869 tem = op0, op0 = op1, op1 = tem;
8870 code = swap_condition (code);
8871 }
8872
8873 /* We now enter a loop during which we will try to simplify the comparison.
8874 For the most part, we only are concerned with comparisons with zero,
8875 but some things may really be comparisons with zero but not start

--- 85 unchanged lines hidden (view full) ---

8961 else if (const_op == 0
8962 && mode_width <= HOST_BITS_PER_WIDE_INT
8963 && (nonzero_bits (op0, mode)
8964 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
8965 code = EQ;
8966 break;
8967
8968 case GE:
9585 {
9586 tem = op0, op0 = op1, op1 = tem;
9587 code = swap_condition (code);
9588 }
9589
9590 /* We now enter a loop during which we will try to simplify the comparison.
9591 For the most part, we only are concerned with comparisons with zero,
9592 but some things may really be comparisons with zero but not start

--- 85 unchanged lines hidden (view full) ---

9678 else if (const_op == 0
9679 && mode_width <= HOST_BITS_PER_WIDE_INT
9680 && (nonzero_bits (op0, mode)
9681 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9682 code = EQ;
9683 break;
9684
9685 case GE:
8969 /* >= C is equivalent to > (C - 1). */
9686 /* >= C is equivalent to > (C - 1). */
8970 if (const_op > 0)
8971 {
8972 const_op -= 1;
8973 op1 = GEN_INT (const_op);
8974 code = GT;
8975 /* ... fall through to GT below. */
8976 }
8977 else

--- 19 unchanged lines hidden (view full) ---

8997
8998 case LTU:
8999 /* < C is equivalent to <= (C - 1). */
9000 if (const_op > 0)
9001 {
9002 const_op -= 1;
9003 op1 = GEN_INT (const_op);
9004 code = LEU;
9687 if (const_op > 0)
9688 {
9689 const_op -= 1;
9690 op1 = GEN_INT (const_op);
9691 code = GT;
9692 /* ... fall through to GT below. */
9693 }
9694 else

--- 19 unchanged lines hidden (view full) ---

9714
9715 case LTU:
9716 /* < C is equivalent to <= (C - 1). */
9717 if (const_op > 0)
9718 {
9719 const_op -= 1;
9720 op1 = GEN_INT (const_op);
9721 code = LEU;
9005 /* ... fall through ... */
9722 /* ... fall through ... */
9006 }
9007
9008 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9723 }
9724
9725 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9009 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
9726 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9727 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9010 {
9011 const_op = 0, op1 = const0_rtx;
9012 code = GE;
9013 break;
9014 }
9015 else
9016 break;
9017
9018 case LEU:
9019 /* unsigned <= 0 is equivalent to == 0 */
9020 if (const_op == 0)
9021 code = EQ;
9022
9728 {
9729 const_op = 0, op1 = const0_rtx;
9730 code = GE;
9731 break;
9732 }
9733 else
9734 break;
9735
9736 case LEU:
9737 /* unsigned <= 0 is equivalent to == 0 */
9738 if (const_op == 0)
9739 code = EQ;
9740
9023 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9024 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
9741 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9742 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9743 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9025 {
9026 const_op = 0, op1 = const0_rtx;
9027 code = GE;
9028 }
9029 break;
9030
9031 case GEU:
9032 /* >= C is equivalent to < (C - 1). */
9033 if (const_op > 1)
9034 {
9035 const_op -= 1;
9036 op1 = GEN_INT (const_op);
9037 code = GTU;
9744 {
9745 const_op = 0, op1 = const0_rtx;
9746 code = GE;
9747 }
9748 break;
9749
9750 case GEU:
9751 /* >= C is equivalent to < (C - 1). */
9752 if (const_op > 1)
9753 {
9754 const_op -= 1;
9755 op1 = GEN_INT (const_op);
9756 code = GTU;
9038 /* ... fall through ... */
9757 /* ... fall through ... */
9039 }
9040
9041 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9758 }
9759
9760 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9042 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
9761 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9762 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9043 {
9044 const_op = 0, op1 = const0_rtx;
9045 code = LT;
9046 break;
9047 }
9048 else
9049 break;
9050
9051 case GTU:
9052 /* unsigned > 0 is equivalent to != 0 */
9053 if (const_op == 0)
9054 code = NE;
9055
9056 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9763 {
9764 const_op = 0, op1 = const0_rtx;
9765 code = LT;
9766 break;
9767 }
9768 else
9769 break;
9770
9771 case GTU:
9772 /* unsigned > 0 is equivalent to != 0 */
9773 if (const_op == 0)
9774 code = NE;
9775
9776 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9057 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
9777 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9778 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9058 {
9059 const_op = 0, op1 = const0_rtx;
9060 code = LT;
9061 }
9062 break;
9779 {
9780 const_op = 0, op1 = const0_rtx;
9781 code = LT;
9782 }
9783 break;
9784
9785 default:
9786 break;
9063 }
9064
9065 /* Compute some predicates to simplify code below. */
9066
9067 equality_comparison_p = (code == EQ || code == NE);
9068 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9069 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9070 || code == LEU);

--- 12 unchanged lines hidden (view full) ---

9083 switch. */
9084
9085 switch (GET_CODE (op0))
9086 {
9087 case ZERO_EXTRACT:
9088 /* If we are extracting a single bit from a variable position in
9089 a constant that has only a single bit set and are comparing it
9090 with zero, we can convert this into an equality comparison
9787 }
9788
9789 /* Compute some predicates to simplify code below. */
9790
9791 equality_comparison_p = (code == EQ || code == NE);
9792 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9793 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9794 || code == LEU);

--- 12 unchanged lines hidden (view full) ---

9807 switch. */
9808
9809 switch (GET_CODE (op0))
9810 {
9811 case ZERO_EXTRACT:
9812 /* If we are extracting a single bit from a variable position in
9813 a constant that has only a single bit set and are comparing it
9814 with zero, we can convert this into an equality comparison
9091 between the position and the location of the single bit. We can't
9092 do this if bit endian and we don't have an extzv since we then
9093 can't know what mode to use for the endianness adjustment. */
9815 between the position and the location of the single bit. */
9094
9095 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9096 && XEXP (op0, 1) == const1_rtx
9097 && equality_comparison_p && const_op == 0
9816
9817 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9818 && XEXP (op0, 1) == const1_rtx
9819 && equality_comparison_p && const_op == 0
9098 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0
9099 && (! BITS_BIG_ENDIAN
9100#ifdef HAVE_extzv
9101 || HAVE_extzv
9102#endif
9103 ))
9820 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9104 {
9821 {
9105#ifdef HAVE_extzv
9106 if (BITS_BIG_ENDIAN)
9822 if (BITS_BIG_ENDIAN)
9823#ifdef HAVE_extzv
9107 i = (GET_MODE_BITSIZE
9108 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
9824 i = (GET_MODE_BITSIZE
9825 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
9826#else
9827 i = BITS_PER_WORD - 1 - i;
9109#endif
9110
9111 op0 = XEXP (op0, 2);
9112 op1 = GEN_INT (i);
9113 const_op = i;
9114
9115 /* Result is nonzero iff shift count is equal to I. */
9116 code = reverse_condition (code);
9117 continue;
9118 }
9119
9828#endif
9829
9830 op0 = XEXP (op0, 2);
9831 op1 = GEN_INT (i);
9832 const_op = i;
9833
9834 /* Result is nonzero iff shift count is equal to I. */
9835 code = reverse_condition (code);
9836 continue;
9837 }
9838
9120 /* ... fall through ... */
9839 /* ... fall through ... */
9121
9122 case SIGN_EXTRACT:
9123 tem = expand_compound_operation (op0);
9124 if (tem != op0)
9125 {
9126 op0 = tem;
9127 continue;
9128 }

--- 43 unchanged lines hidden (view full) ---

9172 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9173 {
9174 op0 = XEXP (op0, 0);
9175 code = (code == LT ? NE : EQ);
9176 continue;
9177 }
9178
9179 /* If we have NEG of something whose two high-order bits are the
9840
9841 case SIGN_EXTRACT:
9842 tem = expand_compound_operation (op0);
9843 if (tem != op0)
9844 {
9845 op0 = tem;
9846 continue;
9847 }

--- 43 unchanged lines hidden (view full) ---

9891 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9892 {
9893 op0 = XEXP (op0, 0);
9894 code = (code == LT ? NE : EQ);
9895 continue;
9896 }
9897
9898 /* If we have NEG of something whose two high-order bits are the
9180 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9899 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9181 if (num_sign_bit_copies (op0, mode) >= 2)
9182 {
9183 op0 = XEXP (op0, 0);
9184 code = swap_condition (code);
9185 continue;
9186 }
9187 break;
9188

--- 19 unchanged lines hidden (view full) ---

9208 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9209 ((HOST_WIDE_INT) 1
9210 << (mode_width - 1
9211 - INTVAL (XEXP (op0, 1)))));
9212 code = (code == LT ? NE : EQ);
9213 continue;
9214 }
9215
9900 if (num_sign_bit_copies (op0, mode) >= 2)
9901 {
9902 op0 = XEXP (op0, 0);
9903 code = swap_condition (code);
9904 continue;
9905 }
9906 break;
9907

--- 19 unchanged lines hidden (view full) ---

9927 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9928 ((HOST_WIDE_INT) 1
9929 << (mode_width - 1
9930 - INTVAL (XEXP (op0, 1)))));
9931 code = (code == LT ? NE : EQ);
9932 continue;
9933 }
9934
9216 /* ... fall through ... */
9935 /* ... fall through ... */
9217
9218 case ABS:
9219 /* ABS is ignorable inside an equality comparison with zero. */
9220 if (const_op == 0 && equality_comparison_p)
9221 {
9222 op0 = XEXP (op0, 0);
9223 continue;
9224 }

--- 50 unchanged lines hidden (view full) ---

9275 /* If the inner mode is narrower and we are extracting the low part,
9276 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9277 if (subreg_lowpart_p (op0)
9278 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9279 /* Fall through */ ;
9280 else
9281 break;
9282
9936
9937 case ABS:
9938 /* ABS is ignorable inside an equality comparison with zero. */
9939 if (const_op == 0 && equality_comparison_p)
9940 {
9941 op0 = XEXP (op0, 0);
9942 continue;
9943 }

--- 50 unchanged lines hidden (view full) ---

9994 /* If the inner mode is narrower and we are extracting the low part,
9995 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9996 if (subreg_lowpart_p (op0)
9997 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9998 /* Fall through */ ;
9999 else
10000 break;
10001
9283 /* ... fall through ... */
10002 /* ... fall through ... */
9284
9285 case ZERO_EXTEND:
9286 if ((unsigned_comparison_p || equality_comparison_p)
9287 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9288 <= HOST_BITS_PER_WIDE_INT)
9289 && ((unsigned HOST_WIDE_INT) const_op
9290 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9291 {

--- 187 unchanged lines hidden (view full) ---

9479 & GET_MODE_MASK (mode))
9480 + 1)) >= 0
9481 && const_op >> i == 0
9482 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
9483 {
9484 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
9485 continue;
9486 }
10003
10004 case ZERO_EXTEND:
10005 if ((unsigned_comparison_p || equality_comparison_p)
10006 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10007 <= HOST_BITS_PER_WIDE_INT)
10008 && ((unsigned HOST_WIDE_INT) const_op
10009 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10010 {

--- 187 unchanged lines hidden (view full) ---

10198 & GET_MODE_MASK (mode))
10199 + 1)) >= 0
10200 && const_op >> i == 0
10201 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10202 {
10203 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10204 continue;
10205 }
10206
10207 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10208 in both M1 and M2 and the SUBREG is either paradoxical or
10209 represents the low part, permute the SUBREG and the AND and
10210 try again. */
10211 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10212 && ((mode_width
10213 >= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10214#ifdef WORD_REGISTER_OPERATIONS
10215 || subreg_lowpart_p (XEXP (op0, 0))
10216#endif
10217 )
10218#ifndef WORD_REGISTER_OPERATIONS
10219 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10220 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10221 As originally written the upper bits have a defined value
10222 due to the AND operation. However, if we commute the AND
10223 inside the SUBREG then they no longer have defined values
10224 and the meaning of the code has been changed. */
10225 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10226 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10227#endif
10228 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10229 && mode_width <= HOST_BITS_PER_WIDE_INT
10230 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10231 <= HOST_BITS_PER_WIDE_INT)
10232 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10233 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10234 & INTVAL (XEXP (op0, 1)))
10235 && INTVAL (XEXP (op0, 1)) != mask
10236 && (INTVAL (XEXP (op0, 1))
10237 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10238
10239 {
10240 op0
10241 = gen_lowpart_for_combine
10242 (mode,
10243 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10244 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10245 continue;
10246 }
10247
9487 break;
9488
9489 case ASHIFT:
9490 /* If we have (compare (ashift FOO N) (const_int C)) and
9491 the high order N bits of FOO (N+1 if an inequality comparison)
9492 are known to be zero, we can do this by comparing FOO with C
9493 shifted right N bits so long as the low-order N bits of C are
9494 zero. */

--- 63 unchanged lines hidden (view full) ---

9558 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
9559 || ((unsigned HOST_WIDE_INT) - const_op
9560 <= GET_MODE_MASK (tmode))))
9561 {
9562 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
9563 continue;
9564 }
9565
10248 break;
10249
10250 case ASHIFT:
10251 /* If we have (compare (ashift FOO N) (const_int C)) and
10252 the high order N bits of FOO (N+1 if an inequality comparison)
10253 are known to be zero, we can do this by comparing FOO with C
10254 shifted right N bits so long as the low-order N bits of C are
10255 zero. */

--- 63 unchanged lines hidden (view full) ---

10319 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10320 || ((unsigned HOST_WIDE_INT) - const_op
10321 <= GET_MODE_MASK (tmode))))
10322 {
10323 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10324 continue;
10325 }
10326
9566 /* ... fall through ... */
10327 /* ... fall through ... */
9567 case LSHIFTRT:
9568 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
9569 the low order N bits of FOO are known to be zero, we can do this
9570 by comparing FOO with C shifted left N bits so long as no
9571 overflow occurs. */
9572 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9573 && INTVAL (XEXP (op0, 1)) >= 0
9574 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT

--- 17 unchanged lines hidden (view full) ---

9592 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9593 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9594 {
9595 op0 = XEXP (op0, 0);
9596 code = (code == NE || code == GT ? LT : GE);
9597 continue;
9598 }
9599 break;
10328 case LSHIFTRT:
10329 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10330 the low order N bits of FOO are known to be zero, we can do this
10331 by comparing FOO with C shifted left N bits so long as no
10332 overflow occurs. */
10333 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10334 && INTVAL (XEXP (op0, 1)) >= 0
10335 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT

--- 17 unchanged lines hidden (view full) ---

10353 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10354 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10355 {
10356 op0 = XEXP (op0, 0);
10357 code = (code == NE || code == GT ? LT : GE);
10358 continue;
10359 }
10360 break;
10361
10362 default:
10363 break;
9600 }
9601
9602 break;
9603 }
9604
9605 /* Now make any compound operations involved in this comparison. Then,
10364 }
10365
10366 break;
10367 }
10368
10369 /* Now make any compound operations involved in this comparison. Then,
9606 check for an outmost SUBREG on OP0 that isn't doing anything or is
10370 check for an outmost SUBREG on OP0 that is not doing anything or is
9607 paradoxical. The latter case can only occur when it is known that the
9608 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
9609 We can never remove a SUBREG for a non-equality comparison because the
9610 sign bit is in a different place in the underlying object. */
9611
9612 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
9613 op1 = make_compound_operation (op1, SET);
9614

--- 107 unchanged lines hidden (view full) ---

9722 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
9723 return 1;
9724
9725 /* Otherwise try and find where the condition codes were last set and
9726 use that. */
9727 x = get_last_value (XEXP (x, 0));
9728 return (x && GET_CODE (x) == COMPARE
9729 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10371 paradoxical. The latter case can only occur when it is known that the
10372 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10373 We can never remove a SUBREG for a non-equality comparison because the
10374 sign bit is in a different place in the underlying object. */
10375
10376 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10377 op1 = make_compound_operation (op1, SET);
10378

--- 107 unchanged lines hidden (view full) ---

10486 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10487 return 1;
10488
10489 /* Otherwise try and find where the condition codes were last set and
10490 use that. */
10491 x = get_last_value (XEXP (x, 0));
10492 return (x && GET_CODE (x) == COMPARE
10493 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10494
10495 default:
10496 return 0;
9730 }
10497 }
9731
9732 return 0;
9733}
9734
9735/* Utility function for following routine. Called when X is part of a value
9736 being stored into reg_last_set_value. Sets reg_last_set_table_tick
9737 for each register mentioned. Similar to mention_regs in cse.c */
9738
9739static void
9740update_table_tick (x)

--- 86 unchanged lines hidden (view full) ---

9827 reg_last_set_invalid[i] = 1;
9828 else
9829 reg_last_set_invalid[i] = 0;
9830 }
9831
9832 /* The value being assigned might refer to X (like in "x++;"). In that
9833 case, we must replace it with (clobber (const_int 0)) to prevent
9834 infinite loops. */
10498}
10499
10500/* Utility function for following routine. Called when X is part of a value
10501 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10502 for each register mentioned. Similar to mention_regs in cse.c */
10503
10504static void
10505update_table_tick (x)

--- 86 unchanged lines hidden (view full) ---

10592 reg_last_set_invalid[i] = 1;
10593 else
10594 reg_last_set_invalid[i] = 0;
10595 }
10596
10597 /* The value being assigned might refer to X (like in "x++;"). In that
10598 case, we must replace it with (clobber (const_int 0)) to prevent
10599 infinite loops. */
9835 if (value && ! get_last_value_validate (&value,
10600 if (value && ! get_last_value_validate (&value, insn,
9836 reg_last_set_label[regno], 0))
9837 {
9838 value = copy_rtx (value);
10601 reg_last_set_label[regno], 0))
10602 {
10603 value = copy_rtx (value);
9839 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
10604 if (! get_last_value_validate (&value, insn,
10605 reg_last_set_label[regno], 1))
9840 value = 0;
9841 }
9842
9843 /* For the main register being modified, update the value, the mode, the
9844 nonzero bits, and the number of sign bit copies. */
9845
9846 reg_last_set_value[regno] = value;
9847

--- 104 unchanged lines hidden (view full) ---

9952
9953 If REPLACE is non-zero, replace the invalid reference with
9954 (clobber (const_int 0)) and return 1. This replacement is useful because
9955 we often can get useful information about the form of a value (e.g., if
9956 it was produced by a shift that always produces -1 or 0) even though
9957 we don't know exactly what registers it was produced from. */
9958
9959static int
10606 value = 0;
10607 }
10608
10609 /* For the main register being modified, update the value, the mode, the
10610 nonzero bits, and the number of sign bit copies. */
10611
10612 reg_last_set_value[regno] = value;
10613

--- 104 unchanged lines hidden (view full) ---

10718
10719 If REPLACE is non-zero, replace the invalid reference with
10720 (clobber (const_int 0)) and return 1. This replacement is useful because
10721 we often can get useful information about the form of a value (e.g., if
10722 it was produced by a shift that always produces -1 or 0) even though
10723 we don't know exactly what registers it was produced from. */
10724
10725static int
9960get_last_value_validate (loc, tick, replace)
10726get_last_value_validate (loc, insn, tick, replace)
9961 rtx *loc;
10727 rtx *loc;
10728 rtx insn;
9962 int tick;
9963 int replace;
9964{
9965 rtx x = *loc;
9966 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
9967 int len = GET_RTX_LENGTH (GET_CODE (x));
9968 int i;
9969
9970 if (GET_CODE (x) == REG)
9971 {
9972 int regno = REGNO (x);
9973 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9974 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
9975 int j;
9976
9977 for (j = regno; j < endregno; j++)
9978 if (reg_last_set_invalid[j]
9979 /* If this is a pseudo-register that was only set once, it is
9980 always valid. */
10729 int tick;
10730 int replace;
10731{
10732 rtx x = *loc;
10733 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10734 int len = GET_RTX_LENGTH (GET_CODE (x));
10735 int i;
10736
10737 if (GET_CODE (x) == REG)
10738 {
10739 int regno = REGNO (x);
10740 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10741 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10742 int j;
10743
10744 for (j = regno; j < endregno; j++)
10745 if (reg_last_set_invalid[j]
10746 /* If this is a pseudo-register that was only set once, it is
10747 always valid. */
9981 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
10748 || (! (regno >= FIRST_PSEUDO_REGISTER && REG_N_SETS (regno) == 1)
9982 && reg_last_set_label[j] > tick))
9983 {
9984 if (replace)
10749 && reg_last_set_label[j] > tick))
10750 {
10751 if (replace)
9985 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10752 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9986 return replace;
9987 }
9988
9989 return 1;
9990 }
10753 return replace;
10754 }
10755
10756 return 1;
10757 }
10758 /* If this is a memory reference, make sure that there were
10759 no stores after it that might have clobbered the value. We don't
10760 have alias info, so we assume any store invalidates it. */
10761 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10762 && INSN_CUID (insn) <= mem_last_set)
10763 {
10764 if (replace)
10765 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10766 return replace;
10767 }
9991
9992 for (i = 0; i < len; i++)
9993 if ((fmt[i] == 'e'
10768
10769 for (i = 0; i < len; i++)
10770 if ((fmt[i] == 'e'
9994 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
10771 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
9995 /* Don't bother with these. They shouldn't occur anyway. */
9996 || fmt[i] == 'E')
9997 return 0;
9998
9999 /* If we haven't found a reason for it to be invalid, it is valid. */
10000 return 1;
10001}
10002

--- 5 unchanged lines hidden (view full) ---

10008get_last_value (x)
10009 rtx x;
10010{
10011 int regno;
10012 rtx value;
10013
10014 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10015 then convert it to the desired mode. If this is a paradoxical SUBREG,
10772 /* Don't bother with these. They shouldn't occur anyway. */
10773 || fmt[i] == 'E')
10774 return 0;
10775
10776 /* If we haven't found a reason for it to be invalid, it is valid. */
10777 return 1;
10778}
10779

--- 5 unchanged lines hidden (view full) ---

10785get_last_value (x)
10786 rtx x;
10787{
10788 int regno;
10789 rtx value;
10790
10791 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10792 then convert it to the desired mode. If this is a paradoxical SUBREG,
10016 we cannot predict what values the "extra" bits might have. */
10793 we cannot predict what values the "extra" bits might have. */
10017 if (GET_CODE (x) == SUBREG
10018 && subreg_lowpart_p (x)
10019 && (GET_MODE_SIZE (GET_MODE (x))
10020 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10021 && (value = get_last_value (SUBREG_REG (x))) != 0)
10022 return gen_lowpart_for_combine (GET_MODE (x), value);
10023
10024 if (GET_CODE (x) != REG)
10025 return 0;
10026
10027 regno = REGNO (x);
10028 value = reg_last_set_value[regno];
10029
10794 if (GET_CODE (x) == SUBREG
10795 && subreg_lowpart_p (x)
10796 && (GET_MODE_SIZE (GET_MODE (x))
10797 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10798 && (value = get_last_value (SUBREG_REG (x))) != 0)
10799 return gen_lowpart_for_combine (GET_MODE (x), value);
10800
10801 if (GET_CODE (x) != REG)
10802 return 0;
10803
10804 regno = REGNO (x);
10805 value = reg_last_set_value[regno];
10806
10030 /* If we don't have a value or if it isn't for this basic block, return 0. */
10807 /* If we don't have a value or if it isn't for this basic block,
10808 return 0. */
10031
10032 if (value == 0
10809
10810 if (value == 0
10033 || (reg_n_sets[regno] != 1
10811 || (REG_N_SETS (regno) != 1
10034 && reg_last_set_label[regno] != label_tick))
10035 return 0;
10036
10037 /* If the value was set in a later insn than the ones we are processing,
10038 we can't use it even if the register was only set once, but make a quick
10039 check to see if the previous insn set it to something. This is commonly
10040 the case when the same pseudo is used by repeated insns.
10041

--- 30 unchanged lines hidden (view full) ---

10072 value = SET_SRC (set);
10073
10074 /* Make sure that VALUE doesn't reference X. Replace any
10075 explicit references with a CLOBBER. If there are any remaining
10076 references (rare), don't use the value. */
10077
10078 if (reg_mentioned_p (x, value))
10079 value = replace_rtx (copy_rtx (value), x,
10812 && reg_last_set_label[regno] != label_tick))
10813 return 0;
10814
10815 /* If the value was set in a later insn than the ones we are processing,
10816 we can't use it even if the register was only set once, but make a quick
10817 check to see if the previous insn set it to something. This is commonly
10818 the case when the same pseudo is used by repeated insns.
10819

--- 30 unchanged lines hidden (view full) ---

10850 value = SET_SRC (set);
10851
10852 /* Make sure that VALUE doesn't reference X. Replace any
10853 explicit references with a CLOBBER. If there are any remaining
10854 references (rare), don't use the value. */
10855
10856 if (reg_mentioned_p (x, value))
10857 value = replace_rtx (copy_rtx (value), x,
10080 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
10858 gen_rtx_CLOBBER (GET_MODE (x), const0_rtx));
10081
10082 if (reg_overlap_mentioned_p (x, value))
10083 return 0;
10084 }
10085 else
10086 return 0;
10087 }
10088
10089 /* If the value has all its registers valid, return it. */
10859
10860 if (reg_overlap_mentioned_p (x, value))
10861 return 0;
10862 }
10863 else
10864 return 0;
10865 }
10866
10867 /* If the value has all its registers valid, return it. */
10090 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
10868 if (get_last_value_validate (&value, reg_last_set[regno],
10869 reg_last_set_label[regno], 0))
10091 return value;
10092
10093 /* Otherwise, make a copy and replace any invalid register with
10094 (clobber (const_int 0)). If that fails for some reason, return 0. */
10095
10096 value = copy_rtx (value);
10870 return value;
10871
10872 /* Otherwise, make a copy and replace any invalid register with
10873 (clobber (const_int 0)). If that fails for some reason, return 0. */
10874
10875 value = copy_rtx (value);
10097 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
10876 if (get_last_value_validate (&value, reg_last_set[regno],
10877 reg_last_set_label[regno], 1))
10098 return value;
10099
10100 return 0;
10101}
10102
10103/* Return nonzero if expression X refers to a REG or to memory
10104 that is set in an instruction more recent than FROM_CUID. */
10105

--- 129 unchanged lines hidden (view full) ---

10235 if (insn == basic_block_head[block])
10236 break;
10237
10238 if (block == n_basic_blocks)
10239 return 0;
10240 }
10241
10242 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10878 return value;
10879
10880 return 0;
10881}
10882
10883/* Return nonzero if expression X refers to a REG or to memory
10884 that is set in an instruction more recent than FROM_CUID. */
10885

--- 129 unchanged lines hidden (view full) ---

11015 if (insn == basic_block_head[block])
11016 break;
11017
11018 if (block == n_basic_blocks)
11019 return 0;
11020 }
11021
11022 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10243 if (basic_block_live_at_start[block][i / REGSET_ELT_BITS]
10244 & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)))
11023 if (REGNO_REG_SET_P (basic_block_live_at_start[block], i))
10245 return 0;
10246
10247 return 1;
10248}
10249
10250/* Note hard registers in X that are used. This code is similar to
10251 that in flow.c, but much simpler since we don't care about pseudos. */
10252

--- 64 unchanged lines hidden (view full) ---

10317 || GET_CODE (testreg) == SIGN_EXTRACT
10318 || GET_CODE (testreg) == STRICT_LOW_PART)
10319 testreg = XEXP (testreg, 0);
10320
10321 if (GET_CODE (testreg) == MEM)
10322 mark_used_regs_combine (XEXP (testreg, 0));
10323
10324 mark_used_regs_combine (SET_SRC (x));
11024 return 0;
11025
11026 return 1;
11027}
11028
11029/* Note hard registers in X that are used. This code is similar to
11030 that in flow.c, but much simpler since we don't care about pseudos. */
11031

--- 64 unchanged lines hidden (view full) ---

11096 || GET_CODE (testreg) == SIGN_EXTRACT
11097 || GET_CODE (testreg) == STRICT_LOW_PART)
11098 testreg = XEXP (testreg, 0);
11099
11100 if (GET_CODE (testreg) == MEM)
11101 mark_used_regs_combine (XEXP (testreg, 0));
11102
11103 mark_used_regs_combine (SET_SRC (x));
10325 return;
10326 }
11104 }
11105 return;
11106
11107 default:
11108 break;
10327 }
10328
10329 /* Recursively scan the operands of this expression. */
10330
10331 {
10332 register char *fmt = GET_RTX_FORMAT (code);
10333
10334 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)

--- 20 unchanged lines hidden (view full) ---

10355remove_death (regno, insn)
10356 int regno;
10357 rtx insn;
10358{
10359 register rtx note = find_regno_note (insn, REG_DEAD, regno);
10360
10361 if (note)
10362 {
11109 }
11110
11111 /* Recursively scan the operands of this expression. */
11112
11113 {
11114 register char *fmt = GET_RTX_FORMAT (code);
11115
11116 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)

--- 20 unchanged lines hidden (view full) ---

11137remove_death (regno, insn)
11138 int regno;
11139 rtx insn;
11140{
11141 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11142
11143 if (note)
11144 {
10363 reg_n_deaths[regno]--;
11145 REG_N_DEATHS (regno)--;
10364 remove_note (insn, note);
10365 }
10366
10367 return note;
10368}
10369
10370/* For each register (hardware or pseudo) used within expression X, if its
10371 death is in an instruction with cuid between FROM_CUID (inclusive) and
10372 TO_INSN (exclusive), put a REG_DEAD note for that register in the
10373 list headed by PNOTES.
10374
11146 remove_note (insn, note);
11147 }
11148
11149 return note;
11150}
11151
11152/* For each register (hardware or pseudo) used within expression X, if its
11153 death is in an instruction with cuid between FROM_CUID (inclusive) and
11154 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11155 list headed by PNOTES.
11156
11157 That said, don't move registers killed by maybe_kill_insn.
11158
10375 This is done when X is being merged by combination into TO_INSN. These
10376 notes will then be distributed as needed. */
10377
10378static void
11159 This is done when X is being merged by combination into TO_INSN. These
11160 notes will then be distributed as needed. */
11161
11162static void
10379move_deaths (x, from_cuid, to_insn, pnotes)
11163move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
10380 rtx x;
11164 rtx x;
11165 rtx maybe_kill_insn;
10381 int from_cuid;
10382 rtx to_insn;
10383 rtx *pnotes;
10384{
10385 register char *fmt;
10386 register int len, i;
10387 register enum rtx_code code = GET_CODE (x);
10388
10389 if (code == REG)
10390 {
10391 register int regno = REGNO (x);
10392 register rtx where_dead = reg_last_death[regno];
10393 register rtx before_dead, after_dead;
10394
11166 int from_cuid;
11167 rtx to_insn;
11168 rtx *pnotes;
11169{
11170 register char *fmt;
11171 register int len, i;
11172 register enum rtx_code code = GET_CODE (x);
11173
11174 if (code == REG)
11175 {
11176 register int regno = REGNO (x);
11177 register rtx where_dead = reg_last_death[regno];
11178 register rtx before_dead, after_dead;
11179
11180 /* Don't move the register if it gets killed in between from and to */
11181 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11182 && !reg_referenced_p (x, maybe_kill_insn))
11183 return;
11184
10395 /* WHERE_DEAD could be a USE insn made by combine, so first we
10396 make sure that we have insns with valid INSN_CUID values. */
10397 before_dead = where_dead;
10398 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
10399 before_dead = PREV_INSN (before_dead);
10400 after_dead = where_dead;
10401 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
10402 after_dead = NEXT_INSN (after_dead);

--- 12 unchanged lines hidden (view full) ---

10415
10416 We must also check for the case where X is a hard register
10417 and NOTE is a death note for a range of hard registers
10418 including X. In that case, we must put REG_DEAD notes for
10419 the remaining registers in place of NOTE. */
10420
10421 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
10422 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11185 /* WHERE_DEAD could be a USE insn made by combine, so first we
11186 make sure that we have insns with valid INSN_CUID values. */
11187 before_dead = where_dead;
11188 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11189 before_dead = PREV_INSN (before_dead);
11190 after_dead = where_dead;
11191 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11192 after_dead = NEXT_INSN (after_dead);

--- 12 unchanged lines hidden (view full) ---

11205
11206 We must also check for the case where X is a hard register
11207 and NOTE is a death note for a range of hard registers
11208 including X. In that case, we must put REG_DEAD notes for
11209 the remaining registers in place of NOTE. */
11210
11211 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11212 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10423 != GET_MODE_SIZE (GET_MODE (x))))
11213 > GET_MODE_SIZE (GET_MODE (x))))
10424 {
10425 int deadregno = REGNO (XEXP (note, 0));
10426 int deadend
10427 = (deadregno + HARD_REGNO_NREGS (deadregno,
10428 GET_MODE (XEXP (note, 0))));
10429 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10430 int i;
10431
10432 for (i = deadregno; i < deadend; i++)
10433 if (i < regno || i >= ourend)
10434 REG_NOTES (where_dead)
11214 {
11215 int deadregno = REGNO (XEXP (note, 0));
11216 int deadend
11217 = (deadregno + HARD_REGNO_NREGS (deadregno,
11218 GET_MODE (XEXP (note, 0))));
11219 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11220 int i;
11221
11222 for (i = deadregno; i < deadend; i++)
11223 if (i < regno || i >= ourend)
11224 REG_NOTES (where_dead)
10435 = gen_rtx (EXPR_LIST, REG_DEAD,
10436 gen_rtx (REG, reg_raw_mode[i], i),
10437 REG_NOTES (where_dead));
11225 = gen_rtx_EXPR_LIST (REG_DEAD,
11226 gen_rtx_REG (reg_raw_mode[i], i),
11227 REG_NOTES (where_dead));
10438 }
11228 }
10439 /* If we didn't find any note, and we have a multi-reg hard
11229 /* If we didn't find any note, or if we found a REG_DEAD note that
11230 covers only part of the given reg, and we have a multi-reg hard
10440 register, then to be safe we must check for REG_DEAD notes
10441 for each register other than the first. They could have
10442 their own REG_DEAD notes lying around. */
11231 register, then to be safe we must check for REG_DEAD notes
11232 for each register other than the first. They could have
11233 their own REG_DEAD notes lying around. */
10443 else if (note == 0 && regno < FIRST_PSEUDO_REGISTER
11234 else if ((note == 0
11235 || (note != 0
11236 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11237 < GET_MODE_SIZE (GET_MODE (x)))))
11238 && regno < FIRST_PSEUDO_REGISTER
10444 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
10445 {
10446 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11239 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11240 {
11241 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10447 int i;
11242 int i, offset;
10448 rtx oldnotes = 0;
10449
11243 rtx oldnotes = 0;
11244
10450 for (i = regno + 1; i < ourend; i++)
10451 move_deaths (gen_rtx (REG, reg_raw_mode[i], i),
10452 from_cuid, to_insn, &oldnotes);
11245 if (note)
11246 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11247 else
11248 offset = 1;
11249
11250 for (i = regno + offset; i < ourend; i++)
11251 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11252 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
10453 }
10454
10455 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
10456 {
10457 XEXP (note, 1) = *pnotes;
10458 *pnotes = note;
10459 }
10460 else
11253 }
11254
11255 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11256 {
11257 XEXP (note, 1) = *pnotes;
11258 *pnotes = note;
11259 }
11260 else
10461 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
11261 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
10462
11262
10463 reg_n_deaths[regno]++;
11263 REG_N_DEATHS (regno)++;
10464 }
10465
10466 return;
10467 }
10468
10469 else if (GET_CODE (x) == SET)
10470 {
10471 rtx dest = SET_DEST (x);
10472
11264 }
11265
11266 return;
11267 }
11268
11269 else if (GET_CODE (x) == SET)
11270 {
11271 rtx dest = SET_DEST (x);
11272
10473 move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes);
11273 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
10474
10475 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
10476 that accesses one word of a multi-word item, some
10477 piece of everything register in the expression is used by
10478 this insn, so remove any old death. */
10479
10480 if (GET_CODE (dest) == ZERO_EXTRACT
10481 || GET_CODE (dest) == STRICT_LOW_PART
10482 || (GET_CODE (dest) == SUBREG
10483 && (((GET_MODE_SIZE (GET_MODE (dest))
10484 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
10485 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
10486 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
10487 {
11274
11275 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11276 that accesses one word of a multi-word item, some
11277 piece of everything register in the expression is used by
11278 this insn, so remove any old death. */
11279
11280 if (GET_CODE (dest) == ZERO_EXTRACT
11281 || GET_CODE (dest) == STRICT_LOW_PART
11282 || (GET_CODE (dest) == SUBREG
11283 && (((GET_MODE_SIZE (GET_MODE (dest))
11284 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11285 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11286 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11287 {
10488 move_deaths (dest, from_cuid, to_insn, pnotes);
11288 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
10489 return;
10490 }
10491
10492 /* If this is some other SUBREG, we know it replaces the entire
10493 value, so use that as the destination. */
10494 if (GET_CODE (dest) == SUBREG)
10495 dest = SUBREG_REG (dest);
10496
10497 /* If this is a MEM, adjust deaths of anything used in the address.
10498 For a REG (the only other possibility), the entire value is
10499 being replaced so the old value is not used in this insn. */
10500
10501 if (GET_CODE (dest) == MEM)
11289 return;
11290 }
11291
11292 /* If this is some other SUBREG, we know it replaces the entire
11293 value, so use that as the destination. */
11294 if (GET_CODE (dest) == SUBREG)
11295 dest = SUBREG_REG (dest);
11296
11297 /* If this is a MEM, adjust deaths of anything used in the address.
11298 For a REG (the only other possibility), the entire value is
11299 being replaced so the old value is not used in this insn. */
11300
11301 if (GET_CODE (dest) == MEM)
10502 move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes);
11302 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11303 to_insn, pnotes);
10503 return;
10504 }
10505
10506 else if (GET_CODE (x) == CLOBBER)
10507 return;
10508
10509 len = GET_RTX_LENGTH (code);
10510 fmt = GET_RTX_FORMAT (code);
10511
10512 for (i = 0; i < len; i++)
10513 {
10514 if (fmt[i] == 'E')
10515 {
10516 register int j;
10517 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11304 return;
11305 }
11306
11307 else if (GET_CODE (x) == CLOBBER)
11308 return;
11309
11310 len = GET_RTX_LENGTH (code);
11311 fmt = GET_RTX_FORMAT (code);
11312
11313 for (i = 0; i < len; i++)
11314 {
11315 if (fmt[i] == 'E')
11316 {
11317 register int j;
11318 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10518 move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes);
11319 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11320 to_insn, pnotes);
10519 }
10520 else if (fmt[i] == 'e')
11321 }
11322 else if (fmt[i] == 'e')
10521 move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes);
11323 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
10522 }
10523}
10524
10525/* Return 1 if X is the target of a bit-field assignment in BODY, the
10526 pattern of an insn. X must be a REG. */
10527
10528static int
10529reg_bitfield_target_p (x, body)

--- 68 unchanged lines hidden (view full) ---

10598 the latest copy of that register. */
10599 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
10600 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
10601 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
10602
10603 next_note = XEXP (note, 1);
10604 switch (REG_NOTE_KIND (note))
10605 {
11324 }
11325}
11326
11327/* Return 1 if X is the target of a bit-field assignment in BODY, the
11328 pattern of an insn. X must be a REG. */
11329
11330static int
11331reg_bitfield_target_p (x, body)

--- 68 unchanged lines hidden (view full) ---

11400 the latest copy of that register. */
11401 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11402 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11403 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11404
11405 next_note = XEXP (note, 1);
11406 switch (REG_NOTE_KIND (note))
11407 {
11408 case REG_BR_PROB:
11409 case REG_EXEC_COUNT:
11410 /* Doesn't matter much where we put this, as long as it's somewhere.
11411 It is preferable to keep these notes on branches, which is most
11412 likely to be i3. */
11413 place = i3;
11414 break;
11415
10606 case REG_UNUSED:
10607 /* Any clobbers for i3 may still exist, and so we must process
10608 REG_UNUSED notes from that insn.
10609
10610 Any clobbers from i2 or i1 can only exist if they were added by
10611 recog_for_combine. In that case, recog_for_combine created the
10612 necessary REG_UNUSED notes. Trying to keep any original
10613 REG_UNUSED notes from these insns can cause incorrect output

--- 28 unchanged lines hidden (view full) ---

10642 PUT_REG_NOTE_KIND (note, REG_DEAD);
10643 place = i3;
10644 }
10645 break;
10646
10647 case REG_EQUAL:
10648 case REG_EQUIV:
10649 case REG_NONNEG:
11416 case REG_UNUSED:
11417 /* Any clobbers for i3 may still exist, and so we must process
11418 REG_UNUSED notes from that insn.
11419
11420 Any clobbers from i2 or i1 can only exist if they were added by
11421 recog_for_combine. In that case, recog_for_combine created the
11422 necessary REG_UNUSED notes. Trying to keep any original
11423 REG_UNUSED notes from these insns can cause incorrect output

--- 28 unchanged lines hidden (view full) ---

11452 PUT_REG_NOTE_KIND (note, REG_DEAD);
11453 place = i3;
11454 }
11455 break;
11456
11457 case REG_EQUAL:
11458 case REG_EQUIV:
11459 case REG_NONNEG:
11460 case REG_NOALIAS:
10650 /* These notes say something about results of an insn. We can
10651 only support them if they used to be on I3 in which case they
10652 remain on I3. Otherwise they are ignored.
10653
10654 If the note refers to an expression that is not a constant, we
10655 must also ignore the note since we cannot tell whether the
10656 equivalence is still true. It might be possible to do
10657 slightly better than this (we only have a problem if I2DEST

--- 86 unchanged lines hidden (view full) ---

10744 /* If the register is used in both I2 and I3 and it dies in I3,
10745 we might have added another reference to it. If reg_n_refs
10746 was 2, bump it to 3. This has to be correct since the
10747 register must have been set somewhere. The reason this is
10748 done is because local-alloc.c treats 2 references as a
10749 special case. */
10750
10751 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
11461 /* These notes say something about results of an insn. We can
11462 only support them if they used to be on I3 in which case they
11463 remain on I3. Otherwise they are ignored.
11464
11465 If the note refers to an expression that is not a constant, we
11466 must also ignore the note since we cannot tell whether the
11467 equivalence is still true. It might be possible to do
11468 slightly better than this (we only have a problem if I2DEST

--- 86 unchanged lines hidden (view full) ---

11555 /* If the register is used in both I2 and I3 and it dies in I3,
11556 we might have added another reference to it. If reg_n_refs
11557 was 2, bump it to 3. This has to be correct since the
11558 register must have been set somewhere. The reason this is
11559 done is because local-alloc.c treats 2 references as a
11560 special case. */
11561
11562 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
10752 && reg_n_refs[REGNO (XEXP (note, 0))]== 2
11563 && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
10753 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11564 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
10754 reg_n_refs[REGNO (XEXP (note, 0))] = 3;
11565 REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
10755
10756 if (place == 0)
10757 {
10758 for (tem = prev_nonnote_insn (i3);
10759 place == 0 && tem
10760 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
10761 tem = prev_nonnote_insn (tem))
10762 {
10763 /* If the register is being set at TEM, see if that is all
10764 TEM is doing. If so, delete TEM. Otherwise, make this
10765 into a REG_UNUSED note instead. */
10766 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
10767 {
10768 rtx set = single_set (tem);
11566
11567 if (place == 0)
11568 {
11569 for (tem = prev_nonnote_insn (i3);
11570 place == 0 && tem
11571 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11572 tem = prev_nonnote_insn (tem))
11573 {
11574 /* If the register is being set at TEM, see if that is all
11575 TEM is doing. If so, delete TEM. Otherwise, make this
11576 into a REG_UNUSED note instead. */
11577 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11578 {
11579 rtx set = single_set (tem);
11580 rtx inner_dest = 0;
10769
11581
11582 if (set != 0)
11583 for (inner_dest = SET_DEST (set);
11584 GET_CODE (inner_dest) == STRICT_LOW_PART
11585 || GET_CODE (inner_dest) == SUBREG
11586 || GET_CODE (inner_dest) == ZERO_EXTRACT;
11587 inner_dest = XEXP (inner_dest, 0))
11588 ;
11589
10770 /* Verify that it was the set, and not a clobber that
10771 modified the register. */
10772
10773 if (set != 0 && ! side_effects_p (SET_SRC (set))
11590 /* Verify that it was the set, and not a clobber that
11591 modified the register. */
11592
11593 if (set != 0 && ! side_effects_p (SET_SRC (set))
10774 && (rtx_equal_p (XEXP (note, 0), SET_DEST (set))
10775 || (GET_CODE (SET_DEST (set)) == SUBREG
10776 && rtx_equal_p (XEXP (note, 0),
10777 XEXP (SET_DEST (set), 0)))))
11594 && rtx_equal_p (XEXP (note, 0), inner_dest))
10778 {
10779 /* Move the notes and links of TEM elsewhere.
10780 This might delete other dead insns recursively.
10781 First set the pattern to something that won't use
10782 any register. */
10783
10784 PATTERN (tem) = pc_rtx;
10785
10786 distribute_notes (REG_NOTES (tem), tem, tem,
10787 NULL_RTX, NULL_RTX, NULL_RTX);
10788 distribute_links (LOG_LINKS (tem));
10789
10790 PUT_CODE (tem, NOTE);
10791 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
10792 NOTE_SOURCE_FILE (tem) = 0;
10793 }
11595 {
11596 /* Move the notes and links of TEM elsewhere.
11597 This might delete other dead insns recursively.
11598 First set the pattern to something that won't use
11599 any register. */
11600
11601 PATTERN (tem) = pc_rtx;
11602
11603 distribute_notes (REG_NOTES (tem), tem, tem,
11604 NULL_RTX, NULL_RTX, NULL_RTX);
11605 distribute_links (LOG_LINKS (tem));
11606
11607 PUT_CODE (tem, NOTE);
11608 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11609 NOTE_SOURCE_FILE (tem) = 0;
11610 }
11611 /* If the register is both set and used here, put the
11612 REG_DEAD note here, but place a REG_UNUSED note
11613 here too unless there already is one. */
11614 else if (reg_referenced_p (XEXP (note, 0),
11615 PATTERN (tem)))
11616 {
11617 place = tem;
11618
11619 if (! find_regno_note (tem, REG_UNUSED,
11620 REGNO (XEXP (note, 0))))
11621 REG_NOTES (tem)
11622 = gen_rtx_EXPR_LIST (REG_UNUSED,
11623 XEXP (note, 0),
11624 REG_NOTES (tem));
11625 }
10794 else
10795 {
10796 PUT_REG_NOTE_KIND (note, REG_UNUSED);
10797
10798 /* If there isn't already a REG_UNUSED note, put one
10799 here. */
10800 if (! find_regno_note (tem, REG_UNUSED,
10801 REGNO (XEXP (note, 0))))

--- 29 unchanged lines hidden (view full) ---

10831 /* If we haven't found an insn for the death note and it
10832 is still a REG_DEAD note, but we have hit a CODE_LABEL,
10833 insert a USE insn for the register at that label and
10834 put the death node there. This prevents problems with
10835 call-state tracking in caller-save.c. */
10836 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
10837 {
10838 place
11626 else
11627 {
11628 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11629
11630 /* If there isn't already a REG_UNUSED note, put one
11631 here. */
11632 if (! find_regno_note (tem, REG_UNUSED,
11633 REGNO (XEXP (note, 0))))

--- 29 unchanged lines hidden (view full) ---

11663 /* If we haven't found an insn for the death note and it
11664 is still a REG_DEAD note, but we have hit a CODE_LABEL,
11665 insert a USE insn for the register at that label and
11666 put the death node there. This prevents problems with
11667 call-state tracking in caller-save.c. */
11668 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
11669 {
11670 place
10839 = emit_insn_after (gen_rtx (USE, VOIDmode, XEXP (note, 0)),
11671 = emit_insn_after (gen_rtx_USE (VOIDmode, XEXP (note, 0)),
10840 tem);
10841
10842 /* If this insn was emitted between blocks, then update
10843 basic_block_head of the current block to include it. */
10844 if (basic_block_end[this_basic_block - 1] == tem)
10845 basic_block_head[this_basic_block] = place;
10846 }
10847 }
10848
10849 /* If the register is set or already dead at PLACE, we needn't do
11672 tem);
11673
11674 /* If this insn was emitted between blocks, then update
11675 basic_block_head of the current block to include it. */
11676 if (basic_block_end[this_basic_block - 1] == tem)
11677 basic_block_head[this_basic_block] = place;
11678 }
11679 }
11680
11681 /* If the register is set or already dead at PLACE, we needn't do
10850 anything with this note if it is still a REG_DEAD note.
11682 anything with this note if it is still a REG_DEAD note.
11683 We can here if it is set at all, not if is it totally replace,
11684 which is what `dead_or_set_p' checks, so also check for it being
11685 set partially. */
10851
11686
10852 Note that we cannot use just `dead_or_set_p' here since we can
10853 convert an assignment to a register into a bit-field assignment.
10854 Therefore, we must also omit the note if the register is the
10855 target of a bitfield assignment. */
10856
11687
10857 if (place && REG_NOTE_KIND (note) == REG_DEAD)
10858 {
10859 int regno = REGNO (XEXP (note, 0));
10860
10861 if (dead_or_set_p (place, XEXP (note, 0))
10862 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
10863 {
10864 /* Unless the register previously died in PLACE, clear

--- 25 unchanged lines hidden (view full) ---

10890 GET_MODE (XEXP (note, 0)));
10891 int all_used = 1;
10892 int i;
10893
10894 for (i = regno; i < endregno; i++)
10895 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
10896 && ! find_regno_fusage (place, USE, i))
10897 {
11688 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11689 {
11690 int regno = REGNO (XEXP (note, 0));
11691
11692 if (dead_or_set_p (place, XEXP (note, 0))
11693 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11694 {
11695 /* Unless the register previously died in PLACE, clear

--- 25 unchanged lines hidden (view full) ---

11721 GET_MODE (XEXP (note, 0)));
11722 int all_used = 1;
11723 int i;
11724
11725 for (i = regno; i < endregno; i++)
11726 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11727 && ! find_regno_fusage (place, USE, i))
11728 {
10898 rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11729 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
10899 rtx p;
10900
10901 /* See if we already placed a USE note for this
10902 register in front of PLACE. */
10903 for (p = place;
10904 GET_CODE (PREV_INSN (p)) == INSN
10905 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
10906 p = PREV_INSN (p))
10907 if (rtx_equal_p (piece,
10908 XEXP (PATTERN (PREV_INSN (p)), 0)))
10909 {
10910 p = 0;
10911 break;
10912 }
10913
10914 if (p)
10915 {
10916 rtx use_insn
11730 rtx p;
11731
11732 /* See if we already placed a USE note for this
11733 register in front of PLACE. */
11734 for (p = place;
11735 GET_CODE (PREV_INSN (p)) == INSN
11736 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11737 p = PREV_INSN (p))
11738 if (rtx_equal_p (piece,
11739 XEXP (PATTERN (PREV_INSN (p)), 0)))
11740 {
11741 p = 0;
11742 break;
11743 }
11744
11745 if (p)
11746 {
11747 rtx use_insn
10917 = emit_insn_before (gen_rtx (USE, VOIDmode,
10918 piece),
11748 = emit_insn_before (gen_rtx_USE (VOIDmode,
11749 piece),
10919 p);
10920 REG_NOTES (use_insn)
11750 p);
11751 REG_NOTES (use_insn)
10921 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
10922 REG_NOTES (use_insn));
11752 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
11753 REG_NOTES (use_insn));
10923 }
10924
10925 all_used = 0;
10926 }
10927
10928 /* Check for the case where the register dying partially
10929 overlaps the register set by this insn. */
10930 if (all_used)

--- 6 unchanged lines hidden (view full) ---

10937
10938 if (! all_used)
10939 {
10940 /* Put only REG_DEAD notes for pieces that are
10941 still used and that are not already dead or set. */
10942
10943 for (i = regno; i < endregno; i++)
10944 {
11754 }
11755
11756 all_used = 0;
11757 }
11758
11759 /* Check for the case where the register dying partially
11760 overlaps the register set by this insn. */
11761 if (all_used)

--- 6 unchanged lines hidden (view full) ---

11768
11769 if (! all_used)
11770 {
11771 /* Put only REG_DEAD notes for pieces that are
11772 still used and that are not already dead or set. */
11773
11774 for (i = regno; i < endregno; i++)
11775 {
10945 rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11776 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
10946
10947 if ((reg_referenced_p (piece, PATTERN (place))
10948 || (GET_CODE (place) == CALL_INSN
10949 && find_reg_fusage (place, USE, piece)))
10950 && ! dead_or_set_p (place, piece)
10951 && ! reg_bitfield_target_p (piece,
10952 PATTERN (place)))
11777
11778 if ((reg_referenced_p (piece, PATTERN (place))
11779 || (GET_CODE (place) == CALL_INSN
11780 && find_reg_fusage (place, USE, piece)))
11781 && ! dead_or_set_p (place, piece)
11782 && ! reg_bitfield_target_p (piece,
11783 PATTERN (place)))
10953 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
10954 piece,
10955 REG_NOTES (place));
11784 REG_NOTES (place)
11785 = gen_rtx_EXPR_LIST (REG_DEAD,
11786 piece, REG_NOTES (place));
10956 }
10957
10958 place = 0;
10959 }
10960 }
10961 }
10962 break;
10963

--- 6 unchanged lines hidden (view full) ---

10970 if (place)
10971 {
10972 XEXP (note, 1) = REG_NOTES (place);
10973 REG_NOTES (place) = note;
10974 }
10975 else if ((REG_NOTE_KIND (note) == REG_DEAD
10976 || REG_NOTE_KIND (note) == REG_UNUSED)
10977 && GET_CODE (XEXP (note, 0)) == REG)
11787 }
11788
11789 place = 0;
11790 }
11791 }
11792 }
11793 break;
11794

--- 6 unchanged lines hidden (view full) ---

11801 if (place)
11802 {
11803 XEXP (note, 1) = REG_NOTES (place);
11804 REG_NOTES (place) = note;
11805 }
11806 else if ((REG_NOTE_KIND (note) == REG_DEAD
11807 || REG_NOTE_KIND (note) == REG_UNUSED)
11808 && GET_CODE (XEXP (note, 0)) == REG)
10978 reg_n_deaths[REGNO (XEXP (note, 0))]--;
11809 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
10979
10980 if (place2)
10981 {
10982 if ((REG_NOTE_KIND (note) == REG_DEAD
10983 || REG_NOTE_KIND (note) == REG_UNUSED)
10984 && GET_CODE (XEXP (note, 0)) == REG)
11810
11811 if (place2)
11812 {
11813 if ((REG_NOTE_KIND (note) == REG_DEAD
11814 || REG_NOTE_KIND (note) == REG_UNUSED)
11815 && GET_CODE (XEXP (note, 0)) == REG)
10985 reg_n_deaths[REGNO (XEXP (note, 0))]++;
11816 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
10986
11817
10987 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
10988 XEXP (note, 0), REG_NOTES (place2));
11818 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
11819 REG_NOTE_KIND (note),
11820 XEXP (note, 0),
11821 REG_NOTES (place2));
10989 }
10990 }
10991}
10992
10993/* Similarly to above, distribute the LOG_LINKS that used to be present on
10994 I3, I2, and I1 to new locations. This is also called in one case to
10995 add a link pointing at I3 when I3's destination is changed. */
10996

--- 80 unchanged lines hidden (view full) ---

11077 if (added_links_insn == 0
11078 || INSN_CUID (added_links_insn) > INSN_CUID (place))
11079 added_links_insn = place;
11080 }
11081 }
11082 }
11083}
11084
11822 }
11823 }
11824}
11825
11826/* Similarly to above, distribute the LOG_LINKS that used to be present on
11827 I3, I2, and I1 to new locations. This is also called in one case to
11828 add a link pointing at I3 when I3's destination is changed. */
11829

--- 80 unchanged lines hidden (view full) ---

11910 if (added_links_insn == 0
11911 || INSN_CUID (added_links_insn) > INSN_CUID (place))
11912 added_links_insn = place;
11913 }
11914 }
11915 }
11916}
11917
11918/* Compute INSN_CUID for INSN, which is an insn made by combine. */
11919
11920static int
11921insn_cuid (insn)
11922 rtx insn;
11923{
11924 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11925 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11926 insn = NEXT_INSN (insn);
11927
11928 if (INSN_UID (insn) > max_uid_cuid)
11929 abort ();
11930
11931 return INSN_CUID (insn);
11932}
11933
11085void
11086dump_combine_stats (file)
11087 FILE *file;
11088{
11089 fprintf
11090 (file,
11091 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11092 combine_attempts, combine_merges, combine_extras, combine_successes);
11093}
11094
11095void
11096dump_combine_total_stats (file)
11097 FILE *file;
11098{
11099 fprintf
11100 (file,
11101 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11102 total_attempts, total_merges, total_extras, total_successes);
11103}
11934void
11935dump_combine_stats (file)
11936 FILE *file;
11937{
11938 fprintf
11939 (file,
11940 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11941 combine_attempts, combine_merges, combine_extras, combine_successes);
11942}
11943
11944void
11945dump_combine_total_stats (file)
11946 FILE *file;
11947{
11948 fprintf
11949 (file,
11950 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11951 total_attempts, total_merges, total_extras, total_successes);
11952}