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pci_emul.h (267341) pci_emul.h (267393)
1/*-
2 * Copyright (c) 2011 NetApp, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
1/*-
2 * Copyright (c) 2011 NetApp, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/10/usr.sbin/bhyve/pci_emul.h 267341 2014-06-10 21:20:37Z jhb $
26 * $FreeBSD: stable/10/usr.sbin/bhyve/pci_emul.h 267393 2014-06-12 13:13:15Z jhb $
27 */
28
29#ifndef _PCI_EMUL_H_
30#define _PCI_EMUL_H_
31
32#include <sys/types.h>
33#include <sys/queue.h>
34#include <sys/kernel.h>
27 */
28
29#ifndef _PCI_EMUL_H_
30#define _PCI_EMUL_H_
31
32#include <sys/types.h>
33#include <sys/queue.h>
34#include <sys/kernel.h>
35#include <sys/_pthreadtypes.h>
35
36#include <dev/pci/pcireg.h>
37
38#include <assert.h>
39
40#define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */
41#define PCIY_RESERVED 0x00
42

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97/*
98 * In case the structure is modified to hold extra information, use a define
99 * for the size that should be emulated.
100 */
101#define MSIX_TABLE_ENTRY_SIZE 16
102#define MAX_MSIX_TABLE_ENTRIES 2048
103#define PBA_TABLE_ENTRY_SIZE 8
104
36
37#include <dev/pci/pcireg.h>
38
39#include <assert.h>
40
41#define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */
42#define PCIY_RESERVED 0x00
43

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98/*
99 * In case the structure is modified to hold extra information, use a define
100 * for the size that should be emulated.
101 */
102#define MSIX_TABLE_ENTRY_SIZE 16
103#define MAX_MSIX_TABLE_ENTRIES 2048
104#define PBA_TABLE_ENTRY_SIZE 8
105
106enum lintr_stat {
107 IDLE,
108 ASSERTED,
109 PENDING
110};
111
105struct pci_devinst {
106 struct pci_devemu *pi_d;
107 struct vmctx *pi_vmctx;
108 uint8_t pi_bus, pi_slot, pi_func;
112struct pci_devinst {
113 struct pci_devemu *pi_d;
114 struct vmctx *pi_vmctx;
115 uint8_t pi_bus, pi_slot, pi_func;
109 int8_t pi_lintr_pin;
110 int8_t pi_lintr_state;
111 char pi_name[PI_NAMESZ];
112 int pi_bar_getsize;
113
114 struct {
116 char pi_name[PI_NAMESZ];
117 int pi_bar_getsize;
118
119 struct {
120 int8_t pin;
121 enum lintr_stat state;
122 int ioapic_irq;
123 pthread_mutex_t lock;
124 } pi_lintr;
125
126 struct {
115 int enabled;
116 uint64_t addr;
117 uint64_t msg_data;
118 int maxmsgnum;
119 } pi_msi;
120
121 struct {
122 int enabled;

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182 uint16_t link_control2;
183 uint16_t link_status2;
184
185 uint32_t slot_capabilities2; /* ports with slots */
186 uint16_t slot_control2;
187 uint16_t slot_status2;
188} __packed;
189
127 int enabled;
128 uint64_t addr;
129 uint64_t msg_data;
130 int maxmsgnum;
131 } pi_msi;
132
133 struct {
134 int enabled;

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194 uint16_t link_control2;
195 uint16_t link_status2;
196
197 uint32_t slot_capabilities2; /* ports with slots */
198 uint16_t slot_control2;
199 uint16_t slot_status2;
200} __packed;
201
202typedef void (*pci_lintr_cb)(int slot, int pin, int ioapic_irq, void *arg);
203
190int init_pci(struct vmctx *ctx);
191void msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
192 int bytes, uint32_t val);
193void msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
194 int bytes, uint32_t val);
195void pci_callback(void);
196int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx,
197 enum pcibar_type type, uint64_t size);
198int pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx,
199 uint64_t hostbase, enum pcibar_type type, uint64_t size);
200int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
201int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
202void pci_generate_msi(struct pci_devinst *pi, int msgnum);
203void pci_generate_msix(struct pci_devinst *pi, int msgnum);
204void pci_lintr_assert(struct pci_devinst *pi);
205void pci_lintr_deassert(struct pci_devinst *pi);
204int init_pci(struct vmctx *ctx);
205void msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
206 int bytes, uint32_t val);
207void msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
208 int bytes, uint32_t val);
209void pci_callback(void);
210int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx,
211 enum pcibar_type type, uint64_t size);
212int pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx,
213 uint64_t hostbase, enum pcibar_type type, uint64_t size);
214int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
215int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
216void pci_generate_msi(struct pci_devinst *pi, int msgnum);
217void pci_generate_msix(struct pci_devinst *pi, int msgnum);
218void pci_lintr_assert(struct pci_devinst *pi);
219void pci_lintr_deassert(struct pci_devinst *pi);
206int pci_lintr_request(struct pci_devinst *pi, int ivec);
220int pci_lintr_request(struct pci_devinst *pi);
207int pci_msi_enabled(struct pci_devinst *pi);
208int pci_msix_enabled(struct pci_devinst *pi);
209int pci_msix_table_bar(struct pci_devinst *pi);
210int pci_msix_pba_bar(struct pci_devinst *pi);
211int pci_msi_msgnum(struct pci_devinst *pi);
212int pci_parse_slot(char *opt);
213void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
214int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
215int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
216 uint64_t value);
217uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
221int pci_msi_enabled(struct pci_devinst *pi);
222int pci_msix_enabled(struct pci_devinst *pi);
223int pci_msix_table_bar(struct pci_devinst *pi);
224int pci_msix_pba_bar(struct pci_devinst *pi);
225int pci_msi_msgnum(struct pci_devinst *pi);
226int pci_parse_slot(char *opt);
227void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
228int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
229int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
230 uint64_t value);
231uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
232int pci_count_lintr(void);
233void pci_walk_lintr(pci_lintr_cb cb, void *arg);
218void pci_write_dsdt(void);
219
220static __inline void
221pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
222{
223 assert(offset <= PCI_REGMAX);
224 *(uint8_t *)(pi->pi_cfgdata + offset) = val;
225}

--- 37 unchanged lines hidden --- 		234void pci_write_dsdt(void);
235
236static __inline void
237pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
238{
239 assert(offset <= PCI_REGMAX);
240 *(uint8_t *)(pi->pi_cfgdata + offset) = val;
241}

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