| intel_utils.c (257251) | intel_utils.c (259512) |
|---|---|
| 1/*- 2 * Copyright (c) 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 14 unchanged lines hidden (view full) --- 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 14 unchanged lines hidden (view full) --- 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> |
| 31__FBSDID("$FreeBSD: head/sys/x86/iommu/intel_utils.c 257251 2013-10-28 13:33:29Z kib $"); | 31__FBSDID("$FreeBSD: stable/10/sys/x86/iommu/intel_utils.c 259512 2013-12-17 13:49:35Z kib $"); |
| 32 33#include <sys/param.h> 34#include <sys/bus.h> 35#include <sys/kernel.h> 36#include <sys/lock.h> 37#include <sys/malloc.h> 38#include <sys/memdesc.h> 39#include <sys/mutex.h> --- 185 unchanged lines hidden (view full) --- 225 226dmar_gaddr_t 227ctx_page_size(struct dmar_ctx *ctx, int lvl) 228{ 229 230 return (pglvl_page_size(ctx->pglvl, lvl)); 231} 232 | 32 33#include <sys/param.h> 34#include <sys/bus.h> 35#include <sys/kernel.h> 36#include <sys/lock.h> 37#include <sys/malloc.h> 38#include <sys/memdesc.h> 39#include <sys/mutex.h> --- 185 unchanged lines hidden (view full) --- 225 226dmar_gaddr_t 227ctx_page_size(struct dmar_ctx *ctx, int lvl) 228{ 229 230 return (pglvl_page_size(ctx->pglvl, lvl)); 231} 232 |
| 233int 234calc_am(struct dmar_unit *unit, dmar_gaddr_t base, dmar_gaddr_t size, 235 dmar_gaddr_t *isizep) 236{ 237 dmar_gaddr_t isize; 238 int am; 239 240 for (am = DMAR_CAP_MAMV(unit->hw_cap);; am--) { 241 isize = 1ULL << (am + DMAR_PAGE_SHIFT); 242 if ((base & (isize - 1)) == 0 && size >= isize) 243 break; 244 if (am == 0) 245 break; 246 } 247 *isizep = isize; 248 return (am); 249} 250 |
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| 233dmar_haddr_t dmar_high; 234int haw; 235int dmar_tbl_pagecnt; 236 237vm_page_t 238dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags) 239{ 240 vm_page_t m; --- 144 unchanged lines hidden (view full) --- 385dmar_inv_ctx_glob(struct dmar_unit *unit) 386{ 387 388 /* 389 * Access to the CCMD register must be serialized while the 390 * command is submitted. 391 */ 392 DMAR_ASSERT_LOCKED(unit); | 251dmar_haddr_t dmar_high; 252int haw; 253int dmar_tbl_pagecnt; 254 255vm_page_t 256dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags) 257{ 258 vm_page_t m; --- 144 unchanged lines hidden (view full) --- 403dmar_inv_ctx_glob(struct dmar_unit *unit) 404{ 405 406 /* 407 * Access to the CCMD register must be serialized while the 408 * command is submitted. 409 */ 410 DMAR_ASSERT_LOCKED(unit); |
| 411 KASSERT(!unit->qi_enabled, ("QI enabled")); |
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| 393 394 /* 395 * The DMAR_CCMD_ICC bit in the upper dword should be written 396 * after the low dword write is completed. Amd64 397 * dmar_write8() does not have this issue, i386 dmar_write8() 398 * writes the upper dword last. 399 */ 400 dmar_write8(unit, DMAR_CCMD_REG, DMAR_CCMD_ICC | DMAR_CCMD_CIRG_GLOB); --- 7 unchanged lines hidden (view full) --- 408 * Globally invalidate the IOTLB, busily waiting for the completion. 409 */ 410int 411dmar_inv_iotlb_glob(struct dmar_unit *unit) 412{ 413 int reg; 414 415 DMAR_ASSERT_LOCKED(unit); | 412 413 /* 414 * The DMAR_CCMD_ICC bit in the upper dword should be written 415 * after the low dword write is completed. Amd64 416 * dmar_write8() does not have this issue, i386 dmar_write8() 417 * writes the upper dword last. 418 */ 419 dmar_write8(unit, DMAR_CCMD_REG, DMAR_CCMD_ICC | DMAR_CCMD_CIRG_GLOB); --- 7 unchanged lines hidden (view full) --- 427 * Globally invalidate the IOTLB, busily waiting for the completion. 428 */ 429int 430dmar_inv_iotlb_glob(struct dmar_unit *unit) 431{ 432 int reg; 433 434 DMAR_ASSERT_LOCKED(unit); |
| 435 KASSERT(!unit->qi_enabled, ("QI enabled")); |
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| 416 417 reg = 16 * DMAR_ECAP_IRO(unit->hw_ecap); 418 /* See a comment about DMAR_CCMD_ICC in dmar_inv_ctx_glob. */ 419 dmar_write8(unit, reg + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT | 420 DMAR_IOTLB_IIRG_GLB | DMAR_IOTLB_DR | DMAR_IOTLB_DW); 421 /* XXXKIB should have a timeout */ 422 while ((dmar_read4(unit, reg + DMAR_IOTLB_REG_OFF + 4) & 423 DMAR_IOTLB_IVT32) != 0) --- 45 unchanged lines hidden (view full) --- 469 unit->hw_gcmd &= ~DMAR_GCMD_TE; 470 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 471 /* XXXKIB should have a timeout */ 472 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) != 0) 473 cpu_spinwait(); 474 return (0); 475} 476 | 436 437 reg = 16 * DMAR_ECAP_IRO(unit->hw_ecap); 438 /* See a comment about DMAR_CCMD_ICC in dmar_inv_ctx_glob. */ 439 dmar_write8(unit, reg + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT | 440 DMAR_IOTLB_IIRG_GLB | DMAR_IOTLB_DR | DMAR_IOTLB_DW); 441 /* XXXKIB should have a timeout */ 442 while ((dmar_read4(unit, reg + DMAR_IOTLB_REG_OFF + 4) & 443 DMAR_IOTLB_IVT32) != 0) --- 45 unchanged lines hidden (view full) --- 489 unit->hw_gcmd &= ~DMAR_GCMD_TE; 490 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 491 /* XXXKIB should have a timeout */ 492 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) != 0) 493 cpu_spinwait(); 494 return (0); 495} 496 |
| 477void 478dmar_enable_intr(struct dmar_unit *unit) 479{ 480 uint32_t fectl; 481 482 fectl = dmar_read4(unit, DMAR_FECTL_REG); 483 fectl &= ~DMAR_FECTL_IM; 484 dmar_write4(unit, DMAR_FECTL_REG, fectl); 485} 486 487void 488dmar_disable_intr(struct dmar_unit *unit) 489{ 490 uint32_t fectl; 491 492 fectl = dmar_read4(unit, DMAR_FECTL_REG); 493 dmar_write4(unit, DMAR_FECTL_REG, fectl | DMAR_FECTL_IM); 494} 495 | |
| 496#define BARRIER_F \ 497 u_int f_done, f_inproc, f_wakeup; \ 498 \ 499 f_done = 1 << (barrier_id * 3); \ 500 f_inproc = 1 << (barrier_id * 3 + 1); \ 501 f_wakeup = 1 << (barrier_id * 3 + 2) 502 503bool --- 59 unchanged lines hidden --- | 497#define BARRIER_F \ 498 u_int f_done, f_inproc, f_wakeup; \ 499 \ 500 f_done = 1 << (barrier_id * 3); \ 501 f_inproc = 1 << (barrier_id * 3 + 1); \ 502 f_wakeup = 1 << (barrier_id * 3 + 2) 503 504bool --- 59 unchanged lines hidden --- |