| intel_reg.h (257251) | intel_reg.h (259512) |
|---|---|
| 1/*- 2 * Copyright (c) 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 12 unchanged lines hidden (view full) --- 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * | 1/*- 2 * Copyright (c) 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 12 unchanged lines hidden (view full) --- 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * |
| 29 * $FreeBSD: head/sys/x86/iommu/intel_reg.h 257251 2013-10-28 13:33:29Z kib $ | 29 * $FreeBSD: stable/10/sys/x86/iommu/intel_reg.h 259512 2013-12-17 13:49:35Z kib $ |
| 30 */ 31 32#ifndef __X86_IOMMU_INTEL_REG_H 33#define __X86_IOMMU_INTEL_REG_H 34 35#define DMAR_PAGE_SIZE PAGE_SIZE 36#define DMAR_PAGE_MASK (DMAR_PAGE_SIZE - 1) 37#define DMAR_PAGE_SHIFT PAGE_SHIFT --- 217 unchanged lines hidden (view full) --- 255#define DMAR_PLMLIMIT_REG 0x6c 256 257/* Protected High-Memory Base register */ 258#define DMAR_PHMBASE_REG 0x70 259 260/* Protected High-Memory Limit register */ 261#define DMAR_PHMLIMIT_REG 0x78 262 | 30 */ 31 32#ifndef __X86_IOMMU_INTEL_REG_H 33#define __X86_IOMMU_INTEL_REG_H 34 35#define DMAR_PAGE_SIZE PAGE_SIZE 36#define DMAR_PAGE_MASK (DMAR_PAGE_SIZE - 1) 37#define DMAR_PAGE_SHIFT PAGE_SHIFT --- 217 unchanged lines hidden (view full) --- 255#define DMAR_PLMLIMIT_REG 0x6c 256 257/* Protected High-Memory Base register */ 258#define DMAR_PHMBASE_REG 0x70 259 260/* Protected High-Memory Limit register */ 261#define DMAR_PHMLIMIT_REG 0x78 262 |
| 263/* Queued Invalidation Descriptors */ 264#define DMAR_IQ_DESCR_SZ_SHIFT 4 /* Shift for descriptor count 265 to ring offset */ 266#define DMAR_IQ_DESCR_SZ (1 << DMAR_IQ_DESCR_SZ_SHIFT) 267 /* Descriptor size */ 268 269#define DMAR_IQ_DESCR_CTX_INV 0x1 /* Context-cache Invalidate 270 Descriptor */ 271#define DMAR_IQ_DESCR_CTX_GLOB (0x1 << 4) /* Granularity: Global */ 272#define DMAR_IQ_DESCR_CTX_DOM (0x2 << 4) /* Granularity: Domain */ 273#define DMAR_IQ_DESCR_CTX_DEV (0x3 << 4) /* Granularity: Device */ 274#define DMAR_IQ_DESCR_CTX_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */ 275#define DMAR_IQ_DESCR_CTX_SRC(x) (((uint64_t)(x)) << 32) /* Source Id */ 276#define DMAR_IQ_DESCR_CTX_FM(x) (((uint64_t)(x)) << 48) /* Function Mask */ 277 278#define DMAR_IQ_DESCR_IOTLB_INV 0x2 /* IOTLB Invalidate Descriptor */ 279#define DMAR_IQ_DESCR_IOTLB_GLOB (0x1 << 4) /* Granularity: Global */ 280#define DMAR_IQ_DESCR_IOTLB_DOM (0x2 << 4) /* Granularity: Domain */ 281#define DMAR_IQ_DESCR_IOTLB_PAGE (0x3 << 4) /* Granularity: Page */ 282#define DMAR_IQ_DESCR_IOTLB_DW (1 << 6) /* Drain Writes */ 283#define DMAR_IQ_DESCR_IOTLB_DR (1 << 7) /* Drain Reads */ 284#define DMAR_IQ_DESCR_IOTLB_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */ 285 286#define DMAR_IQ_DESCR_WAIT_ID 0x5 /* Invalidation Wait Descriptor */ 287#define DMAR_IQ_DESCR_WAIT_IF (1 << 4) /* Interrupt Flag */ 288#define DMAR_IQ_DESCR_WAIT_SW (1 << 5) /* Status Write */ 289#define DMAR_IQ_DESCR_WAIT_FN (1 << 6) /* Fence */ 290#define DMAR_IQ_DESCR_WAIT_SD(x) (((uint64_t)(x)) << 32) /* Status Data */ 291 |
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| 263/* Invalidation Queue Head register */ 264#define DMAR_IQH_REG 0x80 | 292/* Invalidation Queue Head register */ 293#define DMAR_IQH_REG 0x80 |
| 294#define DMAR_IQH_MASK 0x7fff0 /* Next cmd index mask */ |
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| 265 266/* Invalidation Queue Tail register */ 267#define DMAR_IQT_REG 0x88 | 295 296/* Invalidation Queue Tail register */ 297#define DMAR_IQT_REG 0x88 |
| 298#define DMAR_IQT_MASK 0x7fff0 |
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| 268 269/* Invalidation Queue Address register */ 270#define DMAR_IQA_REG 0x90 | 299 300/* Invalidation Queue Address register */ 301#define DMAR_IQA_REG 0x90 |
| 302#define DMAR_IQA_IQA_MASK 0xfffffffffffff000 /* Invalidation Queue 303 Base Address mask */ 304#define DMAR_IQA_QS_MASK 0x7 /* Queue Size in pages */ 305#define DMAR_IQA_QS_MAX 0x7 /* Max Queue size */ 306#define DMAR_IQA_QS_DEF 3 |
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| 271 272 /* Invalidation Completion Status register */ 273#define DMAR_ICS_REG 0x9c 274#define DMAR_ICS_IWC 1 /* Invalidation Wait 275 Descriptor Complete */ 276 277/* Invalidation Event Control register */ 278#define DMAR_IECTL_REG 0xa0 --- 16 unchanged lines hidden --- | 307 308 /* Invalidation Completion Status register */ 309#define DMAR_ICS_REG 0x9c 310#define DMAR_ICS_IWC 1 /* Invalidation Wait 311 Descriptor Complete */ 312 313/* Invalidation Event Control register */ 314#define DMAR_IECTL_REG 0xa0 --- 16 unchanged lines hidden --- |