1/*-
2 * Copyright (c) 2013 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6 * under sponsorship from the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD: head/sys/x86/iommu/intel_reg.h 257251 2013-10-28 13:33:29Z kib $
30 */
31
32#ifndef __X86_IOMMU_INTEL_REG_H
33#define __X86_IOMMU_INTEL_REG_H
34
35#define DMAR_PAGE_SIZE PAGE_SIZE
36#define DMAR_PAGE_MASK (DMAR_PAGE_SIZE - 1)
37#define DMAR_PAGE_SHIFT PAGE_SHIFT
38#define DMAR_NPTEPG (DMAR_PAGE_SIZE / sizeof(dmar_pte_t))
39#define DMAR_NPTEPGSHIFT 9
40#define DMAR_PTEMASK (DMAR_NPTEPG - 1)
41
42typedef struct dmar_root_entry {
43 uint64_t r1;
44 uint64_t r2;
45} dmar_root_entry_t;
46#define DMAR_ROOT_R1_P 1 /* Present */
47#define DMAR_ROOT_R1_CTP_MASK 0xfffffffffffff000 /* Mask for Context-Entry
48 Table Pointer */
49
50#define DMAR_CTX_CNT (DMAR_PAGE_SIZE / sizeof(dmar_root_entry_t))
51
52typedef struct dmar_ctx_entry {
53 uint64_t ctx1;
54 uint64_t ctx2;
55} dmar_ctx_entry_t;
56#define DMAR_CTX1_P 1 /* Present */
57#define DMAR_CTX1_FPD 2 /* Fault Processing Disable */
58 /* Translation Type: */
59#define DMAR_CTX1_T_UNTR 0 /* only Untranslated */
60#define DMAR_CTX1_T_TR 4 /* both Untranslated
61 and Translated */
62#define DMAR_CTX1_T_PASS 8 /* Pass-Through */
63#define DMAR_CTX1_ASR_MASK 0xfffffffffffff000 /* Mask for the Address
64 Space Root */
65#define DMAR_CTX2_AW_2LVL 0 /* 2-level page tables */
66#define DMAR_CTX2_AW_3LVL 1 /* 3-level page tables */
67#define DMAR_CTX2_AW_4LVL 2 /* 4-level page tables */
68#define DMAR_CTX2_AW_5LVL 3 /* 5-level page tables */
69#define DMAR_CTX2_AW_6LVL 4 /* 6-level page tables */
70#define DMAR_CTX2_DID(x) ((x) << 8) /* Domain Identifier */
71
72typedef struct dmar_pte {
73 uint64_t pte;
74} dmar_pte_t;
75#define DMAR_PTE_R 1 /* Read */
76#define DMAR_PTE_W (1 << 1) /* Write */
77#define DMAR_PTE_SP (1 << 7) /* Super Page */
78#define DMAR_PTE_SNP (1 << 11) /* Snoop Behaviour */
79#define DMAR_PTE_ADDR_MASK 0xffffffffff000 /* Address Mask */
80#define DMAR_PTE_TM (1ULL << 62) /* Transient Mapping */
81
82/* Version register */
83#define DMAR_VER_REG 0
84#define DMAR_MAJOR_VER(x) (((x) >> 4) & 0xf)
85#define DMAR_MINOR_VER(x) ((x) & 0xf)
86
87/* Capabilities register */
88#define DMAR_CAP_REG 0x8
89#define DMAR_CAP_DRD (1ULL << 55) /* DMA Read Draining */
90#define DMAR_CAP_DWD (1ULL << 54) /* DMA Write Draining */
91#define DMAR_CAP_MAMV(x) ((u_int)(((x) >> 48) & 0x3f))
92 /* Maximum Address Mask */
93#define DMAR_CAP_NFR(x) ((u_int)(((x) >> 40) & 0xff) + 1)
94 /* Num of Fault-recording regs */
95#define DMAR_CAP_PSI (1ULL << 39) /* Page Selective Invalidation */
96#define DMAR_CAP_SPS(x) ((u_int)(((x) >> 34) & 0xf)) /* Super-Page Support */
97#define DMAR_CAP_SPS_2M 0x1
98#define DMAR_CAP_SPS_1G 0x2
99#define DMAR_CAP_SPS_512G 0x4
100#define DMAR_CAP_SPS_1T 0x8
101#define DMAR_CAP_FRO(x) ((u_int)(((x) >> 24) & 0x1ff))
102 /* Fault-recording reg offset */
103#define DMAR_CAP_ISOCH (1 << 23) /* Isochrony */
104#define DMAR_CAP_ZLR (1 << 22) /* Zero-length reads */
105#define DMAR_CAP_MGAW(x) ((u_int)(((x) >> 16) & 0x3f))
106 /* Max Guest Address Width */
107#define DMAR_CAP_SAGAW(x) ((u_int)(((x) >> 8) & 0x1f))
108 /* Adjusted Guest Address Width */
109#define DMAR_CAP_SAGAW_2LVL 0x01
110#define DMAR_CAP_SAGAW_3LVL 0x02
111#define DMAR_CAP_SAGAW_4LVL 0x04
112#define DMAR_CAP_SAGAW_5LVL 0x08
113#define DMAR_CAP_SAGAW_6LVL 0x10
114#define DMAR_CAP_CM (1 << 7) /* Caching mode */
115#define DMAR_CAP_PHMR (1 << 6) /* Protected High-mem Region */
116#define DMAR_CAP_PLMR (1 << 5) /* Protected Low-mem Region */
117#define DMAR_CAP_RWBF (1 << 4) /* Required Write-Buffer Flushing */
118#define DMAR_CAP_AFL (1 << 3) /* Advanced Fault Logging */
119#define DMAR_CAP_ND(x) ((u_int)((x) & 0x3)) /* Number of domains */
120
121/* Extended Capabilities register */
122#define DMAR_ECAP_REG 0x10
123#define DMAR_ECAP_MHMV(x) ((u_int)(((x) >> 20) & 0xf))
124 /* Maximum Handle Mask Value */
125#define DMAR_ECAP_IRO(x) ((u_int)(((x) >> 8) & 0x3ff))
126 /* IOTLB Register Offset */
127#define DMAR_ECAP_SC (1 << 7) /* Snoop Control */
128#define DMAR_ECAP_PT (1 << 6) /* Pass Through */
129#define DMAR_ECAP_EIM (1 << 4) /* Extended Interrupt Mode */
130#define DMAR_ECAP_IR (1 << 3) /* Interrupt Remapping */
131#define DMAR_ECAP_DI (1 << 2) /* Device IOTLB */
132#define DMAR_ECAP_QI (1 << 1) /* Queued Invalidation */
133#define DMAR_ECAP_C (1 << 0) /* Coherency */
134
135/* Global Command register */
136#define DMAR_GCMD_REG 0x18
137#define DMAR_GCMD_TE (1 << 31) /* Translation Enable */
138#define DMAR_GCMD_SRTP (1 << 30) /* Set Root Table Pointer */
139#define DMAR_GCMD_SFL (1 << 29) /* Set Fault Log */
140#define DMAR_GCMD_EAFL (1 << 28) /* Enable Advanced Fault Logging */
141#define DMAR_GCMD_WBF (1 << 27) /* Write Buffer Flush */
142#define DMAR_GCMD_QIE (1 << 26) /* Queued Invalidation Enable */
143#define DMAR_GCMD_IRE (1 << 25) /* Interrupt Remapping Enable */
144#define DMAR_GCMD_SIRTP (1 << 24) /* Set Interrupt Remap Table Pointer */
145#define DMAR_GCMD_CFI (1 << 23) /* Compatibility Format Interrupt */
146
147/* Global Status register */
148#define DMAR_GSTS_REG 0x1c
149#define DMAR_GSTS_TES (1 << 31) /* Translation Enable Status */
150#define DMAR_GSTS_RTPS (1 << 30) /* Root Table Pointer Status */
151#define DMAR_GSTS_FLS (1 << 29) /* Fault Log Status */
152#define DMAR_GSTS_AFLS (1 << 28) /* Advanced Fault Logging Status */
153#define DMAR_GSTS_WBFS (1 << 27) /* Write Buffer Flush Status */
154#define DMAR_GSTS_QIES (1 << 26) /* Queued Invalidation Enable Status */
155#define DMAR_GSTS_IRES (1 << 25) /* Interrupt Remapping Enable Status */
156#define DMAR_GSTS_IRTPS (1 << 24) /* Interrupt Remapping Table
157 Pointer Status */
158#define DMAR_GSTS_CFIS (1 << 23) /* Compatibility Format
159 Interrupt Status */
160
161/* Root-Entry Table Address register */
162#define DMAR_RTADDR_REG 0x20
163
164/* Context Command register */
165#define DMAR_CCMD_REG 0x28
166#define DMAR_CCMD_ICC (1ULL << 63) /* Invalidate Context-Cache */
167#define DMAR_CCMD_ICC32 (1 << 31)
168#define DMAR_CCMD_CIRG_MASK (0x3ULL << 61) /* Context Invalidation
169 Request Granularity */
170#define DMAR_CCMD_CIRG_GLOB (0x1ULL << 61) /* Global */
171#define DMAR_CCMD_CIRG_DOM (0x2ULL << 61) /* Domain */
172#define DMAR_CCMD_CIRG_DEV (0x3ULL << 61) /* Device */
173#define DMAR_CCMD_CAIG(x) (((x) >> 59) & 0x3) /* Context Actual
174 Invalidation Granularity */
175#define DMAR_CCMD_CAIG_GLOB 0x1 /* Global */
176#define DMAR_CCMD_CAIG_DOM 0x2 /* Domain */
177#define DMAR_CCMD_CAIG_DEV 0x3 /* Device */
178#define DMAR_CCMD_FM (0x3UUL << 32) /* Function Mask */
179#define DMAR_CCMD_SID(x) (((x) & 0xffff) << 16) /* Source-ID */
180#define DMAR_CCMD_DID(x) ((x) & 0xffff) /* Domain-ID */
181
182/* Invalidate Address register */
183#define DMAR_IVA_REG_OFF 0
184#define DMAR_IVA_IH (1 << 6) /* Invalidation Hint */
185#define DMAR_IVA_AM(x) ((x) & 0x1f) /* Address Mask */
186#define DMAR_IVA_ADDR(x) ((x) & ~0xfffULL) /* Address */
187
188/* IOTLB Invalidate register */
189#define DMAR_IOTLB_REG_OFF 0x8
190#define DMAR_IOTLB_IVT (1ULL << 63) /* Invalidate IOTLB */
191#define DMAR_IOTLB_IVT32 (1 << 31)
192#define DMAR_IOTLB_IIRG_MASK (0x3ULL << 60) /* Invalidation Request
193 Granularity */
194#define DMAR_IOTLB_IIRG_GLB (0x1ULL << 60) /* Global */
195#define DMAR_IOTLB_IIRG_DOM (0x2ULL << 60) /* Domain-selective */
196#define DMAR_IOTLB_IIRG_PAGE (0x3ULL << 60) /* Page-selective */
197#define DMAR_IOTLB_IAIG_MASK (0x3ULL << 57) /* Actual Invalidation
198 Granularity */
199#define DMAR_IOTLB_IAIG_INVLD 0 /* Hw detected error */
200#define DMAR_IOTLB_IAIG_GLB (0x1ULL << 57) /* Global */
201#define DMAR_IOTLB_IAIG_DOM (0x2ULL << 57) /* Domain-selective */
202#define DMAR_IOTLB_IAIG_PAGE (0x3ULL << 57) /* Page-selective */
203#define DMAR_IOTLB_DR (0x1ULL << 49) /* Drain Reads */
204#define DMAR_IOTLB_DW (0x1ULL << 48) /* Drain Writes */
205#define DMAR_IOTLB_DID(x) (((uint64_t)(x) & 0xffff) << 32) /* Domain Id */
206
207/* Fault Status register */
208#define DMAR_FSTS_REG 0x34
209#define DMAR_FSTS_FRI(x) (((x) >> 8) & 0xff) /* Fault Record Index */
210#define DMAR_FSTS_ITE (1 << 6) /* Invalidation Time-out */
211#define DMAR_FSTS_ICE (1 << 5) /* Invalidation Completion */
212#define DMAR_FSTS_IQE (1 << 4) /* Invalidation Queue */
213#define DMAR_FSTS_APF (1 << 3) /* Advanced Pending Fault */
214#define DMAR_FSTS_AFO (1 << 2) /* Advanced Fault Overflow */
215#define DMAR_FSTS_PPF (1 << 1) /* Primary Pending Fault */
216#define DMAR_FSTS_PFO 1 /* Fault Overflow */
217
218/* Fault Event Control register */
219#define DMAR_FECTL_REG 0x38
220#define DMAR_FECTL_IM (1 << 31) /* Interrupt Mask */
221#define DMAR_FECTL_IP (1 << 30) /* Interrupt Pending */
222
223/* Fault Event Data register */
224#define DMAR_FEDATA_REG 0x3c
225
226/* Fault Event Address register */
227#define DMAR_FEADDR_REG 0x40
228
229/* Fault Event Upper Address register */
230#define DMAR_FEUADDR_REG 0x44
231
232/* Advanced Fault Log register */
233#define DMAR_AFLOG_REG 0x58
234
235/* Fault Recording Register, also usable for Advanced Fault Log records */
236#define DMAR_FRCD2_F (1ULL << 63) /* Fault */
237#define DMAR_FRCD2_F32 (1 << 31)
238#define DMAR_FRCD2_T(x) ((int)((x >> 62) & 1)) /* Type */
239#define DMAR_FRCD2_T_W 0 /* Write request */
240#define DMAR_FRCD2_T_R 1 /* Read or AtomicOp */
241#define DMAR_FRCD2_AT(x) ((int)((x >> 60) & 0x3)) /* Address Type */
242#define DMAR_FRCD2_FR(x) ((int)((x >> 32) & 0xff)) /* Fault Reason */
243#define DMAR_FRCD2_SID(x) ((int)(x & 0xffff)) /* Source Identifier */
244#define DMAR_FRCS1_FI_MASK 0xffffffffff000 /* Fault Info, Address Mask */
245
246/* Protected Memory Enable register */
247#define DMAR_PMEN_REG 0x64
248#define DMAR_PMEN_EPM (1 << 31) /* Enable Protected Memory */
249#define DMAR_PMEN_PRS 1 /* Protected Region Status */
250
251/* Protected Low-Memory Base register */
252#define DMAR_PLMBASE_REG 0x68
253
254/* Protected Low-Memory Limit register */
255#define DMAR_PLMLIMIT_REG 0x6c
256
257/* Protected High-Memory Base register */
258#define DMAR_PHMBASE_REG 0x70
259
260/* Protected High-Memory Limit register */
261#define DMAR_PHMLIMIT_REG 0x78
262
263/* Invalidation Queue Head register */
264#define DMAR_IQH_REG 0x80
265
266/* Invalidation Queue Tail register */
267#define DMAR_IQT_REG 0x88
268
269/* Invalidation Queue Address register */
270#define DMAR_IQA_REG 0x90
271
272 /* Invalidation Completion Status register */
273#define DMAR_ICS_REG 0x9c
274#define DMAR_ICS_IWC 1 /* Invalidation Wait
275 Descriptor Complete */
276
277/* Invalidation Event Control register */
278#define DMAR_IECTL_REG 0xa0
279#define DMAR_IECTL_IM (1 << 31) /* Interrupt Mask */
280#define DMAR_IECTL_IP (1 << 30) /* Interrupt Pending */
281
282/* Invalidation Event Data register */
283#define DMAR_IEDATA_REG 0xa4
284
285/* Invalidation Event Address register */
286#define DMAR_IEADDR_REG 0xa8
287
288/* Invalidation Event Upper Address register */
289#define DMAR_IEUADDR_REG 0xac
290
291/* Interrupt Remapping Table Address register */
292#define DMAR_IRTA_REG 0xb8
293
294#endif
2 * Copyright (c) 2013 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6 * under sponsorship from the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD: head/sys/x86/iommu/intel_reg.h 257251 2013-10-28 13:33:29Z kib $
30 */
31
32#ifndef __X86_IOMMU_INTEL_REG_H
33#define __X86_IOMMU_INTEL_REG_H
34
35#define DMAR_PAGE_SIZE PAGE_SIZE
36#define DMAR_PAGE_MASK (DMAR_PAGE_SIZE - 1)
37#define DMAR_PAGE_SHIFT PAGE_SHIFT
38#define DMAR_NPTEPG (DMAR_PAGE_SIZE / sizeof(dmar_pte_t))
39#define DMAR_NPTEPGSHIFT 9
40#define DMAR_PTEMASK (DMAR_NPTEPG - 1)
41
42typedef struct dmar_root_entry {
43 uint64_t r1;
44 uint64_t r2;
45} dmar_root_entry_t;
46#define DMAR_ROOT_R1_P 1 /* Present */
47#define DMAR_ROOT_R1_CTP_MASK 0xfffffffffffff000 /* Mask for Context-Entry
48 Table Pointer */
49
50#define DMAR_CTX_CNT (DMAR_PAGE_SIZE / sizeof(dmar_root_entry_t))
51
52typedef struct dmar_ctx_entry {
53 uint64_t ctx1;
54 uint64_t ctx2;
55} dmar_ctx_entry_t;
56#define DMAR_CTX1_P 1 /* Present */
57#define DMAR_CTX1_FPD 2 /* Fault Processing Disable */
58 /* Translation Type: */
59#define DMAR_CTX1_T_UNTR 0 /* only Untranslated */
60#define DMAR_CTX1_T_TR 4 /* both Untranslated
61 and Translated */
62#define DMAR_CTX1_T_PASS 8 /* Pass-Through */
63#define DMAR_CTX1_ASR_MASK 0xfffffffffffff000 /* Mask for the Address
64 Space Root */
65#define DMAR_CTX2_AW_2LVL 0 /* 2-level page tables */
66#define DMAR_CTX2_AW_3LVL 1 /* 3-level page tables */
67#define DMAR_CTX2_AW_4LVL 2 /* 4-level page tables */
68#define DMAR_CTX2_AW_5LVL 3 /* 5-level page tables */
69#define DMAR_CTX2_AW_6LVL 4 /* 6-level page tables */
70#define DMAR_CTX2_DID(x) ((x) << 8) /* Domain Identifier */
71
72typedef struct dmar_pte {
73 uint64_t pte;
74} dmar_pte_t;
75#define DMAR_PTE_R 1 /* Read */
76#define DMAR_PTE_W (1 << 1) /* Write */
77#define DMAR_PTE_SP (1 << 7) /* Super Page */
78#define DMAR_PTE_SNP (1 << 11) /* Snoop Behaviour */
79#define DMAR_PTE_ADDR_MASK 0xffffffffff000 /* Address Mask */
80#define DMAR_PTE_TM (1ULL << 62) /* Transient Mapping */
81
82/* Version register */
83#define DMAR_VER_REG 0
84#define DMAR_MAJOR_VER(x) (((x) >> 4) & 0xf)
85#define DMAR_MINOR_VER(x) ((x) & 0xf)
86
87/* Capabilities register */
88#define DMAR_CAP_REG 0x8
89#define DMAR_CAP_DRD (1ULL << 55) /* DMA Read Draining */
90#define DMAR_CAP_DWD (1ULL << 54) /* DMA Write Draining */
91#define DMAR_CAP_MAMV(x) ((u_int)(((x) >> 48) & 0x3f))
92 /* Maximum Address Mask */
93#define DMAR_CAP_NFR(x) ((u_int)(((x) >> 40) & 0xff) + 1)
94 /* Num of Fault-recording regs */
95#define DMAR_CAP_PSI (1ULL << 39) /* Page Selective Invalidation */
96#define DMAR_CAP_SPS(x) ((u_int)(((x) >> 34) & 0xf)) /* Super-Page Support */
97#define DMAR_CAP_SPS_2M 0x1
98#define DMAR_CAP_SPS_1G 0x2
99#define DMAR_CAP_SPS_512G 0x4
100#define DMAR_CAP_SPS_1T 0x8
101#define DMAR_CAP_FRO(x) ((u_int)(((x) >> 24) & 0x1ff))
102 /* Fault-recording reg offset */
103#define DMAR_CAP_ISOCH (1 << 23) /* Isochrony */
104#define DMAR_CAP_ZLR (1 << 22) /* Zero-length reads */
105#define DMAR_CAP_MGAW(x) ((u_int)(((x) >> 16) & 0x3f))
106 /* Max Guest Address Width */
107#define DMAR_CAP_SAGAW(x) ((u_int)(((x) >> 8) & 0x1f))
108 /* Adjusted Guest Address Width */
109#define DMAR_CAP_SAGAW_2LVL 0x01
110#define DMAR_CAP_SAGAW_3LVL 0x02
111#define DMAR_CAP_SAGAW_4LVL 0x04
112#define DMAR_CAP_SAGAW_5LVL 0x08
113#define DMAR_CAP_SAGAW_6LVL 0x10
114#define DMAR_CAP_CM (1 << 7) /* Caching mode */
115#define DMAR_CAP_PHMR (1 << 6) /* Protected High-mem Region */
116#define DMAR_CAP_PLMR (1 << 5) /* Protected Low-mem Region */
117#define DMAR_CAP_RWBF (1 << 4) /* Required Write-Buffer Flushing */
118#define DMAR_CAP_AFL (1 << 3) /* Advanced Fault Logging */
119#define DMAR_CAP_ND(x) ((u_int)((x) & 0x3)) /* Number of domains */
120
121/* Extended Capabilities register */
122#define DMAR_ECAP_REG 0x10
123#define DMAR_ECAP_MHMV(x) ((u_int)(((x) >> 20) & 0xf))
124 /* Maximum Handle Mask Value */
125#define DMAR_ECAP_IRO(x) ((u_int)(((x) >> 8) & 0x3ff))
126 /* IOTLB Register Offset */
127#define DMAR_ECAP_SC (1 << 7) /* Snoop Control */
128#define DMAR_ECAP_PT (1 << 6) /* Pass Through */
129#define DMAR_ECAP_EIM (1 << 4) /* Extended Interrupt Mode */
130#define DMAR_ECAP_IR (1 << 3) /* Interrupt Remapping */
131#define DMAR_ECAP_DI (1 << 2) /* Device IOTLB */
132#define DMAR_ECAP_QI (1 << 1) /* Queued Invalidation */
133#define DMAR_ECAP_C (1 << 0) /* Coherency */
134
135/* Global Command register */
136#define DMAR_GCMD_REG 0x18
137#define DMAR_GCMD_TE (1 << 31) /* Translation Enable */
138#define DMAR_GCMD_SRTP (1 << 30) /* Set Root Table Pointer */
139#define DMAR_GCMD_SFL (1 << 29) /* Set Fault Log */
140#define DMAR_GCMD_EAFL (1 << 28) /* Enable Advanced Fault Logging */
141#define DMAR_GCMD_WBF (1 << 27) /* Write Buffer Flush */
142#define DMAR_GCMD_QIE (1 << 26) /* Queued Invalidation Enable */
143#define DMAR_GCMD_IRE (1 << 25) /* Interrupt Remapping Enable */
144#define DMAR_GCMD_SIRTP (1 << 24) /* Set Interrupt Remap Table Pointer */
145#define DMAR_GCMD_CFI (1 << 23) /* Compatibility Format Interrupt */
146
147/* Global Status register */
148#define DMAR_GSTS_REG 0x1c
149#define DMAR_GSTS_TES (1 << 31) /* Translation Enable Status */
150#define DMAR_GSTS_RTPS (1 << 30) /* Root Table Pointer Status */
151#define DMAR_GSTS_FLS (1 << 29) /* Fault Log Status */
152#define DMAR_GSTS_AFLS (1 << 28) /* Advanced Fault Logging Status */
153#define DMAR_GSTS_WBFS (1 << 27) /* Write Buffer Flush Status */
154#define DMAR_GSTS_QIES (1 << 26) /* Queued Invalidation Enable Status */
155#define DMAR_GSTS_IRES (1 << 25) /* Interrupt Remapping Enable Status */
156#define DMAR_GSTS_IRTPS (1 << 24) /* Interrupt Remapping Table
157 Pointer Status */
158#define DMAR_GSTS_CFIS (1 << 23) /* Compatibility Format
159 Interrupt Status */
160
161/* Root-Entry Table Address register */
162#define DMAR_RTADDR_REG 0x20
163
164/* Context Command register */
165#define DMAR_CCMD_REG 0x28
166#define DMAR_CCMD_ICC (1ULL << 63) /* Invalidate Context-Cache */
167#define DMAR_CCMD_ICC32 (1 << 31)
168#define DMAR_CCMD_CIRG_MASK (0x3ULL << 61) /* Context Invalidation
169 Request Granularity */
170#define DMAR_CCMD_CIRG_GLOB (0x1ULL << 61) /* Global */
171#define DMAR_CCMD_CIRG_DOM (0x2ULL << 61) /* Domain */
172#define DMAR_CCMD_CIRG_DEV (0x3ULL << 61) /* Device */
173#define DMAR_CCMD_CAIG(x) (((x) >> 59) & 0x3) /* Context Actual
174 Invalidation Granularity */
175#define DMAR_CCMD_CAIG_GLOB 0x1 /* Global */
176#define DMAR_CCMD_CAIG_DOM 0x2 /* Domain */
177#define DMAR_CCMD_CAIG_DEV 0x3 /* Device */
178#define DMAR_CCMD_FM (0x3UUL << 32) /* Function Mask */
179#define DMAR_CCMD_SID(x) (((x) & 0xffff) << 16) /* Source-ID */
180#define DMAR_CCMD_DID(x) ((x) & 0xffff) /* Domain-ID */
181
182/* Invalidate Address register */
183#define DMAR_IVA_REG_OFF 0
184#define DMAR_IVA_IH (1 << 6) /* Invalidation Hint */
185#define DMAR_IVA_AM(x) ((x) & 0x1f) /* Address Mask */
186#define DMAR_IVA_ADDR(x) ((x) & ~0xfffULL) /* Address */
187
188/* IOTLB Invalidate register */
189#define DMAR_IOTLB_REG_OFF 0x8
190#define DMAR_IOTLB_IVT (1ULL << 63) /* Invalidate IOTLB */
191#define DMAR_IOTLB_IVT32 (1 << 31)
192#define DMAR_IOTLB_IIRG_MASK (0x3ULL << 60) /* Invalidation Request
193 Granularity */
194#define DMAR_IOTLB_IIRG_GLB (0x1ULL << 60) /* Global */
195#define DMAR_IOTLB_IIRG_DOM (0x2ULL << 60) /* Domain-selective */
196#define DMAR_IOTLB_IIRG_PAGE (0x3ULL << 60) /* Page-selective */
197#define DMAR_IOTLB_IAIG_MASK (0x3ULL << 57) /* Actual Invalidation
198 Granularity */
199#define DMAR_IOTLB_IAIG_INVLD 0 /* Hw detected error */
200#define DMAR_IOTLB_IAIG_GLB (0x1ULL << 57) /* Global */
201#define DMAR_IOTLB_IAIG_DOM (0x2ULL << 57) /* Domain-selective */
202#define DMAR_IOTLB_IAIG_PAGE (0x3ULL << 57) /* Page-selective */
203#define DMAR_IOTLB_DR (0x1ULL << 49) /* Drain Reads */
204#define DMAR_IOTLB_DW (0x1ULL << 48) /* Drain Writes */
205#define DMAR_IOTLB_DID(x) (((uint64_t)(x) & 0xffff) << 32) /* Domain Id */
206
207/* Fault Status register */
208#define DMAR_FSTS_REG 0x34
209#define DMAR_FSTS_FRI(x) (((x) >> 8) & 0xff) /* Fault Record Index */
210#define DMAR_FSTS_ITE (1 << 6) /* Invalidation Time-out */
211#define DMAR_FSTS_ICE (1 << 5) /* Invalidation Completion */
212#define DMAR_FSTS_IQE (1 << 4) /* Invalidation Queue */
213#define DMAR_FSTS_APF (1 << 3) /* Advanced Pending Fault */
214#define DMAR_FSTS_AFO (1 << 2) /* Advanced Fault Overflow */
215#define DMAR_FSTS_PPF (1 << 1) /* Primary Pending Fault */
216#define DMAR_FSTS_PFO 1 /* Fault Overflow */
217
218/* Fault Event Control register */
219#define DMAR_FECTL_REG 0x38
220#define DMAR_FECTL_IM (1 << 31) /* Interrupt Mask */
221#define DMAR_FECTL_IP (1 << 30) /* Interrupt Pending */
222
223/* Fault Event Data register */
224#define DMAR_FEDATA_REG 0x3c
225
226/* Fault Event Address register */
227#define DMAR_FEADDR_REG 0x40
228
229/* Fault Event Upper Address register */
230#define DMAR_FEUADDR_REG 0x44
231
232/* Advanced Fault Log register */
233#define DMAR_AFLOG_REG 0x58
234
235/* Fault Recording Register, also usable for Advanced Fault Log records */
236#define DMAR_FRCD2_F (1ULL << 63) /* Fault */
237#define DMAR_FRCD2_F32 (1 << 31)
238#define DMAR_FRCD2_T(x) ((int)((x >> 62) & 1)) /* Type */
239#define DMAR_FRCD2_T_W 0 /* Write request */
240#define DMAR_FRCD2_T_R 1 /* Read or AtomicOp */
241#define DMAR_FRCD2_AT(x) ((int)((x >> 60) & 0x3)) /* Address Type */
242#define DMAR_FRCD2_FR(x) ((int)((x >> 32) & 0xff)) /* Fault Reason */
243#define DMAR_FRCD2_SID(x) ((int)(x & 0xffff)) /* Source Identifier */
244#define DMAR_FRCS1_FI_MASK 0xffffffffff000 /* Fault Info, Address Mask */
245
246/* Protected Memory Enable register */
247#define DMAR_PMEN_REG 0x64
248#define DMAR_PMEN_EPM (1 << 31) /* Enable Protected Memory */
249#define DMAR_PMEN_PRS 1 /* Protected Region Status */
250
251/* Protected Low-Memory Base register */
252#define DMAR_PLMBASE_REG 0x68
253
254/* Protected Low-Memory Limit register */
255#define DMAR_PLMLIMIT_REG 0x6c
256
257/* Protected High-Memory Base register */
258#define DMAR_PHMBASE_REG 0x70
259
260/* Protected High-Memory Limit register */
261#define DMAR_PHMLIMIT_REG 0x78
262
263/* Invalidation Queue Head register */
264#define DMAR_IQH_REG 0x80
265
266/* Invalidation Queue Tail register */
267#define DMAR_IQT_REG 0x88
268
269/* Invalidation Queue Address register */
270#define DMAR_IQA_REG 0x90
271
272 /* Invalidation Completion Status register */
273#define DMAR_ICS_REG 0x9c
274#define DMAR_ICS_IWC 1 /* Invalidation Wait
275 Descriptor Complete */
276
277/* Invalidation Event Control register */
278#define DMAR_IECTL_REG 0xa0
279#define DMAR_IECTL_IM (1 << 31) /* Interrupt Mask */
280#define DMAR_IECTL_IP (1 << 30) /* Interrupt Pending */
281
282/* Invalidation Event Data register */
283#define DMAR_IEDATA_REG 0xa4
284
285/* Invalidation Event Address register */
286#define DMAR_IEADDR_REG 0xa8
287
288/* Invalidation Event Upper Address register */
289#define DMAR_IEUADDR_REG 0xac
290
291/* Interrupt Remapping Table Address register */
292#define DMAR_IRTA_REG 0xb8
293
294#endif