1/*-
2 * Copyright (c) 2013 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6 * under sponsorship from the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
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21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD: head/sys/x86/iommu/intel_reg.h 257251 2013-10-28 13:33:29Z kib $
30 */
31
32#ifndef __X86_IOMMU_INTEL_REG_H
33#define __X86_IOMMU_INTEL_REG_H
34
35#define DMAR_PAGE_SIZE PAGE_SIZE
36#define DMAR_PAGE_MASK (DMAR_PAGE_SIZE - 1)
37#define DMAR_PAGE_SHIFT PAGE_SHIFT
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255#define DMAR_PLMLIMIT_REG 0x6c
256
257/* Protected High-Memory Base register */
258#define DMAR_PHMBASE_REG 0x70
259
260/* Protected High-Memory Limit register */
261#define DMAR_PHMLIMIT_REG 0x78
262
263/* Invalidation Queue Head register */
264#define DMAR_IQH_REG 0x80
265
266/* Invalidation Queue Tail register */
267#define DMAR_IQT_REG 0x88
268
269/* Invalidation Queue Address register */
270#define DMAR_IQA_REG 0x90
271
272 /* Invalidation Completion Status register */
273#define DMAR_ICS_REG 0x9c
274#define DMAR_ICS_IWC 1 /* Invalidation Wait
275 Descriptor Complete */
276
277/* Invalidation Event Control register */
278#define DMAR_IECTL_REG 0xa0
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2 * Copyright (c) 2013 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6 * under sponsorship from the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
--- 12 unchanged lines hidden (view full) ---
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD: head/sys/x86/iommu/intel_reg.h 257251 2013-10-28 13:33:29Z kib $
30 */
31
32#ifndef __X86_IOMMU_INTEL_REG_H
33#define __X86_IOMMU_INTEL_REG_H
34
35#define DMAR_PAGE_SIZE PAGE_SIZE
36#define DMAR_PAGE_MASK (DMAR_PAGE_SIZE - 1)
37#define DMAR_PAGE_SHIFT PAGE_SHIFT
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255#define DMAR_PLMLIMIT_REG 0x6c
256
257/* Protected High-Memory Base register */
258#define DMAR_PHMBASE_REG 0x70
259
260/* Protected High-Memory Limit register */
261#define DMAR_PHMLIMIT_REG 0x78
262
263/* Invalidation Queue Head register */
264#define DMAR_IQH_REG 0x80
265
266/* Invalidation Queue Tail register */
267#define DMAR_IQT_REG 0x88
268
269/* Invalidation Queue Address register */
270#define DMAR_IQA_REG 0x90
271
272 /* Invalidation Completion Status register */
273#define DMAR_ICS_REG 0x9c
274#define DMAR_ICS_IWC 1 /* Invalidation Wait
275 Descriptor Complete */
276
277/* Invalidation Event Control register */
278#define DMAR_IECTL_REG 0xa0
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