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est.c (155996) est.c (158446)
1/*-
2 * Copyright (c) 2004 Colin Percival
3 * Copyright (c) 2005 Nate Lawson
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted providing that the following conditions
8 * are met:

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
24 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2004 Colin Percival
3 * Copyright (c) 2005 Nate Lawson
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted providing that the following conditions
8 * are met:

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
24 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/i386/cpufreq/est.c 155996 2006-02-25 04:55:38Z cperciva $");
29__FBSDID("$FreeBSD: head/sys/i386/cpufreq/est.c 158446 2006-05-11 17:35:44Z njl $");
30
31#include <sys/param.h>
32#include <sys/bus.h>
33#include <sys/cpu.h>
34#include <sys/kernel.h>
35#include <sys/malloc.h>
36#include <sys/module.h>
37#include <sys/smp.h>

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59 uint16_t id16;
60 int power;
61} freq_info;
62
63/* Identifying characteristics of a processor and supported frequencies. */
64typedef struct {
65 const char *vendor;
66 uint32_t id32;
30
31#include <sys/param.h>
32#include <sys/bus.h>
33#include <sys/cpu.h>
34#include <sys/kernel.h>
35#include <sys/malloc.h>
36#include <sys/module.h>
37#include <sys/smp.h>

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59 uint16_t id16;
60 int power;
61} freq_info;
62
63/* Identifying characteristics of a processor and supported frequencies. */
64typedef struct {
65 const char *vendor;
66 uint32_t id32;
67 uint32_t bus_clk;
68 freq_info *freqtab;
69} cpu_info;
70
71struct est_softc {
72 device_t dev;
73 int acpi_settings;
74 freq_info *freq_list;
75};
76
77/* Convert MHz and mV into IDs for passing to the MSR. */
78#define ID16(MHz, mV, bus_clk) \
79 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
80#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \
81 ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk)))
82
83/* Format for storing IDs in our table. */
67 freq_info *freqtab;
68} cpu_info;
69
70struct est_softc {
71 device_t dev;
72 int acpi_settings;
73 freq_info *freq_list;
74};
75
76/* Convert MHz and mV into IDs for passing to the MSR. */
77#define ID16(MHz, mV, bus_clk) \
78 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
79#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \
80 ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk)))
81
82/* Format for storing IDs in our table. */
83#define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \
84 { MHz, mV, ID16(MHz, mV, bus_clk), mW }
84#define FREQ_INFO(MHz, mV, bus_clk) \
85#define FREQ_INFO(MHz, mV, bus_clk) \
85 { MHz, mV, ID16(MHz, mV, bus_clk), CPUFREQ_VAL_UNKNOWN }
86 FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN)
86#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \
87#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \
87 { GenuineIntel, ID32(zhi, vhi, zlo, vlo, bus_clk), bus_clk, tab }
88 { intel_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
89#define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \
90 { centaur_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
88
91
89const char GenuineIntel[] = "GenuineIntel";
92const char intel_id[] = "GenuineIntel";
93const char centaur_id[] = "CentaurHauls";
90
91/* Default bus clock value for Centrino processors. */
92#define INTEL_BUS_CLK 100
93
94/* XXX Update this if new CPUs have more settings. */
95#define EST_MAX_SETTINGS 10
96CTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS);
97

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679 /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */
680 FREQ_INFO(1000, 940, INTEL_BUS_CLK),
681 FREQ_INFO( 900, 908, INTEL_BUS_CLK),
682 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
683 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
684 FREQ_INFO( 0, 0, 1),
685};
686
94
95/* Default bus clock value for Centrino processors. */
96#define INTEL_BUS_CLK 100
97
98/* XXX Update this if new CPUs have more settings. */
99#define EST_MAX_SETTINGS 10
100CTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS);
101

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683 /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */
684 FREQ_INFO(1000, 940, INTEL_BUS_CLK),
685 FREQ_INFO( 900, 908, INTEL_BUS_CLK),
686 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
687 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
688 FREQ_INFO( 0, 0, 1),
689};
690
691/*
692 * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants.
693 * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet.
694 */
695static freq_info C7M_795[] = {
696 /* 2.00GHz Centaur C7-M 533 Mhz FSB */
697 FREQ_INFO_PWR(2000, 1148, 133, 20000),
698 FREQ_INFO_PWR(1867, 1132, 133, 18000),
699 FREQ_INFO_PWR(1600, 1100, 133, 15000),
700 FREQ_INFO_PWR(1467, 1052, 133, 13000),
701 FREQ_INFO_PWR(1200, 1004, 133, 10000),
702 FREQ_INFO_PWR( 800, 844, 133, 7000),
703 FREQ_INFO_PWR( 667, 844, 133, 6000),
704 FREQ_INFO_PWR( 533, 844, 133, 5000),
705 FREQ_INFO(0, 0, 1),
706};
707static freq_info C7M_785[] = {
708 /* 1.80GHz Centaur C7-M 533 Mhz FSB */
709 FREQ_INFO_PWR(1867, 1148, 133, 18000),
710 FREQ_INFO_PWR(1600, 1100, 133, 15000),
711 FREQ_INFO_PWR(1467, 1052, 133, 13000),
712 FREQ_INFO_PWR(1200, 1004, 133, 10000),
713 FREQ_INFO_PWR( 800, 844, 133, 7000),
714 FREQ_INFO_PWR( 667, 844, 133, 6000),
715 FREQ_INFO_PWR( 533, 844, 133, 5000),
716 FREQ_INFO(0, 0, 1),
717};
718static freq_info C7M_765[] = {
719 /* 1.60GHz Centaur C7-M 533 Mhz FSB */
720 FREQ_INFO_PWR(1600, 1084, 133, 15000),
721 FREQ_INFO_PWR(1467, 1052, 133, 13000),
722 FREQ_INFO_PWR(1200, 1004, 133, 10000),
723 FREQ_INFO_PWR( 800, 844, 133, 7000),
724 FREQ_INFO_PWR( 667, 844, 133, 6000),
725 FREQ_INFO_PWR( 533, 844, 133, 5000),
726 FREQ_INFO(0, 0, 1),
727};
728
729static freq_info C7M_794[] = {
730 /* 2.00GHz Centaur C7-M 400 Mhz FSB */
731 FREQ_INFO_PWR(2000, 1148, 100, 20000),
732 FREQ_INFO_PWR(1800, 1132, 100, 18000),
733 FREQ_INFO_PWR(1600, 1100, 100, 15000),
734 FREQ_INFO_PWR(1400, 1052, 100, 13000),
735 FREQ_INFO_PWR(1000, 1004, 100, 10000),
736 FREQ_INFO_PWR( 800, 844, 100, 7000),
737 FREQ_INFO_PWR( 600, 844, 100, 6000),
738 FREQ_INFO_PWR( 400, 844, 100, 5000),
739 FREQ_INFO(0, 0, 1),
740};
741static freq_info C7M_784[] = {
742 /* 1.80GHz Centaur C7-M 400 Mhz FSB */
743 FREQ_INFO_PWR(1800, 1148, 100, 18000),
744 FREQ_INFO_PWR(1600, 1100, 100, 15000),
745 FREQ_INFO_PWR(1400, 1052, 100, 13000),
746 FREQ_INFO_PWR(1000, 1004, 100, 10000),
747 FREQ_INFO_PWR( 800, 844, 100, 7000),
748 FREQ_INFO_PWR( 600, 844, 100, 6000),
749 FREQ_INFO_PWR( 400, 844, 100, 5000),
750 FREQ_INFO(0, 0, 1),
751};
752static freq_info C7M_764[] = {
753 /* 1.60GHz Centaur C7-M 400 Mhz FSB */
754 FREQ_INFO_PWR(1600, 1084, 100, 15000),
755 FREQ_INFO_PWR(1400, 1052, 100, 13000),
756 FREQ_INFO_PWR(1000, 1004, 100, 10000),
757 FREQ_INFO_PWR( 800, 844, 100, 7000),
758 FREQ_INFO_PWR( 600, 844, 100, 6000),
759 FREQ_INFO_PWR( 400, 844, 100, 5000),
760 FREQ_INFO(0, 0, 1),
761};
762static freq_info C7M_754[] = {
763 /* 1.50GHz Centaur C7-M 400 Mhz FSB */
764 FREQ_INFO_PWR(1500, 1004, 100, 12000),
765 FREQ_INFO_PWR(1400, 988, 100, 11000),
766 FREQ_INFO_PWR(1000, 940, 100, 9000),
767 FREQ_INFO_PWR( 800, 844, 100, 7000),
768 FREQ_INFO_PWR( 600, 844, 100, 6000),
769 FREQ_INFO_PWR( 400, 844, 100, 5000),
770 FREQ_INFO(0, 0, 1),
771};
772static freq_info C7M_771[] = {
773 /* 1.20GHz Centaur C7-M 400 Mhz FSB */
774 FREQ_INFO_PWR(1200, 860, 100, 7000),
775 FREQ_INFO_PWR(1000, 860, 100, 6000),
776 FREQ_INFO_PWR( 800, 844, 100, 5500),
777 FREQ_INFO_PWR( 600, 844, 100, 5000),
778 FREQ_INFO_PWR( 400, 844, 100, 4000),
779 FREQ_INFO(0, 0, 1),
780};
781
782static freq_info C7M_775_ULV[] = {
783 /* 1.50GHz Centaur C7-M ULV */
784 FREQ_INFO_PWR(1500, 956, 100, 7500),
785 FREQ_INFO_PWR(1400, 940, 100, 6000),
786 FREQ_INFO_PWR(1000, 860, 100, 5000),
787 FREQ_INFO_PWR( 800, 828, 100, 2800),
788 FREQ_INFO_PWR( 600, 796, 100, 2500),
789 FREQ_INFO_PWR( 400, 796, 100, 2000),
790 FREQ_INFO(0, 0, 1),
791};
792static freq_info C7M_772_ULV[] = {
793 /* 1.20GHz Centaur C7-M ULV */
794 FREQ_INFO_PWR(1200, 844, 100, 5000),
795 FREQ_INFO_PWR(1000, 844, 100, 4000),
796 FREQ_INFO_PWR( 800, 828, 100, 2800),
797 FREQ_INFO_PWR( 600, 796, 100, 2500),
798 FREQ_INFO_PWR( 400, 796, 100, 2000),
799 FREQ_INFO(0, 0, 1),
800};
801static freq_info C7M_779_ULV[] = {
802 /* 1.00GHz Centaur C7-M ULV */
803 FREQ_INFO_PWR(1000, 796, 100, 3500),
804 FREQ_INFO_PWR( 800, 796, 100, 2800),
805 FREQ_INFO_PWR( 600, 796, 100, 2500),
806 FREQ_INFO_PWR( 400, 796, 100, 2000),
807 FREQ_INFO(0, 0, 1),
808};
809static freq_info C7M_770_ULV[] = {
810 /* 1.00GHz Centaur C7-M ULV */
811 FREQ_INFO_PWR(1000, 844, 100, 5000),
812 FREQ_INFO_PWR( 800, 796, 100, 2800),
813 FREQ_INFO_PWR( 600, 796, 100, 2500),
814 FREQ_INFO_PWR( 400, 796, 100, 2000),
815 FREQ_INFO(0, 0, 1),
816};
817
687static cpu_info ESTprocs[] = {
688 INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK),
689 INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK),
690 INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK),
691 INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK),
692 INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK),
693 INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK),
694 INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK),

--- 42 unchanged lines hidden (view full) ---

737 INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK),
738 INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK),
739 INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK),
740 INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK),
741 INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK),
742 INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK),
743 INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK),
744 INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK),
818static cpu_info ESTprocs[] = {
819 INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK),
820 INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK),
821 INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK),
822 INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK),
823 INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK),
824 INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK),
825 INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK),

--- 42 unchanged lines hidden (view full) ---

868 INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK),
869 INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK),
870 INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK),
871 INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK),
872 INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK),
873 INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK),
874 INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK),
875 INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK),
745 { NULL, 0, 0, NULL },
876
877 CENTAUR(C7M_795, 2000, 1148, 533, 844, 133),
878 CENTAUR(C7M_794, 2000, 1148, 400, 844, 100),
879 CENTAUR(C7M_785, 1867, 1148, 533, 844, 133),
880 CENTAUR(C7M_784, 1800, 1148, 400, 844, 100),
881 CENTAUR(C7M_765, 1600, 1084, 533, 844, 133),
882 CENTAUR(C7M_764, 1600, 1084, 400, 844, 100),
883 CENTAUR(C7M_754, 1500, 1004, 400, 844, 100),
884 CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100),
885 CENTAUR(C7M_771, 1200, 860, 400, 844, 100),
886 CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100),
887 CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100),
888 CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100),
889 { NULL, 0, NULL },
746};
747
748static void est_identify(driver_t *driver, device_t parent);
749static int est_features(driver_t *driver, u_int *features);
750static int est_probe(device_t parent);
751static int est_attach(device_t parent);
752static int est_detach(device_t parent);
753static int est_get_info(device_t dev);
754static int est_acpi_info(device_t dev, freq_info **freqs);
890};
891
892static void est_identify(driver_t *driver, device_t parent);
893static int est_features(driver_t *driver, u_int *features);
894static int est_probe(device_t parent);
895static int est_attach(device_t parent);
896static int est_detach(device_t parent);
897static int est_get_info(device_t dev);
898static int est_acpi_info(device_t dev, freq_info **freqs);
755static int est_table_info(device_t dev, uint64_t msr, uint32_t bus_clk,
756 freq_info **freqs);
899static int est_table_info(device_t dev, uint64_t msr, freq_info **freqs);
757static freq_info *est_get_current(freq_info *freq_list);
758static int est_settings(device_t dev, struct cf_setting *sets, int *count);
759static int est_set(device_t dev, const struct cf_setting *set);
760static int est_get(device_t dev, struct cf_setting *set);
761static int est_type(device_t dev, int *type);
762
763static device_method_t est_methods[] = {
764 /* Device interface */

--- 38 unchanged lines hidden (view full) ---

803 device_t child;
804 u_int p[4];
805
806 /* Make sure we're not being doubly invoked. */
807 if (device_find_child(parent, "est", -1) != NULL)
808 return;
809
810 /* Check that CPUID is supported and the vendor is Intel.*/
900static freq_info *est_get_current(freq_info *freq_list);
901static int est_settings(device_t dev, struct cf_setting *sets, int *count);
902static int est_set(device_t dev, const struct cf_setting *set);
903static int est_get(device_t dev, struct cf_setting *set);
904static int est_type(device_t dev, int *type);
905
906static device_method_t est_methods[] = {
907 /* Device interface */

--- 38 unchanged lines hidden (view full) ---

946 device_t child;
947 u_int p[4];
948
949 /* Make sure we're not being doubly invoked. */
950 if (device_find_child(parent, "est", -1) != NULL)
951 return;
952
953 /* Check that CPUID is supported and the vendor is Intel.*/
811 if (cpu_high == 0 || strcmp(cpu_vendor, GenuineIntel) != 0)
954 if (cpu_high == 0 || (strcmp(cpu_vendor, intel_id) != 0 &&
955 strcmp(cpu_vendor, centaur_id) != 0))
812 return;
813
956 return;
957
814 /* Read capability bits and check if the CPU supports EST. */
958 /*
959 * Read capability bits and check if the CPU supports EST.
960 * This is indicated by bit 7 of ECX.
961 */
815 do_cpuid(1, p);
816 if ((p[2] & 0x80) == 0)
817 return;
818
819 /*
820 * We add a child for each CPU since settings must be performed
821 * on each CPU in the SMP case.
822 */

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903est_get_info(device_t dev)
904{
905 struct est_softc *sc;
906 uint64_t msr;
907 int error;
908
909 sc = device_get_softc(dev);
910 msr = rdmsr(MSR_PERF_STATUS);
962 do_cpuid(1, p);
963 if ((p[2] & 0x80) == 0)
964 return;
965
966 /*
967 * We add a child for each CPU since settings must be performed
968 * on each CPU in the SMP case.
969 */

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1050est_get_info(device_t dev)
1051{
1052 struct est_softc *sc;
1053 uint64_t msr;
1054 int error;
1055
1056 sc = device_get_softc(dev);
1057 msr = rdmsr(MSR_PERF_STATUS);
911 error = est_table_info(dev, msr, INTEL_BUS_CLK, &sc->freq_list);
1058 error = est_table_info(dev, msr, &sc->freq_list);
912 if (error)
913 error = est_acpi_info(dev, &sc->freq_list);
914
915 if (error) {
916 printf(
917 "est: CPU supports Enhanced Speedstep, but is not recognized.\n"
918 "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr);
919 return (ENXIO);

--- 53 unchanged lines hidden (view full) ---

973 if (sets)
974 free(sets, M_TEMP);
975 if (error && table)
976 free(table, M_DEVBUF);
977 return (error);
978}
979
980static int
1059 if (error)
1060 error = est_acpi_info(dev, &sc->freq_list);
1061
1062 if (error) {
1063 printf(
1064 "est: CPU supports Enhanced Speedstep, but is not recognized.\n"
1065 "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr);
1066 return (ENXIO);

--- 53 unchanged lines hidden (view full) ---

1120 if (sets)
1121 free(sets, M_TEMP);
1122 if (error && table)
1123 free(table, M_DEVBUF);
1124 return (error);
1125}
1126
1127static int
981est_table_info(device_t dev, uint64_t msr, uint32_t bus_clk, freq_info **freqs)
1128est_table_info(device_t dev, uint64_t msr, freq_info **freqs)
982{
983 cpu_info *p;
984 uint32_t id;
985
1129{
1130 cpu_info *p;
1131 uint32_t id;
1132
986 /* Find a table which matches (vendor, id, bus_clk). */
1133 /* Find a table which matches (vendor, id32). */
987 id = msr >> 32;
988 for (p = ESTprocs; p->id32 != 0; p++) {
1134 id = msr >> 32;
1135 for (p = ESTprocs; p->id32 != 0; p++) {
989 if (strcmp(p->vendor, cpu_vendor) == 0 && p->id32 == id &&
990 p->bus_clk == bus_clk)
1136 if (strcmp(p->vendor, cpu_vendor) == 0 && p->id32 == id)
991 break;
992 }
993 if (p->id32 == 0)
994 return (EOPNOTSUPP);
995
996 /* Make sure the current setpoint is valid. */
997 if (est_get_current(p->freqtab) == NULL) {
998 device_printf(dev, "current setting not found in table\n");

--- 110 unchanged lines hidden --- 		1137 break;
1138 }
1139 if (p->id32 == 0)
1140 return (EOPNOTSUPP);
1141
1142 /* Make sure the current setpoint is valid. */
1143 if (est_get_current(p->freqtab) == NULL) {
1144 device_printf(dev, "current setting not found in table\n");

--- 110 unchanged lines hidden ---