| psychoreg.h (139825) | psychoreg.h (152696) |
|---|---|
| 1/*- 2 * Copyright (c) 1998, 1999 Eduardo E. Horvath 3 * Copyright (c) 1999 Matthew R. Green 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 14 unchanged lines hidden (view full) --- 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psychoreg.h,v 1.8 2001/09/10 16:17:06 eeh Exp 30 * | 1/*- 2 * Copyright (c) 1998, 1999 Eduardo E. Horvath 3 * Copyright (c) 1999 Matthew R. Green 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 14 unchanged lines hidden (view full) --- 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psychoreg.h,v 1.8 2001/09/10 16:17:06 eeh Exp 30 * |
| 31 * $FreeBSD: head/sys/sparc64/pci/psychoreg.h 139825 2005-01-07 02:29:27Z imp $ | 31 * $FreeBSD: head/sys/sparc64/pci/psychoreg.h 152696 2005-11-22 21:34:26Z marius $ |
| 32 */ 33 34#ifndef _SPARC64_PCI_PSYCHOREG_H_ 35#define _SPARC64_PCI_PSYCHOREG_H_ 36 37/* 38 * Sun4u PCI definitions. Here's where we deal w/the machine | 32 */ 33 34#ifndef _SPARC64_PCI_PSYCHOREG_H_ 35#define _SPARC64_PCI_PSYCHOREG_H_ 36 37/* 38 * Sun4u PCI definitions. Here's where we deal w/the machine |
| 39 * dependencies of psycho and the PCI controller on the UltraIIi. | 39 * dependencies of Psycho and the PCI controller on the UltraIIi. |
| 40 * 41 * All PCI registers are bit-swapped, however they are not byte-swapped. 42 * This means that they must be accessed using little-endian access modes, 43 * either map the pages little-endian or use little-endian ASIs. 44 * 45 * PSYCHO implements two PCI buses, A and B. 46 */ 47 | 40 * 41 * All PCI registers are bit-swapped, however they are not byte-swapped. 42 * This means that they must be accessed using little-endian access modes, 43 * either map the pages little-endian or use little-endian ASIs. 44 * 45 * PSYCHO implements two PCI buses, A and B. 46 */ 47 |
| 48#define PSYCHO_NINTR 6 49#define PSYCHO_NRANGE 4 50 |
|
| 48/* | 51/* |
| 49 * psycho register offsets. | 52 * Psycho register offsets |
| 50 * 51 * NB: FFB0 and FFB1 intr map regs also appear at 0x6000 and 0x8000 52 * respectively. 53 */ 54#define PSR_UPA_PORTID 0x0000 /* UPA port ID register */ 55#define PSR_UPA_CONFIG 0x0008 /* UPA config register */ 56#define PSR_CS 0x0010 /* PSYCHO control/status register */ 57#define PSR_ECCC 0x0020 /* ECC control register */ 58#define PSR_UE_AFS 0x0030 /* Uncorrectable Error AFSR */ 59#define PSR_UE_AFA 0x0038 /* Uncorrectable Error AFAR */ 60#define PSR_CE_AFS 0x0040 /* Correctable Error AFSR */ 61#define PSR_CE_AFA 0x0048 /* Correctable Error AFAR */ 62#define PSR_PM_CTL 0x0100 /* Performance monitor control reg */ 63#define PSR_PM_COUNT 0x0108 /* Performance monitor counter reg */ | 53 * 54 * NB: FFB0 and FFB1 intr map regs also appear at 0x6000 and 0x8000 55 * respectively. 56 */ 57#define PSR_UPA_PORTID 0x0000 /* UPA port ID register */ 58#define PSR_UPA_CONFIG 0x0008 /* UPA config register */ 59#define PSR_CS 0x0010 /* PSYCHO control/status register */ 60#define PSR_ECCC 0x0020 /* ECC control register */ 61#define PSR_UE_AFS 0x0030 /* Uncorrectable Error AFSR */ 62#define PSR_UE_AFA 0x0038 /* Uncorrectable Error AFAR */ 63#define PSR_CE_AFS 0x0040 /* Correctable Error AFSR */ 64#define PSR_CE_AFA 0x0048 /* Correctable Error AFAR */ 65#define PSR_PM_CTL 0x0100 /* Performance monitor control reg */ 66#define PSR_PM_COUNT 0x0108 /* Performance monitor counter reg */ |
| 64#define PSR_IOMMU 0x0200 /* IOMMU registers. */ | 67#define PSR_IOMMU 0x0200 /* IOMMU registers */ |
| 65#define PSR_PCIA0_INT_MAP 0x0c00 /* PCI bus a slot 0 irq map reg */ 66#define PSR_PCIA1_INT_MAP 0x0c08 /* PCI bus a slot 1 irq map reg */ 67#define PSR_PCIA2_INT_MAP 0x0c10 /* PCI bus a slot 2 irq map reg (IIi) */ 68#define PSR_PCIA3_INT_MAP 0x0c18 /* PCI bus a slot 3 irq map reg (IIi) */ 69#define PSR_PCIB0_INT_MAP 0x0c20 /* PCI bus b slot 0 irq map reg */ 70#define PSR_PCIB1_INT_MAP 0x0c28 /* PCI bus b slot 1 irq map reg */ 71#define PSR_PCIB2_INT_MAP 0x0c30 /* PCI bus b slot 2 irq map reg */ 72#define PSR_PCIB3_INT_MAP 0x0c38 /* PCI bus b slot 3 irq map reg */ --- 45 unchanged lines hidden (view full) --- 118#define PSR_CE_INT_CLR 0x1878 /* CE clear int reg */ 119#define PSR_PCIAERR_INT_CLR 0x1880 /* PCI bus a error clear int reg */ 120#define PSR_PCIBERR_INT_CLR 0x1888 /* PCI bus b error clear int reg */ 121#define PSR_PWRMGT_INT_CLR 0x1890 /* power mgmt wake clr interrupt reg */ 122#define PSR_INTR_RETRY_TIM 0x1a00 /* interrupt retry timer */ 123#define PSR_TC0 0x1c00 /* timer/counter 0 */ 124#define PSR_TC1 0x1c10 /* timer/counter 1 */ 125#define PSR_DMA_WRITE_SYNC 0x1c20 /* PCI DMA write sync register (IIi) */ | 68#define PSR_PCIA0_INT_MAP 0x0c00 /* PCI bus a slot 0 irq map reg */ 69#define PSR_PCIA1_INT_MAP 0x0c08 /* PCI bus a slot 1 irq map reg */ 70#define PSR_PCIA2_INT_MAP 0x0c10 /* PCI bus a slot 2 irq map reg (IIi) */ 71#define PSR_PCIA3_INT_MAP 0x0c18 /* PCI bus a slot 3 irq map reg (IIi) */ 72#define PSR_PCIB0_INT_MAP 0x0c20 /* PCI bus b slot 0 irq map reg */ 73#define PSR_PCIB1_INT_MAP 0x0c28 /* PCI bus b slot 1 irq map reg */ 74#define PSR_PCIB2_INT_MAP 0x0c30 /* PCI bus b slot 2 irq map reg */ 75#define PSR_PCIB3_INT_MAP 0x0c38 /* PCI bus b slot 3 irq map reg */ --- 45 unchanged lines hidden (view full) --- 121#define PSR_CE_INT_CLR 0x1878 /* CE clear int reg */ 122#define PSR_PCIAERR_INT_CLR 0x1880 /* PCI bus a error clear int reg */ 123#define PSR_PCIBERR_INT_CLR 0x1888 /* PCI bus b error clear int reg */ 124#define PSR_PWRMGT_INT_CLR 0x1890 /* power mgmt wake clr interrupt reg */ 125#define PSR_INTR_RETRY_TIM 0x1a00 /* interrupt retry timer */ 126#define PSR_TC0 0x1c00 /* timer/counter 0 */ 127#define PSR_TC1 0x1c10 /* timer/counter 1 */ 128#define PSR_DMA_WRITE_SYNC 0x1c20 /* PCI DMA write sync register (IIi) */ |
| 126#define PSR_PCICTL0 0x2000 /* PCICTL registers for 1st psycho. */ 127#define PSR_PCICTL1 0x4000 /* PCICTL registers for 2nd psycho. */ | 129#define PSR_PCICTL0 0x2000 /* PCICTL registers for 1st Psycho */ 130#define PSR_PCICTL1 0x4000 /* PCICTL registers for 2nd Psycho */ |
| 128#define PSR_DMA_SCB_DIAG0 0xa000 /* DMA scoreboard diag reg 0 */ 129#define PSR_DMA_SCB_DIAG1 0xa008 /* DMA scoreboard diag reg 1 */ 130#define PSR_IOMMU_SVADIAG 0xa400 /* IOMMU virtual addr diag reg */ 131#define PSR_IOMMU_TLB_CMP_DIAG 0xa408 /* IOMMU TLB tag compare diag reg */ 132#define PSR_IOMMU_QUEUE_DIAG 0xa500 /* IOMMU LRU queue diag regs 0..15 */ 133#define PSR_IOMMU_TLB_TAG_DIAG 0xa580 /* TLB tag diag regs 0..15 */ 134#define PSR_IOMMU_TLB_DATA_DIAG 0xa600 /* TLB data RAM diag regs 0..15 */ 135#define PSR_PCI_INT_DIAG 0xa800 /* PCI int state diag reg */ --- 15 unchanged lines hidden (view full) --- 151 * 152 * Note that the SUNW,sabre/SUNW,simba combinations found on the 153 * Ultra5 and Ultra10 machines uses slightly differrent addresses 154 * than the above. This is mostly due to the fact that the APB is 155 * a multi-function PCI device with two PCI bridges, and the U2P is 156 * two separate PCI bridges. It uses the same PCI configuration 157 * space, though the configuration header for each PCI bus is 158 * located differently due to the SUNW,simba PCI busses being | 131#define PSR_DMA_SCB_DIAG0 0xa000 /* DMA scoreboard diag reg 0 */ 132#define PSR_DMA_SCB_DIAG1 0xa008 /* DMA scoreboard diag reg 1 */ 133#define PSR_IOMMU_SVADIAG 0xa400 /* IOMMU virtual addr diag reg */ 134#define PSR_IOMMU_TLB_CMP_DIAG 0xa408 /* IOMMU TLB tag compare diag reg */ 135#define PSR_IOMMU_QUEUE_DIAG 0xa500 /* IOMMU LRU queue diag regs 0..15 */ 136#define PSR_IOMMU_TLB_TAG_DIAG 0xa580 /* TLB tag diag regs 0..15 */ 137#define PSR_IOMMU_TLB_DATA_DIAG 0xa600 /* TLB data RAM diag regs 0..15 */ 138#define PSR_PCI_INT_DIAG 0xa800 /* PCI int state diag reg */ --- 15 unchanged lines hidden (view full) --- 154 * 155 * Note that the SUNW,sabre/SUNW,simba combinations found on the 156 * Ultra5 and Ultra10 machines uses slightly differrent addresses 157 * than the above. This is mostly due to the fact that the APB is 158 * a multi-function PCI device with two PCI bridges, and the U2P is 159 * two separate PCI bridges. It uses the same PCI configuration 160 * space, though the configuration header for each PCI bus is 161 * located differently due to the SUNW,simba PCI busses being |
| 159 * function 0 and function 1 of the APB, whereas the psycho's are | 162 * function 0 and function 1 of the APB, whereas the Psycho's are |
| 160 * each their own PCI device. The I/O and memory spaces are each 161 * split into 8 equally sized areas (8x2MB blocks for I/O space, 162 * and 8x512MB blocks for memory space). These are allocated in to 163 * either PCI A or PCI B, or neither in the APB's `I/O Address Map 164 * Register A/B' (0xde) and `Memory Address Map Register A/B' (0xdf) | 163 * each their own PCI device. The I/O and memory spaces are each 164 * split into 8 equally sized areas (8x2MB blocks for I/O space, 165 * and 8x512MB blocks for memory space). These are allocated in to 166 * either PCI A or PCI B, or neither in the APB's `I/O Address Map 167 * Register A/B' (0xde) and `Memory Address Map Register A/B' (0xdf) |
| 165 * registers of each simba. We must ensure that both of the | 168 * registers of each Simba. We must ensure that both of the |
| 166 * following are correct (the prom should do this for us): 167 * 168 * (PCI A Memory Address Map) & (PCI B Memory Address Map) == 0 169 * 170 * (PCI A I/O Address Map) & (PCI B I/O Address Map) == 0 171 * 172 * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space 173 * 1fe.0100.0800 - 1fe.0100.08ff PCI B configuration header --- 15 unchanged lines hidden (view full) --- 189#define PSYCHO_GCSR_VERS(csr) ((u_int)(((csr) >> 56) & 0xf)) 190#define PSYCHO_GCSR_MID(csr) ((u_int)(((csr) >> 51) & 0x1f)) 191#define PSYCHO_GCSR_IGN(csr) ((u_int)(((csr) >> 46) & 0x1f)) 192#define PSYCHO_CSR_APCKEN 8 /* UPA addr parity check enable */ 193#define PSYCHO_CSR_APERR 4 /* UPA addr parity error */ 194#define PSYCHO_CSR_IAP 2 /* invert UPA address parity */ 195#define PSYCHO_CSR_MODE 1 /* UPA/PCI handshake */ 196 | 169 * following are correct (the prom should do this for us): 170 * 171 * (PCI A Memory Address Map) & (PCI B Memory Address Map) == 0 172 * 173 * (PCI A I/O Address Map) & (PCI B I/O Address Map) == 0 174 * 175 * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space 176 * 1fe.0100.0800 - 1fe.0100.08ff PCI B configuration header --- 15 unchanged lines hidden (view full) --- 192#define PSYCHO_GCSR_VERS(csr) ((u_int)(((csr) >> 56) & 0xf)) 193#define PSYCHO_GCSR_MID(csr) ((u_int)(((csr) >> 51) & 0x1f)) 194#define PSYCHO_GCSR_IGN(csr) ((u_int)(((csr) >> 46) & 0x1f)) 195#define PSYCHO_CSR_APCKEN 8 /* UPA addr parity check enable */ 196#define PSYCHO_CSR_APERR 4 /* UPA addr parity error */ 197#define PSYCHO_CSR_IAP 2 /* invert UPA address parity */ 198#define PSYCHO_CSR_MODE 1 /* UPA/PCI handshake */ 199 |
| 197/* Offsets into the PSR_PCICTL* register block. */ | 200/* Offsets into the PSR_PCICTL* register block */ |
| 198#define PCR_CS 0x0000 /* PCI control/status register */ 199#define PCR_AFS 0x0010 /* PCI AFSR register */ 200#define PCR_AFA 0x0018 /* PCI AFAR register */ 201#define PCR_DIAG 0x0020 /* PCI diagnostic register */ 202#define PCR_TAS 0x0028 /* PCI target address space reg (IIi) */ 203#define PCR_STRBUF 0x0800 /* IOMMU streaming buffer registers. */ 204 | 201#define PCR_CS 0x0000 /* PCI control/status register */ 202#define PCR_AFS 0x0010 /* PCI AFSR register */ 203#define PCR_AFA 0x0018 /* PCI AFAR register */ 204#define PCR_DIAG 0x0020 /* PCI diagnostic register */ 205#define PCR_TAS 0x0028 /* PCI target address space reg (IIi) */ 206#define PCR_STRBUF 0x0800 /* IOMMU streaming buffer registers. */ 207 |
| 205/* Device space defines. */ | 208/* Device space defines */ |
| 206#define PSYCHO_CONF_SIZE 0x1000000 207#define PSYCHO_CONF_BUS_SHIFT 16 208#define PSYCHO_CONF_DEV_SHIFT 11 209#define PSYCHO_CONF_FUNC_SHIFT 8 210#define PSYCHO_CONF_REG_SHIFT 0 211#define PSYCHO_IO_SIZE 0x1000000 212#define PSYCHO_MEM_SIZE 0x100000000 213 214#define PSYCHO_CONF_OFF(bus, slot, func, reg) \ 215 (((bus) << PSYCHO_CONF_BUS_SHIFT) | \ 216 ((slot) << PSYCHO_CONF_DEV_SHIFT) | \ 217 ((func) << PSYCHO_CONF_FUNC_SHIFT) | \ 218 ((reg) << PSYCHO_CONF_REG_SHIFT)) 219 220/* what the bits mean! */ 221 222/* PCI [a|b] control/status register */ | 209#define PSYCHO_CONF_SIZE 0x1000000 210#define PSYCHO_CONF_BUS_SHIFT 16 211#define PSYCHO_CONF_DEV_SHIFT 11 212#define PSYCHO_CONF_FUNC_SHIFT 8 213#define PSYCHO_CONF_REG_SHIFT 0 214#define PSYCHO_IO_SIZE 0x1000000 215#define PSYCHO_MEM_SIZE 0x100000000 216 217#define PSYCHO_CONF_OFF(bus, slot, func, reg) \ 218 (((bus) << PSYCHO_CONF_BUS_SHIFT) | \ 219 ((slot) << PSYCHO_CONF_DEV_SHIFT) | \ 220 ((func) << PSYCHO_CONF_FUNC_SHIFT) | \ 221 ((reg) << PSYCHO_CONF_REG_SHIFT)) 222 223/* what the bits mean! */ 224 225/* PCI [a|b] control/status register */ |
| 223/* note that the sabre only has one set of PCI control/status registers */ | 226/* note that the Sabre only has one set of PCI control/status registers */ |
| 224#define PCICTL_MRLM 0x0000001000000000 /* Memory Read Line/Multiple */ 225#define PCICTL_SERR 0x0000000400000000 /* SERR asserted; W1C */ 226#define PCICTL_ARB_PARK 0x0000000000200000 /* PCI arbitration parking */ 227#define PCICTL_CPU_PRIO 0x0000000000100000 /* PCI arbitration parking */ 228#define PCICTL_ARB_PRIO 0x00000000000f0000 /* PCI arbitration parking */ 229#define PCICTL_ERRINTEN 0x0000000000000100 /* PCI error interrupt enable */ 230#define PCICTL_RTRYWAIT 0x0000000000000080 /* PCI error interrupt enable */ 231#define PCICTL_4ENABLE 0x000000000000000f /* enable 4 PCI slots */ 232#define PCICTL_6ENABLE 0x000000000000003f /* enable 6 PCI slots */ 233 234/* Uncorrectable error asynchronous fault status registers */ | 227#define PCICTL_MRLM 0x0000001000000000 /* Memory Read Line/Multiple */ 228#define PCICTL_SERR 0x0000000400000000 /* SERR asserted; W1C */ 229#define PCICTL_ARB_PARK 0x0000000000200000 /* PCI arbitration parking */ 230#define PCICTL_CPU_PRIO 0x0000000000100000 /* PCI arbitration parking */ 231#define PCICTL_ARB_PRIO 0x00000000000f0000 /* PCI arbitration parking */ 232#define PCICTL_ERRINTEN 0x0000000000000100 /* PCI error interrupt enable */ 233#define PCICTL_RTRYWAIT 0x0000000000000080 /* PCI error interrupt enable */ 234#define PCICTL_4ENABLE 0x000000000000000f /* enable 4 PCI slots */ 235#define PCICTL_6ENABLE 0x000000000000003f /* enable 6 PCI slots */ 236 237/* Uncorrectable error asynchronous fault status registers */ |
| 235#define UEAFSR_BLK (1UL << 23) /* Error caused by block transaction. */ 236#define UEAFSR_P_DTE (1UL << 56) /* Pri. DVMA translation error. */ 237#define UEAFSR_S_DTE (1UL << 57) /* Sec. DVMA translation error. */ 238#define UEAFSR_S_DWR (1UL << 58) /* Sec. error during DVMA write. */ 239#define UEAFSR_S_DRD (1UL << 59) /* Sec. error during DVMA read. */ 240#define UEAFSR_S_PIO (1UL << 60) /* Sec. error during PIO access. */ 241#define UEAFSR_P_DWR (1UL << 61) /* Pri. error during DVMA write. */ 242#define UEAFSR_P_DRD (1UL << 62) /* Pri. error during DVMA read. */ 243#define UEAFSR_P_PIO (1UL << 63) /* Pri. error during PIO access. */ | 238#define UEAFSR_BLK (1UL << 23) /* Error caused by block transaction */ 239#define UEAFSR_P_DTE (1UL << 56) /* Pri. DVMA translation error */ 240#define UEAFSR_S_DTE (1UL << 57) /* Sec. DVMA translation error */ 241#define UEAFSR_S_DWR (1UL << 58) /* Sec. error during DVMA write */ 242#define UEAFSR_S_DRD (1UL << 59) /* Sec. error during DVMA read */ 243#define UEAFSR_S_PIO (1UL << 60) /* Sec. error during PIO access */ 244#define UEAFSR_P_DWR (1UL << 61) /* Pri. error during DVMA write */ 245#define UEAFSR_P_DRD (1UL << 62) /* Pri. error during DVMA read */ 246#define UEAFSR_P_PIO (1UL << 63) /* Pri. error during PIO access */ |
| 244 245/* Correctable error asynchronous fault status registers */ | 247 248/* Correctable error asynchronous fault status registers */ |
| 246#define CEAFSR_BLK (1UL << 23) /* Error caused by block transaction. */ 247#define CEAFSR_S_DWR (1UL << 58) /* Sec. error caused by DVMA write. */ 248#define CEAFSR_S_DRD (1UL << 59) /* Sec. error caused by DVMA read. */ 249#define CEAFSR_S_PIO (1UL << 60) /* Sec. error caused by PIO access. */ 250#define CEAFSR_P_DWR (1UL << 61) /* Pri. error caused by DVMA write. */ 251#define CEAFSR_P_DRD (1UL << 62) /* Pri. error caused by DVMA read. */ 252#define CEAFSR_P_PIO (1UL << 63) /* Pri. error caused by PIO access. */ | 249#define CEAFSR_BLK (1UL << 23) /* Error caused by block transaction */ 250#define CEAFSR_S_DWR (1UL << 58) /* Sec. error caused by DVMA write */ 251#define CEAFSR_S_DRD (1UL << 59) /* Sec. error caused by DVMA read */ 252#define CEAFSR_S_PIO (1UL << 60) /* Sec. error caused by PIO access */ 253#define CEAFSR_P_DWR (1UL << 61) /* Pri. error caused by DVMA write */ 254#define CEAFSR_P_DRD (1UL << 62) /* Pri. error caused by DVMA read */ 255#define CEAFSR_P_PIO (1UL << 63) /* Pri. error caused by PIO access */ |
| 253 254#define CEAFSR_ERRMASK \ 255 (CEAFSR_P_PIO | CEAFSR_P_DRD | CEAFSR_P_DWR | \ 256 CEAFSR_S_PIO | CEAFSR_S_DRD | CEAFSR_S_DWR) 257 | 256 257#define CEAFSR_ERRMASK \ 258 (CEAFSR_P_PIO | CEAFSR_P_DRD | CEAFSR_P_DWR | \ 259 CEAFSR_S_PIO | CEAFSR_S_DRD | CEAFSR_S_DWR) 260 |
| 258/* Definitions for the target address space register. */ | 261/* Definitions for the target address space register */ |
| 259#define PCITAS_ADDR_SHIFT 29 260 | 262#define PCITAS_ADDR_SHIFT 29 263 |
| 261/* Definitions for the psycho configuration space */ 262#define PCS_DEVICE 0 /* Device number of psycho CS entry */ 263#define PCS_FUNC 0 /* Function number of psycho CS entry */ | 264/* Definitions for the Psycho configuration space */ 265#define PCS_DEVICE 0 /* Device number of Psycho CS entry */ 266#define PCS_FUNC 0 /* Function number of Psycho CS entry */ |
| 264 265/* Non-Standard registers in the configration space */ 266#define PCSR_SECBUS 0x40 /* Secondary bus number register */ 267#define PCSR_SUBBUS 0x41 /* Subordinate bus number register */ 268 | 267 268/* Non-Standard registers in the configration space */ 269#define PCSR_SECBUS 0x40 /* Secondary bus number register */ 270#define PCSR_SUBBUS 0x41 /* Subordinate bus number register */ 271 |
| 269#endif /* _SPARC64_PCI_PSYCHOREG_H_ */ | 272#endif /* !_SPARC64_PCI_PSYCHOREG_H_ */ |