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psycho.c (128625) psycho.c (129051)
1/*
2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 14 unchanged lines hidden (view full) ---

23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
30 *
1/*
2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
30 *
31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 128625 2004-04-25 00:30:28Z tmm $
31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 129051 2004-05-08 13:53:47Z marius $
32 */
33
34/*
35 * Support for `psycho' and `psycho+' UPA to PCI bridge and
36 * UltraSPARC IIi and IIe `sabre' PCI controllers.
37 */
38
39#include "opt_ofw_pci.h"

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54#include <machine/iommureg.h>
55#include <machine/bus_common.h>
56#include <machine/frame.h>
57#include <machine/intr_machdep.h>
58#include <machine/nexusvar.h>
59#include <machine/ofw_bus.h>
60#include <machine/ofw_upa.h>
61#include <machine/resource.h>
32 */
33
34/*
35 * Support for `psycho' and `psycho+' UPA to PCI bridge and
36 * UltraSPARC IIi and IIe `sabre' PCI controllers.
37 */
38
39#include "opt_ofw_pci.h"

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54#include <machine/iommureg.h>
55#include <machine/bus_common.h>
56#include <machine/frame.h>
57#include <machine/intr_machdep.h>
58#include <machine/nexusvar.h>
59#include <machine/ofw_bus.h>
60#include <machine/ofw_upa.h>
61#include <machine/resource.h>
62#include <machine/cpu.h>
63
64#include <sys/rman.h>
65
66#include <machine/iommuvar.h>
67
68#include <dev/pci/pcivar.h>
69#include <dev/pci/pcireg.h>
70

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75#include "pcib_if.h"
76
77static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t,
78 int, driver_intr_t);
79static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *,
80 bus_addr_t *, u_long *);
81static void psycho_intr_stub(void *);
82static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int);
62
63#include <sys/rman.h>
64
65#include <machine/iommuvar.h>
66
67#include <dev/pci/pcivar.h>
68#include <dev/pci/pcireg.h>
69

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74#include "pcib_if.h"
75
76static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t,
77 int, driver_intr_t);
78static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *,
79 bus_addr_t *, u_long *);
80static void psycho_intr_stub(void *);
81static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int);
83#ifndef OFW_NEWPCI
84static ofw_pci_binit_t psycho_binit;
85#endif
86
87/* Interrupt handlers */
88static void psycho_ue(void *);
89static void psycho_ce(void *);
90static void psycho_bus_a(void *);
91static void psycho_bus_b(void *);
92static void psycho_powerfail(void *);
93#ifdef PSYCHO_MAP_WAKEUP

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109static bus_activate_resource_t psycho_activate_resource;
110static bus_deactivate_resource_t psycho_deactivate_resource;
111static bus_release_resource_t psycho_release_resource;
112static pcib_maxslots_t psycho_maxslots;
113static pcib_read_config_t psycho_read_config;
114static pcib_write_config_t psycho_write_config;
115static pcib_route_interrupt_t psycho_route_interrupt;
116static ofw_pci_intr_pending_t psycho_intr_pending;
82
83/* Interrupt handlers */
84static void psycho_ue(void *);
85static void psycho_ce(void *);
86static void psycho_bus_a(void *);
87static void psycho_bus_b(void *);
88static void psycho_powerfail(void *);
89#ifdef PSYCHO_MAP_WAKEUP

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105static bus_activate_resource_t psycho_activate_resource;
106static bus_deactivate_resource_t psycho_deactivate_resource;
107static bus_release_resource_t psycho_release_resource;
108static pcib_maxslots_t psycho_maxslots;
109static pcib_read_config_t psycho_read_config;
110static pcib_write_config_t psycho_write_config;
111static pcib_route_interrupt_t psycho_route_interrupt;
112static ofw_pci_intr_pending_t psycho_intr_pending;
117#ifndef OFW_NEWPCI
118static ofw_pci_guess_ino_t psycho_guess_ino;
119#endif
120static ofw_pci_get_bus_handle_t psycho_get_bus_handle;
113static ofw_pci_get_bus_handle_t psycho_get_bus_handle;
121#ifdef OFW_NEWPCI
122static ofw_pci_get_node_t psycho_get_node;
123static ofw_pci_adjust_busrange_t psycho_adjust_busrange;
114static ofw_pci_get_node_t psycho_get_node;
115static ofw_pci_adjust_busrange_t psycho_adjust_busrange;
124#endif
125
126static device_method_t psycho_methods[] = {
127 /* Device interface */
128 DEVMETHOD(device_probe, psycho_probe),
129 DEVMETHOD(device_attach, psycho_attach),
130
131 /* Bus interface */
132 DEVMETHOD(bus_print_child, bus_generic_print_child),

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141 /* pcib interface */
142 DEVMETHOD(pcib_maxslots, psycho_maxslots),
143 DEVMETHOD(pcib_read_config, psycho_read_config),
144 DEVMETHOD(pcib_write_config, psycho_write_config),
145 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
146
147 /* ofw_pci interface */
148 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending),
116
117static device_method_t psycho_methods[] = {
118 /* Device interface */
119 DEVMETHOD(device_probe, psycho_probe),
120 DEVMETHOD(device_attach, psycho_attach),
121
122 /* Bus interface */
123 DEVMETHOD(bus_print_child, bus_generic_print_child),

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132 /* pcib interface */
133 DEVMETHOD(pcib_maxslots, psycho_maxslots),
134 DEVMETHOD(pcib_read_config, psycho_read_config),
135 DEVMETHOD(pcib_write_config, psycho_write_config),
136 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
137
138 /* ofw_pci interface */
139 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending),
149#ifndef OFW_NEWPCI
150 DEVMETHOD(ofw_pci_guess_ino, psycho_guess_ino),
151#endif
152 DEVMETHOD(ofw_pci_get_bus_handle, psycho_get_bus_handle),
140 DEVMETHOD(ofw_pci_get_bus_handle, psycho_get_bus_handle),
153#ifdef OFW_NEWPCI
154 DEVMETHOD(ofw_pci_get_node, psycho_get_node),
155 DEVMETHOD(ofw_pci_adjust_busrange, psycho_adjust_busrange),
141 DEVMETHOD(ofw_pci_get_node, psycho_get_node),
142 DEVMETHOD(ofw_pci_adjust_busrange, psycho_adjust_busrange),
156#endif
157
158 { 0, 0 }
159};
160
161static driver_t psycho_driver = {
162 "pcib",
163 psycho_methods,
164 sizeof(struct psycho_softc),

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292
293static int
294psycho_attach(device_t dev)
295{
296 struct psycho_softc *sc;
297 struct psycho_softc *osc = NULL;
298 struct psycho_softc *asc;
299 struct upa_regs *reg;
143
144 { 0, 0 }
145};
146
147static driver_t psycho_driver = {
148 "pcib",
149 psycho_methods,
150 sizeof(struct psycho_softc),

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278
279static int
280psycho_attach(device_t dev)
281{
282 struct psycho_softc *sc;
283 struct psycho_softc *osc = NULL;
284 struct psycho_softc *asc;
285 struct upa_regs *reg;
300#ifndef OFW_NEWPCI
301 struct ofw_pci_bdesc obd;
302#endif
303 struct psycho_desc *desc;
304 phandle_t node;
305 u_int64_t csr;
306 u_long mlen;
307 int psycho_br[2];
308 int n, i, nreg, rid;
309#ifdef PSYCHO_DEBUG
310 bus_addr_t map, clr;

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578 * The sabre always uses bus 0, but there only can be one sabre per
579 * machine.
580 */
581 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SUBBUS,
582 sc->sc_subbus, 1);
583 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SECBUS,
584 sc->sc_secbus, 1);
585
286 struct psycho_desc *desc;
287 phandle_t node;
288 u_int64_t csr;
289 u_long mlen;
290 int psycho_br[2];
291 int n, i, nreg, rid;
292#ifdef PSYCHO_DEBUG
293 bus_addr_t map, clr;

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561 * The sabre always uses bus 0, but there only can be one sabre per
562 * machine.
563 */
564 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SUBBUS,
565 sc->sc_subbus, 1);
566 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SECBUS,
567 sc->sc_secbus, 1);
568
586#ifdef OFW_NEWPCI
587 ofw_bus_setup_iinfo(node, &sc->sc_iinfo, sizeof(ofw_pci_intr_t));
569 ofw_bus_setup_iinfo(node, &sc->sc_iinfo, sizeof(ofw_pci_intr_t));
588#else
589 obd.obd_bus = obd.obd_secbus = sc->sc_secbus;
590 obd.obd_subbus = sc->sc_subbus;
591 obd.obd_slot = PCS_DEVICE;
592 obd.obd_func = PCS_FUNC;
593 obd.obd_init = psycho_binit;
594 obd.obd_super = NULL;
595
570
596 /*
597 * Initialize the interrupt registers of all devices hanging from
598 * the host bridge directly or indirectly via PCI-PCI bridges.
599 * The MI code (and the PCI spec) assume that this is done during
600 * system initialization, however the firmware does not do this
601 * at least on some models, and we probably shouldn't trust that
602 * the firmware uses the same model as this driver if it does.
603 * Additionally, set up the bus numbers and ranges.
604 */
605 ofw_pci_init(dev, sc->sc_node, sc->sc_ign, &obd);
606#endif /* OFW_NEWPCI */
607
608 device_add_child(dev, "pci", sc->sc_secbus);
609 return (bus_generic_attach(dev));
610}
611
612static void
613psycho_set_intr(struct psycho_softc *sc, int index,
614 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler)
615{

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787 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT);
788 if (name == 0)
789 panic("couldn't malloc iommu name");
790 snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev));
791
792 iommu_init(name, is, tsbsize, sc->sc_dvmabase, 0);
793}
794
571 device_add_child(dev, "pci", sc->sc_secbus);
572 return (bus_generic_attach(dev));
573}
574
575static void
576psycho_set_intr(struct psycho_softc *sc, int index,
577 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler)
578{

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750 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT);
751 if (name == 0)
752 panic("couldn't malloc iommu name");
753 snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev));
754
755 iommu_init(name, is, tsbsize, sc->sc_dvmabase, 0);
756}
757
795#ifndef OFW_NEWPCI
796static void
797psycho_binit(device_t busdev, struct ofw_pci_bdesc *obd)
798{
799
800#ifdef PSYCHO_DEBUG
801 printf("psycho at %u/%u/%u: setting bus #s to %u/%u/%u\n",
802 obd->obd_bus, obd->obd_slot, obd->obd_func, obd->obd_bus,
803 obd->obd_secbus, obd->obd_subbus);
804#endif /* PSYCHO_DEBUG */
805 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func,
806 PCSR_SUBBUS, obd->obd_subbus, 1);
807}
808#endif
809
810static int
811psycho_maxslots(device_t dev)
812{
813
814 /* XXX: is this correct? */
815 return (PCI_SLOTMAX);
816}
817
758static int
759psycho_maxslots(device_t dev)
760{
761
762 /* XXX: is this correct? */
763 return (PCI_SLOTMAX);
764}
765
818#ifndef OFW_NEWPCI
819/*
820 * Keep a table of quirky PCI devices that need fixups before the MI PCI code
821 * creates the resource lists. This needs to be moved around once other bus
822 * drivers are added. Moving it to the MI code should maybe be reconsidered
823 * if one of these devices appear in non-sparc64 boxen. It's likely that not
824 * all BIOSes/firmwares can deal with them.
825 */
826struct psycho_dquirk {
827 u_int32_t dq_devid;
828 int dq_quirk;
829};
830
831/* Quirk types. May be or'ed together. */
832#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */
833
834static struct psycho_dquirk dquirks[] = {
835 { 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */
836 { 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */
837 { 0x1102108e, DQT_BAD_INTPIN }, /* Sun FireWire ctl. (PCIO2 func. 2) */
838 { 0x1103108e, DQT_BAD_INTPIN }, /* Sun USB ctl. (PCIO2 func. 3) */
839};
840#endif /* !OFW_NEWPCI */
841
842#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0]))
843
844static u_int32_t
845psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
846 int width)
847{
848 struct psycho_softc *sc;
849 bus_space_handle_t bh;
850 u_long offset = 0;
766static u_int32_t
767psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
768 int width)
769{
770 struct psycho_softc *sc;
771 bus_space_handle_t bh;
772 u_long offset = 0;
851#ifndef OFW_NEWPCI
852 u_int32_t devid;
853#endif
854 u_int8_t byte;
855 u_int16_t shrt;
856 u_int32_t wrd;
857 u_int32_t r;
858 int i;
859
860 sc = (struct psycho_softc *)device_get_softc(dev);
861 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);

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879
880 if (i) {
881#ifdef PSYCHO_DEBUG
882 printf("psycho read data error reading: %d.%d.%d: 0x%x\n",
883 bus, slot, func, reg);
884#endif
885 r = -1;
886 }
773 u_int8_t byte;
774 u_int16_t shrt;
775 u_int32_t wrd;
776 u_int32_t r;
777 int i;
778
779 sc = (struct psycho_softc *)device_get_softc(dev);
780 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);

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798
799 if (i) {
800#ifdef PSYCHO_DEBUG
801 printf("psycho read data error reading: %d.%d.%d: 0x%x\n",
802 bus, slot, func, reg);
803#endif
804 r = -1;
805 }
887
888#ifndef OFW_NEWPCI
889 if (reg == PCIR_INTPIN && r == 0) {
890 /* Check for DQT_BAD_INTPIN quirk. */
891 devid = psycho_read_config(dev, bus, slot, func,
892 PCIR_DEVVENDOR, 4);
893 for (i = 0; i < NDQUIRKS; i++) {
894 if (dquirks[i].dq_devid == devid) {
895 /*
896 * Need to set the intpin to a value != 0 so
897 * that the MI code will think that this device
898 * has an interrupt.
899 * Just use 1 (intpin a) for now. This is, of
900 * course, bogus, but since interrupts are
901 * routed in advance, this does not really
902 * matter.
903 */
904 if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0)
905 r = 1;
906 break;
907 }
908 }
909 }
910#endif /* !OFW_NEWPCI */
911 return (r);
912}
913
914static void
915psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func,
916 u_int reg, u_int32_t val, int width)
917{
918 struct psycho_softc *sc;

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935 default:
936 panic("psycho_write_config: bad width");
937 }
938}
939
940static int
941psycho_route_interrupt(device_t bridge, device_t dev, int pin)
942{
806 return (r);
807}
808
809static void
810psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func,
811 u_int reg, u_int32_t val, int width)
812{
813 struct psycho_softc *sc;

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830 default:
831 panic("psycho_write_config: bad width");
832 }
833}
834
835static int
836psycho_route_interrupt(device_t bridge, device_t dev, int pin)
837{
943#ifdef OFW_NEWPCI
944 struct psycho_softc *sc = device_get_softc(bridge);
945 struct ofw_pci_register reg;
946 bus_addr_t intrmap;
947 phandle_t node = ofw_pci_get_node(dev);
948 ofw_pci_intr_t pintr, mintr;
949 u_int8_t maskbuf[sizeof(reg) + sizeof(pintr)];
950
951 pintr = pin;

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970 * offset of 2 (hence the factor of 3 below).
971 */
972 intrmap = PSR_PCIA0_INT_MAP +
973 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
974 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
975 device_printf(bridge, "guessing interrupt %d for device %d/%d pin %d\n",
976 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
977 return (mintr);
838 struct psycho_softc *sc = device_get_softc(bridge);
839 struct ofw_pci_register reg;
840 bus_addr_t intrmap;
841 phandle_t node = ofw_pci_get_node(dev);
842 ofw_pci_intr_t pintr, mintr;
843 u_int8_t maskbuf[sizeof(reg) + sizeof(pintr)];
844
845 pintr = pin;

--- 18 unchanged lines hidden (view full) ---

864 * offset of 2 (hence the factor of 3 below).
865 */
866 intrmap = PSR_PCIA0_INT_MAP +
867 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
868 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
869 device_printf(bridge, "guessing interrupt %d for device %d/%d pin %d\n",
870 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
871 return (mintr);
978#else
979 /*
980 * XXX: ugly loathsome hack:
981 * We can't use ofw_pci_route_intr() here; the device passed may be
982 * the one of a bridge, so the original device can't be recovered.
983 *
984 * We need to use the firmware to route interrupts, however it has
985 * no interface which could be used to interpret intpins; instead,
986 * all assignments are done by device.
987 *
988 * The MI pci code will try to reroute interrupts of 0, although they
989 * are correct; all other interrupts are preinitialized, so if we
990 * get here, the intline is either 0 (so return 0), or we hit a
991 * device which was not preinitialized (e.g. hotplugged stuff), in
992 * which case we are lost.
993 */
994 return (0);
995#endif /* OFW_NEWPCI */
996}
997
998static int
999psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1000{
1001 struct psycho_softc *sc;
1002
1003 sc = (struct psycho_softc *)device_get_softc(dev);

--- 229 unchanged lines hidden (view full) ---

1233 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) {
1234 device_printf(dev, "psycho_intr_pending: mapping not found for"
1235 " %d\n", intr);
1236 return (0);
1237 }
1238 return (diag != 0);
1239}
1240
872}
873
874static int
875psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
876{
877 struct psycho_softc *sc;
878
879 sc = (struct psycho_softc *)device_get_softc(dev);

--- 229 unchanged lines hidden (view full) ---

1109 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) {
1110 device_printf(dev, "psycho_intr_pending: mapping not found for"
1111 " %d\n", intr);
1112 return (0);
1113 }
1114 return (diag != 0);
1115}
1116
1241#ifndef OFW_NEWPCI
1242static ofw_pci_intr_t
1243psycho_guess_ino(device_t dev, phandle_t node, u_int slot, u_int pin)
1244{
1245 struct psycho_softc *sc = (struct psycho_softc *)device_get_softc(dev);
1246 bus_addr_t intrmap;
1247
1248 /*
1249 * If this is not for one of our direct children (i.e. we are mapping
1250 * at our node), tell the interrupt mapper to go on - we need the
1251 * slot number of the device or it's topmost parent bridge to guess
1252 * the INO.
1253 */
1254 if (node != sc->sc_node)
1255 return (PCI_INVALID_IRQ);
1256 /*
1257 * Actually guess the INO. We always assume that this is a non-OBIO
1258 * device, and use from the slot number to determine it.
1259 * We only need to do this on e450s, it seems; here, the slot numbers
1260 * for bus A are one-based, while those for bus B seemingly have an
1261 * offset of 2 (hence the factor of 3 below).
1262 */
1263 intrmap = PSR_PCIA0_INT_MAP + 8 * (slot - 1 + 3 * sc->sc_half);
1264 return (INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1);
1265}
1266#endif /* !OFW_NEWPCI */
1267
1268static bus_space_handle_t
1269psycho_get_bus_handle(device_t dev, int type, bus_space_handle_t childhdl,
1270 bus_space_tag_t *tag)
1271{
1272 struct psycho_softc *sc;
1273
1274 sc = (struct psycho_softc *)device_get_softc(dev);
1275 switch (type) {
1276 case SYS_RES_IOPORT:
1277 *tag = sc->sc_iot;
1278 return (sc->sc_bh[PCI_CS_IO] + childhdl);
1279 case SYS_RES_MEMORY:
1280 *tag = sc->sc_memt;
1281 return (sc->sc_bh[PCI_CS_MEM32] + childhdl);
1282 default:
1283 panic("psycho_get_bus_handle: illegal space\n");
1284 }
1285}
1286
1117static bus_space_handle_t
1118psycho_get_bus_handle(device_t dev, int type, bus_space_handle_t childhdl,
1119 bus_space_tag_t *tag)
1120{
1121 struct psycho_softc *sc;
1122
1123 sc = (struct psycho_softc *)device_get_softc(dev);
1124 switch (type) {
1125 case SYS_RES_IOPORT:
1126 *tag = sc->sc_iot;
1127 return (sc->sc_bh[PCI_CS_IO] + childhdl);
1128 case SYS_RES_MEMORY:
1129 *tag = sc->sc_memt;
1130 return (sc->sc_bh[PCI_CS_MEM32] + childhdl);
1131 default:
1132 panic("psycho_get_bus_handle: illegal space\n");
1133 }
1134}
1135
1287#ifdef OFW_NEWPCI
1288static phandle_t
1289psycho_get_node(device_t bus, device_t dev)
1290{
1291 struct psycho_softc *sc = device_get_softc(bus);
1292
1293 /* We only have one child, the PCI bus, which needs our own node. */
1294 return (sc->sc_node);
1295}

--- 10 unchanged lines hidden (view full) ---

1306 "adjusting secondary bus number from %d to %d\n",
1307 sc->sc_subbus, subbus);
1308#endif
1309 sc->sc_subbus = subbus;
1310 PCIB_WRITE_CONFIG(dev, sc->sc_secbus, PCS_DEVICE, PCS_FUNC,
1311 PCSR_SUBBUS, subbus, 1);
1312 }
1313}
1136static phandle_t
1137psycho_get_node(device_t bus, device_t dev)
1138{
1139 struct psycho_softc *sc = device_get_softc(bus);
1140
1141 /* We only have one child, the PCI bus, which needs our own node. */
1142 return (sc->sc_node);
1143}

--- 10 unchanged lines hidden (view full) ---

1154 "adjusting secondary bus number from %d to %d\n",
1155 sc->sc_subbus, subbus);
1156#endif
1157 sc->sc_subbus = subbus;
1158 PCIB_WRITE_CONFIG(dev, sc->sc_secbus, PCS_DEVICE, PCS_FUNC,
1159 PCSR_SUBBUS, subbus, 1);
1160 }
1161}
1314#endif
1315
1316static bus_space_tag_t
1317psycho_alloc_bus_tag(struct psycho_softc *sc, int type)
1318{
1319 bus_space_tag_t bt;
1320
1321 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF,
1322 M_NOWAIT | M_ZERO);
1323 if (bt == NULL)
1324 panic("psycho_alloc_bus_tag: out of memory");
1325
1326 bzero(bt, sizeof *bt);
1327 bt->bst_cookie = sc;
1328 bt->bst_parent = sc->sc_bustag;
1329 bt->bst_type = type;
1330 return (bt);
1331}
1162
1163static bus_space_tag_t
1164psycho_alloc_bus_tag(struct psycho_softc *sc, int type)
1165{
1166 bus_space_tag_t bt;
1167
1168 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF,
1169 M_NOWAIT | M_ZERO);
1170 if (bt == NULL)
1171 panic("psycho_alloc_bus_tag: out of memory");
1172
1173 bzero(bt, sizeof *bt);
1174 bt->bst_cookie = sc;
1175 bt->bst_parent = sc->sc_bustag;
1176 bt->bst_type = type;
1177 return (bt);
1178}